lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_dev.h>
  51
  52 #include "i40e_logs.h"
  53 #include "i40e/i40e_register_x710_int.h"
  54 #include "i40e/i40e_prototype.h"
  55 #include "i40e/i40e_adminq_cmd.h"
  56 #include "i40e/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59 #include "i40e_pf.h"
  60
  61 /* Maximun number of MAC addresses */
  62 #define I40E_NUM_MACADDR_MAX       64
  63 #define I40E_CLEAR_PXE_WAIT_MS     200
  64
  65 /* Maximun number of capability elements */
  66 #define I40E_MAX_CAP_ELE_NUM       128
  67
  68 /* Wait count and inteval */
  69 #define I40E_CHK_Q_ENA_COUNT       1000
  70 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  71
  72 /* Maximun number of VSI */
  73 #define I40E_MAX_NUM_VSIS          (384UL)
  74
  75 /* Bit shift and mask */
  76 #define I40E_16_BIT_SHIFT 16
  77 #define I40E_16_BIT_MASK  0xFFFF
  78 #define I40E_32_BIT_SHIFT 32
  79 #define I40E_32_BIT_MASK  0xFFFFFFFF
  80 #define I40E_48_BIT_SHIFT 48
  81 #define I40E_48_BIT_MASK  0xFFFFFFFFFFFFULL
  82
  83 /* Default queue interrupt throttling time in microseconds*/
  84 #define I40E_ITR_INDEX_DEFAULT          0
  85 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  86 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  87
  88 #define I40E_RSS_OFFLOAD_ALL ( \
  89         ETH_RSS_NONF_IPV4_UDP | \
  90         ETH_RSS_NONF_IPV4_TCP | \
  91         ETH_RSS_NONF_IPV4_SCTP | \
  92         ETH_RSS_NONF_IPV4_OTHER | \
  93         ETH_RSS_FRAG_IPV4 | \
  94         ETH_RSS_NONF_IPV6_UDP | \
  95         ETH_RSS_NONF_IPV6_TCP | \
  96         ETH_RSS_NONF_IPV6_SCTP | \
  97         ETH_RSS_NONF_IPV6_OTHER | \
  98         ETH_RSS_FRAG_IPV6 | \
  99         ETH_RSS_L2_PAYLOAD)
 100
 101 /* All bits of RSS hash enable */
 102 #define I40E_RSS_HENA_ALL ( \
 103         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
 104         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
 105         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
 106         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
 107         (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
 108         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
 109         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
 110         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
 111         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
 112         (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
 113         (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
 114         (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
 115         (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
 116         (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
 117
 118 static int eth_i40e_dev_init(\
 119                         __attribute__((unused)) struct eth_driver *eth_drv,
 120                         struct rte_eth_dev *eth_dev);
 121 static int i40e_dev_configure(struct rte_eth_dev *dev);
 122 static int i40e_dev_start(struct rte_eth_dev *dev);
 123 static void i40e_dev_stop(struct rte_eth_dev *dev);
 124 static void i40e_dev_close(struct rte_eth_dev *dev);
 125 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 126 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 127 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 128 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 129 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 130                                struct rte_eth_stats *stats);
 131 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 132 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 133                                             uint16_t queue_id,
 134                                             uint8_t stat_idx,
 135                                             uint8_t is_rx);
 136 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 137                               struct rte_eth_dev_info *dev_info);
 138 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 139                                 uint16_t vlan_id,
 140                                 int on);
 141 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 142 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 143 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 144                                       uint16_t queue,
 145                                       int on);
 146 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 147 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 148 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 149 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 150                               struct rte_eth_fc_conf *fc_conf);
 151 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 152                                        struct rte_eth_pfc_conf *pfc_conf);
 153 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 154                           struct ether_addr *mac_addr,
 155                           uint32_t index,
 156                           uint32_t pool);
 157 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 158 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 159                                     struct rte_eth_rss_reta *reta_conf);
 160 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 161                                    struct rte_eth_rss_reta *reta_conf);
 162
 163 static int i40e_get_cap(struct i40e_hw *hw);
 164 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 165 static int i40e_pf_setup(struct i40e_pf *pf);
 166 static int i40e_vsi_init(struct i40e_vsi *vsi);
 167 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 168                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 169 static void i40e_stat_update_48(struct i40e_hw *hw,
 170                                uint32_t hireg,
 171                                uint32_t loreg,
 172                                bool offset_loaded,
 173                                uint64_t *offset,
 174                                uint64_t *stat);
 175 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 176 static void i40e_dev_interrupt_handler(
 177                 __rte_unused struct rte_intr_handle *handle, void *param);
 178 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 179                                 uint32_t base, uint32_t num);
 180 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 181 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 182                         uint32_t base);
 183 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 184                         uint16_t num);
 185 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 186 static int i40e_veb_release(struct i40e_veb *veb);
 187 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 188                                                 struct i40e_vsi *vsi);
 189 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 190 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 191 static int i40e_pf_disable_all_queues(struct i40e_hw *hw);
 192 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 193                                              struct i40e_macvlan_filter *mv_f,
 194                                              int num,
 195                                              struct ether_addr *addr);
 196 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 197                                              struct i40e_macvlan_filter *mv_f,
 198                                              int num,
 199                                              uint16_t vlan);
 200 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 201 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 202                                     struct rte_eth_rss_conf *rss_conf);
 203 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 204                                       struct rte_eth_rss_conf *rss_conf);
 205
 206 /* Default hash key buffer for RSS */
 207 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
 208
 209 static struct rte_pci_id pci_id_i40e_map[] = {
 210 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 211 #include "rte_pci_dev_ids.h"
 212 { .vendor_id = 0, /* sentinel */ },
 213 };
 214
 215 static struct eth_dev_ops i40e_eth_dev_ops = {
 216         .dev_configure                = i40e_dev_configure,
 217         .dev_start                    = i40e_dev_start,
 218         .dev_stop                     = i40e_dev_stop,
 219         .dev_close                    = i40e_dev_close,
 220         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 221         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 222         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 223         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 224         .link_update                  = i40e_dev_link_update,
 225         .stats_get                    = i40e_dev_stats_get,
 226         .stats_reset                  = i40e_dev_stats_reset,
 227         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 228         .dev_infos_get                = i40e_dev_info_get,
 229         .vlan_filter_set              = i40e_vlan_filter_set,
 230         .vlan_tpid_set                = i40e_vlan_tpid_set,
 231         .vlan_offload_set             = i40e_vlan_offload_set,
 232         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 233         .vlan_pvid_set                = i40e_vlan_pvid_set,
 234         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 235         .rx_queue_release             = i40e_dev_rx_queue_release,
 236         .rx_queue_count               = i40e_dev_rx_queue_count,
 237         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 238         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 239         .tx_queue_release             = i40e_dev_tx_queue_release,
 240         .dev_led_on                   = i40e_dev_led_on,
 241         .dev_led_off                  = i40e_dev_led_off,
 242         .flow_ctrl_set                = i40e_flow_ctrl_set,
 243         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 244         .mac_addr_add                 = i40e_macaddr_add,
 245         .mac_addr_remove              = i40e_macaddr_remove,
 246         .reta_update                  = i40e_dev_rss_reta_update,
 247         .reta_query                   = i40e_dev_rss_reta_query,
 248         .rss_hash_update              = i40e_dev_rss_hash_update,
 249         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 250 };
 251
 252 static struct eth_driver rte_i40e_pmd = {
 253         {
 254                 .name = "rte_i40e_pmd",
 255                 .id_table = pci_id_i40e_map,
 256                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 257         },
 258         .eth_dev_init = eth_i40e_dev_init,
 259         .dev_private_size = sizeof(struct i40e_adapter),
 260 };
 261
 262 static inline int
 263 i40e_prev_power_of_2(int n)
 264 {
 265        int p = n;
 266
 267        --p;
 268        p |= p >> 1;
 269        p |= p >> 2;
 270        p |= p >> 4;
 271        p |= p >> 8;
 272        p |= p >> 16;
 273        if (p == (n - 1))
 274                return n;
 275        p >>= 1;
 276
 277        return ++p;
 278 }
 279
 280 static inline int
 281 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 282                                      struct rte_eth_link *link)
 283 {
 284         struct rte_eth_link *dst = link;
 285         struct rte_eth_link *src = &(dev->data->dev_link);
 286
 287         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 288                                         *(uint64_t *)src) == 0)
 289                 return -1;
 290
 291         return 0;
 292 }
 293
 294 static inline int
 295 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 296                                       struct rte_eth_link *link)
 297 {
 298         struct rte_eth_link *dst = &(dev->data->dev_link);
 299         struct rte_eth_link *src = link;
 300
 301         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 302                                         *(uint64_t *)src) == 0)
 303                 return -1;
 304
 305         return 0;
 306 }
 307
 308 /*
 309  * Driver initialization routine.
 310  * Invoked once at EAL init time.
 311  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 312  */
 313 static int
 314 rte_i40e_pmd_init(const char *name __rte_unused,
 315                   const char *params __rte_unused)
 316 {
 317         PMD_INIT_FUNC_TRACE();
 318         rte_eth_driver_register(&rte_i40e_pmd);
 319
 320         return 0;
 321 }
 322
 323 static struct rte_driver rte_i40e_driver = {
 324         .type = PMD_PDEV,
 325         .init = rte_i40e_pmd_init,
 326 };
 327
 328 PMD_REGISTER_DRIVER(rte_i40e_driver);
 329
 330 static int
 331 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 332                   struct rte_eth_dev *dev)
 333 {
 334         struct rte_pci_device *pci_dev;
 335         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 336         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 337         struct i40e_vsi *vsi;
 338         int ret;
 339         uint32_t len;
 340         uint8_t aq_fail = 0;
 341
 342         PMD_INIT_FUNC_TRACE();
 343
 344         dev->dev_ops = &i40e_eth_dev_ops;
 345         dev->rx_pkt_burst = i40e_recv_pkts;
 346         dev->tx_pkt_burst = i40e_xmit_pkts;
 347
 348         /* for secondary processes, we don't initialise any further as primary
 349          * has already done this work. Only check we don't need a different
 350          * RX function */
 351         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 352                 if (dev->data->scattered_rx)
 353                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 354                 return 0;
 355         }
 356         pci_dev = dev->pci_dev;
 357         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 358         pf->adapter->eth_dev = dev;
 359         pf->dev_data = dev->data;
 360
 361         hw->back = I40E_PF_TO_ADAPTER(pf);
 362         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 363         if (!hw->hw_addr) {
 364                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 365                                         "as address is NULL\n");
 366                 return -ENODEV;
 367         }
 368
 369         hw->vendor_id = pci_dev->id.vendor_id;
 370         hw->device_id = pci_dev->id.device_id;
 371         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 372         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 373         hw->bus.device = pci_dev->addr.devid;
 374         hw->bus.func = pci_dev->addr.function;
 375
 376         /* Disable all queues before PF reset, as required */
 377         ret = i40e_pf_disable_all_queues(hw);
 378         if (ret != I40E_SUCCESS) {
 379                 PMD_INIT_LOG(ERR, "Failed to disable queues %u\n", ret);
 380                 return ret;
 381         }
 382
 383         /* Reset here to make sure all is clean for each PF */
 384         ret = i40e_pf_reset(hw);
 385         if (ret) {
 386                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 387                 return ret;
 388         }
 389
 390         /* Initialize the shared code (base driver) */
 391         ret = i40e_init_shared_code(hw);
 392         if (ret) {
 393                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 394                 return ret;
 395         }
 396
 397         /* Initialize the parameters for adminq */
 398         i40e_init_adminq_parameter(hw);
 399         ret = i40e_init_adminq(hw);
 400         if (ret != I40E_SUCCESS) {
 401                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 402                 return -EIO;
 403         }
 404         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM "
 405                         "%02d.%02d.%02d eetrack %04x\n",
 406                         hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 407                         hw->aq.api_maj_ver, hw->aq.api_min_ver,
 408                         ((hw->nvm.version >> 12) & 0xf),
 409                         ((hw->nvm.version >> 4) & 0xff),
 410                         (hw->nvm.version & 0xf), hw->nvm.eetrack);
 411
 412         /* Disable LLDP */
 413         ret = i40e_aq_stop_lldp(hw, true, NULL);
 414         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 415                 PMD_INIT_LOG(INFO, "Failed to stop lldp\n");
 416
 417         /* Clear PXE mode */
 418         i40e_clear_pxe_mode(hw);
 419
 420         /* Get hw capabilities */
 421         ret = i40e_get_cap(hw);
 422         if (ret != I40E_SUCCESS) {
 423                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 424                 goto err_get_capabilities;
 425         }
 426
 427         /* Initialize parameters for PF */
 428         ret = i40e_pf_parameter_init(dev);
 429         if (ret != 0) {
 430                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 431                 goto err_parameter_init;
 432         }
 433
 434         /* Initialize the queue management */
 435         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 436         if (ret < 0) {
 437                 PMD_INIT_LOG(ERR, "Failed to init queue pool\n");
 438                 goto err_qp_pool_init;
 439         }
 440         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 441                                 hw->func_caps.num_msix_vectors - 1);
 442         if (ret < 0) {
 443                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool\n");
 444                 goto err_msix_pool_init;
 445         }
 446
 447         /* Initialize lan hmc */
 448         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 449                                 hw->func_caps.num_rx_qp, 0, 0);
 450         if (ret != I40E_SUCCESS) {
 451                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 452                 goto err_init_lan_hmc;
 453         }
 454
 455         /* Configure lan hmc */
 456         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 457         if (ret != I40E_SUCCESS) {
 458                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 459                 goto err_configure_lan_hmc;
 460         }
 461
 462         /* Get and check the mac address */
 463         i40e_get_mac_addr(hw, hw->mac.addr);
 464         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 465                 PMD_INIT_LOG(ERR, "mac address is not valid");
 466                 ret = -EIO;
 467                 goto err_get_mac_addr;
 468         }
 469         /* Copy the permanent MAC address */
 470         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 471                         (struct ether_addr *) hw->mac.perm_addr);
 472
 473         /* Disable flow control */
 474         hw->fc.requested_mode = I40E_FC_NONE;
 475         i40e_set_fc(hw, &aq_fail, TRUE);
 476
 477         /* PF setup, which includes VSI setup */
 478         ret = i40e_pf_setup(pf);
 479         if (ret) {
 480                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 481                 goto err_setup_pf_switch;
 482         }
 483
 484         vsi = pf->main_vsi;
 485
 486         /* Disable double vlan by default */
 487         i40e_vsi_config_double_vlan(vsi, FALSE);
 488
 489         if (!vsi->max_macaddrs)
 490                 len = ETHER_ADDR_LEN;
 491         else
 492                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 493
 494         /* Should be after VSI initialized */
 495         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 496         if (!dev->data->mac_addrs) {
 497                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 498                                         "for storing mac address");
 499                 goto err_get_mac_addr;
 500         }
 501         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 502                                         &dev->data->mac_addrs[0]);
 503
 504         /* initialize pf host driver to setup SRIOV resource if applicable */
 505         i40e_pf_host_init(dev);
 506
 507         /* register callback func to eal lib */
 508         rte_intr_callback_register(&(pci_dev->intr_handle),
 509                 i40e_dev_interrupt_handler, (void *)dev);
 510
 511         /* configure and enable device interrupt */
 512         i40e_pf_config_irq0(hw);
 513         i40e_pf_enable_irq0(hw);
 514
 515         /* enable uio intr after callback register */
 516         rte_intr_enable(&(pci_dev->intr_handle));
 517
 518         return 0;
 519
 520 err_setup_pf_switch:
 521         rte_free(pf->main_vsi);
 522 err_get_mac_addr:
 523 err_configure_lan_hmc:
 524         (void)i40e_shutdown_lan_hmc(hw);
 525 err_init_lan_hmc:
 526         i40e_res_pool_destroy(&pf->msix_pool);
 527 err_msix_pool_init:
 528         i40e_res_pool_destroy(&pf->qp_pool);
 529 err_qp_pool_init:
 530 err_parameter_init:
 531 err_get_capabilities:
 532         (void)i40e_shutdown_adminq(hw);
 533
 534         return ret;
 535 }
 536
 537 static int
 538 i40e_dev_configure(struct rte_eth_dev *dev)
 539 {
 540         return i40e_dev_init_vlan(dev);
 541 }
 542
 543 void
 544 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 545 {
 546         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 547         uint16_t msix_vect = vsi->msix_intr;
 548         uint16_t i;
 549
 550         for (i = 0; i < vsi->nb_qps; i++) {
 551                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 552                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 553                 rte_wmb();
 554         }
 555
 556         if (vsi->type != I40E_VSI_SRIOV) {
 557                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 558                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 559                                 msix_vect - 1), 0);
 560         } else {
 561                 uint32_t reg;
 562                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 563                         vsi->user_param + (msix_vect - 1);
 564
 565                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 566         }
 567         I40E_WRITE_FLUSH(hw);
 568 }
 569
 570 static inline uint16_t
 571 i40e_calc_itr_interval(int16_t interval)
 572 {
 573         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 574                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 575
 576         /* Convert to hardware count, as writing each 1 represents 2 us */
 577         return (interval/2);
 578 }
 579
 580 void
 581 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 582 {
 583         uint32_t val;
 584         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 585         uint16_t msix_vect = vsi->msix_intr;
 586         uint16_t interval = i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 587         int i;
 588
 589         for (i = 0; i < vsi->nb_qps; i++)
 590                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 591
 592         /* Bind all RX queues to allocated MSIX interrupt */
 593         for (i = 0; i < vsi->nb_qps; i++) {
 594                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 595                         (interval << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
 596                         ((vsi->base_queue + i + 1) <<
 597                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 598                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 599                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 600
 601                 if (i == vsi->nb_qps - 1)
 602                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 603                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 604         }
 605
 606         /* Write first RX queue to Link list register as the head element */
 607         if (vsi->type != I40E_VSI_SRIOV) {
 608                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 609                         (vsi->base_queue << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 610                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 611
 612                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 613                                 msix_vect - 1), interval);
 614
 615                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 616                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 617                                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 618         }
 619         else {
 620                 uint32_t reg;
 621                 /* num_msix_vectors_vf needs to minus irq0 */
 622                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 623                         vsi->user_param + (msix_vect - 1);
 624
 625                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
 626                         (vsi->base_queue << I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 627                         (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 628         }
 629
 630         I40E_WRITE_FLUSH(hw);
 631 }
 632
 633 static void
 634 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 635 {
 636         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 637         uint16_t interval = i40e_calc_itr_interval(\
 638                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 639
 640         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 641                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 642                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 643                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 644                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 645 }
 646
 647 static void
 648 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 649 {
 650         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 651
 652         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 653 }
 654
 655 static int
 656 i40e_dev_start(struct rte_eth_dev *dev)
 657 {
 658         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 659         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 660         struct i40e_vsi *vsi = pf->main_vsi;
 661         int ret;
 662
 663         /* Initialize VSI */
 664         ret = i40e_vsi_init(vsi);
 665         if (ret != I40E_SUCCESS) {
 666                 PMD_DRV_LOG(ERR, "Failed to init VSI\n");
 667                 goto err_up;
 668         }
 669
 670         /* Map queues with MSIX interrupt */
 671         i40e_vsi_queues_bind_intr(vsi);
 672         i40e_vsi_enable_queues_intr(vsi);
 673
 674         /* Enable all queues which have been configured */
 675         ret = i40e_vsi_switch_queues(vsi, TRUE);
 676         if (ret != I40E_SUCCESS) {
 677                 PMD_DRV_LOG(ERR, "Failed to enable VSI\n");
 678                 goto err_up;
 679         }
 680
 681         /* Enable receiving broadcast packets */
 682         if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
 683                 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
 684                 if (ret != I40E_SUCCESS)
 685                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast\n");
 686         }
 687
 688         return I40E_SUCCESS;
 689
 690 err_up:
 691         i40e_vsi_switch_queues(vsi, FALSE);
 692         i40e_dev_clear_queues(dev);
 693
 694         return ret;
 695 }
 696
 697 static void
 698 i40e_dev_stop(struct rte_eth_dev *dev)
 699 {
 700         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 701         struct i40e_vsi *vsi = pf->main_vsi;
 702
 703         /* Disable all queues */
 704         i40e_vsi_switch_queues(vsi, FALSE);
 705
 706         /* Clear all queues and release memory */
 707         i40e_dev_clear_queues(dev);
 708
 709         /* un-map queues with interrupt registers */
 710         i40e_vsi_disable_queues_intr(vsi);
 711         i40e_vsi_queues_unbind_intr(vsi);
 712 }
 713
 714 static void
 715 i40e_dev_close(struct rte_eth_dev *dev)
 716 {
 717         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 719         uint32_t reg;
 720
 721         PMD_INIT_FUNC_TRACE();
 722
 723         i40e_dev_stop(dev);
 724
 725         /* Disable interrupt */
 726         i40e_pf_disable_irq0(hw);
 727         rte_intr_disable(&(dev->pci_dev->intr_handle));
 728
 729         /* shutdown and destroy the HMC */
 730         i40e_shutdown_lan_hmc(hw);
 731
 732         /* release all the existing VSIs and VEBs */
 733         i40e_vsi_release(pf->main_vsi);
 734
 735         /* shutdown the adminq */
 736         i40e_aq_queue_shutdown(hw, true);
 737         i40e_shutdown_adminq(hw);
 738
 739         i40e_res_pool_destroy(&pf->qp_pool);
 740         i40e_res_pool_destroy(&pf->msix_pool);
 741
 742         /* force a PF reset to clean anything leftover */
 743         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 744         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 745                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 746         I40E_WRITE_FLUSH(hw);
 747 }
 748
 749 static void
 750 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 751 {
 752         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 753         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 754         struct i40e_vsi *vsi = pf->main_vsi;
 755         int status;
 756
 757         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 758                                                         true, NULL);
 759         if (status != I40E_SUCCESS)
 760                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous\n");
 761 }
 762
 763 static void
 764 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
 765 {
 766         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 767         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 768         struct i40e_vsi *vsi = pf->main_vsi;
 769         int status;
 770
 771         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 772                                                         false, NULL);
 773         if (status != I40E_SUCCESS)
 774                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous\n");
 775 }
 776
 777 static void
 778 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
 779 {
 780         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 782         struct i40e_vsi *vsi = pf->main_vsi;
 783         int ret;
 784
 785         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
 786         if (ret != I40E_SUCCESS)
 787                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous\n");
 788 }
 789
 790 static void
 791 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
 792 {
 793         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 794         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 795         struct i40e_vsi *vsi = pf->main_vsi;
 796         int ret;
 797
 798         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
 799                                 vsi->seid, FALSE, NULL);
 800         if (ret != I40E_SUCCESS)
 801                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous\n");
 802 }
 803
 804 int
 805 i40e_dev_link_update(struct rte_eth_dev *dev,
 806                      __rte_unused int wait_to_complete)
 807 {
 808         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 809         struct i40e_link_status link_status;
 810         struct rte_eth_link link, old;
 811         int status;
 812
 813         memset(&link, 0, sizeof(link));
 814         memset(&old, 0, sizeof(old));
 815         memset(&link_status, 0, sizeof(link_status));
 816         rte_i40e_dev_atomic_read_link_status(dev, &old);
 817
 818         /* Get link status information from hardware */
 819         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
 820         if (status != I40E_SUCCESS) {
 821                 link.link_speed = ETH_LINK_SPEED_100;
 822                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
 823                 PMD_DRV_LOG(ERR, "Failed to get link info\n");
 824                 goto out;
 825         }
 826
 827         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
 828
 829         if (!link.link_status)
 830                 goto out;
 831
 832         /* i40e uses full duplex only */
 833         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 834
 835         /* Parse the link status */
 836         switch (link_status.link_speed) {
 837         case I40E_LINK_SPEED_100MB:
 838                 link.link_speed = ETH_LINK_SPEED_100;
 839                 break;
 840         case I40E_LINK_SPEED_1GB:
 841                 link.link_speed = ETH_LINK_SPEED_1000;
 842                 break;
 843         case I40E_LINK_SPEED_10GB:
 844                 link.link_speed = ETH_LINK_SPEED_10G;
 845                 break;
 846         case I40E_LINK_SPEED_20GB:
 847                 link.link_speed = ETH_LINK_SPEED_20G;
 848                 break;
 849         case I40E_LINK_SPEED_40GB:
 850                 link.link_speed = ETH_LINK_SPEED_40G;
 851                 break;
 852         default:
 853                 link.link_speed = ETH_LINK_SPEED_100;
 854                 break;
 855         }
 856
 857 out:
 858         rte_i40e_dev_atomic_write_link_status(dev, &link);
 859         if (link.link_status == old.link_status)
 860                 return -1;
 861
 862         return 0;
 863 }
 864
 865 /* Get all the statistics of a VSI */
 866 void
 867 i40e_update_vsi_stats(struct i40e_vsi *vsi)
 868 {
 869         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
 870         struct i40e_eth_stats *nes = &vsi->eth_stats;
 871         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 872         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
 873
 874         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
 875                             vsi->offset_loaded, &oes->rx_bytes,
 876                             &nes->rx_bytes);
 877         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
 878                             vsi->offset_loaded, &oes->rx_unicast,
 879                             &nes->rx_unicast);
 880         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
 881                             vsi->offset_loaded, &oes->rx_multicast,
 882                             &nes->rx_multicast);
 883         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
 884                             vsi->offset_loaded, &oes->rx_broadcast,
 885                             &nes->rx_broadcast);
 886         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
 887                             &oes->rx_discards, &nes->rx_discards);
 888         /* GLV_REPC not supported */
 889         /* GLV_RMPC not supported */
 890         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
 891                             &oes->rx_unknown_protocol,
 892                             &nes->rx_unknown_protocol);
 893         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
 894                             vsi->offset_loaded, &oes->tx_bytes,
 895                             &nes->tx_bytes);
 896         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
 897                             vsi->offset_loaded, &oes->tx_unicast,
 898                             &nes->tx_unicast);
 899         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
 900                             vsi->offset_loaded, &oes->tx_multicast,
 901                             &nes->tx_multicast);
 902         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
 903                             vsi->offset_loaded,  &oes->tx_broadcast,
 904                             &nes->tx_broadcast);
 905         /* GLV_TDPC not supported */
 906         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
 907                             &oes->tx_errors, &nes->tx_errors);
 908         vsi->offset_loaded = true;
 909
 910 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
 911         printf("***************** VSI[%u] stats start *******************\n",
 912                                                                 vsi->vsi_id);
 913         printf("rx_bytes:            %lu\n", nes->rx_bytes);
 914         printf("rx_unicast:          %lu\n", nes->rx_unicast);
 915         printf("rx_multicast:        %lu\n", nes->rx_multicast);
 916         printf("rx_broadcast:        %lu\n", nes->rx_broadcast);
 917         printf("rx_discards:         %lu\n", nes->rx_discards);
 918         printf("rx_unknown_protocol: %lu\n", nes->rx_unknown_protocol);
 919         printf("tx_bytes:            %lu\n", nes->tx_bytes);
 920         printf("tx_unicast:          %lu\n", nes->tx_unicast);
 921         printf("tx_multicast:        %lu\n", nes->tx_multicast);
 922         printf("tx_broadcast:        %lu\n", nes->tx_broadcast);
 923         printf("tx_discards:         %lu\n", nes->tx_discards);
 924         printf("tx_errors:           %lu\n", nes->tx_errors);
 925         printf("***************** VSI[%u] stats end *******************\n",
 926                                                                 vsi->vsi_id);
 927 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
 928 }
 929
 930 /* Get all statistics of a port */
 931 static void
 932 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 933 {
 934         uint32_t i;
 935         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 936         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 937         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
 938         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
 939
 940         /* Get statistics of struct i40e_eth_stats */
 941         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
 942                             I40E_GLPRT_GORCL(hw->port),
 943                             pf->offset_loaded, &os->eth.rx_bytes,
 944                             &ns->eth.rx_bytes);
 945         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
 946                             I40E_GLPRT_UPRCL(hw->port),
 947                             pf->offset_loaded, &os->eth.rx_unicast,
 948                             &ns->eth.rx_unicast);
 949         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
 950                             I40E_GLPRT_MPRCL(hw->port),
 951                             pf->offset_loaded, &os->eth.rx_multicast,
 952                             &ns->eth.rx_multicast);
 953         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
 954                             I40E_GLPRT_BPRCL(hw->port),
 955                             pf->offset_loaded, &os->eth.rx_broadcast,
 956                             &ns->eth.rx_broadcast);
 957         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
 958                             pf->offset_loaded, &os->eth.rx_discards,
 959                             &ns->eth.rx_discards);
 960         /* GLPRT_REPC not supported */
 961         /* GLPRT_RMPC not supported */
 962         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
 963                             pf->offset_loaded,
 964                             &os->eth.rx_unknown_protocol,
 965                             &ns->eth.rx_unknown_protocol);
 966         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
 967                             I40E_GLPRT_GOTCL(hw->port),
 968                             pf->offset_loaded, &os->eth.tx_bytes,
 969                             &ns->eth.tx_bytes);
 970         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
 971                             I40E_GLPRT_UPTCL(hw->port),
 972                             pf->offset_loaded, &os->eth.tx_unicast,
 973                             &ns->eth.tx_unicast);
 974         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
 975                             I40E_GLPRT_MPTCL(hw->port),
 976                             pf->offset_loaded, &os->eth.tx_multicast,
 977                             &ns->eth.tx_multicast);
 978         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
 979                             I40E_GLPRT_BPTCL(hw->port),
 980                             pf->offset_loaded, &os->eth.tx_broadcast,
 981                             &ns->eth.tx_broadcast);
 982         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
 983                             pf->offset_loaded, &os->eth.tx_discards,
 984                             &ns->eth.tx_discards);
 985         /* GLPRT_TEPC not supported */
 986
 987         /* additional port specific stats */
 988         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
 989                             pf->offset_loaded, &os->tx_dropped_link_down,
 990                             &ns->tx_dropped_link_down);
 991         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
 992                             pf->offset_loaded, &os->crc_errors,
 993                             &ns->crc_errors);
 994         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
 995                             pf->offset_loaded, &os->illegal_bytes,
 996                             &ns->illegal_bytes);
 997         /* GLPRT_ERRBC not supported */
 998         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
 999                             pf->offset_loaded, &os->mac_local_faults,
1000                             &ns->mac_local_faults);
1001         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1002                             pf->offset_loaded, &os->mac_remote_faults,
1003                             &ns->mac_remote_faults);
1004         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1005                             pf->offset_loaded, &os->rx_length_errors,
1006                             &ns->rx_length_errors);
1007         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1008                             pf->offset_loaded, &os->link_xon_rx,
1009                             &ns->link_xon_rx);
1010         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1011                             pf->offset_loaded, &os->link_xoff_rx,
1012                             &ns->link_xoff_rx);
1013         for (i = 0; i < 8; i++) {
1014                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1015                                     pf->offset_loaded,
1016                                     &os->priority_xon_rx[i],
1017                                     &ns->priority_xon_rx[i]);
1018                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1019                                     pf->offset_loaded,
1020                                     &os->priority_xoff_rx[i],
1021                                     &ns->priority_xoff_rx[i]);
1022         }
1023         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1024                             pf->offset_loaded, &os->link_xon_tx,
1025                             &ns->link_xon_tx);
1026         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1027                             pf->offset_loaded, &os->link_xoff_tx,
1028                             &ns->link_xoff_tx);
1029         for (i = 0; i < 8; i++) {
1030                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1031                                     pf->offset_loaded,
1032                                     &os->priority_xon_tx[i],
1033                                     &ns->priority_xon_tx[i]);
1034                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1035                                     pf->offset_loaded,
1036                                     &os->priority_xoff_tx[i],
1037                                     &ns->priority_xoff_tx[i]);
1038                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1039                                     pf->offset_loaded,
1040                                     &os->priority_xon_2_xoff[i],
1041                                     &ns->priority_xon_2_xoff[i]);
1042         }
1043         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1044                             I40E_GLPRT_PRC64L(hw->port),
1045                             pf->offset_loaded, &os->rx_size_64,
1046                             &ns->rx_size_64);
1047         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1048                             I40E_GLPRT_PRC127L(hw->port),
1049                             pf->offset_loaded, &os->rx_size_127,
1050                             &ns->rx_size_127);
1051         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1052                             I40E_GLPRT_PRC255L(hw->port),
1053                             pf->offset_loaded, &os->rx_size_255,
1054                             &ns->rx_size_255);
1055         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1056                             I40E_GLPRT_PRC511L(hw->port),
1057                             pf->offset_loaded, &os->rx_size_511,
1058                             &ns->rx_size_511);
1059         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1060                             I40E_GLPRT_PRC1023L(hw->port),
1061                             pf->offset_loaded, &os->rx_size_1023,
1062                             &ns->rx_size_1023);
1063         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1064                             I40E_GLPRT_PRC1522L(hw->port),
1065                             pf->offset_loaded, &os->rx_size_1522,
1066                             &ns->rx_size_1522);
1067         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1068                             I40E_GLPRT_PRC9522L(hw->port),
1069                             pf->offset_loaded, &os->rx_size_big,
1070                             &ns->rx_size_big);
1071         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1072                             pf->offset_loaded, &os->rx_undersize,
1073                             &ns->rx_undersize);
1074         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1075                             pf->offset_loaded, &os->rx_fragments,
1076                             &ns->rx_fragments);
1077         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1078                             pf->offset_loaded, &os->rx_oversize,
1079                             &ns->rx_oversize);
1080         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1081                             pf->offset_loaded, &os->rx_jabber,
1082                             &ns->rx_jabber);
1083         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1084                             I40E_GLPRT_PTC64L(hw->port),
1085                             pf->offset_loaded, &os->tx_size_64,
1086                             &ns->tx_size_64);
1087         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1088                             I40E_GLPRT_PTC127L(hw->port),
1089                             pf->offset_loaded, &os->tx_size_127,
1090                             &ns->tx_size_127);
1091         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1092                             I40E_GLPRT_PTC255L(hw->port),
1093                             pf->offset_loaded, &os->tx_size_255,
1094                             &ns->tx_size_255);
1095         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1096                             I40E_GLPRT_PTC511L(hw->port),
1097                             pf->offset_loaded, &os->tx_size_511,
1098                             &ns->tx_size_511);
1099         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1100                             I40E_GLPRT_PTC1023L(hw->port),
1101                             pf->offset_loaded, &os->tx_size_1023,
1102                             &ns->tx_size_1023);
1103         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1104                             I40E_GLPRT_PTC1522L(hw->port),
1105                             pf->offset_loaded, &os->tx_size_1522,
1106                             &ns->tx_size_1522);
1107         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1108                             I40E_GLPRT_PTC9522L(hw->port),
1109                             pf->offset_loaded, &os->tx_size_big,
1110                             &ns->tx_size_big);
1111         /* GLPRT_MSPDC not supported */
1112         /* GLPRT_XEC not supported */
1113
1114         pf->offset_loaded = true;
1115
1116         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1117                                                 ns->eth.rx_broadcast;
1118         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1119                                                 ns->eth.tx_broadcast;
1120         stats->ibytes   = ns->eth.rx_bytes;
1121         stats->obytes   = ns->eth.tx_bytes;
1122         stats->oerrors  = ns->eth.tx_errors;
1123         stats->imcasts  = ns->eth.rx_multicast;
1124
1125         if (pf->main_vsi)
1126                 i40e_update_vsi_stats(pf->main_vsi);
1127
1128 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
1129         printf("***************** PF stats start *******************\n");
1130         printf("rx_bytes:            %lu\n", ns->eth.rx_bytes);
1131         printf("rx_unicast:          %lu\n", ns->eth.rx_unicast);
1132         printf("rx_multicast:        %lu\n", ns->eth.rx_multicast);
1133         printf("rx_broadcast:        %lu\n", ns->eth.rx_broadcast);
1134         printf("rx_discards:         %lu\n", ns->eth.rx_discards);
1135         printf("rx_unknown_protocol: %lu\n", ns->eth.rx_unknown_protocol);
1136         printf("tx_bytes:            %lu\n", ns->eth.tx_bytes);
1137         printf("tx_unicast:          %lu\n", ns->eth.tx_unicast);
1138         printf("tx_multicast:        %lu\n", ns->eth.tx_multicast);
1139         printf("tx_broadcast:        %lu\n", ns->eth.tx_broadcast);
1140         printf("tx_discards:         %lu\n", ns->eth.tx_discards);
1141         printf("tx_errors:           %lu\n", ns->eth.tx_errors);
1142
1143         printf("tx_dropped_link_down:     %lu\n", ns->tx_dropped_link_down);
1144         printf("crc_errors:               %lu\n", ns->crc_errors);
1145         printf("illegal_bytes:            %lu\n", ns->illegal_bytes);
1146         printf("error_bytes:              %lu\n", ns->error_bytes);
1147         printf("mac_local_faults:         %lu\n", ns->mac_local_faults);
1148         printf("mac_remote_faults:        %lu\n", ns->mac_remote_faults);
1149         printf("rx_length_errors:         %lu\n", ns->rx_length_errors);
1150         printf("link_xon_rx:              %lu\n", ns->link_xon_rx);
1151         printf("link_xoff_rx:             %lu\n", ns->link_xoff_rx);
1152         for (i = 0; i < 8; i++) {
1153                 printf("priority_xon_rx[%d]:      %lu\n",
1154                                 i, ns->priority_xon_rx[i]);
1155                 printf("priority_xoff_rx[%d]:     %lu\n",
1156                                 i, ns->priority_xoff_rx[i]);
1157         }
1158         printf("link_xon_tx:              %lu\n", ns->link_xon_tx);
1159         printf("link_xoff_tx:             %lu\n", ns->link_xoff_tx);
1160         for (i = 0; i < 8; i++) {
1161                 printf("priority_xon_tx[%d]:      %lu\n",
1162                                 i, ns->priority_xon_tx[i]);
1163                 printf("priority_xoff_tx[%d]:     %lu\n",
1164                                 i, ns->priority_xoff_tx[i]);
1165                 printf("priority_xon_2_xoff[%d]:  %lu\n",
1166                                 i, ns->priority_xon_2_xoff[i]);
1167         }
1168         printf("rx_size_64:               %lu\n", ns->rx_size_64);
1169         printf("rx_size_127:              %lu\n", ns->rx_size_127);
1170         printf("rx_size_255:              %lu\n", ns->rx_size_255);
1171         printf("rx_size_511:              %lu\n", ns->rx_size_511);
1172         printf("rx_size_1023:             %lu\n", ns->rx_size_1023);
1173         printf("rx_size_1522:             %lu\n", ns->rx_size_1522);
1174         printf("rx_size_big:              %lu\n", ns->rx_size_big);
1175         printf("rx_undersize:             %lu\n", ns->rx_undersize);
1176         printf("rx_fragments:             %lu\n", ns->rx_fragments);
1177         printf("rx_oversize:              %lu\n", ns->rx_oversize);
1178         printf("rx_jabber:                %lu\n", ns->rx_jabber);
1179         printf("tx_size_64:               %lu\n", ns->tx_size_64);
1180         printf("tx_size_127:              %lu\n", ns->tx_size_127);
1181         printf("tx_size_255:              %lu\n", ns->tx_size_255);
1182         printf("tx_size_511:              %lu\n", ns->tx_size_511);
1183         printf("tx_size_1023:             %lu\n", ns->tx_size_1023);
1184         printf("tx_size_1522:             %lu\n", ns->tx_size_1522);
1185         printf("tx_size_big:              %lu\n", ns->tx_size_big);
1186         printf("mac_short_packet_dropped: %lu\n",
1187                         ns->mac_short_packet_dropped);
1188         printf("checksum_error:           %lu\n", ns->checksum_error);
1189         printf("***************** PF stats end ********************\n");
1190 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
1191 }
1192
1193 /* Reset the statistics */
1194 static void
1195 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1196 {
1197         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1198
1199         /* It results in reloading the start point of each counter */
1200         pf->offset_loaded = false;
1201 }
1202
1203 static int
1204 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1205                                  __rte_unused uint16_t queue_id,
1206                                  __rte_unused uint8_t stat_idx,
1207                                  __rte_unused uint8_t is_rx)
1208 {
1209         PMD_INIT_FUNC_TRACE();
1210
1211         return -ENOSYS;
1212 }
1213
1214 static void
1215 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1216 {
1217         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1218         struct i40e_vsi *vsi = pf->main_vsi;
1219
1220         dev_info->max_rx_queues = vsi->nb_qps;
1221         dev_info->max_tx_queues = vsi->nb_qps;
1222         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1223         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1224         dev_info->max_mac_addrs = vsi->max_macaddrs;
1225         dev_info->max_vfs = dev->pci_dev->max_vfs;
1226         dev_info->rx_offload_capa =
1227                 DEV_RX_OFFLOAD_VLAN_STRIP |
1228                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1229                 DEV_RX_OFFLOAD_UDP_CKSUM |
1230                 DEV_RX_OFFLOAD_TCP_CKSUM;
1231         dev_info->tx_offload_capa =
1232                 DEV_TX_OFFLOAD_VLAN_INSERT |
1233                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1234                 DEV_TX_OFFLOAD_UDP_CKSUM |
1235                 DEV_TX_OFFLOAD_TCP_CKSUM |
1236                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1237 }
1238
1239 static int
1240 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1241 {
1242         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1243         struct i40e_vsi *vsi = pf->main_vsi;
1244         PMD_INIT_FUNC_TRACE();
1245
1246         if (on)
1247                 return i40e_vsi_add_vlan(vsi, vlan_id);
1248         else
1249                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1250 }
1251
1252 static void
1253 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1254                    __rte_unused uint16_t tpid)
1255 {
1256         PMD_INIT_FUNC_TRACE();
1257 }
1258
1259 static void
1260 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1261 {
1262         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1263         struct i40e_vsi *vsi = pf->main_vsi;
1264
1265         if (mask & ETH_VLAN_STRIP_MASK) {
1266                 /* Enable or disable VLAN stripping */
1267                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1268                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1269                 else
1270                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1271         }
1272
1273         if (mask & ETH_VLAN_EXTEND_MASK) {
1274                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1275                         i40e_vsi_config_double_vlan(vsi, TRUE);
1276                 else
1277                         i40e_vsi_config_double_vlan(vsi, FALSE);
1278         }
1279 }
1280
1281 static void
1282 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1283                           __rte_unused uint16_t queue,
1284                           __rte_unused int on)
1285 {
1286         PMD_INIT_FUNC_TRACE();
1287 }
1288
1289 static int
1290 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1291 {
1292         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1293         struct i40e_vsi *vsi = pf->main_vsi;
1294         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1295         struct i40e_vsi_vlan_pvid_info info;
1296
1297         memset(&info, 0, sizeof(info));
1298         info.on = on;
1299         if (info.on)
1300                 info.config.pvid = pvid;
1301         else {
1302                 info.config.reject.tagged =
1303                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1304                 info.config.reject.untagged =
1305                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1306         }
1307
1308         return i40e_vsi_vlan_pvid_set(vsi, &info);
1309 }
1310
1311 static int
1312 i40e_dev_led_on(struct rte_eth_dev *dev)
1313 {
1314         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1315         uint32_t mode = i40e_led_get(hw);
1316
1317         if (mode == 0)
1318                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1319
1320         return 0;
1321 }
1322
1323 static int
1324 i40e_dev_led_off(struct rte_eth_dev *dev)
1325 {
1326         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1327         uint32_t mode = i40e_led_get(hw);
1328
1329         if (mode != 0)
1330                 i40e_led_set(hw, 0, false);
1331
1332         return 0;
1333 }
1334
1335 static int
1336 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1337                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1338 {
1339         PMD_INIT_FUNC_TRACE();
1340
1341         return -ENOSYS;
1342 }
1343
1344 static int
1345 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1346                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1347 {
1348         PMD_INIT_FUNC_TRACE();
1349
1350         return -ENOSYS;
1351 }
1352
1353 /* Add a MAC address, and update filters */
1354 static void
1355 i40e_macaddr_add(struct rte_eth_dev *dev,
1356                  struct ether_addr *mac_addr,
1357                  __attribute__((unused)) uint32_t index,
1358                  __attribute__((unused)) uint32_t pool)
1359 {
1360         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1361         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1362         struct i40e_vsi *vsi = pf->main_vsi;
1363         struct ether_addr old_mac;
1364         int ret;
1365
1366         if (!is_valid_assigned_ether_addr(mac_addr)) {
1367                 PMD_DRV_LOG(ERR, "Invalid ethernet address\n");
1368                 return;
1369         }
1370
1371         if (is_same_ether_addr(mac_addr, &(pf->dev_addr))) {
1372                 PMD_DRV_LOG(INFO, "Ignore adding permanent mac address\n");
1373                 return;
1374         }
1375
1376         /* Write mac address */
1377         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1378                                         mac_addr->addr_bytes, NULL);
1379         if (ret != I40E_SUCCESS) {
1380                 PMD_DRV_LOG(ERR, "Failed to write mac address\n");
1381                 return;
1382         }
1383
1384         (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1385         (void)rte_memcpy(hw->mac.addr, mac_addr->addr_bytes,
1386                         ETHER_ADDR_LEN);
1387
1388         ret = i40e_vsi_add_mac(vsi, mac_addr);
1389         if (ret != I40E_SUCCESS) {
1390                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter\n");
1391                 return;
1392         }
1393
1394         ether_addr_copy(mac_addr, &pf->dev_addr);
1395         i40e_vsi_delete_mac(vsi, &old_mac);
1396 }
1397
1398 /* Remove a MAC address, and update filters */
1399 static void
1400 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1401 {
1402         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1403         struct i40e_vsi *vsi = pf->main_vsi;
1404         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1405         struct ether_addr *macaddr;
1406         int ret;
1407         struct i40e_hw *hw =
1408                 I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1409
1410         if (index >= vsi->max_macaddrs)
1411                 return;
1412
1413         macaddr = &(data->mac_addrs[index]);
1414         if (!is_valid_assigned_ether_addr(macaddr))
1415                 return;
1416
1417         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1418                                         hw->mac.perm_addr, NULL);
1419         if (ret != I40E_SUCCESS) {
1420                 PMD_DRV_LOG(ERR, "Failed to write mac address\n");
1421                 return;
1422         }
1423
1424         (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);
1425
1426         ret = i40e_vsi_delete_mac(vsi, macaddr);
1427         if (ret != I40E_SUCCESS)
1428                 return;
1429
1430         /* Clear device address as it has been removed */
1431         if (is_same_ether_addr(&(pf->dev_addr), macaddr))
1432                 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1433 }
1434
1435 static int
1436 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1437                          struct rte_eth_rss_reta *reta_conf)
1438 {
1439         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1440         uint32_t lut, l;
1441         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1442
1443         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1444                 if (i < max)
1445                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1446                 else
1447                         mask = (uint8_t)((reta_conf->mask_hi >>
1448                                                 (i - max)) & 0xF);
1449
1450                 if (!mask)
1451                         continue;
1452
1453                 if (mask == 0xF)
1454                         l = 0;
1455                 else
1456                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1457
1458                 for (j = 0, lut = 0; j < 4; j++) {
1459                         if (mask & (0x1 << j))
1460                                 lut |= reta_conf->reta[i + j] << (8 * j);
1461                         else
1462                                 lut |= l & (0xFF << (8 * j));
1463                 }
1464                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1465         }
1466
1467         return 0;
1468 }
1469
1470 static int
1471 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1472                         struct rte_eth_rss_reta *reta_conf)
1473 {
1474         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1475         uint32_t lut;
1476         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1477
1478         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1479                 if (i < max)
1480                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1481                 else
1482                         mask = (uint8_t)((reta_conf->mask_hi >>
1483                                                 (i - max)) & 0xF);
1484
1485                 if (!mask)
1486                         continue;
1487
1488                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1489                 for (j = 0; j < 4; j++) {
1490                         if (mask & (0x1 << j))
1491                                 reta_conf->reta[i + j] =
1492                                         (uint8_t)((lut >> (8 * j)) & 0xFF);
1493                 }
1494         }
1495
1496         return 0;
1497 }
1498
1499 /**
1500  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1501  * @hw:   pointer to the HW structure
1502  * @mem:  pointer to mem struct to fill out
1503  * @size: size of memory requested
1504  * @alignment: what to align the allocation to
1505  **/
1506 enum i40e_status_code
1507 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1508                         struct i40e_dma_mem *mem,
1509                         u64 size,
1510                         u32 alignment)
1511 {
1512         static uint64_t id = 0;
1513         const struct rte_memzone *mz = NULL;
1514         char z_name[RTE_MEMZONE_NAMESIZE];
1515
1516         if (!mem)
1517                 return I40E_ERR_PARAM;
1518
1519         id++;
1520         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1521         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1522         if (!mz)
1523                 return I40E_ERR_NO_MEMORY;
1524
1525         mem->id = id;
1526         mem->size = size;
1527         mem->va = mz->addr;
1528         mem->pa = mz->phys_addr;
1529
1530         return I40E_SUCCESS;
1531 }
1532
1533 /**
1534  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1535  * @hw:   pointer to the HW structure
1536  * @mem:  ptr to mem struct to free
1537  **/
1538 enum i40e_status_code
1539 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1540                     struct i40e_dma_mem *mem)
1541 {
1542         if (!mem || !mem->va)
1543                 return I40E_ERR_PARAM;
1544
1545         mem->va = NULL;
1546         mem->pa = (u64)0;
1547
1548         return I40E_SUCCESS;
1549 }
1550
1551 /**
1552  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1553  * @hw:   pointer to the HW structure
1554  * @mem:  pointer to mem struct to fill out
1555  * @size: size of memory requested
1556  **/
1557 enum i40e_status_code
1558 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1559                          struct i40e_virt_mem *mem,
1560                          u32 size)
1561 {
1562         if (!mem)
1563                 return I40E_ERR_PARAM;
1564
1565         mem->size = size;
1566         mem->va = rte_zmalloc("i40e", size, 0);
1567
1568         if (mem->va)
1569                 return I40E_SUCCESS;
1570         else
1571                 return I40E_ERR_NO_MEMORY;
1572 }
1573
1574 /**
1575  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1576  * @hw:   pointer to the HW structure
1577  * @mem:  pointer to mem struct to free
1578  **/
1579 enum i40e_status_code
1580 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1581                      struct i40e_virt_mem *mem)
1582 {
1583         if (!mem)
1584                 return I40E_ERR_PARAM;
1585
1586         rte_free(mem->va);
1587         mem->va = NULL;
1588
1589         return I40E_SUCCESS;
1590 }
1591
1592 void
1593 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1594 {
1595         rte_spinlock_init(&sp->spinlock);
1596 }
1597
1598 void
1599 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1600 {
1601         rte_spinlock_lock(&sp->spinlock);
1602 }
1603
1604 void
1605 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1606 {
1607         rte_spinlock_unlock(&sp->spinlock);
1608 }
1609
1610 void
1611 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1612 {
1613         return;
1614 }
1615
1616 /**
1617  * Get the hardware capabilities, which will be parsed
1618  * and saved into struct i40e_hw.
1619  */
1620 static int
1621 i40e_get_cap(struct i40e_hw *hw)
1622 {
1623         struct i40e_aqc_list_capabilities_element_resp *buf;
1624         uint16_t len, size = 0;
1625         int ret;
1626
1627         /* Calculate a huge enough buff for saving response data temporarily */
1628         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1629                                                 I40E_MAX_CAP_ELE_NUM;
1630         buf = rte_zmalloc("i40e", len, 0);
1631         if (!buf) {
1632                 PMD_DRV_LOG(ERR, "Failed to allocate memory\n");
1633                 return I40E_ERR_NO_MEMORY;
1634         }
1635
1636         /* Get, parse the capabilities and save it to hw */
1637         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1638                         i40e_aqc_opc_list_func_capabilities, NULL);
1639         if (ret != I40E_SUCCESS)
1640                 PMD_DRV_LOG(ERR, "Failed to discover capabilities\n");
1641
1642         /* Free the temporary buffer after being used */
1643         rte_free(buf);
1644
1645         return ret;
1646 }
1647
1648 static int
1649 i40e_pf_parameter_init(struct rte_eth_dev *dev)
1650 {
1651         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1652         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1653         uint16_t sum_queues = 0, sum_vsis;
1654
1655         /* First check if FW support SRIOV */
1656         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
1657                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV\n");
1658                 return -EINVAL;
1659         }
1660
1661         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
1662         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
1663         PMD_INIT_LOG(INFO, "Max supported VSIs:%u\n", pf->max_num_vsi);
1664         /* Allocate queues for pf */
1665         if (hw->func_caps.rss) {
1666                 pf->flags |= I40E_FLAG_RSS;
1667                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
1668                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
1669                 pf->lan_nb_qps = i40e_prev_power_of_2(pf->lan_nb_qps);
1670         } else
1671                 pf->lan_nb_qps = 1;
1672         sum_queues = pf->lan_nb_qps;
1673         /* Default VSI is not counted in */
1674         sum_vsis = 0;
1675         PMD_INIT_LOG(INFO, "PF queue pairs:%u\n", pf->lan_nb_qps);
1676
1677         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
1678                 pf->flags |= I40E_FLAG_SRIOV;
1679                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
1680                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
1681                         PMD_INIT_LOG(ERR, "Config VF number %u, "
1682                                 "max supported %u.\n", dev->pci_dev->max_vfs,
1683                                                 hw->func_caps.num_vfs);
1684                         return -EINVAL;
1685                 }
1686                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
1687                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
1688                                 "max support %u queues.\n", pf->vf_nb_qps,
1689                                                 I40E_MAX_QP_NUM_PER_VF);
1690                         return -EINVAL;
1691                 }
1692                 pf->vf_num = dev->pci_dev->max_vfs;
1693                 sum_queues += pf->vf_nb_qps * pf->vf_num;
1694                 sum_vsis   += pf->vf_num;
1695                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u\n",
1696                                                 pf->vf_num, pf->vf_nb_qps);
1697         } else
1698                 pf->vf_num = 0;
1699
1700         if (hw->func_caps.vmdq) {
1701                 pf->flags |= I40E_FLAG_VMDQ;
1702                 pf->vmdq_nb_qps = I40E_DEFAULT_QP_NUM_VMDQ;
1703                 sum_queues += pf->vmdq_nb_qps;
1704                 sum_vsis += 1;
1705                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u\n", pf->vmdq_nb_qps);
1706         }
1707
1708         if (hw->func_caps.fd) {
1709                 pf->flags |= I40E_FLAG_FDIR;
1710                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
1711                 /**
1712                  * Each flow director consumes one VSI and one queue,
1713                  * but can't calculate out predictably here.
1714                  */
1715         }
1716
1717         if (sum_vsis > pf->max_num_vsi ||
1718                 sum_queues > hw->func_caps.num_rx_qp) {
1719                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied\n");
1720                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u\n",
1721                                 pf->max_num_vsi, sum_vsis);
1722                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u\n",
1723                                 hw->func_caps.num_rx_qp, sum_queues);
1724                 return -EINVAL;
1725         }
1726
1727         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr cause */
1728         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
1729                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough\n",
1730                                 sum_vsis, hw->func_caps.num_msix_vectors);
1731                 return -EINVAL;
1732         }
1733         return I40E_SUCCESS;
1734 }
1735
1736 static int
1737 i40e_pf_get_switch_config(struct i40e_pf *pf)
1738 {
1739         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1740         struct i40e_aqc_get_switch_config_resp *switch_config;
1741         struct i40e_aqc_switch_config_element_resp *element;
1742         uint16_t start_seid = 0, num_reported;
1743         int ret;
1744
1745         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
1746                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
1747         if (!switch_config) {
1748                 PMD_DRV_LOG(ERR, "Failed to allocated memory\n");
1749                 return -ENOMEM;
1750         }
1751
1752         /* Get the switch configurations */
1753         ret = i40e_aq_get_switch_config(hw, switch_config,
1754                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
1755         if (ret != I40E_SUCCESS) {
1756                 PMD_DRV_LOG(ERR, "Failed to get switch configurations\n");
1757                 goto fail;
1758         }
1759         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
1760         if (num_reported != 1) { /* The number should be 1 */
1761                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported\n");
1762                 goto fail;
1763         }
1764
1765         /* Parse the switch configuration elements */
1766         element = &(switch_config->element[0]);
1767         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
1768                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
1769                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
1770         } else
1771                 PMD_DRV_LOG(INFO, "Unknown element type\n");
1772
1773 fail:
1774         rte_free(switch_config);
1775
1776         return ret;
1777 }
1778
1779 static int
1780 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
1781                         uint32_t num)
1782 {
1783         struct pool_entry *entry;
1784
1785         if (pool == NULL || num == 0)
1786                 return -EINVAL;
1787
1788         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
1789         if (entry == NULL) {
1790                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1791                                                 "resource pool\n");
1792                 return -ENOMEM;
1793         }
1794
1795         /* queue heap initialize */
1796         pool->num_free = num;
1797         pool->num_alloc = 0;
1798         pool->base = base;
1799         LIST_INIT(&pool->alloc_list);
1800         LIST_INIT(&pool->free_list);
1801
1802         /* Initialize element  */
1803         entry->base = 0;
1804         entry->len = num;
1805
1806         LIST_INSERT_HEAD(&pool->free_list, entry, next);
1807         return 0;
1808 }
1809
1810 static void
1811 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
1812 {
1813         struct pool_entry *entry;
1814
1815         if (pool == NULL)
1816                 return;
1817
1818         LIST_FOREACH(entry, &pool->alloc_list, next) {
1819                 LIST_REMOVE(entry, next);
1820                 rte_free(entry);
1821         }
1822
1823         LIST_FOREACH(entry, &pool->free_list, next) {
1824                 LIST_REMOVE(entry, next);
1825                 rte_free(entry);
1826         }
1827
1828         pool->num_free = 0;
1829         pool->num_alloc = 0;
1830         pool->base = 0;
1831         LIST_INIT(&pool->alloc_list);
1832         LIST_INIT(&pool->free_list);
1833 }
1834
1835 static int
1836 i40e_res_pool_free(struct i40e_res_pool_info *pool,
1837                        uint32_t base)
1838 {
1839         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
1840         uint32_t pool_offset;
1841         int insert;
1842
1843         if (pool == NULL) {
1844                 PMD_DRV_LOG(ERR, "Invalid parameter\n");
1845                 return -EINVAL;
1846         }
1847
1848         pool_offset = base - pool->base;
1849         /* Lookup in alloc list */
1850         LIST_FOREACH(entry, &pool->alloc_list, next) {
1851                 if (entry->base == pool_offset) {
1852                         valid_entry = entry;
1853                         LIST_REMOVE(entry, next);
1854                         break;
1855                 }
1856         }
1857
1858         /* Not find, return */
1859         if (valid_entry == NULL) {
1860                 PMD_DRV_LOG(ERR, "Failed to find entry\n");
1861                 return -EINVAL;
1862         }
1863
1864         /**
1865          * Found it, move it to free list  and try to merge.
1866          * In order to make merge easier, always sort it by qbase.
1867          * Find adjacent prev and last entries.
1868          */
1869         prev = next = NULL;
1870         LIST_FOREACH(entry, &pool->free_list, next) {
1871                 if (entry->base > valid_entry->base) {
1872                         next = entry;
1873                         break;
1874                 }
1875                 prev = entry;
1876         }
1877
1878         insert = 0;
1879         /* Try to merge with next one*/
1880         if (next != NULL) {
1881                 /* Merge with next one */
1882                 if (valid_entry->base + valid_entry->len == next->base) {
1883                         next->base = valid_entry->base;
1884                         next->len += valid_entry->len;
1885                         rte_free(valid_entry);
1886                         valid_entry = next;
1887                         insert = 1;
1888                 }
1889         }
1890
1891         if (prev != NULL) {
1892                 /* Merge with previous one */
1893                 if (prev->base + prev->len == valid_entry->base) {
1894                         prev->len += valid_entry->len;
1895                         /* If it merge with next one, remove next node */
1896                         if (insert == 1) {
1897                                 LIST_REMOVE(valid_entry, next);
1898                                 rte_free(valid_entry);
1899                         } else {
1900                                 rte_free(valid_entry);
1901                                 insert = 1;
1902                         }
1903                 }
1904         }
1905
1906         /* Not find any entry to merge, insert */
1907         if (insert == 0) {
1908                 if (prev != NULL)
1909                         LIST_INSERT_AFTER(prev, valid_entry, next);
1910                 else if (next != NULL)
1911                         LIST_INSERT_BEFORE(next, valid_entry, next);
1912                 else /* It's empty list, insert to head */
1913                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
1914         }
1915
1916         pool->num_free += valid_entry->len;
1917         pool->num_alloc -= valid_entry->len;
1918
1919         return 0;
1920 }
1921
1922 static int
1923 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
1924                        uint16_t num)
1925 {
1926         struct pool_entry *entry, *valid_entry;
1927
1928         if (pool == NULL || num == 0) {
1929                 PMD_DRV_LOG(ERR, "Invalid parameter\n");
1930                 return -EINVAL;
1931         }
1932
1933         if (pool->num_free < num) {
1934                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u\n",
1935                                 num, pool->num_free);
1936                 return -ENOMEM;
1937         }
1938
1939         valid_entry = NULL;
1940         /* Lookup  in free list and find most fit one */
1941         LIST_FOREACH(entry, &pool->free_list, next) {
1942                 if (entry->len >= num) {
1943                         /* Find best one */
1944                         if (entry->len == num) {
1945                                 valid_entry = entry;
1946                                 break;
1947                         }
1948                         if (valid_entry == NULL || valid_entry->len > entry->len)
1949                                 valid_entry = entry;
1950                 }
1951         }
1952
1953         /* Not find one to satisfy the request, return */
1954         if (valid_entry == NULL) {
1955                 PMD_DRV_LOG(ERR, "No valid entry found\n");
1956                 return -ENOMEM;
1957         }
1958         /**
1959          * The entry have equal queue number as requested,
1960          * remove it from alloc_list.
1961          */
1962         if (valid_entry->len == num) {
1963                 LIST_REMOVE(valid_entry, next);
1964         } else {
1965                 /**
1966                  * The entry have more numbers than requested,
1967                  * create a new entry for alloc_list and minus its
1968                  * queue base and number in free_list.
1969                  */
1970                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
1971                 if (entry == NULL) {
1972                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1973                                         "resource pool\n");
1974                         return -ENOMEM;
1975                 }
1976                 entry->base = valid_entry->base;
1977                 entry->len = num;
1978                 valid_entry->base += num;
1979                 valid_entry->len -= num;
1980                 valid_entry = entry;
1981         }
1982
1983         /* Insert it into alloc list, not sorted */
1984         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
1985
1986         pool->num_free -= valid_entry->len;
1987         pool->num_alloc += valid_entry->len;
1988
1989         return (valid_entry->base + pool->base);
1990 }
1991
1992 /**
1993  * bitmap_is_subset - Check whether src2 is subset of src1
1994  **/
1995 static inline int
1996 bitmap_is_subset(uint8_t src1, uint8_t src2)
1997 {
1998         return !((src1 ^ src2) & src2);
1999 }
2000
2001 static int
2002 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2003 {
2004         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2005
2006         /* If DCB is not supported, only default TC is supported */
2007         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2008                 PMD_DRV_LOG(ERR, "DCB is not enabled, "
2009                                 "only TC0 is supported\n");
2010                 return -EINVAL;
2011         }
2012
2013         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2014                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2015                         "HW support 0x%x\n", hw->func_caps.enabled_tcmap,
2016                                                         enabled_tcmap);
2017                 return -EINVAL;
2018         }
2019         return I40E_SUCCESS;
2020 }
2021
2022 int
2023 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2024                                 struct i40e_vsi_vlan_pvid_info *info)
2025 {
2026         struct i40e_hw *hw;
2027         struct i40e_vsi_context ctxt;
2028         uint8_t vlan_flags = 0;
2029         int ret;
2030
2031         if (vsi == NULL || info == NULL) {
2032                 PMD_DRV_LOG(ERR, "invalid parameters\n");
2033                 return I40E_ERR_PARAM;
2034         }
2035
2036         if (info->on) {
2037                 vsi->info.pvid = info->config.pvid;
2038                 /**
2039                  * If insert pvid is enabled, only tagged pkts are
2040                  * allowed to be sent out.
2041                  */
2042                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2043                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2044         } else {
2045                 vsi->info.pvid = 0;
2046                 if (info->config.reject.tagged == 0)
2047                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2048
2049                 if (info->config.reject.untagged == 0)
2050                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2051         }
2052         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2053                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2054         vsi->info.port_vlan_flags |= vlan_flags;
2055         vsi->info.valid_sections =
2056                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2057         memset(&ctxt, 0, sizeof(ctxt));
2058         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2059         ctxt.seid = vsi->seid;
2060
2061         hw = I40E_VSI_TO_HW(vsi);
2062         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2063         if (ret != I40E_SUCCESS)
2064                 PMD_DRV_LOG(ERR, "Failed to update VSI params\n");
2065
2066         return ret;
2067 }
2068
2069 static int
2070 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2071 {
2072         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2073         int i, ret;
2074         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2075
2076         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2077         if (ret != I40E_SUCCESS)
2078                 return ret;
2079
2080         if (!vsi->seid) {
2081                 PMD_DRV_LOG(ERR, "seid not valid\n");
2082                 return -EINVAL;
2083         }
2084
2085         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2086         tc_bw_data.tc_valid_bits = enabled_tcmap;
2087         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2088                 tc_bw_data.tc_bw_credits[i] =
2089                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2090
2091         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2092         if (ret != I40E_SUCCESS) {
2093                 PMD_DRV_LOG(ERR, "Failed to configure TC BW\n");
2094                 return ret;
2095         }
2096
2097         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2098                                         sizeof(vsi->info.qs_handle));
2099         return I40E_SUCCESS;
2100 }
2101
2102 static int
2103 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2104                                  struct i40e_aqc_vsi_properties_data *info,
2105                                  uint8_t enabled_tcmap)
2106 {
2107         int ret, total_tc = 0, i;
2108         uint16_t qpnum_per_tc, bsf, qp_idx;
2109
2110         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2111         if (ret != I40E_SUCCESS)
2112                 return ret;
2113
2114         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2115                 if (enabled_tcmap & (1 << i))
2116                         total_tc++;
2117         vsi->enabled_tc = enabled_tcmap;
2118
2119         /* Number of queues per enabled TC */
2120         qpnum_per_tc = i40e_prev_power_of_2(vsi->nb_qps / total_tc);
2121         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2122         bsf = rte_bsf32(qpnum_per_tc);
2123
2124         /* Adjust the queue number to actual queues that can be applied */
2125         vsi->nb_qps = qpnum_per_tc * total_tc;
2126
2127         /**
2128          * Configure TC and queue mapping parameters, for enabled TC,
2129          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2130          * default queue will serve it.
2131          */
2132         qp_idx = 0;
2133         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2134                 if (vsi->enabled_tc & (1 << i)) {
2135                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2136                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2137                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2138                         qp_idx += qpnum_per_tc;
2139                 } else
2140                         info->tc_mapping[i] = 0;
2141         }
2142
2143         /* Associate queue number with VSI */
2144         if (vsi->type == I40E_VSI_SRIOV) {
2145                 info->mapping_flags |=
2146                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2147                 for (i = 0; i < vsi->nb_qps; i++)
2148                         info->queue_mapping[i] =
2149                                 rte_cpu_to_le_16(vsi->base_queue + i);
2150         } else {
2151                 info->mapping_flags |=
2152                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2153                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2154         }
2155         info->valid_sections =
2156                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2157
2158         return I40E_SUCCESS;
2159 }
2160
2161 static int
2162 i40e_veb_release(struct i40e_veb *veb)
2163 {
2164         struct i40e_vsi *vsi;
2165         struct i40e_hw *hw;
2166
2167         if (veb == NULL || veb->associate_vsi == NULL)
2168                 return -EINVAL;
2169
2170         if (!TAILQ_EMPTY(&veb->head)) {
2171                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove\n");
2172                 return -EACCES;
2173         }
2174
2175         vsi = veb->associate_vsi;
2176         hw = I40E_VSI_TO_HW(vsi);
2177
2178         vsi->uplink_seid = veb->uplink_seid;
2179         i40e_aq_delete_element(hw, veb->seid, NULL);
2180         rte_free(veb);
2181         vsi->veb = NULL;
2182         return I40E_SUCCESS;
2183 }
2184
2185 /* Setup a veb */
2186 static struct i40e_veb *
2187 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2188 {
2189         struct i40e_veb *veb;
2190         int ret;
2191         struct i40e_hw *hw;
2192
2193         if (NULL == pf || vsi == NULL) {
2194                 PMD_DRV_LOG(ERR, "veb setup failed, "
2195                         "associated VSI shouldn't null\n");
2196                 return NULL;
2197         }
2198         hw = I40E_PF_TO_HW(pf);
2199
2200         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2201         if (!veb) {
2202                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb\n");
2203                 goto fail;
2204         }
2205
2206         veb->associate_vsi = vsi;
2207         TAILQ_INIT(&veb->head);
2208         veb->uplink_seid = vsi->uplink_seid;
2209
2210         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2211                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2212
2213         if (ret != I40E_SUCCESS) {
2214                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d\n",
2215                                         hw->aq.asq_last_status);
2216                 goto fail;
2217         }
2218
2219         /* get statistics index */
2220         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2221                                 &veb->stats_idx, NULL, NULL, NULL);
2222         if (ret != I40E_SUCCESS) {
2223                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d\n",
2224                                                 hw->aq.asq_last_status);
2225                 goto fail;
2226         }
2227
2228         /* Get VEB bandwidth, to be implemented */
2229         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2230         vsi->uplink_seid = veb->seid;
2231
2232         return veb;
2233 fail:
2234         rte_free(veb);
2235         return NULL;
2236 }
2237
2238 int
2239 i40e_vsi_release(struct i40e_vsi *vsi)
2240 {
2241         struct i40e_pf *pf;
2242         struct i40e_hw *hw;
2243         struct i40e_vsi_list *vsi_list;
2244         int ret;
2245         struct i40e_mac_filter *f;
2246
2247         if (!vsi)
2248                 return I40E_SUCCESS;
2249
2250         pf = I40E_VSI_TO_PF(vsi);
2251         hw = I40E_VSI_TO_HW(vsi);
2252
2253         /* VSI has child to attach, release child first */
2254         if (vsi->veb) {
2255                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2256                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2257                                 return -1;
2258                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2259                 }
2260                 i40e_veb_release(vsi->veb);
2261         }
2262
2263         /* Remove all macvlan filters of the VSI */
2264         i40e_vsi_remove_all_macvlan_filter(vsi);
2265         TAILQ_FOREACH(f, &vsi->mac_list, next)
2266                 rte_free(f);
2267
2268         if (vsi->type != I40E_VSI_MAIN) {
2269                 /* Remove vsi from parent's sibling list */
2270                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2271                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL\n");
2272                         return I40E_ERR_PARAM;
2273                 }
2274                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2275                                 &vsi->sib_vsi_list, list);
2276
2277                 /* Remove all switch element of the VSI */
2278                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2279                 if (ret != I40E_SUCCESS)
2280                         PMD_DRV_LOG(ERR, "Failed to delete element\n");
2281         }
2282         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2283
2284         if (vsi->type != I40E_VSI_SRIOV)
2285                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2286         rte_free(vsi);
2287
2288         return I40E_SUCCESS;
2289 }
2290
2291 static int
2292 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2293 {
2294         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2295         struct i40e_aqc_remove_macvlan_element_data def_filter;
2296         int ret;
2297
2298         if (vsi->type != I40E_VSI_MAIN)
2299                 return I40E_ERR_CONFIG;
2300         memset(&def_filter, 0, sizeof(def_filter));
2301         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2302                                         ETH_ADDR_LEN);
2303         def_filter.vlan_tag = 0;
2304         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2305                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2306         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2307         if (ret != I40E_SUCCESS) {
2308                 struct i40e_mac_filter *f;
2309
2310                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2311                                                 "macvlan filter\n");
2312                 /* It needs to add the permanent mac into mac list */
2313                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2314                 if (f == NULL) {
2315                         PMD_DRV_LOG(ERR, "failed to allocate memory\n");
2316                         return I40E_ERR_NO_MEMORY;
2317                 }
2318                 (void)rte_memcpy(&f->macaddr.addr_bytes, hw->mac.perm_addr,
2319                                 ETH_ADDR_LEN);
2320                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2321                 vsi->mac_num++;
2322
2323                 return ret;
2324         }
2325
2326         return i40e_vsi_add_mac(vsi, (struct ether_addr *)(hw->mac.perm_addr));
2327 }
2328
2329 static int
2330 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2331 {
2332         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2333         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2334         struct i40e_hw *hw = &vsi->adapter->hw;
2335         i40e_status ret;
2336         int i;
2337
2338         memset(&bw_config, 0, sizeof(bw_config));
2339         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2340         if (ret != I40E_SUCCESS) {
2341                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth "
2342                         "configuration %u\n", hw->aq.asq_last_status);
2343                 return ret;
2344         }
2345
2346         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2347         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2348                                         &ets_sla_config, NULL);
2349         if (ret != I40E_SUCCESS) {
2350                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2351                         "configuration %u\n", hw->aq.asq_last_status);
2352                 return ret;
2353         }
2354
2355         /* Not store the info yet, just print out */
2356         PMD_DRV_LOG(INFO, "VSI bw limit:%u\n", bw_config.port_bw_limit);
2357         PMD_DRV_LOG(INFO, "VSI max_bw:%u\n", bw_config.max_bw);
2358         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2359                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u\n", i,
2360                                         ets_sla_config.share_credits[i]);
2361                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u\n", i,
2362                         rte_le_to_cpu_16(ets_sla_config.credits[i]));
2363                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2364                         rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2365                                                                 (i * 4));
2366         }
2367
2368         return 0;
2369 }
2370
2371 /* Setup a VSI */
2372 struct i40e_vsi *
2373 i40e_vsi_setup(struct i40e_pf *pf,
2374                enum i40e_vsi_type type,
2375                struct i40e_vsi *uplink_vsi,
2376                uint16_t user_param)
2377 {
2378         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2379         struct i40e_vsi *vsi;
2380         int ret;
2381         struct i40e_vsi_context ctxt;
2382         struct ether_addr broadcast =
2383                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2384
2385         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2386                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2387                         "VSI link shouldn't be NULL\n");
2388                 return NULL;
2389         }
2390
2391         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2392                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2393                                 "uplink VSI should be NULL\n");
2394                 return NULL;
2395         }
2396
2397         /* If uplink vsi didn't setup VEB, create one first */
2398         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2399                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2400
2401                 if (NULL == uplink_vsi->veb) {
2402                         PMD_DRV_LOG(ERR, "VEB setup failed\n");
2403                         return NULL;
2404                 }
2405         }
2406
2407         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2408         if (!vsi) {
2409                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi\n");
2410                 return NULL;
2411         }
2412         TAILQ_INIT(&vsi->mac_list);
2413         vsi->type = type;
2414         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2415         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2416         vsi->parent_vsi = uplink_vsi;
2417         vsi->user_param = user_param;
2418         /* Allocate queues */
2419         switch (vsi->type) {
2420         case I40E_VSI_MAIN  :
2421                 vsi->nb_qps = pf->lan_nb_qps;
2422                 break;
2423         case I40E_VSI_SRIOV :
2424                 vsi->nb_qps = pf->vf_nb_qps;
2425                 break;
2426         default:
2427                 goto fail_mem;
2428         }
2429         ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2430         if (ret < 0) {
2431                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2432                                 vsi->seid, ret);
2433                 goto fail_mem;
2434         }
2435         vsi->base_queue = ret;
2436
2437         /* VF has MSIX interrupt in VF range, don't allocate here */
2438         if (type != I40E_VSI_SRIOV) {
2439                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2440                 if (ret < 0) {
2441                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2442                         goto fail_queue_alloc;
2443                 }
2444                 vsi->msix_intr = ret;
2445         } else
2446                 vsi->msix_intr = 0;
2447         /* Add VSI */
2448         if (type == I40E_VSI_MAIN) {
2449                 /* For main VSI, no need to add since it's default one */
2450                 vsi->uplink_seid = pf->mac_seid;
2451                 vsi->seid = pf->main_vsi_seid;
2452                 /* Bind queues with specific MSIX interrupt */
2453                 /**
2454                  * Needs 2 interrupt at least, one for misc cause which will
2455                  * enabled from OS side, Another for queues binding the
2456                  * interrupt from device side only.
2457                  */
2458
2459                 /* Get default VSI parameters from hardware */
2460                 memset(&ctxt, 0, sizeof(ctxt));
2461                 ctxt.seid = vsi->seid;
2462                 ctxt.pf_num = hw->pf_id;
2463                 ctxt.uplink_seid = vsi->uplink_seid;
2464                 ctxt.vf_num = 0;
2465                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2466                 if (ret != I40E_SUCCESS) {
2467                         PMD_DRV_LOG(ERR, "Failed to get VSI params\n");
2468                         goto fail_msix_alloc;
2469                 }
2470                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2471                         sizeof(struct i40e_aqc_vsi_properties_data));
2472                 vsi->vsi_id = ctxt.vsi_number;
2473                 vsi->info.valid_sections = 0;
2474
2475                 /* Configure tc, enabled TC0 only */
2476                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2477                         I40E_SUCCESS) {
2478                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth\n");
2479                         goto fail_msix_alloc;
2480                 }
2481
2482                 /* TC, queue mapping */
2483                 memset(&ctxt, 0, sizeof(ctxt));
2484                 vsi->info.valid_sections |=
2485                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2486                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2487                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2488                 (void)rte_memcpy(&ctxt.info, &vsi->info,
2489                         sizeof(struct i40e_aqc_vsi_properties_data));
2490                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2491                                                 I40E_DEFAULT_TCMAP);
2492                 if (ret != I40E_SUCCESS) {
2493                         PMD_DRV_LOG(ERR, "Failed to configure "
2494                                         "TC queue mapping\n");
2495                         goto fail_msix_alloc;
2496                 }
2497                 ctxt.seid = vsi->seid;
2498                 ctxt.pf_num = hw->pf_id;
2499                 ctxt.uplink_seid = vsi->uplink_seid;
2500                 ctxt.vf_num = 0;
2501
2502                 /* Update VSI parameters */
2503                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2504                 if (ret != I40E_SUCCESS) {
2505                         PMD_DRV_LOG(ERR, "Failed to update VSI params\n");
2506                         goto fail_msix_alloc;
2507                 }
2508
2509                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2510                                                 sizeof(vsi->info.tc_mapping));
2511                 (void)rte_memcpy(&vsi->info.queue_mapping,
2512                                 &ctxt.info.queue_mapping,
2513                         sizeof(vsi->info.queue_mapping));
2514                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2515                 vsi->info.valid_sections = 0;
2516
2517                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2518                                 ETH_ADDR_LEN);
2519
2520                 /**
2521                  * Updating default filter settings are necessary to prevent
2522                  * reception of tagged packets.
2523                  * Some old firmware configurations load a default macvlan
2524                  * filter which accepts both tagged and untagged packets.
2525                  * The updating is to use a normal filter instead if needed.
2526                  * For NVM 4.2.2 or after, the updating is not needed anymore.
2527                  * The firmware with correct configurations load the default
2528                  * macvlan filter which is expected and cannot be removed.
2529                  */
2530                 i40e_update_default_filter_setting(vsi);
2531         } else if (type == I40E_VSI_SRIOV) {
2532                 memset(&ctxt, 0, sizeof(ctxt));
2533                 /**
2534                  * For other VSI, the uplink_seid equals to uplink VSI's
2535                  * uplink_seid since they share same VEB
2536                  */
2537                 vsi->uplink_seid = uplink_vsi->uplink_seid;
2538                 ctxt.pf_num = hw->pf_id;
2539                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2540                 ctxt.uplink_seid = vsi->uplink_seid;
2541                 ctxt.connection_type = 0x1;
2542                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2543
2544                 /* Configure switch ID */
2545                 ctxt.info.valid_sections |=
2546                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2547                 ctxt.info.switch_id =
2548                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2549                 /* Configure port/vlan */
2550                 ctxt.info.valid_sections |=
2551                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2552                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2553                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2554                                                 I40E_DEFAULT_TCMAP);
2555                 if (ret != I40E_SUCCESS) {
2556                         PMD_DRV_LOG(ERR, "Failed to configure "
2557                                         "TC queue mapping\n");
2558                         goto fail_msix_alloc;
2559                 }
2560                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2561                 ctxt.info.valid_sections |=
2562                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2563                 /**
2564                  * Since VSI is not created yet, only configure parameter,
2565                  * will add vsi below.
2566                  */
2567         }
2568         else {
2569                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet\n");
2570                 goto fail_msix_alloc;
2571         }
2572
2573         if (vsi->type != I40E_VSI_MAIN) {
2574                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
2575                 if (ret) {
2576                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d\n",
2577                                  hw->aq.asq_last_status);
2578                         goto fail_msix_alloc;
2579                 }
2580                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
2581                 vsi->info.valid_sections = 0;
2582                 vsi->seid = ctxt.seid;
2583                 vsi->vsi_id = ctxt.vsi_number;
2584                 vsi->sib_vsi_list.vsi = vsi;
2585                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
2586                                 &vsi->sib_vsi_list, list);
2587         }
2588
2589         /* MAC/VLAN configuration */
2590         ret = i40e_vsi_add_mac(vsi, &broadcast);
2591         if (ret != I40E_SUCCESS) {
2592                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter\n");
2593                 goto fail_msix_alloc;
2594         }
2595
2596         /* Get VSI BW information */
2597         i40e_vsi_dump_bw_config(vsi);
2598         return vsi;
2599 fail_msix_alloc:
2600         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
2601 fail_queue_alloc:
2602         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
2603 fail_mem:
2604         rte_free(vsi);
2605         return NULL;
2606 }
2607
2608 /* Configure vlan stripping on or off */
2609 int
2610 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
2611 {
2612         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2613         struct i40e_vsi_context ctxt;
2614         uint8_t vlan_flags;
2615         int ret = I40E_SUCCESS;
2616
2617         /* Check if it has been already on or off */
2618         if (vsi->info.valid_sections &
2619                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
2620                 if (on) {
2621                         if ((vsi->info.port_vlan_flags &
2622                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
2623                                 return 0; /* already on */
2624                 } else {
2625                         if ((vsi->info.port_vlan_flags &
2626                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2627                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
2628                                 return 0; /* already off */
2629                 }
2630         }
2631
2632         if (on)
2633                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2634         else
2635                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2636         vsi->info.valid_sections =
2637                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2638         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
2639         vsi->info.port_vlan_flags |= vlan_flags;
2640         ctxt.seid = vsi->seid;
2641         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2642         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2643         if (ret)
2644                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping\n",
2645                                                 on ? "enable" : "disable");
2646
2647         return ret;
2648 }
2649
2650 static int
2651 i40e_dev_init_vlan(struct rte_eth_dev *dev)
2652 {
2653         struct rte_eth_dev_data *data = dev->data;
2654         int ret;
2655
2656         /* Apply vlan offload setting */
2657         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
2658
2659         /* Apply double-vlan setting, not implemented yet */
2660
2661         /* Apply pvid setting */
2662         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
2663                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
2664         if (ret)
2665                 PMD_DRV_LOG(INFO, "Failed to update VSI params\n");
2666
2667         return ret;
2668 }
2669
2670 static int
2671 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
2672 {
2673         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2674
2675         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
2676 }
2677
2678 static int
2679 i40e_update_flow_control(struct i40e_hw *hw)
2680 {
2681 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
2682         struct i40e_link_status link_status;
2683         uint32_t rxfc = 0, txfc = 0, reg;
2684         uint8_t an_info;
2685         int ret;
2686
2687         memset(&link_status, 0, sizeof(link_status));
2688         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
2689         if (ret != I40E_SUCCESS) {
2690                 PMD_DRV_LOG(ERR, "Failed to get link status information\n");
2691                 goto write_reg; /* Disable flow control */
2692         }
2693
2694         an_info = hw->phy.link_info.an_info;
2695         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
2696                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed\n");
2697                 ret = I40E_ERR_NOT_READY;
2698                 goto write_reg; /* Disable flow control */
2699         }
2700         /**
2701          * If link auto negotiation is enabled, flow control needs to
2702          * be configured according to it
2703          */
2704         switch (an_info & I40E_LINK_PAUSE_RXTX) {
2705         case I40E_LINK_PAUSE_RXTX:
2706                 rxfc = 1;
2707                 txfc = 1;
2708                 hw->fc.current_mode = I40E_FC_FULL;
2709                 break;
2710         case I40E_AQ_LINK_PAUSE_RX:
2711                 rxfc = 1;
2712                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2713                 break;
2714         case I40E_AQ_LINK_PAUSE_TX:
2715                 txfc = 1;
2716                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2717                 break;
2718         default:
2719                 hw->fc.current_mode = I40E_FC_NONE;
2720                 break;
2721         }
2722
2723 write_reg:
2724         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
2725                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
2726         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2727         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
2728         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
2729         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
2730
2731         return ret;
2732 }
2733
2734 /* PF setup */
2735 static int
2736 i40e_pf_setup(struct i40e_pf *pf)
2737 {
2738         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2739         struct i40e_filter_control_settings settings;
2740         struct rte_eth_dev_data *dev_data = pf->dev_data;
2741         struct i40e_vsi *vsi;
2742         int ret;
2743
2744         /* Clear all stats counters */
2745         pf->offset_loaded = FALSE;
2746         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
2747         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
2748
2749         ret = i40e_pf_get_switch_config(pf);
2750         if (ret != I40E_SUCCESS) {
2751                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
2752                 return ret;
2753         }
2754
2755         /* VSI setup */
2756         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
2757         if (!vsi) {
2758                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
2759                 return I40E_ERR_NOT_READY;
2760         }
2761         pf->main_vsi = vsi;
2762         dev_data->nb_rx_queues = vsi->nb_qps;
2763         dev_data->nb_tx_queues = vsi->nb_qps;
2764
2765         /* Configure filter control */
2766         memset(&settings, 0, sizeof(settings));
2767         settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
2768         /* Enable ethtype and macvlan filters */
2769         settings.enable_ethtype = TRUE;
2770         settings.enable_macvlan = TRUE;
2771         ret = i40e_set_filter_control(hw, &settings);
2772         if (ret)
2773                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2774                                                                 ret);
2775
2776         /* Update flow control according to the auto negotiation */
2777         i40e_update_flow_control(hw);
2778
2779         return I40E_SUCCESS;
2780 }
2781
2782 int
2783 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2784 {
2785         uint32_t reg;
2786         uint16_t j;
2787
2788         /* Wait until the request is finished */
2789         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2790                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2791                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2792                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2793                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
2794                                                         & 0x1))) {
2795                         break;
2796                 }
2797         }
2798         if (on) {
2799                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
2800                         return I40E_SUCCESS; /* already on, skip next steps */
2801                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
2802         } else {
2803                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
2804                         return I40E_SUCCESS; /* already off, skip next steps */
2805                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
2806         }
2807         /* Write the register */
2808         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
2809         /* Check the result */
2810         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2811                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2812                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2813                 if (on) {
2814                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
2815                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
2816                                 break;
2817                 } else {
2818                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
2819                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
2820                                 break;
2821                 }
2822         }
2823         /* Check if it is timeout */
2824         if (j >= I40E_CHK_Q_ENA_COUNT) {
2825                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]\n",
2826                         (on ? "enable" : "disable"), q_idx);
2827                 return I40E_ERR_TIMEOUT;
2828         }
2829         return I40E_SUCCESS;
2830 }
2831 /* Swith on or off the tx queues */
2832 static int
2833 i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on)
2834 {
2835         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
2836         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2837         struct i40e_tx_queue *txq;
2838         uint16_t i, pf_q;
2839         int ret;
2840
2841         pf_q = vsi->base_queue;
2842         for (i = 0; i < dev_data->nb_tx_queues; i++, pf_q++) {
2843                 txq = dev_data->tx_queues[i];
2844                 if (!txq->q_set)
2845                         continue; /* Queue not configured */
2846                 ret = i40e_switch_tx_queue(hw, pf_q, on);
2847                 if ( ret != I40E_SUCCESS)
2848                         return ret;
2849         }
2850
2851         return I40E_SUCCESS;
2852 }
2853
2854 int
2855 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2856 {
2857         uint32_t reg;
2858         uint16_t j;
2859
2860         /* Wait until the request is finished */
2861         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2862                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2863                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
2864                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2865                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
2866                         break;
2867         }
2868
2869         if (on) {
2870                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
2871                         return I40E_SUCCESS; /* Already on, skip next steps */
2872                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
2873         } else {
2874                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
2875                         return I40E_SUCCESS; /* Already off, skip next steps */
2876                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
2877         }
2878
2879         /* Write the register */
2880         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
2881         /* Check the result */
2882         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2883                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2884                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
2885                 if (on) {
2886                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
2887                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
2888                                 break;
2889                 } else {
2890                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
2891                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
2892                                 break;
2893                 }
2894         }
2895
2896         /* Check if it is timeout */
2897         if (j >= I40E_CHK_Q_ENA_COUNT) {
2898                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]\n",
2899                         (on ? "enable" : "disable"), q_idx);
2900                 return I40E_ERR_TIMEOUT;
2901         }
2902
2903         return I40E_SUCCESS;
2904 }
2905 /* Switch on or off the rx queues */
2906 static int
2907 i40e_vsi_switch_rx_queues(struct i40e_vsi *vsi, bool on)
2908 {
2909         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
2910         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2911         struct i40e_rx_queue *rxq;
2912         uint16_t i, pf_q;
2913         int ret;
2914
2915         pf_q = vsi->base_queue;
2916         for (i = 0; i < dev_data->nb_rx_queues; i++, pf_q++) {
2917                 rxq = dev_data->rx_queues[i];
2918                 if (!rxq->q_set)
2919                         continue; /* Queue not configured */
2920                 ret = i40e_switch_rx_queue(hw, pf_q, on);
2921                 if ( ret != I40E_SUCCESS)
2922                         return ret;
2923         }
2924
2925         return I40E_SUCCESS;
2926 }
2927
2928 /* Switch on or off all the rx/tx queues */
2929 int
2930 i40e_vsi_switch_queues(struct i40e_vsi *vsi, bool on)
2931 {
2932         int ret;
2933
2934         if (on) {
2935                 /* enable rx queues before enabling tx queues */
2936                 ret = i40e_vsi_switch_rx_queues(vsi, on);
2937                 if (ret) {
2938                         PMD_DRV_LOG(ERR, "Failed to switch rx queues\n");
2939                         return ret;
2940                 }
2941                 ret = i40e_vsi_switch_tx_queues(vsi, on);
2942         } else {
2943                 /* Stop tx queues before stopping rx queues */
2944                 ret = i40e_vsi_switch_tx_queues(vsi, on);
2945                 if (ret) {
2946                         PMD_DRV_LOG(ERR, "Failed to switch tx queues\n");
2947                         return ret;
2948                 }
2949                 ret = i40e_vsi_switch_rx_queues(vsi, on);
2950         }
2951
2952         return ret;
2953 }
2954
2955 /* Initialize VSI for TX */
2956 static int
2957 i40e_vsi_tx_init(struct i40e_vsi *vsi)
2958 {
2959         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2960         struct rte_eth_dev_data *data = pf->dev_data;
2961         uint16_t i;
2962         uint32_t ret = I40E_SUCCESS;
2963
2964         for (i = 0; i < data->nb_tx_queues; i++) {
2965                 ret = i40e_tx_queue_init(data->tx_queues[i]);
2966                 if (ret != I40E_SUCCESS)
2967                         break;
2968         }
2969
2970         return ret;
2971 }
2972
2973 /* Initialize VSI for RX */
2974 static int
2975 i40e_vsi_rx_init(struct i40e_vsi *vsi)
2976 {
2977         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2978         struct rte_eth_dev_data *data = pf->dev_data;
2979         int ret = I40E_SUCCESS;
2980         uint16_t i;
2981
2982         i40e_pf_config_mq_rx(pf);
2983         for (i = 0; i < data->nb_rx_queues; i++) {
2984                 ret = i40e_rx_queue_init(data->rx_queues[i]);
2985                 if (ret != I40E_SUCCESS) {
2986                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
2987                                         "initialization\n");
2988                         break;
2989                 }
2990         }
2991
2992         return ret;
2993 }
2994
2995 /* Initialize VSI */
2996 static int
2997 i40e_vsi_init(struct i40e_vsi *vsi)
2998 {
2999         int err;
3000
3001         err = i40e_vsi_tx_init(vsi);
3002         if (err) {
3003                 PMD_DRV_LOG(ERR, "Failed to do vsi TX initialization\n");
3004                 return err;
3005         }
3006         err = i40e_vsi_rx_init(vsi);
3007         if (err) {
3008                 PMD_DRV_LOG(ERR, "Failed to do vsi RX initialization\n");
3009                 return err;
3010         }
3011
3012         return err;
3013 }
3014
3015 static void
3016 i40e_stat_update_32(struct i40e_hw *hw,
3017                    uint32_t reg,
3018                    bool offset_loaded,
3019                    uint64_t *offset,
3020                    uint64_t *stat)
3021 {
3022         uint64_t new_data;
3023
3024         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3025         if (!offset_loaded)
3026                 *offset = new_data;
3027
3028         if (new_data >= *offset)
3029                 *stat = (uint64_t)(new_data - *offset);
3030         else
3031                 *stat = (uint64_t)((new_data +
3032                         ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3033 }
3034
3035 static void
3036 i40e_stat_update_48(struct i40e_hw *hw,
3037                    uint32_t hireg,
3038                    uint32_t loreg,
3039                    bool offset_loaded,
3040                    uint64_t *offset,
3041                    uint64_t *stat)
3042 {
3043         uint64_t new_data;
3044
3045         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3046         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3047                         I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3048
3049         if (!offset_loaded)
3050                 *offset = new_data;
3051
3052         if (new_data >= *offset)
3053                 *stat = new_data - *offset;
3054         else
3055                 *stat = (uint64_t)((new_data +
3056                         ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3057
3058         *stat &= I40E_48_BIT_MASK;
3059 }
3060
3061 /* Disable IRQ0 */
3062 void
3063 i40e_pf_disable_irq0(struct i40e_hw *hw)
3064 {
3065         /* Disable all interrupt types */
3066         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3067         I40E_WRITE_FLUSH(hw);
3068 }
3069
3070 /* Enable IRQ0 */
3071 void
3072 i40e_pf_enable_irq0(struct i40e_hw *hw)
3073 {
3074         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3075                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3076                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3077                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3078         I40E_WRITE_FLUSH(hw);
3079 }
3080
3081 static void
3082 i40e_pf_config_irq0(struct i40e_hw *hw)
3083 {
3084         uint32_t enable;
3085
3086         /* read pending request and disable first */
3087         i40e_pf_disable_irq0(hw);
3088         /**
3089          * Enable all interrupt error options to detect possible errors,
3090          * other informative int are ignored
3091          */
3092         enable = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3093                  I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3094                  I40E_PFINT_ICR0_ENA_GRST_MASK |
3095                  I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3096                  I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK |
3097                  I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3098                  I40E_PFINT_ICR0_ENA_VFLR_MASK |
3099                  I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3100
3101         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3102         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3103                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3104
3105         /* Link no queues with irq0 */
3106         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3107                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3108 }
3109
3110 static void
3111 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3112 {
3113         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3114         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3115         int i;
3116         uint16_t abs_vf_id;
3117         uint32_t index, offset, val;
3118
3119         if (!pf->vfs)
3120                 return;
3121         /**
3122          * Try to find which VF trigger a reset, use absolute VF id to access
3123          * since the reg is global register.
3124          */
3125         for (i = 0; i < pf->vf_num; i++) {
3126                 abs_vf_id = hw->func_caps.vf_base_id + i;
3127                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3128                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3129                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3130                 /* VFR event occured */
3131                 if (val & (0x1 << offset)) {
3132                         int ret;
3133
3134                         /* Clear the event first */
3135                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3136                                                         (0x1 << offset));
3137                         PMD_DRV_LOG(INFO, "VF %u reset occured\n", abs_vf_id);
3138                         /**
3139                          * Only notify a VF reset event occured,
3140                          * don't trigger another SW reset
3141                          */
3142                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3143                         if (ret != I40E_SUCCESS)
3144                                 PMD_DRV_LOG(ERR, "Failed to do VF reset\n");
3145                 }
3146         }
3147 }
3148
3149 static void
3150 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3151 {
3152         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3153         struct i40e_arq_event_info info;
3154         uint16_t pending, opcode;
3155         int ret;
3156
3157         info.msg_size = I40E_AQ_BUF_SZ;
3158         info.msg_buf = rte_zmalloc("msg_buffer", I40E_AQ_BUF_SZ, 0);
3159         if (!info.msg_buf) {
3160                 PMD_DRV_LOG(ERR, "Failed to allocate mem\n");
3161                 return;
3162         }
3163
3164         pending = 1;
3165         while (pending) {
3166                 ret = i40e_clean_arq_element(hw, &info, &pending);
3167
3168                 if (ret != I40E_SUCCESS) {
3169                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3170                                 "aq_err: %u\n", hw->aq.asq_last_status);
3171                         break;
3172                 }
3173                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3174
3175                 switch (opcode) {
3176                 case i40e_aqc_opc_send_msg_to_pf:
3177                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3178                         i40e_pf_host_handle_vf_msg(dev,
3179                                         rte_le_to_cpu_16(info.desc.retval),
3180                                         rte_le_to_cpu_32(info.desc.cookie_high),
3181                                         rte_le_to_cpu_32(info.desc.cookie_low),
3182                                         info.msg_buf,
3183                                         info.msg_size);
3184                         break;
3185                 default:
3186                         PMD_DRV_LOG(ERR, "Request %u is not supported yet\n",
3187                                 opcode);
3188                         break;
3189                 }
3190                 /* Reset the buffer after processing one */
3191                 info.msg_size = I40E_AQ_BUF_SZ;
3192         }
3193         rte_free(info.msg_buf);
3194 }
3195
3196 /**
3197  * Interrupt handler triggered by NIC  for handling
3198  * specific interrupt.
3199  *
3200  * @param handle
3201  *  Pointer to interrupt handle.
3202  * @param param
3203  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3204  *
3205  * @return
3206  *  void
3207  */
3208 static void
3209 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3210                            void *param)
3211 {
3212         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3213         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3214         uint32_t cause, enable;
3215
3216         i40e_pf_disable_irq0(hw);
3217
3218         cause = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3219         enable = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
3220
3221         /* Shared IRQ case, return */
3222         if (!(cause & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3223                 PMD_DRV_LOG(INFO, "Port%d INT0:share IRQ case, "
3224                         "no INT event to process\n", hw->pf_id);
3225                 goto done;
3226         }
3227
3228         if (cause & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3229                 PMD_DRV_LOG(INFO, "INT:Link status changed\n");
3230                 i40e_dev_link_update(dev, 0);
3231         }
3232
3233         if (cause & I40E_PFINT_ICR0_ECC_ERR_MASK)
3234                 PMD_DRV_LOG(INFO, "INT:Unrecoverable ECC Error\n");
3235
3236         if (cause & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3237                 PMD_DRV_LOG(INFO, "INT:Malicious programming detected\n");
3238
3239         if (cause & I40E_PFINT_ICR0_GRST_MASK)
3240                 PMD_DRV_LOG(INFO, "INT:Global Resets Requested\n");
3241
3242         if (cause & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3243                 PMD_DRV_LOG(INFO, "INT:PCI EXCEPTION occured\n");
3244
3245         if (cause & I40E_PFINT_ICR0_HMC_ERR_MASK)
3246                 PMD_DRV_LOG(INFO, "INT:HMC error occured\n");
3247
3248         /* Add processing func to deal with VF reset vent */
3249         if (cause & I40E_PFINT_ICR0_VFLR_MASK) {
3250                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3251                 i40e_dev_handle_vfr_event(dev);
3252         }
3253         /* Find admin queue event */
3254         if (cause & I40E_PFINT_ICR0_ADMINQ_MASK) {
3255                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3256                 i40e_dev_handle_aq_msg(dev);
3257         }
3258
3259 done:
3260         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3261         /* Re-enable interrupt from device side */
3262         i40e_pf_enable_irq0(hw);
3263         /* Re-enable interrupt from host side */
3264         rte_intr_enable(&(dev->pci_dev->intr_handle));
3265 }
3266
3267 static int
3268 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3269                          struct i40e_macvlan_filter *filter,
3270                          int total)
3271 {
3272         int ele_num, ele_buff_size;
3273         int num, actual_num, i;
3274         int ret = I40E_SUCCESS;
3275         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3276         struct i40e_aqc_add_macvlan_element_data *req_list;
3277
3278         if (filter == NULL  || total == 0)
3279                 return I40E_ERR_PARAM;
3280         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3281         ele_buff_size = hw->aq.asq_buf_size;
3282
3283         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3284         if (req_list == NULL) {
3285                 PMD_DRV_LOG(ERR, "Fail to allocate memory\n");
3286                 return I40E_ERR_NO_MEMORY;
3287         }
3288
3289         num = 0;
3290         do {
3291                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3292                 memset(req_list, 0, ele_buff_size);
3293
3294                 for (i = 0; i < actual_num; i++) {
3295                         (void)rte_memcpy(req_list[i].mac_addr,
3296                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3297                         req_list[i].vlan_tag =
3298                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3299                         req_list[i].flags = rte_cpu_to_le_16(\
3300                                 I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
3301                         req_list[i].queue_number = 0;
3302                 }
3303
3304                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3305                                                 actual_num, NULL);
3306                 if (ret != I40E_SUCCESS) {
3307                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter\n");
3308                         goto DONE;
3309                 }
3310                 num += actual_num;
3311         } while (num < total);
3312
3313 DONE:
3314         rte_free(req_list);
3315         return ret;
3316 }
3317
3318 static int
3319 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3320                             struct i40e_macvlan_filter *filter,
3321                             int total)
3322 {
3323         int ele_num, ele_buff_size;
3324         int num, actual_num, i;
3325         int ret = I40E_SUCCESS;
3326         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3327         struct i40e_aqc_remove_macvlan_element_data *req_list;
3328
3329         if (filter == NULL  || total == 0)
3330                 return I40E_ERR_PARAM;
3331
3332         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3333         ele_buff_size = hw->aq.asq_buf_size;
3334
3335         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3336         if (req_list == NULL) {
3337                 PMD_DRV_LOG(ERR, "Fail to allocate memory\n");
3338                 return I40E_ERR_NO_MEMORY;
3339         }
3340
3341         num = 0;
3342         do {
3343                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3344                 memset(req_list, 0, ele_buff_size);
3345
3346                 for (i = 0; i < actual_num; i++) {
3347                         (void)rte_memcpy(req_list[i].mac_addr,
3348                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3349                         req_list[i].vlan_tag =
3350                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3351                         req_list[i].flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3352                 }
3353
3354                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
3355                                                 actual_num, NULL);
3356                 if (ret != I40E_SUCCESS) {
3357                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter\n");
3358                         goto DONE;
3359                 }
3360                 num += actual_num;
3361         } while (num < total);
3362
3363 DONE:
3364         rte_free(req_list);
3365         return ret;
3366 }
3367
3368 /* Find out specific MAC filter */
3369 static struct i40e_mac_filter *
3370 i40e_find_mac_filter(struct i40e_vsi *vsi,
3371                          struct ether_addr *macaddr)
3372 {
3373         struct i40e_mac_filter *f;
3374
3375         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3376                 if (is_same_ether_addr(macaddr, &(f->macaddr)))
3377                         return f;
3378         }
3379
3380         return NULL;
3381 }
3382
3383 static bool
3384 i40e_find_vlan_filter(struct i40e_vsi *vsi,
3385                          uint16_t vlan_id)
3386 {
3387         uint32_t vid_idx, vid_bit;
3388
3389         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3390         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3391
3392         if (vsi->vfta[vid_idx] & vid_bit)
3393                 return 1;
3394         else
3395                 return 0;
3396 }
3397
3398 static void
3399 i40e_set_vlan_filter(struct i40e_vsi *vsi,
3400                          uint16_t vlan_id, bool on)
3401 {
3402         uint32_t vid_idx, vid_bit;
3403
3404 #define UINT32_BIT_MASK      0x1F
3405 #define VALID_VLAN_BIT_MASK  0xFFF
3406         /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
3407          *  element first, then find the bits it belongs to
3408          */
3409         vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
3410                   sizeof(uint32_t));
3411         vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
3412
3413         if (on)
3414                 vsi->vfta[vid_idx] |= vid_bit;
3415         else
3416                 vsi->vfta[vid_idx] &= ~vid_bit;
3417 }
3418
3419 /**
3420  * Find all vlan options for specific mac addr,
3421  * return with actual vlan found.
3422  */
3423 static inline int
3424 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
3425                            struct i40e_macvlan_filter *mv_f,
3426                            int num, struct ether_addr *addr)
3427 {
3428         int i;
3429         uint32_t j, k;
3430
3431         /**
3432          * Not to use i40e_find_vlan_filter to decrease the loop time,
3433          * although the code looks complex.
3434           */
3435         if (num < vsi->vlan_num)
3436                 return I40E_ERR_PARAM;
3437
3438         i = 0;
3439         for (j = 0; j < I40E_VFTA_SIZE; j++) {
3440                 if (vsi->vfta[j]) {
3441                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
3442                                 if (vsi->vfta[j] & (1 << k)) {
3443                                         if (i > num - 1) {
3444                                                 PMD_DRV_LOG(ERR, "vlan number "
3445                                                                 "not match\n");
3446                                                 return I40E_ERR_PARAM;
3447                                         }
3448                                         (void)rte_memcpy(&mv_f[i].macaddr,
3449                                                         addr, ETH_ADDR_LEN);
3450                                         mv_f[i].vlan_id =
3451                                                 j * I40E_UINT32_BIT_SIZE + k;
3452                                         i++;
3453                                 }
3454                         }
3455                 }
3456         }
3457         return I40E_SUCCESS;
3458 }
3459
3460 static inline int
3461 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
3462                            struct i40e_macvlan_filter *mv_f,
3463                            int num,
3464                            uint16_t vlan)
3465 {
3466         int i = 0;
3467         struct i40e_mac_filter *f;
3468
3469         if (num < vsi->mac_num)
3470                 return I40E_ERR_PARAM;
3471
3472         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3473                 if (i > num - 1) {
3474                         PMD_DRV_LOG(ERR, "buffer number not match\n");
3475                         return I40E_ERR_PARAM;
3476                 }
3477                 (void)rte_memcpy(&mv_f[i].macaddr, &f->macaddr, ETH_ADDR_LEN);
3478                 mv_f[i].vlan_id = vlan;
3479                 i++;
3480         }
3481
3482         return I40E_SUCCESS;
3483 }
3484
3485 static int
3486 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
3487 {
3488         int i, num;
3489         struct i40e_mac_filter *f;
3490         struct i40e_macvlan_filter *mv_f;
3491         int ret = I40E_SUCCESS;
3492
3493         if (vsi == NULL || vsi->mac_num == 0)
3494                 return I40E_ERR_PARAM;
3495
3496         /* Case that no vlan is set */
3497         if (vsi->vlan_num == 0)
3498                 num = vsi->mac_num;
3499         else
3500                 num = vsi->mac_num * vsi->vlan_num;
3501
3502         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
3503         if (mv_f == NULL) {
3504                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3505                 return I40E_ERR_NO_MEMORY;
3506         }
3507
3508         i = 0;
3509         if (vsi->vlan_num == 0) {
3510                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3511                         (void)rte_memcpy(&mv_f[i].macaddr,
3512                                 &f->macaddr, ETH_ADDR_LEN);
3513                         mv_f[i].vlan_id = 0;
3514                         i++;
3515                 }
3516         } else {
3517                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3518                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
3519                                         vsi->vlan_num, &f->macaddr);
3520                         if (ret != I40E_SUCCESS)
3521                                 goto DONE;
3522                         i += vsi->vlan_num;
3523                 }
3524         }
3525
3526         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
3527 DONE:
3528         rte_free(mv_f);
3529
3530         return ret;
3531 }
3532
3533 int
3534 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3535 {
3536         struct i40e_macvlan_filter *mv_f;
3537         int mac_num;
3538         int ret = I40E_SUCCESS;
3539
3540         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
3541                 return I40E_ERR_PARAM;
3542
3543         /* If it's already set, just return */
3544         if (i40e_find_vlan_filter(vsi,vlan))
3545                 return I40E_SUCCESS;
3546
3547         mac_num = vsi->mac_num;
3548
3549         if (mac_num == 0) {
3550                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr\n");
3551                 return I40E_ERR_PARAM;
3552         }
3553
3554         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3555
3556         if (mv_f == NULL) {
3557                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3558                 return I40E_ERR_NO_MEMORY;
3559         }
3560
3561         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3562
3563         if (ret != I40E_SUCCESS)
3564                 goto DONE;
3565
3566         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3567
3568         if (ret != I40E_SUCCESS)
3569                 goto DONE;
3570
3571         i40e_set_vlan_filter(vsi, vlan, 1);
3572
3573         vsi->vlan_num++;
3574         ret = I40E_SUCCESS;
3575 DONE:
3576         rte_free(mv_f);
3577         return ret;
3578 }
3579
3580 int
3581 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3582 {
3583         struct i40e_macvlan_filter *mv_f;
3584         int mac_num;
3585         int ret = I40E_SUCCESS;
3586
3587         /**
3588          * Vlan 0 is the generic filter for untagged packets
3589          * and can't be removed.
3590          */
3591         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
3592                 return I40E_ERR_PARAM;
3593
3594         /* If can't find it, just return */
3595         if (!i40e_find_vlan_filter(vsi, vlan))
3596                 return I40E_ERR_PARAM;
3597
3598         mac_num = vsi->mac_num;
3599
3600         if (mac_num == 0) {
3601                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr\n");
3602                 return I40E_ERR_PARAM;
3603         }
3604
3605         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3606
3607         if (mv_f == NULL) {
3608                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3609                 return I40E_ERR_NO_MEMORY;
3610         }
3611
3612         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3613
3614         if (ret != I40E_SUCCESS)
3615                 goto DONE;
3616
3617         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
3618
3619         if (ret != I40E_SUCCESS)
3620                 goto DONE;
3621
3622         /* This is last vlan to remove, replace all mac filter with vlan 0 */
3623         if (vsi->vlan_num == 1) {
3624                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
3625                 if (ret != I40E_SUCCESS)
3626                         goto DONE;
3627
3628                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3629                 if (ret != I40E_SUCCESS)
3630                         goto DONE;
3631         }
3632
3633         i40e_set_vlan_filter(vsi, vlan, 0);
3634
3635         vsi->vlan_num--;
3636         ret = I40E_SUCCESS;
3637 DONE:
3638         rte_free(mv_f);
3639         return ret;
3640 }
3641
3642 int
3643 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3644 {
3645         struct i40e_mac_filter *f;
3646         struct i40e_macvlan_filter *mv_f;
3647         int vlan_num;
3648         int ret = I40E_SUCCESS;
3649
3650         /* If it's add and we've config it, return */
3651         f = i40e_find_mac_filter(vsi, addr);
3652         if (f != NULL)
3653                 return I40E_SUCCESS;
3654
3655         /**
3656          * If vlan_num is 0, that's the first time to add mac,
3657          * set mask for vlan_id 0.
3658          */
3659         if (vsi->vlan_num == 0) {
3660                 i40e_set_vlan_filter(vsi, 0, 1);
3661                 vsi->vlan_num = 1;
3662         }
3663
3664         vlan_num = vsi->vlan_num;
3665
3666         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3667         if (mv_f == NULL) {
3668                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3669                 return I40E_ERR_NO_MEMORY;
3670         }
3671
3672         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3673         if (ret != I40E_SUCCESS)
3674                 goto DONE;
3675
3676         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
3677         if (ret != I40E_SUCCESS)
3678                 goto DONE;
3679
3680         /* Add the mac addr into mac list */
3681         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3682         if (f == NULL) {
3683                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3684                 ret = I40E_ERR_NO_MEMORY;
3685                 goto DONE;
3686         }
3687         (void)rte_memcpy(&f->macaddr, addr, ETH_ADDR_LEN);
3688         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3689         vsi->mac_num++;
3690
3691         ret = I40E_SUCCESS;
3692 DONE:
3693         rte_free(mv_f);
3694
3695         return ret;
3696 }
3697
3698 int
3699 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3700 {
3701         struct i40e_mac_filter *f;
3702         struct i40e_macvlan_filter *mv_f;
3703         int vlan_num;
3704         int ret = I40E_SUCCESS;
3705
3706         /* Can't find it, return an error */
3707         f = i40e_find_mac_filter(vsi, addr);
3708         if (f == NULL)
3709                 return I40E_ERR_PARAM;
3710
3711         vlan_num = vsi->vlan_num;
3712         if (vlan_num == 0) {
3713                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
3714                 return I40E_ERR_PARAM;
3715         }
3716         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3717         if (mv_f == NULL) {
3718                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3719                 return I40E_ERR_NO_MEMORY;
3720         }
3721
3722         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3723         if (ret != I40E_SUCCESS)
3724                 goto DONE;
3725
3726         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
3727         if (ret != I40E_SUCCESS)
3728                 goto DONE;
3729
3730         /* Remove the mac addr into mac list */
3731         TAILQ_REMOVE(&vsi->mac_list, f, next);
3732         rte_free(f);
3733         vsi->mac_num--;
3734
3735         ret = I40E_SUCCESS;
3736 DONE:
3737         rte_free(mv_f);
3738         return ret;
3739 }
3740
3741 /* Configure hash enable flags for RSS */
3742 static uint64_t
3743 i40e_config_hena(uint64_t flags)
3744 {
3745         uint64_t hena = 0;
3746
3747         if (!flags)
3748                 return hena;
3749
3750         if (flags & ETH_RSS_NONF_IPV4_UDP)
3751                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3752         if (flags & ETH_RSS_NONF_IPV4_TCP)
3753                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3754         if (flags & ETH_RSS_NONF_IPV4_SCTP)
3755                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3756         if (flags & ETH_RSS_NONF_IPV4_OTHER)
3757                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3758         if (flags & ETH_RSS_FRAG_IPV4)
3759                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
3760         if (flags & ETH_RSS_NONF_IPV6_UDP)
3761                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3762         if (flags & ETH_RSS_NONF_IPV6_TCP)
3763                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3764         if (flags & ETH_RSS_NONF_IPV6_SCTP)
3765                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3766         if (flags & ETH_RSS_NONF_IPV6_OTHER)
3767                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
3768         if (flags & ETH_RSS_FRAG_IPV6)
3769                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
3770         if (flags & ETH_RSS_L2_PAYLOAD)
3771                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
3772
3773         return hena;
3774 }
3775
3776 /* Parse the hash enable flags */
3777 static uint64_t
3778 i40e_parse_hena(uint64_t flags)
3779 {
3780         uint64_t rss_hf = 0;
3781
3782         if (!flags)
3783                 return rss_hf;
3784
3785         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
3786                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
3787         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
3788                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
3789         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
3790                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
3791         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
3792                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
3793         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
3794                 rss_hf |= ETH_RSS_FRAG_IPV4;
3795         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
3796                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
3797         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
3798                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
3799         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
3800                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
3801         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
3802                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
3803         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
3804                 rss_hf |= ETH_RSS_FRAG_IPV6;
3805         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
3806                 rss_hf |= ETH_RSS_L2_PAYLOAD;
3807
3808         return rss_hf;
3809 }
3810
3811 /* Disable RSS */
3812 static void
3813 i40e_pf_disable_rss(struct i40e_pf *pf)
3814 {
3815         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3816         uint64_t hena;
3817
3818         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3819         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3820         hena &= ~I40E_RSS_HENA_ALL;
3821         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
3822         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
3823         I40E_WRITE_FLUSH(hw);
3824 }
3825
3826 static int
3827 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
3828 {
3829         uint32_t *hash_key;
3830         uint8_t hash_key_len;
3831         uint64_t rss_hf;
3832         uint16_t i;
3833         uint64_t hena;
3834
3835         hash_key = (uint32_t *)(rss_conf->rss_key);
3836         hash_key_len = rss_conf->rss_key_len;
3837         if (hash_key != NULL && hash_key_len >=
3838                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
3839                 /* Fill in RSS hash key */
3840                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
3841                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
3842         }
3843
3844         rss_hf = rss_conf->rss_hf;
3845         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3846         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3847         hena &= ~I40E_RSS_HENA_ALL;
3848         hena |= i40e_config_hena(rss_hf);
3849         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
3850         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
3851         I40E_WRITE_FLUSH(hw);
3852
3853         return 0;
3854 }
3855
3856 static int
3857 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
3858                          struct rte_eth_rss_conf *rss_conf)
3859 {
3860         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3861         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
3862         uint64_t hena;
3863
3864         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3865         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3866         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
3867                 if (rss_hf != 0) /* Enable RSS */
3868                         return -EINVAL;
3869                 return 0; /* Nothing to do */
3870         }
3871         /* RSS enabled */
3872         if (rss_hf == 0) /* Disable RSS */
3873                 return -EINVAL;
3874
3875         return i40e_hw_rss_hash_set(hw, rss_conf);
3876 }
3877
3878 static int
3879 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
3880                            struct rte_eth_rss_conf *rss_conf)
3881 {
3882         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3883         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
3884         uint64_t hena;
3885         uint16_t i;
3886
3887         if (hash_key != NULL) {
3888                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
3889                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
3890                 rss_conf->rss_key_len = i * sizeof(uint32_t);
3891         }
3892         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3893         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3894         rss_conf->rss_hf = i40e_parse_hena(hena);
3895
3896         return 0;
3897 }
3898
3899 /* Configure RSS */
3900 static int
3901 i40e_pf_config_rss(struct i40e_pf *pf)
3902 {
3903         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3904         struct rte_eth_rss_conf rss_conf;
3905         uint32_t i, lut = 0;
3906         uint16_t j, num = i40e_prev_power_of_2(pf->dev_data->nb_rx_queues);
3907
3908         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
3909                 if (j == num)
3910                         j = 0;
3911                 lut = (lut << 8) | (j & ((0x1 <<
3912                         hw->func_caps.rss_table_entry_width) - 1));
3913                 if ((i & 3) == 3)
3914                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
3915         }
3916
3917         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
3918         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
3919                 i40e_pf_disable_rss(pf);
3920                 return 0;
3921         }
3922         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
3923                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
3924                 /* Calculate the default hash key */
3925                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
3926                         rss_key_default[i] = (uint32_t)rte_rand();
3927                 rss_conf.rss_key = (uint8_t *)rss_key_default;
3928                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3929                                                         sizeof(uint32_t);
3930         }
3931
3932         return i40e_hw_rss_hash_set(hw, &rss_conf);
3933 }
3934
3935 static int
3936 i40e_pf_config_mq_rx(struct i40e_pf *pf)
3937 {
3938         if (!pf->dev_data->sriov.active) {
3939                 switch (pf->dev_data->dev_conf.rxmode.mq_mode) {
3940                 case ETH_MQ_RX_RSS:
3941                         i40e_pf_config_rss(pf);
3942                         break;
3943                 default:
3944                         i40e_pf_disable_rss(pf);
3945                         break;
3946                 }
3947         }
3948
3949         return 0;
3950 }
3951
3952 static int
3953 i40e_disable_queue(struct i40e_hw *hw, uint16_t q_idx)
3954 {
3955         uint16_t i;
3956         uint32_t reg;
3957
3958         /* Disable TX queue */
3959         for (i = 0; i < I40E_CHK_Q_ENA_COUNT; i++) {
3960                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3961                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3962                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 0x1)))
3963                         break;
3964                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3965         }
3966         if (i >= I40E_CHK_Q_ENA_COUNT) {
3967                 PMD_DRV_LOG(ERR, "Failed to disable "
3968                         "tx queue[%u]\n", q_idx);
3969                 return I40E_ERR_TIMEOUT;
3970         }
3971
3972         if (reg & I40E_QTX_ENA_QENA_STAT_MASK) {
3973                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3974                 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3975                 for (i = 0; i < I40E_CHK_Q_ENA_COUNT; i++) {
3976                         rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3977                         reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3978                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3979                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3980                                 break;
3981                 }
3982                 if (i >= I40E_CHK_Q_ENA_COUNT) {
3983                         PMD_DRV_LOG(ERR, "Failed to disable "
3984                                 "tx queue[%u]\n", q_idx);
3985                         return I40E_ERR_TIMEOUT;
3986                 }
3987         }
3988
3989         /* Disable RX queue */
3990         for (i = 0; i < I40E_CHK_Q_ENA_COUNT; i++) {
3991                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3992                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3993                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3994                         break;
3995                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3996         }
3997         if (i >= I40E_CHK_Q_ENA_COUNT) {
3998                 PMD_DRV_LOG(ERR, "Failed to disable "
3999                         "rx queue[%u]\n", q_idx);
4000                 return I40E_ERR_TIMEOUT;
4001         }
4002
4003         if (reg & I40E_QRX_ENA_QENA_STAT_MASK) {
4004                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4005                 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4006                 for (i = 0; i < I40E_CHK_Q_ENA_COUNT; i++) {
4007                         rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4008                         reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4009                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4010                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4011                                 break;
4012                 }
4013                 if (i >= I40E_CHK_Q_ENA_COUNT) {
4014                         PMD_DRV_LOG(ERR, "Failed to disable "
4015                                 "rx queue[%u]\n", q_idx);
4016                         return I40E_ERR_TIMEOUT;
4017                 }
4018         }
4019
4020         return I40E_SUCCESS;
4021 }
4022
4023 static int
4024 i40e_pf_disable_all_queues(struct i40e_hw *hw)
4025 {
4026         uint32_t reg;
4027         uint16_t firstq, lastq, maxq, i;
4028         int ret;
4029         reg = I40E_READ_REG(hw, I40E_PFLAN_QALLOC);
4030         if (!(reg & I40E_PFLAN_QALLOC_VALID_MASK)) {
4031                 PMD_DRV_LOG(INFO, "PF queue allocation is invalid\n");
4032                 return I40E_ERR_PARAM;
4033         }
4034         firstq = reg & I40E_PFLAN_QALLOC_FIRSTQ_MASK;
4035         lastq = (reg & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
4036                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
4037         maxq = lastq - firstq;
4038         for (i = 0; i <= maxq; i++) {
4039                 ret = i40e_disable_queue(hw, i);
4040                 if (ret != I40E_SUCCESS)
4041                         return ret;
4042         }
4043         return I40E_SUCCESS;
4044 }