lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_dev.h>
  51
  52 #include "i40e_logs.h"
  53 #include "i40e/i40e_register_x710_int.h"
  54 #include "i40e/i40e_prototype.h"
  55 #include "i40e/i40e_adminq_cmd.h"
  56 #include "i40e/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59 #include "i40e_pf.h"
  60
  61 /* Maximun number of MAC addresses */
  62 #define I40E_NUM_MACADDR_MAX       64
  63 #define I40E_CLEAR_PXE_WAIT_MS     200
  64
  65 /* Maximun number of capability elements */
  66 #define I40E_MAX_CAP_ELE_NUM       128
  67
  68 /* Wait count and inteval */
  69 #define I40E_CHK_Q_ENA_COUNT       1000
  70 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  71
  72 /* Maximun number of VSI */
  73 #define I40E_MAX_NUM_VSIS          (384UL)
  74
  75 /* Bit shift and mask */
  76 #define I40E_16_BIT_SHIFT 16
  77 #define I40E_16_BIT_MASK  0xFFFF
  78 #define I40E_32_BIT_SHIFT 32
  79 #define I40E_32_BIT_MASK  0xFFFFFFFF
  80 #define I40E_48_BIT_SHIFT 48
  81 #define I40E_48_BIT_MASK  0xFFFFFFFFFFFFULL
  82
  83 /* Default queue interrupt throttling time in microseconds*/
  84 #define I40E_ITR_INDEX_DEFAULT          0
  85 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  86 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  87
  88 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  89
  90 #define I40E_RSS_OFFLOAD_ALL ( \
  91         ETH_RSS_NONF_IPV4_UDP | \
  92         ETH_RSS_NONF_IPV4_TCP | \
  93         ETH_RSS_NONF_IPV4_SCTP | \
  94         ETH_RSS_NONF_IPV4_OTHER | \
  95         ETH_RSS_FRAG_IPV4 | \
  96         ETH_RSS_NONF_IPV6_UDP | \
  97         ETH_RSS_NONF_IPV6_TCP | \
  98         ETH_RSS_NONF_IPV6_SCTP | \
  99         ETH_RSS_NONF_IPV6_OTHER | \
 100         ETH_RSS_FRAG_IPV6 | \
 101         ETH_RSS_L2_PAYLOAD)
 102
 103 /* All bits of RSS hash enable */
 104 #define I40E_RSS_HENA_ALL ( \
 105         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
 106         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
 107         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
 108         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
 109         (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
 110         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
 111         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
 112         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
 113         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
 114         (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
 115         (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
 116         (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
 117         (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
 118         (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
 119
 120 static int eth_i40e_dev_init(\
 121                         __attribute__((unused)) struct eth_driver *eth_drv,
 122                         struct rte_eth_dev *eth_dev);
 123 static int i40e_dev_configure(struct rte_eth_dev *dev);
 124 static int i40e_dev_start(struct rte_eth_dev *dev);
 125 static void i40e_dev_stop(struct rte_eth_dev *dev);
 126 static void i40e_dev_close(struct rte_eth_dev *dev);
 127 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 128 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 129 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 130 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 131 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 132                                struct rte_eth_stats *stats);
 133 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 134 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 135                                             uint16_t queue_id,
 136                                             uint8_t stat_idx,
 137                                             uint8_t is_rx);
 138 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 139                               struct rte_eth_dev_info *dev_info);
 140 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 141                                 uint16_t vlan_id,
 142                                 int on);
 143 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 144 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 145 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 146                                       uint16_t queue,
 147                                       int on);
 148 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 149 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 150 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 151 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 152                               struct rte_eth_fc_conf *fc_conf);
 153 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 154                                        struct rte_eth_pfc_conf *pfc_conf);
 155 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 156                           struct ether_addr *mac_addr,
 157                           uint32_t index,
 158                           uint32_t pool);
 159 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 160 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 161                                     struct rte_eth_rss_reta *reta_conf);
 162 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 163                                    struct rte_eth_rss_reta *reta_conf);
 164
 165 static int i40e_get_cap(struct i40e_hw *hw);
 166 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 167 static int i40e_pf_setup(struct i40e_pf *pf);
 168 static int i40e_vsi_init(struct i40e_vsi *vsi);
 169 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 170                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 171 static void i40e_stat_update_48(struct i40e_hw *hw,
 172                                uint32_t hireg,
 173                                uint32_t loreg,
 174                                bool offset_loaded,
 175                                uint64_t *offset,
 176                                uint64_t *stat);
 177 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 178 static void i40e_dev_interrupt_handler(
 179                 __rte_unused struct rte_intr_handle *handle, void *param);
 180 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 181                                 uint32_t base, uint32_t num);
 182 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 183 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 184                         uint32_t base);
 185 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 186                         uint16_t num);
 187 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 188 static int i40e_veb_release(struct i40e_veb *veb);
 189 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 190                                                 struct i40e_vsi *vsi);
 191 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 192 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 193 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 194                                              struct i40e_macvlan_filter *mv_f,
 195                                              int num,
 196                                              struct ether_addr *addr);
 197 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 198                                              struct i40e_macvlan_filter *mv_f,
 199                                              int num,
 200                                              uint16_t vlan);
 201 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 202 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 203                                     struct rte_eth_rss_conf *rss_conf);
 204 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 205                                       struct rte_eth_rss_conf *rss_conf);
 206
 207 /* Default hash key buffer for RSS */
 208 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
 209
 210 static struct rte_pci_id pci_id_i40e_map[] = {
 211 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 212 #include "rte_pci_dev_ids.h"
 213 { .vendor_id = 0, /* sentinel */ },
 214 };
 215
 216 static struct eth_dev_ops i40e_eth_dev_ops = {
 217         .dev_configure                = i40e_dev_configure,
 218         .dev_start                    = i40e_dev_start,
 219         .dev_stop                     = i40e_dev_stop,
 220         .dev_close                    = i40e_dev_close,
 221         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 222         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 223         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 224         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 225         .link_update                  = i40e_dev_link_update,
 226         .stats_get                    = i40e_dev_stats_get,
 227         .stats_reset                  = i40e_dev_stats_reset,
 228         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 229         .dev_infos_get                = i40e_dev_info_get,
 230         .vlan_filter_set              = i40e_vlan_filter_set,
 231         .vlan_tpid_set                = i40e_vlan_tpid_set,
 232         .vlan_offload_set             = i40e_vlan_offload_set,
 233         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 234         .vlan_pvid_set                = i40e_vlan_pvid_set,
 235         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 236         .rx_queue_release             = i40e_dev_rx_queue_release,
 237         .rx_queue_count               = i40e_dev_rx_queue_count,
 238         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 239         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 240         .tx_queue_release             = i40e_dev_tx_queue_release,
 241         .dev_led_on                   = i40e_dev_led_on,
 242         .dev_led_off                  = i40e_dev_led_off,
 243         .flow_ctrl_set                = i40e_flow_ctrl_set,
 244         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 245         .mac_addr_add                 = i40e_macaddr_add,
 246         .mac_addr_remove              = i40e_macaddr_remove,
 247         .reta_update                  = i40e_dev_rss_reta_update,
 248         .reta_query                   = i40e_dev_rss_reta_query,
 249         .rss_hash_update              = i40e_dev_rss_hash_update,
 250         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 251 };
 252
 253 static struct eth_driver rte_i40e_pmd = {
 254         {
 255                 .name = "rte_i40e_pmd",
 256                 .id_table = pci_id_i40e_map,
 257                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 258         },
 259         .eth_dev_init = eth_i40e_dev_init,
 260         .dev_private_size = sizeof(struct i40e_adapter),
 261 };
 262
 263 static inline int
 264 i40e_prev_power_of_2(int n)
 265 {
 266        int p = n;
 267
 268        --p;
 269        p |= p >> 1;
 270        p |= p >> 2;
 271        p |= p >> 4;
 272        p |= p >> 8;
 273        p |= p >> 16;
 274        if (p == (n - 1))
 275                return n;
 276        p >>= 1;
 277
 278        return ++p;
 279 }
 280
 281 static inline int
 282 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 283                                      struct rte_eth_link *link)
 284 {
 285         struct rte_eth_link *dst = link;
 286         struct rte_eth_link *src = &(dev->data->dev_link);
 287
 288         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 289                                         *(uint64_t *)src) == 0)
 290                 return -1;
 291
 292         return 0;
 293 }
 294
 295 static inline int
 296 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 297                                       struct rte_eth_link *link)
 298 {
 299         struct rte_eth_link *dst = &(dev->data->dev_link);
 300         struct rte_eth_link *src = link;
 301
 302         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 303                                         *(uint64_t *)src) == 0)
 304                 return -1;
 305
 306         return 0;
 307 }
 308
 309 /*
 310  * Driver initialization routine.
 311  * Invoked once at EAL init time.
 312  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 313  */
 314 static int
 315 rte_i40e_pmd_init(const char *name __rte_unused,
 316                   const char *params __rte_unused)
 317 {
 318         PMD_INIT_FUNC_TRACE();
 319         rte_eth_driver_register(&rte_i40e_pmd);
 320
 321         return 0;
 322 }
 323
 324 static struct rte_driver rte_i40e_driver = {
 325         .type = PMD_PDEV,
 326         .init = rte_i40e_pmd_init,
 327 };
 328
 329 PMD_REGISTER_DRIVER(rte_i40e_driver);
 330
 331 static int
 332 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 333                   struct rte_eth_dev *dev)
 334 {
 335         struct rte_pci_device *pci_dev;
 336         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 337         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 338         struct i40e_vsi *vsi;
 339         int ret;
 340         uint32_t len;
 341         uint8_t aq_fail = 0;
 342
 343         PMD_INIT_FUNC_TRACE();
 344
 345         dev->dev_ops = &i40e_eth_dev_ops;
 346         dev->rx_pkt_burst = i40e_recv_pkts;
 347         dev->tx_pkt_burst = i40e_xmit_pkts;
 348
 349         /* for secondary processes, we don't initialise any further as primary
 350          * has already done this work. Only check we don't need a different
 351          * RX function */
 352         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 353                 if (dev->data->scattered_rx)
 354                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 355                 return 0;
 356         }
 357         pci_dev = dev->pci_dev;
 358         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 359         pf->adapter->eth_dev = dev;
 360         pf->dev_data = dev->data;
 361
 362         hw->back = I40E_PF_TO_ADAPTER(pf);
 363         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 364         if (!hw->hw_addr) {
 365                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 366                                         "as address is NULL\n");
 367                 return -ENODEV;
 368         }
 369
 370         hw->vendor_id = pci_dev->id.vendor_id;
 371         hw->device_id = pci_dev->id.device_id;
 372         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 373         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 374         hw->bus.device = pci_dev->addr.devid;
 375         hw->bus.func = pci_dev->addr.function;
 376
 377         /* Make sure all is clean before doing PF reset */
 378         i40e_clear_hw(hw);
 379
 380         /* Reset here to make sure all is clean for each PF */
 381         ret = i40e_pf_reset(hw);
 382         if (ret) {
 383                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 384                 return ret;
 385         }
 386
 387         /* Initialize the shared code (base driver) */
 388         ret = i40e_init_shared_code(hw);
 389         if (ret) {
 390                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 391                 return ret;
 392         }
 393
 394         /* Initialize the parameters for adminq */
 395         i40e_init_adminq_parameter(hw);
 396         ret = i40e_init_adminq(hw);
 397         if (ret != I40E_SUCCESS) {
 398                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 399                 return -EIO;
 400         }
 401         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM "
 402                         "%02d.%02d.%02d eetrack %04x\n",
 403                         hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 404                         hw->aq.api_maj_ver, hw->aq.api_min_ver,
 405                         ((hw->nvm.version >> 12) & 0xf),
 406                         ((hw->nvm.version >> 4) & 0xff),
 407                         (hw->nvm.version & 0xf), hw->nvm.eetrack);
 408
 409         /* Disable LLDP */
 410         ret = i40e_aq_stop_lldp(hw, true, NULL);
 411         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 412                 PMD_INIT_LOG(INFO, "Failed to stop lldp\n");
 413
 414         /* Clear PXE mode */
 415         i40e_clear_pxe_mode(hw);
 416
 417         /* Get hw capabilities */
 418         ret = i40e_get_cap(hw);
 419         if (ret != I40E_SUCCESS) {
 420                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 421                 goto err_get_capabilities;
 422         }
 423
 424         /* Initialize parameters for PF */
 425         ret = i40e_pf_parameter_init(dev);
 426         if (ret != 0) {
 427                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 428                 goto err_parameter_init;
 429         }
 430
 431         /* Initialize the queue management */
 432         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 433         if (ret < 0) {
 434                 PMD_INIT_LOG(ERR, "Failed to init queue pool\n");
 435                 goto err_qp_pool_init;
 436         }
 437         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 438                                 hw->func_caps.num_msix_vectors - 1);
 439         if (ret < 0) {
 440                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool\n");
 441                 goto err_msix_pool_init;
 442         }
 443
 444         /* Initialize lan hmc */
 445         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 446                                 hw->func_caps.num_rx_qp, 0, 0);
 447         if (ret != I40E_SUCCESS) {
 448                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 449                 goto err_init_lan_hmc;
 450         }
 451
 452         /* Configure lan hmc */
 453         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 454         if (ret != I40E_SUCCESS) {
 455                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 456                 goto err_configure_lan_hmc;
 457         }
 458
 459         /* Get and check the mac address */
 460         i40e_get_mac_addr(hw, hw->mac.addr);
 461         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 462                 PMD_INIT_LOG(ERR, "mac address is not valid");
 463                 ret = -EIO;
 464                 goto err_get_mac_addr;
 465         }
 466         /* Copy the permanent MAC address */
 467         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 468                         (struct ether_addr *) hw->mac.perm_addr);
 469
 470         /* Disable flow control */
 471         hw->fc.requested_mode = I40E_FC_NONE;
 472         i40e_set_fc(hw, &aq_fail, TRUE);
 473
 474         /* PF setup, which includes VSI setup */
 475         ret = i40e_pf_setup(pf);
 476         if (ret) {
 477                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 478                 goto err_setup_pf_switch;
 479         }
 480
 481         vsi = pf->main_vsi;
 482
 483         /* Disable double vlan by default */
 484         i40e_vsi_config_double_vlan(vsi, FALSE);
 485
 486         if (!vsi->max_macaddrs)
 487                 len = ETHER_ADDR_LEN;
 488         else
 489                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 490
 491         /* Should be after VSI initialized */
 492         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 493         if (!dev->data->mac_addrs) {
 494                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 495                                         "for storing mac address");
 496                 goto err_get_mac_addr;
 497         }
 498         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 499                                         &dev->data->mac_addrs[0]);
 500
 501         /* initialize pf host driver to setup SRIOV resource if applicable */
 502         i40e_pf_host_init(dev);
 503
 504         /* register callback func to eal lib */
 505         rte_intr_callback_register(&(pci_dev->intr_handle),
 506                 i40e_dev_interrupt_handler, (void *)dev);
 507
 508         /* configure and enable device interrupt */
 509         i40e_pf_config_irq0(hw);
 510         i40e_pf_enable_irq0(hw);
 511
 512         /* enable uio intr after callback register */
 513         rte_intr_enable(&(pci_dev->intr_handle));
 514
 515         return 0;
 516
 517 err_setup_pf_switch:
 518         rte_free(pf->main_vsi);
 519 err_get_mac_addr:
 520 err_configure_lan_hmc:
 521         (void)i40e_shutdown_lan_hmc(hw);
 522 err_init_lan_hmc:
 523         i40e_res_pool_destroy(&pf->msix_pool);
 524 err_msix_pool_init:
 525         i40e_res_pool_destroy(&pf->qp_pool);
 526 err_qp_pool_init:
 527 err_parameter_init:
 528 err_get_capabilities:
 529         (void)i40e_shutdown_adminq(hw);
 530
 531         return ret;
 532 }
 533
 534 static int
 535 i40e_dev_configure(struct rte_eth_dev *dev)
 536 {
 537         return i40e_dev_init_vlan(dev);
 538 }
 539
 540 void
 541 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 542 {
 543         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 544         uint16_t msix_vect = vsi->msix_intr;
 545         uint16_t i;
 546
 547         for (i = 0; i < vsi->nb_qps; i++) {
 548                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 549                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 550                 rte_wmb();
 551         }
 552
 553         if (vsi->type != I40E_VSI_SRIOV) {
 554                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 555                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 556                                 msix_vect - 1), 0);
 557         } else {
 558                 uint32_t reg;
 559                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 560                         vsi->user_param + (msix_vect - 1);
 561
 562                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 563         }
 564         I40E_WRITE_FLUSH(hw);
 565 }
 566
 567 static inline uint16_t
 568 i40e_calc_itr_interval(int16_t interval)
 569 {
 570         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 571                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 572
 573         /* Convert to hardware count, as writing each 1 represents 2 us */
 574         return (interval/2);
 575 }
 576
 577 void
 578 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 579 {
 580         uint32_t val;
 581         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 582         uint16_t msix_vect = vsi->msix_intr;
 583         uint16_t interval = i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 584         int i;
 585
 586         for (i = 0; i < vsi->nb_qps; i++)
 587                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 588
 589         /* Bind all RX queues to allocated MSIX interrupt */
 590         for (i = 0; i < vsi->nb_qps; i++) {
 591                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 592                         (interval << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
 593                         ((vsi->base_queue + i + 1) <<
 594                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 595                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 596                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 597
 598                 if (i == vsi->nb_qps - 1)
 599                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 600                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 601         }
 602
 603         /* Write first RX queue to Link list register as the head element */
 604         if (vsi->type != I40E_VSI_SRIOV) {
 605                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 606                         (vsi->base_queue << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 607                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 608
 609                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 610                                 msix_vect - 1), interval);
 611
 612                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 613                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 614                                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 615         }
 616         else {
 617                 uint32_t reg;
 618                 /* num_msix_vectors_vf needs to minus irq0 */
 619                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 620                         vsi->user_param + (msix_vect - 1);
 621
 622                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
 623                         (vsi->base_queue << I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 624                         (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 625         }
 626
 627         I40E_WRITE_FLUSH(hw);
 628 }
 629
 630 static void
 631 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 632 {
 633         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 634         uint16_t interval = i40e_calc_itr_interval(\
 635                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 636
 637         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 638                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 639                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 640                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 641                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 642 }
 643
 644 static void
 645 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 646 {
 647         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 648
 649         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 650 }
 651
 652 static int
 653 i40e_dev_start(struct rte_eth_dev *dev)
 654 {
 655         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 656         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 657         struct i40e_vsi *vsi = pf->main_vsi;
 658         int ret;
 659
 660         /* Initialize VSI */
 661         ret = i40e_vsi_init(vsi);
 662         if (ret != I40E_SUCCESS) {
 663                 PMD_DRV_LOG(ERR, "Failed to init VSI\n");
 664                 goto err_up;
 665         }
 666
 667         /* Map queues with MSIX interrupt */
 668         i40e_vsi_queues_bind_intr(vsi);
 669         i40e_vsi_enable_queues_intr(vsi);
 670
 671         /* Enable all queues which have been configured */
 672         ret = i40e_vsi_switch_queues(vsi, TRUE);
 673         if (ret != I40E_SUCCESS) {
 674                 PMD_DRV_LOG(ERR, "Failed to enable VSI\n");
 675                 goto err_up;
 676         }
 677
 678         /* Enable receiving broadcast packets */
 679         if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
 680                 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
 681                 if (ret != I40E_SUCCESS)
 682                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast\n");
 683         }
 684
 685         return I40E_SUCCESS;
 686
 687 err_up:
 688         i40e_vsi_switch_queues(vsi, FALSE);
 689         i40e_dev_clear_queues(dev);
 690
 691         return ret;
 692 }
 693
 694 static void
 695 i40e_dev_stop(struct rte_eth_dev *dev)
 696 {
 697         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 698         struct i40e_vsi *vsi = pf->main_vsi;
 699
 700         /* Disable all queues */
 701         i40e_vsi_switch_queues(vsi, FALSE);
 702
 703         /* Clear all queues and release memory */
 704         i40e_dev_clear_queues(dev);
 705
 706         /* un-map queues with interrupt registers */
 707         i40e_vsi_disable_queues_intr(vsi);
 708         i40e_vsi_queues_unbind_intr(vsi);
 709 }
 710
 711 static void
 712 i40e_dev_close(struct rte_eth_dev *dev)
 713 {
 714         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 715         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 716         uint32_t reg;
 717
 718         PMD_INIT_FUNC_TRACE();
 719
 720         i40e_dev_stop(dev);
 721
 722         /* Disable interrupt */
 723         i40e_pf_disable_irq0(hw);
 724         rte_intr_disable(&(dev->pci_dev->intr_handle));
 725
 726         /* shutdown and destroy the HMC */
 727         i40e_shutdown_lan_hmc(hw);
 728
 729         /* release all the existing VSIs and VEBs */
 730         i40e_vsi_release(pf->main_vsi);
 731
 732         /* shutdown the adminq */
 733         i40e_aq_queue_shutdown(hw, true);
 734         i40e_shutdown_adminq(hw);
 735
 736         i40e_res_pool_destroy(&pf->qp_pool);
 737         i40e_res_pool_destroy(&pf->msix_pool);
 738
 739         /* force a PF reset to clean anything leftover */
 740         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 741         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 742                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 743         I40E_WRITE_FLUSH(hw);
 744 }
 745
 746 static void
 747 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 748 {
 749         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 750         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 751         struct i40e_vsi *vsi = pf->main_vsi;
 752         int status;
 753
 754         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 755                                                         true, NULL);
 756         if (status != I40E_SUCCESS)
 757                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous\n");
 758 }
 759
 760 static void
 761 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
 762 {
 763         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 764         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 765         struct i40e_vsi *vsi = pf->main_vsi;
 766         int status;
 767
 768         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 769                                                         false, NULL);
 770         if (status != I40E_SUCCESS)
 771                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous\n");
 772 }
 773
 774 static void
 775 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
 776 {
 777         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 778         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 779         struct i40e_vsi *vsi = pf->main_vsi;
 780         int ret;
 781
 782         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
 783         if (ret != I40E_SUCCESS)
 784                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous\n");
 785 }
 786
 787 static void
 788 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
 789 {
 790         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 791         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 792         struct i40e_vsi *vsi = pf->main_vsi;
 793         int ret;
 794
 795         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
 796                                 vsi->seid, FALSE, NULL);
 797         if (ret != I40E_SUCCESS)
 798                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous\n");
 799 }
 800
 801 int
 802 i40e_dev_link_update(struct rte_eth_dev *dev,
 803                      __rte_unused int wait_to_complete)
 804 {
 805         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 806         struct i40e_link_status link_status;
 807         struct rte_eth_link link, old;
 808         int status;
 809
 810         memset(&link, 0, sizeof(link));
 811         memset(&old, 0, sizeof(old));
 812         memset(&link_status, 0, sizeof(link_status));
 813         rte_i40e_dev_atomic_read_link_status(dev, &old);
 814
 815         /* Get link status information from hardware */
 816         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
 817         if (status != I40E_SUCCESS) {
 818                 link.link_speed = ETH_LINK_SPEED_100;
 819                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
 820                 PMD_DRV_LOG(ERR, "Failed to get link info\n");
 821                 goto out;
 822         }
 823
 824         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
 825
 826         if (!link.link_status)
 827                 goto out;
 828
 829         /* i40e uses full duplex only */
 830         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 831
 832         /* Parse the link status */
 833         switch (link_status.link_speed) {
 834         case I40E_LINK_SPEED_100MB:
 835                 link.link_speed = ETH_LINK_SPEED_100;
 836                 break;
 837         case I40E_LINK_SPEED_1GB:
 838                 link.link_speed = ETH_LINK_SPEED_1000;
 839                 break;
 840         case I40E_LINK_SPEED_10GB:
 841                 link.link_speed = ETH_LINK_SPEED_10G;
 842                 break;
 843         case I40E_LINK_SPEED_20GB:
 844                 link.link_speed = ETH_LINK_SPEED_20G;
 845                 break;
 846         case I40E_LINK_SPEED_40GB:
 847                 link.link_speed = ETH_LINK_SPEED_40G;
 848                 break;
 849         default:
 850                 link.link_speed = ETH_LINK_SPEED_100;
 851                 break;
 852         }
 853
 854 out:
 855         rte_i40e_dev_atomic_write_link_status(dev, &link);
 856         if (link.link_status == old.link_status)
 857                 return -1;
 858
 859         return 0;
 860 }
 861
 862 /* Get all the statistics of a VSI */
 863 void
 864 i40e_update_vsi_stats(struct i40e_vsi *vsi)
 865 {
 866         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
 867         struct i40e_eth_stats *nes = &vsi->eth_stats;
 868         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 869         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
 870
 871         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
 872                             vsi->offset_loaded, &oes->rx_bytes,
 873                             &nes->rx_bytes);
 874         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
 875                             vsi->offset_loaded, &oes->rx_unicast,
 876                             &nes->rx_unicast);
 877         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
 878                             vsi->offset_loaded, &oes->rx_multicast,
 879                             &nes->rx_multicast);
 880         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
 881                             vsi->offset_loaded, &oes->rx_broadcast,
 882                             &nes->rx_broadcast);
 883         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
 884                             &oes->rx_discards, &nes->rx_discards);
 885         /* GLV_REPC not supported */
 886         /* GLV_RMPC not supported */
 887         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
 888                             &oes->rx_unknown_protocol,
 889                             &nes->rx_unknown_protocol);
 890         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
 891                             vsi->offset_loaded, &oes->tx_bytes,
 892                             &nes->tx_bytes);
 893         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
 894                             vsi->offset_loaded, &oes->tx_unicast,
 895                             &nes->tx_unicast);
 896         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
 897                             vsi->offset_loaded, &oes->tx_multicast,
 898                             &nes->tx_multicast);
 899         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
 900                             vsi->offset_loaded,  &oes->tx_broadcast,
 901                             &nes->tx_broadcast);
 902         /* GLV_TDPC not supported */
 903         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
 904                             &oes->tx_errors, &nes->tx_errors);
 905         vsi->offset_loaded = true;
 906
 907 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
 908         printf("***************** VSI[%u] stats start *******************\n",
 909                                                                 vsi->vsi_id);
 910         printf("rx_bytes:            %lu\n", nes->rx_bytes);
 911         printf("rx_unicast:          %lu\n", nes->rx_unicast);
 912         printf("rx_multicast:        %lu\n", nes->rx_multicast);
 913         printf("rx_broadcast:        %lu\n", nes->rx_broadcast);
 914         printf("rx_discards:         %lu\n", nes->rx_discards);
 915         printf("rx_unknown_protocol: %lu\n", nes->rx_unknown_protocol);
 916         printf("tx_bytes:            %lu\n", nes->tx_bytes);
 917         printf("tx_unicast:          %lu\n", nes->tx_unicast);
 918         printf("tx_multicast:        %lu\n", nes->tx_multicast);
 919         printf("tx_broadcast:        %lu\n", nes->tx_broadcast);
 920         printf("tx_discards:         %lu\n", nes->tx_discards);
 921         printf("tx_errors:           %lu\n", nes->tx_errors);
 922         printf("***************** VSI[%u] stats end *******************\n",
 923                                                                 vsi->vsi_id);
 924 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
 925 }
 926
 927 /* Get all statistics of a port */
 928 static void
 929 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 930 {
 931         uint32_t i;
 932         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 933         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 934         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
 935         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
 936
 937         /* Get statistics of struct i40e_eth_stats */
 938         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
 939                             I40E_GLPRT_GORCL(hw->port),
 940                             pf->offset_loaded, &os->eth.rx_bytes,
 941                             &ns->eth.rx_bytes);
 942         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
 943                             I40E_GLPRT_UPRCL(hw->port),
 944                             pf->offset_loaded, &os->eth.rx_unicast,
 945                             &ns->eth.rx_unicast);
 946         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
 947                             I40E_GLPRT_MPRCL(hw->port),
 948                             pf->offset_loaded, &os->eth.rx_multicast,
 949                             &ns->eth.rx_multicast);
 950         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
 951                             I40E_GLPRT_BPRCL(hw->port),
 952                             pf->offset_loaded, &os->eth.rx_broadcast,
 953                             &ns->eth.rx_broadcast);
 954         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
 955                             pf->offset_loaded, &os->eth.rx_discards,
 956                             &ns->eth.rx_discards);
 957         /* GLPRT_REPC not supported */
 958         /* GLPRT_RMPC not supported */
 959         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
 960                             pf->offset_loaded,
 961                             &os->eth.rx_unknown_protocol,
 962                             &ns->eth.rx_unknown_protocol);
 963         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
 964                             I40E_GLPRT_GOTCL(hw->port),
 965                             pf->offset_loaded, &os->eth.tx_bytes,
 966                             &ns->eth.tx_bytes);
 967         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
 968                             I40E_GLPRT_UPTCL(hw->port),
 969                             pf->offset_loaded, &os->eth.tx_unicast,
 970                             &ns->eth.tx_unicast);
 971         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
 972                             I40E_GLPRT_MPTCL(hw->port),
 973                             pf->offset_loaded, &os->eth.tx_multicast,
 974                             &ns->eth.tx_multicast);
 975         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
 976                             I40E_GLPRT_BPTCL(hw->port),
 977                             pf->offset_loaded, &os->eth.tx_broadcast,
 978                             &ns->eth.tx_broadcast);
 979         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
 980                             pf->offset_loaded, &os->eth.tx_discards,
 981                             &ns->eth.tx_discards);
 982         /* GLPRT_TEPC not supported */
 983
 984         /* additional port specific stats */
 985         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
 986                             pf->offset_loaded, &os->tx_dropped_link_down,
 987                             &ns->tx_dropped_link_down);
 988         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
 989                             pf->offset_loaded, &os->crc_errors,
 990                             &ns->crc_errors);
 991         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
 992                             pf->offset_loaded, &os->illegal_bytes,
 993                             &ns->illegal_bytes);
 994         /* GLPRT_ERRBC not supported */
 995         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
 996                             pf->offset_loaded, &os->mac_local_faults,
 997                             &ns->mac_local_faults);
 998         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
 999                             pf->offset_loaded, &os->mac_remote_faults,
1000                             &ns->mac_remote_faults);
1001         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1002                             pf->offset_loaded, &os->rx_length_errors,
1003                             &ns->rx_length_errors);
1004         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1005                             pf->offset_loaded, &os->link_xon_rx,
1006                             &ns->link_xon_rx);
1007         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1008                             pf->offset_loaded, &os->link_xoff_rx,
1009                             &ns->link_xoff_rx);
1010         for (i = 0; i < 8; i++) {
1011                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1012                                     pf->offset_loaded,
1013                                     &os->priority_xon_rx[i],
1014                                     &ns->priority_xon_rx[i]);
1015                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1016                                     pf->offset_loaded,
1017                                     &os->priority_xoff_rx[i],
1018                                     &ns->priority_xoff_rx[i]);
1019         }
1020         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1021                             pf->offset_loaded, &os->link_xon_tx,
1022                             &ns->link_xon_tx);
1023         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1024                             pf->offset_loaded, &os->link_xoff_tx,
1025                             &ns->link_xoff_tx);
1026         for (i = 0; i < 8; i++) {
1027                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1028                                     pf->offset_loaded,
1029                                     &os->priority_xon_tx[i],
1030                                     &ns->priority_xon_tx[i]);
1031                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1032                                     pf->offset_loaded,
1033                                     &os->priority_xoff_tx[i],
1034                                     &ns->priority_xoff_tx[i]);
1035                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1036                                     pf->offset_loaded,
1037                                     &os->priority_xon_2_xoff[i],
1038                                     &ns->priority_xon_2_xoff[i]);
1039         }
1040         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1041                             I40E_GLPRT_PRC64L(hw->port),
1042                             pf->offset_loaded, &os->rx_size_64,
1043                             &ns->rx_size_64);
1044         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1045                             I40E_GLPRT_PRC127L(hw->port),
1046                             pf->offset_loaded, &os->rx_size_127,
1047                             &ns->rx_size_127);
1048         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1049                             I40E_GLPRT_PRC255L(hw->port),
1050                             pf->offset_loaded, &os->rx_size_255,
1051                             &ns->rx_size_255);
1052         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1053                             I40E_GLPRT_PRC511L(hw->port),
1054                             pf->offset_loaded, &os->rx_size_511,
1055                             &ns->rx_size_511);
1056         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1057                             I40E_GLPRT_PRC1023L(hw->port),
1058                             pf->offset_loaded, &os->rx_size_1023,
1059                             &ns->rx_size_1023);
1060         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1061                             I40E_GLPRT_PRC1522L(hw->port),
1062                             pf->offset_loaded, &os->rx_size_1522,
1063                             &ns->rx_size_1522);
1064         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1065                             I40E_GLPRT_PRC9522L(hw->port),
1066                             pf->offset_loaded, &os->rx_size_big,
1067                             &ns->rx_size_big);
1068         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1069                             pf->offset_loaded, &os->rx_undersize,
1070                             &ns->rx_undersize);
1071         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1072                             pf->offset_loaded, &os->rx_fragments,
1073                             &ns->rx_fragments);
1074         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1075                             pf->offset_loaded, &os->rx_oversize,
1076                             &ns->rx_oversize);
1077         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1078                             pf->offset_loaded, &os->rx_jabber,
1079                             &ns->rx_jabber);
1080         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1081                             I40E_GLPRT_PTC64L(hw->port),
1082                             pf->offset_loaded, &os->tx_size_64,
1083                             &ns->tx_size_64);
1084         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1085                             I40E_GLPRT_PTC127L(hw->port),
1086                             pf->offset_loaded, &os->tx_size_127,
1087                             &ns->tx_size_127);
1088         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1089                             I40E_GLPRT_PTC255L(hw->port),
1090                             pf->offset_loaded, &os->tx_size_255,
1091                             &ns->tx_size_255);
1092         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1093                             I40E_GLPRT_PTC511L(hw->port),
1094                             pf->offset_loaded, &os->tx_size_511,
1095                             &ns->tx_size_511);
1096         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1097                             I40E_GLPRT_PTC1023L(hw->port),
1098                             pf->offset_loaded, &os->tx_size_1023,
1099                             &ns->tx_size_1023);
1100         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1101                             I40E_GLPRT_PTC1522L(hw->port),
1102                             pf->offset_loaded, &os->tx_size_1522,
1103                             &ns->tx_size_1522);
1104         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1105                             I40E_GLPRT_PTC9522L(hw->port),
1106                             pf->offset_loaded, &os->tx_size_big,
1107                             &ns->tx_size_big);
1108         /* GLPRT_MSPDC not supported */
1109         /* GLPRT_XEC not supported */
1110
1111         pf->offset_loaded = true;
1112
1113         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1114                                                 ns->eth.rx_broadcast;
1115         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1116                                                 ns->eth.tx_broadcast;
1117         stats->ibytes   = ns->eth.rx_bytes;
1118         stats->obytes   = ns->eth.tx_bytes;
1119         stats->oerrors  = ns->eth.tx_errors;
1120         stats->imcasts  = ns->eth.rx_multicast;
1121
1122         if (pf->main_vsi)
1123                 i40e_update_vsi_stats(pf->main_vsi);
1124
1125 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
1126         printf("***************** PF stats start *******************\n");
1127         printf("rx_bytes:            %lu\n", ns->eth.rx_bytes);
1128         printf("rx_unicast:          %lu\n", ns->eth.rx_unicast);
1129         printf("rx_multicast:        %lu\n", ns->eth.rx_multicast);
1130         printf("rx_broadcast:        %lu\n", ns->eth.rx_broadcast);
1131         printf("rx_discards:         %lu\n", ns->eth.rx_discards);
1132         printf("rx_unknown_protocol: %lu\n", ns->eth.rx_unknown_protocol);
1133         printf("tx_bytes:            %lu\n", ns->eth.tx_bytes);
1134         printf("tx_unicast:          %lu\n", ns->eth.tx_unicast);
1135         printf("tx_multicast:        %lu\n", ns->eth.tx_multicast);
1136         printf("tx_broadcast:        %lu\n", ns->eth.tx_broadcast);
1137         printf("tx_discards:         %lu\n", ns->eth.tx_discards);
1138         printf("tx_errors:           %lu\n", ns->eth.tx_errors);
1139
1140         printf("tx_dropped_link_down:     %lu\n", ns->tx_dropped_link_down);
1141         printf("crc_errors:               %lu\n", ns->crc_errors);
1142         printf("illegal_bytes:            %lu\n", ns->illegal_bytes);
1143         printf("error_bytes:              %lu\n", ns->error_bytes);
1144         printf("mac_local_faults:         %lu\n", ns->mac_local_faults);
1145         printf("mac_remote_faults:        %lu\n", ns->mac_remote_faults);
1146         printf("rx_length_errors:         %lu\n", ns->rx_length_errors);
1147         printf("link_xon_rx:              %lu\n", ns->link_xon_rx);
1148         printf("link_xoff_rx:             %lu\n", ns->link_xoff_rx);
1149         for (i = 0; i < 8; i++) {
1150                 printf("priority_xon_rx[%d]:      %lu\n",
1151                                 i, ns->priority_xon_rx[i]);
1152                 printf("priority_xoff_rx[%d]:     %lu\n",
1153                                 i, ns->priority_xoff_rx[i]);
1154         }
1155         printf("link_xon_tx:              %lu\n", ns->link_xon_tx);
1156         printf("link_xoff_tx:             %lu\n", ns->link_xoff_tx);
1157         for (i = 0; i < 8; i++) {
1158                 printf("priority_xon_tx[%d]:      %lu\n",
1159                                 i, ns->priority_xon_tx[i]);
1160                 printf("priority_xoff_tx[%d]:     %lu\n",
1161                                 i, ns->priority_xoff_tx[i]);
1162                 printf("priority_xon_2_xoff[%d]:  %lu\n",
1163                                 i, ns->priority_xon_2_xoff[i]);
1164         }
1165         printf("rx_size_64:               %lu\n", ns->rx_size_64);
1166         printf("rx_size_127:              %lu\n", ns->rx_size_127);
1167         printf("rx_size_255:              %lu\n", ns->rx_size_255);
1168         printf("rx_size_511:              %lu\n", ns->rx_size_511);
1169         printf("rx_size_1023:             %lu\n", ns->rx_size_1023);
1170         printf("rx_size_1522:             %lu\n", ns->rx_size_1522);
1171         printf("rx_size_big:              %lu\n", ns->rx_size_big);
1172         printf("rx_undersize:             %lu\n", ns->rx_undersize);
1173         printf("rx_fragments:             %lu\n", ns->rx_fragments);
1174         printf("rx_oversize:              %lu\n", ns->rx_oversize);
1175         printf("rx_jabber:                %lu\n", ns->rx_jabber);
1176         printf("tx_size_64:               %lu\n", ns->tx_size_64);
1177         printf("tx_size_127:              %lu\n", ns->tx_size_127);
1178         printf("tx_size_255:              %lu\n", ns->tx_size_255);
1179         printf("tx_size_511:              %lu\n", ns->tx_size_511);
1180         printf("tx_size_1023:             %lu\n", ns->tx_size_1023);
1181         printf("tx_size_1522:             %lu\n", ns->tx_size_1522);
1182         printf("tx_size_big:              %lu\n", ns->tx_size_big);
1183         printf("mac_short_packet_dropped: %lu\n",
1184                         ns->mac_short_packet_dropped);
1185         printf("checksum_error:           %lu\n", ns->checksum_error);
1186         printf("***************** PF stats end ********************\n");
1187 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
1188 }
1189
1190 /* Reset the statistics */
1191 static void
1192 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1193 {
1194         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1195
1196         /* It results in reloading the start point of each counter */
1197         pf->offset_loaded = false;
1198 }
1199
1200 static int
1201 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1202                                  __rte_unused uint16_t queue_id,
1203                                  __rte_unused uint8_t stat_idx,
1204                                  __rte_unused uint8_t is_rx)
1205 {
1206         PMD_INIT_FUNC_TRACE();
1207
1208         return -ENOSYS;
1209 }
1210
1211 static void
1212 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1213 {
1214         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1215         struct i40e_vsi *vsi = pf->main_vsi;
1216
1217         dev_info->max_rx_queues = vsi->nb_qps;
1218         dev_info->max_tx_queues = vsi->nb_qps;
1219         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1220         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1221         dev_info->max_mac_addrs = vsi->max_macaddrs;
1222         dev_info->max_vfs = dev->pci_dev->max_vfs;
1223         dev_info->rx_offload_capa =
1224                 DEV_RX_OFFLOAD_VLAN_STRIP |
1225                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1226                 DEV_RX_OFFLOAD_UDP_CKSUM |
1227                 DEV_RX_OFFLOAD_TCP_CKSUM;
1228         dev_info->tx_offload_capa =
1229                 DEV_TX_OFFLOAD_VLAN_INSERT |
1230                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1231                 DEV_TX_OFFLOAD_UDP_CKSUM |
1232                 DEV_TX_OFFLOAD_TCP_CKSUM |
1233                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1234 }
1235
1236 static int
1237 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1238 {
1239         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1240         struct i40e_vsi *vsi = pf->main_vsi;
1241         PMD_INIT_FUNC_TRACE();
1242
1243         if (on)
1244                 return i40e_vsi_add_vlan(vsi, vlan_id);
1245         else
1246                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1247 }
1248
1249 static void
1250 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1251                    __rte_unused uint16_t tpid)
1252 {
1253         PMD_INIT_FUNC_TRACE();
1254 }
1255
1256 static void
1257 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1258 {
1259         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1260         struct i40e_vsi *vsi = pf->main_vsi;
1261
1262         if (mask & ETH_VLAN_STRIP_MASK) {
1263                 /* Enable or disable VLAN stripping */
1264                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1265                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1266                 else
1267                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1268         }
1269
1270         if (mask & ETH_VLAN_EXTEND_MASK) {
1271                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1272                         i40e_vsi_config_double_vlan(vsi, TRUE);
1273                 else
1274                         i40e_vsi_config_double_vlan(vsi, FALSE);
1275         }
1276 }
1277
1278 static void
1279 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1280                           __rte_unused uint16_t queue,
1281                           __rte_unused int on)
1282 {
1283         PMD_INIT_FUNC_TRACE();
1284 }
1285
1286 static int
1287 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1288 {
1289         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1290         struct i40e_vsi *vsi = pf->main_vsi;
1291         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1292         struct i40e_vsi_vlan_pvid_info info;
1293
1294         memset(&info, 0, sizeof(info));
1295         info.on = on;
1296         if (info.on)
1297                 info.config.pvid = pvid;
1298         else {
1299                 info.config.reject.tagged =
1300                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1301                 info.config.reject.untagged =
1302                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1303         }
1304
1305         return i40e_vsi_vlan_pvid_set(vsi, &info);
1306 }
1307
1308 static int
1309 i40e_dev_led_on(struct rte_eth_dev *dev)
1310 {
1311         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1312         uint32_t mode = i40e_led_get(hw);
1313
1314         if (mode == 0)
1315                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1316
1317         return 0;
1318 }
1319
1320 static int
1321 i40e_dev_led_off(struct rte_eth_dev *dev)
1322 {
1323         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1324         uint32_t mode = i40e_led_get(hw);
1325
1326         if (mode != 0)
1327                 i40e_led_set(hw, 0, false);
1328
1329         return 0;
1330 }
1331
1332 static int
1333 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1334                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1335 {
1336         PMD_INIT_FUNC_TRACE();
1337
1338         return -ENOSYS;
1339 }
1340
1341 static int
1342 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1343                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1344 {
1345         PMD_INIT_FUNC_TRACE();
1346
1347         return -ENOSYS;
1348 }
1349
1350 /* Add a MAC address, and update filters */
1351 static void
1352 i40e_macaddr_add(struct rte_eth_dev *dev,
1353                  struct ether_addr *mac_addr,
1354                  __attribute__((unused)) uint32_t index,
1355                  __attribute__((unused)) uint32_t pool)
1356 {
1357         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1358         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1359         struct i40e_vsi *vsi = pf->main_vsi;
1360         struct ether_addr old_mac;
1361         int ret;
1362
1363         if (!is_valid_assigned_ether_addr(mac_addr)) {
1364                 PMD_DRV_LOG(ERR, "Invalid ethernet address\n");
1365                 return;
1366         }
1367
1368         if (is_same_ether_addr(mac_addr, &(pf->dev_addr))) {
1369                 PMD_DRV_LOG(INFO, "Ignore adding permanent mac address\n");
1370                 return;
1371         }
1372
1373         /* Write mac address */
1374         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1375                                         mac_addr->addr_bytes, NULL);
1376         if (ret != I40E_SUCCESS) {
1377                 PMD_DRV_LOG(ERR, "Failed to write mac address\n");
1378                 return;
1379         }
1380
1381         (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1382         (void)rte_memcpy(hw->mac.addr, mac_addr->addr_bytes,
1383                         ETHER_ADDR_LEN);
1384
1385         ret = i40e_vsi_add_mac(vsi, mac_addr);
1386         if (ret != I40E_SUCCESS) {
1387                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter\n");
1388                 return;
1389         }
1390
1391         ether_addr_copy(mac_addr, &pf->dev_addr);
1392         i40e_vsi_delete_mac(vsi, &old_mac);
1393 }
1394
1395 /* Remove a MAC address, and update filters */
1396 static void
1397 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1398 {
1399         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1400         struct i40e_vsi *vsi = pf->main_vsi;
1401         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1402         struct ether_addr *macaddr;
1403         int ret;
1404         struct i40e_hw *hw =
1405                 I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1406
1407         if (index >= vsi->max_macaddrs)
1408                 return;
1409
1410         macaddr = &(data->mac_addrs[index]);
1411         if (!is_valid_assigned_ether_addr(macaddr))
1412                 return;
1413
1414         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1415                                         hw->mac.perm_addr, NULL);
1416         if (ret != I40E_SUCCESS) {
1417                 PMD_DRV_LOG(ERR, "Failed to write mac address\n");
1418                 return;
1419         }
1420
1421         (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);
1422
1423         ret = i40e_vsi_delete_mac(vsi, macaddr);
1424         if (ret != I40E_SUCCESS)
1425                 return;
1426
1427         /* Clear device address as it has been removed */
1428         if (is_same_ether_addr(&(pf->dev_addr), macaddr))
1429                 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1430 }
1431
1432 static int
1433 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1434                          struct rte_eth_rss_reta *reta_conf)
1435 {
1436         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1437         uint32_t lut, l;
1438         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1439
1440         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1441                 if (i < max)
1442                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1443                 else
1444                         mask = (uint8_t)((reta_conf->mask_hi >>
1445                                                 (i - max)) & 0xF);
1446
1447                 if (!mask)
1448                         continue;
1449
1450                 if (mask == 0xF)
1451                         l = 0;
1452                 else
1453                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1454
1455                 for (j = 0, lut = 0; j < 4; j++) {
1456                         if (mask & (0x1 << j))
1457                                 lut |= reta_conf->reta[i + j] << (8 * j);
1458                         else
1459                                 lut |= l & (0xFF << (8 * j));
1460                 }
1461                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int
1468 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1469                         struct rte_eth_rss_reta *reta_conf)
1470 {
1471         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1472         uint32_t lut;
1473         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1474
1475         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1476                 if (i < max)
1477                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1478                 else
1479                         mask = (uint8_t)((reta_conf->mask_hi >>
1480                                                 (i - max)) & 0xF);
1481
1482                 if (!mask)
1483                         continue;
1484
1485                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1486                 for (j = 0; j < 4; j++) {
1487                         if (mask & (0x1 << j))
1488                                 reta_conf->reta[i + j] =
1489                                         (uint8_t)((lut >> (8 * j)) & 0xFF);
1490                 }
1491         }
1492
1493         return 0;
1494 }
1495
1496 /**
1497  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1498  * @hw:   pointer to the HW structure
1499  * @mem:  pointer to mem struct to fill out
1500  * @size: size of memory requested
1501  * @alignment: what to align the allocation to
1502  **/
1503 enum i40e_status_code
1504 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1505                         struct i40e_dma_mem *mem,
1506                         u64 size,
1507                         u32 alignment)
1508 {
1509         static uint64_t id = 0;
1510         const struct rte_memzone *mz = NULL;
1511         char z_name[RTE_MEMZONE_NAMESIZE];
1512
1513         if (!mem)
1514                 return I40E_ERR_PARAM;
1515
1516         id++;
1517         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1518         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1519         if (!mz)
1520                 return I40E_ERR_NO_MEMORY;
1521
1522         mem->id = id;
1523         mem->size = size;
1524         mem->va = mz->addr;
1525         mem->pa = mz->phys_addr;
1526
1527         return I40E_SUCCESS;
1528 }
1529
1530 /**
1531  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1532  * @hw:   pointer to the HW structure
1533  * @mem:  ptr to mem struct to free
1534  **/
1535 enum i40e_status_code
1536 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1537                     struct i40e_dma_mem *mem)
1538 {
1539         if (!mem || !mem->va)
1540                 return I40E_ERR_PARAM;
1541
1542         mem->va = NULL;
1543         mem->pa = (u64)0;
1544
1545         return I40E_SUCCESS;
1546 }
1547
1548 /**
1549  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1550  * @hw:   pointer to the HW structure
1551  * @mem:  pointer to mem struct to fill out
1552  * @size: size of memory requested
1553  **/
1554 enum i40e_status_code
1555 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1556                          struct i40e_virt_mem *mem,
1557                          u32 size)
1558 {
1559         if (!mem)
1560                 return I40E_ERR_PARAM;
1561
1562         mem->size = size;
1563         mem->va = rte_zmalloc("i40e", size, 0);
1564
1565         if (mem->va)
1566                 return I40E_SUCCESS;
1567         else
1568                 return I40E_ERR_NO_MEMORY;
1569 }
1570
1571 /**
1572  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1573  * @hw:   pointer to the HW structure
1574  * @mem:  pointer to mem struct to free
1575  **/
1576 enum i40e_status_code
1577 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1578                      struct i40e_virt_mem *mem)
1579 {
1580         if (!mem)
1581                 return I40E_ERR_PARAM;
1582
1583         rte_free(mem->va);
1584         mem->va = NULL;
1585
1586         return I40E_SUCCESS;
1587 }
1588
1589 void
1590 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1591 {
1592         rte_spinlock_init(&sp->spinlock);
1593 }
1594
1595 void
1596 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1597 {
1598         rte_spinlock_lock(&sp->spinlock);
1599 }
1600
1601 void
1602 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1603 {
1604         rte_spinlock_unlock(&sp->spinlock);
1605 }
1606
1607 void
1608 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1609 {
1610         return;
1611 }
1612
1613 /**
1614  * Get the hardware capabilities, which will be parsed
1615  * and saved into struct i40e_hw.
1616  */
1617 static int
1618 i40e_get_cap(struct i40e_hw *hw)
1619 {
1620         struct i40e_aqc_list_capabilities_element_resp *buf;
1621         uint16_t len, size = 0;
1622         int ret;
1623
1624         /* Calculate a huge enough buff for saving response data temporarily */
1625         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1626                                                 I40E_MAX_CAP_ELE_NUM;
1627         buf = rte_zmalloc("i40e", len, 0);
1628         if (!buf) {
1629                 PMD_DRV_LOG(ERR, "Failed to allocate memory\n");
1630                 return I40E_ERR_NO_MEMORY;
1631         }
1632
1633         /* Get, parse the capabilities and save it to hw */
1634         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1635                         i40e_aqc_opc_list_func_capabilities, NULL);
1636         if (ret != I40E_SUCCESS)
1637                 PMD_DRV_LOG(ERR, "Failed to discover capabilities\n");
1638
1639         /* Free the temporary buffer after being used */
1640         rte_free(buf);
1641
1642         return ret;
1643 }
1644
1645 static int
1646 i40e_pf_parameter_init(struct rte_eth_dev *dev)
1647 {
1648         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1649         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1650         uint16_t sum_queues = 0, sum_vsis;
1651
1652         /* First check if FW support SRIOV */
1653         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
1654                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV\n");
1655                 return -EINVAL;
1656         }
1657
1658         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
1659         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
1660         PMD_INIT_LOG(INFO, "Max supported VSIs:%u\n", pf->max_num_vsi);
1661         /* Allocate queues for pf */
1662         if (hw->func_caps.rss) {
1663                 pf->flags |= I40E_FLAG_RSS;
1664                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
1665                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
1666                 pf->lan_nb_qps = i40e_prev_power_of_2(pf->lan_nb_qps);
1667         } else
1668                 pf->lan_nb_qps = 1;
1669         sum_queues = pf->lan_nb_qps;
1670         /* Default VSI is not counted in */
1671         sum_vsis = 0;
1672         PMD_INIT_LOG(INFO, "PF queue pairs:%u\n", pf->lan_nb_qps);
1673
1674         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
1675                 pf->flags |= I40E_FLAG_SRIOV;
1676                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
1677                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
1678                         PMD_INIT_LOG(ERR, "Config VF number %u, "
1679                                 "max supported %u.\n", dev->pci_dev->max_vfs,
1680                                                 hw->func_caps.num_vfs);
1681                         return -EINVAL;
1682                 }
1683                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
1684                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
1685                                 "max support %u queues.\n", pf->vf_nb_qps,
1686                                                 I40E_MAX_QP_NUM_PER_VF);
1687                         return -EINVAL;
1688                 }
1689                 pf->vf_num = dev->pci_dev->max_vfs;
1690                 sum_queues += pf->vf_nb_qps * pf->vf_num;
1691                 sum_vsis   += pf->vf_num;
1692                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u\n",
1693                                                 pf->vf_num, pf->vf_nb_qps);
1694         } else
1695                 pf->vf_num = 0;
1696
1697         if (hw->func_caps.vmdq) {
1698                 pf->flags |= I40E_FLAG_VMDQ;
1699                 pf->vmdq_nb_qps = I40E_DEFAULT_QP_NUM_VMDQ;
1700                 sum_queues += pf->vmdq_nb_qps;
1701                 sum_vsis += 1;
1702                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u\n", pf->vmdq_nb_qps);
1703         }
1704
1705         if (hw->func_caps.fd) {
1706                 pf->flags |= I40E_FLAG_FDIR;
1707                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
1708                 /**
1709                  * Each flow director consumes one VSI and one queue,
1710                  * but can't calculate out predictably here.
1711                  */
1712         }
1713
1714         if (sum_vsis > pf->max_num_vsi ||
1715                 sum_queues > hw->func_caps.num_rx_qp) {
1716                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied\n");
1717                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u\n",
1718                                 pf->max_num_vsi, sum_vsis);
1719                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u\n",
1720                                 hw->func_caps.num_rx_qp, sum_queues);
1721                 return -EINVAL;
1722         }
1723
1724         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr cause */
1725         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
1726                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough\n",
1727                                 sum_vsis, hw->func_caps.num_msix_vectors);
1728                 return -EINVAL;
1729         }
1730         return I40E_SUCCESS;
1731 }
1732
1733 static int
1734 i40e_pf_get_switch_config(struct i40e_pf *pf)
1735 {
1736         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1737         struct i40e_aqc_get_switch_config_resp *switch_config;
1738         struct i40e_aqc_switch_config_element_resp *element;
1739         uint16_t start_seid = 0, num_reported;
1740         int ret;
1741
1742         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
1743                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
1744         if (!switch_config) {
1745                 PMD_DRV_LOG(ERR, "Failed to allocated memory\n");
1746                 return -ENOMEM;
1747         }
1748
1749         /* Get the switch configurations */
1750         ret = i40e_aq_get_switch_config(hw, switch_config,
1751                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
1752         if (ret != I40E_SUCCESS) {
1753                 PMD_DRV_LOG(ERR, "Failed to get switch configurations\n");
1754                 goto fail;
1755         }
1756         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
1757         if (num_reported != 1) { /* The number should be 1 */
1758                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported\n");
1759                 goto fail;
1760         }
1761
1762         /* Parse the switch configuration elements */
1763         element = &(switch_config->element[0]);
1764         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
1765                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
1766                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
1767         } else
1768                 PMD_DRV_LOG(INFO, "Unknown element type\n");
1769
1770 fail:
1771         rte_free(switch_config);
1772
1773         return ret;
1774 }
1775
1776 static int
1777 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
1778                         uint32_t num)
1779 {
1780         struct pool_entry *entry;
1781
1782         if (pool == NULL || num == 0)
1783                 return -EINVAL;
1784
1785         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
1786         if (entry == NULL) {
1787                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1788                                                 "resource pool\n");
1789                 return -ENOMEM;
1790         }
1791
1792         /* queue heap initialize */
1793         pool->num_free = num;
1794         pool->num_alloc = 0;
1795         pool->base = base;
1796         LIST_INIT(&pool->alloc_list);
1797         LIST_INIT(&pool->free_list);
1798
1799         /* Initialize element  */
1800         entry->base = 0;
1801         entry->len = num;
1802
1803         LIST_INSERT_HEAD(&pool->free_list, entry, next);
1804         return 0;
1805 }
1806
1807 static void
1808 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
1809 {
1810         struct pool_entry *entry;
1811
1812         if (pool == NULL)
1813                 return;
1814
1815         LIST_FOREACH(entry, &pool->alloc_list, next) {
1816                 LIST_REMOVE(entry, next);
1817                 rte_free(entry);
1818         }
1819
1820         LIST_FOREACH(entry, &pool->free_list, next) {
1821                 LIST_REMOVE(entry, next);
1822                 rte_free(entry);
1823         }
1824
1825         pool->num_free = 0;
1826         pool->num_alloc = 0;
1827         pool->base = 0;
1828         LIST_INIT(&pool->alloc_list);
1829         LIST_INIT(&pool->free_list);
1830 }
1831
1832 static int
1833 i40e_res_pool_free(struct i40e_res_pool_info *pool,
1834                        uint32_t base)
1835 {
1836         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
1837         uint32_t pool_offset;
1838         int insert;
1839
1840         if (pool == NULL) {
1841                 PMD_DRV_LOG(ERR, "Invalid parameter\n");
1842                 return -EINVAL;
1843         }
1844
1845         pool_offset = base - pool->base;
1846         /* Lookup in alloc list */
1847         LIST_FOREACH(entry, &pool->alloc_list, next) {
1848                 if (entry->base == pool_offset) {
1849                         valid_entry = entry;
1850                         LIST_REMOVE(entry, next);
1851                         break;
1852                 }
1853         }
1854
1855         /* Not find, return */
1856         if (valid_entry == NULL) {
1857                 PMD_DRV_LOG(ERR, "Failed to find entry\n");
1858                 return -EINVAL;
1859         }
1860
1861         /**
1862          * Found it, move it to free list  and try to merge.
1863          * In order to make merge easier, always sort it by qbase.
1864          * Find adjacent prev and last entries.
1865          */
1866         prev = next = NULL;
1867         LIST_FOREACH(entry, &pool->free_list, next) {
1868                 if (entry->base > valid_entry->base) {
1869                         next = entry;
1870                         break;
1871                 }
1872                 prev = entry;
1873         }
1874
1875         insert = 0;
1876         /* Try to merge with next one*/
1877         if (next != NULL) {
1878                 /* Merge with next one */
1879                 if (valid_entry->base + valid_entry->len == next->base) {
1880                         next->base = valid_entry->base;
1881                         next->len += valid_entry->len;
1882                         rte_free(valid_entry);
1883                         valid_entry = next;
1884                         insert = 1;
1885                 }
1886         }
1887
1888         if (prev != NULL) {
1889                 /* Merge with previous one */
1890                 if (prev->base + prev->len == valid_entry->base) {
1891                         prev->len += valid_entry->len;
1892                         /* If it merge with next one, remove next node */
1893                         if (insert == 1) {
1894                                 LIST_REMOVE(valid_entry, next);
1895                                 rte_free(valid_entry);
1896                         } else {
1897                                 rte_free(valid_entry);
1898                                 insert = 1;
1899                         }
1900                 }
1901         }
1902
1903         /* Not find any entry to merge, insert */
1904         if (insert == 0) {
1905                 if (prev != NULL)
1906                         LIST_INSERT_AFTER(prev, valid_entry, next);
1907                 else if (next != NULL)
1908                         LIST_INSERT_BEFORE(next, valid_entry, next);
1909                 else /* It's empty list, insert to head */
1910                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
1911         }
1912
1913         pool->num_free += valid_entry->len;
1914         pool->num_alloc -= valid_entry->len;
1915
1916         return 0;
1917 }
1918
1919 static int
1920 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
1921                        uint16_t num)
1922 {
1923         struct pool_entry *entry, *valid_entry;
1924
1925         if (pool == NULL || num == 0) {
1926                 PMD_DRV_LOG(ERR, "Invalid parameter\n");
1927                 return -EINVAL;
1928         }
1929
1930         if (pool->num_free < num) {
1931                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u\n",
1932                                 num, pool->num_free);
1933                 return -ENOMEM;
1934         }
1935
1936         valid_entry = NULL;
1937         /* Lookup  in free list and find most fit one */
1938         LIST_FOREACH(entry, &pool->free_list, next) {
1939                 if (entry->len >= num) {
1940                         /* Find best one */
1941                         if (entry->len == num) {
1942                                 valid_entry = entry;
1943                                 break;
1944                         }
1945                         if (valid_entry == NULL || valid_entry->len > entry->len)
1946                                 valid_entry = entry;
1947                 }
1948         }
1949
1950         /* Not find one to satisfy the request, return */
1951         if (valid_entry == NULL) {
1952                 PMD_DRV_LOG(ERR, "No valid entry found\n");
1953                 return -ENOMEM;
1954         }
1955         /**
1956          * The entry have equal queue number as requested,
1957          * remove it from alloc_list.
1958          */
1959         if (valid_entry->len == num) {
1960                 LIST_REMOVE(valid_entry, next);
1961         } else {
1962                 /**
1963                  * The entry have more numbers than requested,
1964                  * create a new entry for alloc_list and minus its
1965                  * queue base and number in free_list.
1966                  */
1967                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
1968                 if (entry == NULL) {
1969                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1970                                         "resource pool\n");
1971                         return -ENOMEM;
1972                 }
1973                 entry->base = valid_entry->base;
1974                 entry->len = num;
1975                 valid_entry->base += num;
1976                 valid_entry->len -= num;
1977                 valid_entry = entry;
1978         }
1979
1980         /* Insert it into alloc list, not sorted */
1981         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
1982
1983         pool->num_free -= valid_entry->len;
1984         pool->num_alloc += valid_entry->len;
1985
1986         return (valid_entry->base + pool->base);
1987 }
1988
1989 /**
1990  * bitmap_is_subset - Check whether src2 is subset of src1
1991  **/
1992 static inline int
1993 bitmap_is_subset(uint8_t src1, uint8_t src2)
1994 {
1995         return !((src1 ^ src2) & src2);
1996 }
1997
1998 static int
1999 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2000 {
2001         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2002
2003         /* If DCB is not supported, only default TC is supported */
2004         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2005                 PMD_DRV_LOG(ERR, "DCB is not enabled, "
2006                                 "only TC0 is supported\n");
2007                 return -EINVAL;
2008         }
2009
2010         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2011                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2012                         "HW support 0x%x\n", hw->func_caps.enabled_tcmap,
2013                                                         enabled_tcmap);
2014                 return -EINVAL;
2015         }
2016         return I40E_SUCCESS;
2017 }
2018
2019 int
2020 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2021                                 struct i40e_vsi_vlan_pvid_info *info)
2022 {
2023         struct i40e_hw *hw;
2024         struct i40e_vsi_context ctxt;
2025         uint8_t vlan_flags = 0;
2026         int ret;
2027
2028         if (vsi == NULL || info == NULL) {
2029                 PMD_DRV_LOG(ERR, "invalid parameters\n");
2030                 return I40E_ERR_PARAM;
2031         }
2032
2033         if (info->on) {
2034                 vsi->info.pvid = info->config.pvid;
2035                 /**
2036                  * If insert pvid is enabled, only tagged pkts are
2037                  * allowed to be sent out.
2038                  */
2039                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2040                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2041         } else {
2042                 vsi->info.pvid = 0;
2043                 if (info->config.reject.tagged == 0)
2044                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2045
2046                 if (info->config.reject.untagged == 0)
2047                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2048         }
2049         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2050                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2051         vsi->info.port_vlan_flags |= vlan_flags;
2052         vsi->info.valid_sections =
2053                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2054         memset(&ctxt, 0, sizeof(ctxt));
2055         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2056         ctxt.seid = vsi->seid;
2057
2058         hw = I40E_VSI_TO_HW(vsi);
2059         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2060         if (ret != I40E_SUCCESS)
2061                 PMD_DRV_LOG(ERR, "Failed to update VSI params\n");
2062
2063         return ret;
2064 }
2065
2066 static int
2067 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2068 {
2069         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2070         int i, ret;
2071         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2072
2073         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2074         if (ret != I40E_SUCCESS)
2075                 return ret;
2076
2077         if (!vsi->seid) {
2078                 PMD_DRV_LOG(ERR, "seid not valid\n");
2079                 return -EINVAL;
2080         }
2081
2082         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2083         tc_bw_data.tc_valid_bits = enabled_tcmap;
2084         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2085                 tc_bw_data.tc_bw_credits[i] =
2086                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2087
2088         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2089         if (ret != I40E_SUCCESS) {
2090                 PMD_DRV_LOG(ERR, "Failed to configure TC BW\n");
2091                 return ret;
2092         }
2093
2094         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2095                                         sizeof(vsi->info.qs_handle));
2096         return I40E_SUCCESS;
2097 }
2098
2099 static int
2100 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2101                                  struct i40e_aqc_vsi_properties_data *info,
2102                                  uint8_t enabled_tcmap)
2103 {
2104         int ret, total_tc = 0, i;
2105         uint16_t qpnum_per_tc, bsf, qp_idx;
2106
2107         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2108         if (ret != I40E_SUCCESS)
2109                 return ret;
2110
2111         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2112                 if (enabled_tcmap & (1 << i))
2113                         total_tc++;
2114         vsi->enabled_tc = enabled_tcmap;
2115
2116         /* Number of queues per enabled TC */
2117         qpnum_per_tc = i40e_prev_power_of_2(vsi->nb_qps / total_tc);
2118         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2119         bsf = rte_bsf32(qpnum_per_tc);
2120
2121         /* Adjust the queue number to actual queues that can be applied */
2122         vsi->nb_qps = qpnum_per_tc * total_tc;
2123
2124         /**
2125          * Configure TC and queue mapping parameters, for enabled TC,
2126          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2127          * default queue will serve it.
2128          */
2129         qp_idx = 0;
2130         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2131                 if (vsi->enabled_tc & (1 << i)) {
2132                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2133                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2134                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2135                         qp_idx += qpnum_per_tc;
2136                 } else
2137                         info->tc_mapping[i] = 0;
2138         }
2139
2140         /* Associate queue number with VSI */
2141         if (vsi->type == I40E_VSI_SRIOV) {
2142                 info->mapping_flags |=
2143                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2144                 for (i = 0; i < vsi->nb_qps; i++)
2145                         info->queue_mapping[i] =
2146                                 rte_cpu_to_le_16(vsi->base_queue + i);
2147         } else {
2148                 info->mapping_flags |=
2149                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2150                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2151         }
2152         info->valid_sections =
2153                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2154
2155         return I40E_SUCCESS;
2156 }
2157
2158 static int
2159 i40e_veb_release(struct i40e_veb *veb)
2160 {
2161         struct i40e_vsi *vsi;
2162         struct i40e_hw *hw;
2163
2164         if (veb == NULL || veb->associate_vsi == NULL)
2165                 return -EINVAL;
2166
2167         if (!TAILQ_EMPTY(&veb->head)) {
2168                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove\n");
2169                 return -EACCES;
2170         }
2171
2172         vsi = veb->associate_vsi;
2173         hw = I40E_VSI_TO_HW(vsi);
2174
2175         vsi->uplink_seid = veb->uplink_seid;
2176         i40e_aq_delete_element(hw, veb->seid, NULL);
2177         rte_free(veb);
2178         vsi->veb = NULL;
2179         return I40E_SUCCESS;
2180 }
2181
2182 /* Setup a veb */
2183 static struct i40e_veb *
2184 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2185 {
2186         struct i40e_veb *veb;
2187         int ret;
2188         struct i40e_hw *hw;
2189
2190         if (NULL == pf || vsi == NULL) {
2191                 PMD_DRV_LOG(ERR, "veb setup failed, "
2192                         "associated VSI shouldn't null\n");
2193                 return NULL;
2194         }
2195         hw = I40E_PF_TO_HW(pf);
2196
2197         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2198         if (!veb) {
2199                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb\n");
2200                 goto fail;
2201         }
2202
2203         veb->associate_vsi = vsi;
2204         TAILQ_INIT(&veb->head);
2205         veb->uplink_seid = vsi->uplink_seid;
2206
2207         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2208                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2209
2210         if (ret != I40E_SUCCESS) {
2211                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d\n",
2212                                         hw->aq.asq_last_status);
2213                 goto fail;
2214         }
2215
2216         /* get statistics index */
2217         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2218                                 &veb->stats_idx, NULL, NULL, NULL);
2219         if (ret != I40E_SUCCESS) {
2220                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d\n",
2221                                                 hw->aq.asq_last_status);
2222                 goto fail;
2223         }
2224
2225         /* Get VEB bandwidth, to be implemented */
2226         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2227         vsi->uplink_seid = veb->seid;
2228
2229         return veb;
2230 fail:
2231         rte_free(veb);
2232         return NULL;
2233 }
2234
2235 int
2236 i40e_vsi_release(struct i40e_vsi *vsi)
2237 {
2238         struct i40e_pf *pf;
2239         struct i40e_hw *hw;
2240         struct i40e_vsi_list *vsi_list;
2241         int ret;
2242         struct i40e_mac_filter *f;
2243
2244         if (!vsi)
2245                 return I40E_SUCCESS;
2246
2247         pf = I40E_VSI_TO_PF(vsi);
2248         hw = I40E_VSI_TO_HW(vsi);
2249
2250         /* VSI has child to attach, release child first */
2251         if (vsi->veb) {
2252                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2253                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2254                                 return -1;
2255                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2256                 }
2257                 i40e_veb_release(vsi->veb);
2258         }
2259
2260         /* Remove all macvlan filters of the VSI */
2261         i40e_vsi_remove_all_macvlan_filter(vsi);
2262         TAILQ_FOREACH(f, &vsi->mac_list, next)
2263                 rte_free(f);
2264
2265         if (vsi->type != I40E_VSI_MAIN) {
2266                 /* Remove vsi from parent's sibling list */
2267                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2268                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL\n");
2269                         return I40E_ERR_PARAM;
2270                 }
2271                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2272                                 &vsi->sib_vsi_list, list);
2273
2274                 /* Remove all switch element of the VSI */
2275                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2276                 if (ret != I40E_SUCCESS)
2277                         PMD_DRV_LOG(ERR, "Failed to delete element\n");
2278         }
2279         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2280
2281         if (vsi->type != I40E_VSI_SRIOV)
2282                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2283         rte_free(vsi);
2284
2285         return I40E_SUCCESS;
2286 }
2287
2288 static int
2289 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2290 {
2291         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2292         struct i40e_aqc_remove_macvlan_element_data def_filter;
2293         int ret;
2294
2295         if (vsi->type != I40E_VSI_MAIN)
2296                 return I40E_ERR_CONFIG;
2297         memset(&def_filter, 0, sizeof(def_filter));
2298         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2299                                         ETH_ADDR_LEN);
2300         def_filter.vlan_tag = 0;
2301         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2302                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2303         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2304         if (ret != I40E_SUCCESS) {
2305                 struct i40e_mac_filter *f;
2306
2307                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2308                                                 "macvlan filter\n");
2309                 /* It needs to add the permanent mac into mac list */
2310                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2311                 if (f == NULL) {
2312                         PMD_DRV_LOG(ERR, "failed to allocate memory\n");
2313                         return I40E_ERR_NO_MEMORY;
2314                 }
2315                 (void)rte_memcpy(&f->macaddr.addr_bytes, hw->mac.perm_addr,
2316                                 ETH_ADDR_LEN);
2317                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2318                 vsi->mac_num++;
2319
2320                 return ret;
2321         }
2322
2323         return i40e_vsi_add_mac(vsi, (struct ether_addr *)(hw->mac.perm_addr));
2324 }
2325
2326 static int
2327 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2328 {
2329         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2330         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2331         struct i40e_hw *hw = &vsi->adapter->hw;
2332         i40e_status ret;
2333         int i;
2334
2335         memset(&bw_config, 0, sizeof(bw_config));
2336         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2337         if (ret != I40E_SUCCESS) {
2338                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth "
2339                         "configuration %u\n", hw->aq.asq_last_status);
2340                 return ret;
2341         }
2342
2343         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2344         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2345                                         &ets_sla_config, NULL);
2346         if (ret != I40E_SUCCESS) {
2347                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2348                         "configuration %u\n", hw->aq.asq_last_status);
2349                 return ret;
2350         }
2351
2352         /* Not store the info yet, just print out */
2353         PMD_DRV_LOG(INFO, "VSI bw limit:%u\n", bw_config.port_bw_limit);
2354         PMD_DRV_LOG(INFO, "VSI max_bw:%u\n", bw_config.max_bw);
2355         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2356                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u\n", i,
2357                                         ets_sla_config.share_credits[i]);
2358                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u\n", i,
2359                         rte_le_to_cpu_16(ets_sla_config.credits[i]));
2360                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2361                         rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2362                                                                 (i * 4));
2363         }
2364
2365         return 0;
2366 }
2367
2368 /* Setup a VSI */
2369 struct i40e_vsi *
2370 i40e_vsi_setup(struct i40e_pf *pf,
2371                enum i40e_vsi_type type,
2372                struct i40e_vsi *uplink_vsi,
2373                uint16_t user_param)
2374 {
2375         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2376         struct i40e_vsi *vsi;
2377         int ret;
2378         struct i40e_vsi_context ctxt;
2379         struct ether_addr broadcast =
2380                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2381
2382         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2383                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2384                         "VSI link shouldn't be NULL\n");
2385                 return NULL;
2386         }
2387
2388         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2389                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2390                                 "uplink VSI should be NULL\n");
2391                 return NULL;
2392         }
2393
2394         /* If uplink vsi didn't setup VEB, create one first */
2395         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2396                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2397
2398                 if (NULL == uplink_vsi->veb) {
2399                         PMD_DRV_LOG(ERR, "VEB setup failed\n");
2400                         return NULL;
2401                 }
2402         }
2403
2404         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2405         if (!vsi) {
2406                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi\n");
2407                 return NULL;
2408         }
2409         TAILQ_INIT(&vsi->mac_list);
2410         vsi->type = type;
2411         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2412         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2413         vsi->parent_vsi = uplink_vsi;
2414         vsi->user_param = user_param;
2415         /* Allocate queues */
2416         switch (vsi->type) {
2417         case I40E_VSI_MAIN  :
2418                 vsi->nb_qps = pf->lan_nb_qps;
2419                 break;
2420         case I40E_VSI_SRIOV :
2421                 vsi->nb_qps = pf->vf_nb_qps;
2422                 break;
2423         default:
2424                 goto fail_mem;
2425         }
2426         ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2427         if (ret < 0) {
2428                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2429                                 vsi->seid, ret);
2430                 goto fail_mem;
2431         }
2432         vsi->base_queue = ret;
2433
2434         /* VF has MSIX interrupt in VF range, don't allocate here */
2435         if (type != I40E_VSI_SRIOV) {
2436                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2437                 if (ret < 0) {
2438                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2439                         goto fail_queue_alloc;
2440                 }
2441                 vsi->msix_intr = ret;
2442         } else
2443                 vsi->msix_intr = 0;
2444         /* Add VSI */
2445         if (type == I40E_VSI_MAIN) {
2446                 /* For main VSI, no need to add since it's default one */
2447                 vsi->uplink_seid = pf->mac_seid;
2448                 vsi->seid = pf->main_vsi_seid;
2449                 /* Bind queues with specific MSIX interrupt */
2450                 /**
2451                  * Needs 2 interrupt at least, one for misc cause which will
2452                  * enabled from OS side, Another for queues binding the
2453                  * interrupt from device side only.
2454                  */
2455
2456                 /* Get default VSI parameters from hardware */
2457                 memset(&ctxt, 0, sizeof(ctxt));
2458                 ctxt.seid = vsi->seid;
2459                 ctxt.pf_num = hw->pf_id;
2460                 ctxt.uplink_seid = vsi->uplink_seid;
2461                 ctxt.vf_num = 0;
2462                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2463                 if (ret != I40E_SUCCESS) {
2464                         PMD_DRV_LOG(ERR, "Failed to get VSI params\n");
2465                         goto fail_msix_alloc;
2466                 }
2467                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2468                         sizeof(struct i40e_aqc_vsi_properties_data));
2469                 vsi->vsi_id = ctxt.vsi_number;
2470                 vsi->info.valid_sections = 0;
2471
2472                 /* Configure tc, enabled TC0 only */
2473                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2474                         I40E_SUCCESS) {
2475                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth\n");
2476                         goto fail_msix_alloc;
2477                 }
2478
2479                 /* TC, queue mapping */
2480                 memset(&ctxt, 0, sizeof(ctxt));
2481                 vsi->info.valid_sections |=
2482                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2483                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2484                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2485                 (void)rte_memcpy(&ctxt.info, &vsi->info,
2486                         sizeof(struct i40e_aqc_vsi_properties_data));
2487                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2488                                                 I40E_DEFAULT_TCMAP);
2489                 if (ret != I40E_SUCCESS) {
2490                         PMD_DRV_LOG(ERR, "Failed to configure "
2491                                         "TC queue mapping\n");
2492                         goto fail_msix_alloc;
2493                 }
2494                 ctxt.seid = vsi->seid;
2495                 ctxt.pf_num = hw->pf_id;
2496                 ctxt.uplink_seid = vsi->uplink_seid;
2497                 ctxt.vf_num = 0;
2498
2499                 /* Update VSI parameters */
2500                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2501                 if (ret != I40E_SUCCESS) {
2502                         PMD_DRV_LOG(ERR, "Failed to update VSI params\n");
2503                         goto fail_msix_alloc;
2504                 }
2505
2506                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2507                                                 sizeof(vsi->info.tc_mapping));
2508                 (void)rte_memcpy(&vsi->info.queue_mapping,
2509                                 &ctxt.info.queue_mapping,
2510                         sizeof(vsi->info.queue_mapping));
2511                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2512                 vsi->info.valid_sections = 0;
2513
2514                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2515                                 ETH_ADDR_LEN);
2516
2517                 /**
2518                  * Updating default filter settings are necessary to prevent
2519                  * reception of tagged packets.
2520                  * Some old firmware configurations load a default macvlan
2521                  * filter which accepts both tagged and untagged packets.
2522                  * The updating is to use a normal filter instead if needed.
2523                  * For NVM 4.2.2 or after, the updating is not needed anymore.
2524                  * The firmware with correct configurations load the default
2525                  * macvlan filter which is expected and cannot be removed.
2526                  */
2527                 i40e_update_default_filter_setting(vsi);
2528         } else if (type == I40E_VSI_SRIOV) {
2529                 memset(&ctxt, 0, sizeof(ctxt));
2530                 /**
2531                  * For other VSI, the uplink_seid equals to uplink VSI's
2532                  * uplink_seid since they share same VEB
2533                  */
2534                 vsi->uplink_seid = uplink_vsi->uplink_seid;
2535                 ctxt.pf_num = hw->pf_id;
2536                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2537                 ctxt.uplink_seid = vsi->uplink_seid;
2538                 ctxt.connection_type = 0x1;
2539                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2540
2541                 /* Configure switch ID */
2542                 ctxt.info.valid_sections |=
2543                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2544                 ctxt.info.switch_id =
2545                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2546                 /* Configure port/vlan */
2547                 ctxt.info.valid_sections |=
2548                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2549                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2550                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2551                                                 I40E_DEFAULT_TCMAP);
2552                 if (ret != I40E_SUCCESS) {
2553                         PMD_DRV_LOG(ERR, "Failed to configure "
2554                                         "TC queue mapping\n");
2555                         goto fail_msix_alloc;
2556                 }
2557                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2558                 ctxt.info.valid_sections |=
2559                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2560                 /**
2561                  * Since VSI is not created yet, only configure parameter,
2562                  * will add vsi below.
2563                  */
2564         }
2565         else {
2566                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet\n");
2567                 goto fail_msix_alloc;
2568         }
2569
2570         if (vsi->type != I40E_VSI_MAIN) {
2571                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
2572                 if (ret) {
2573                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d\n",
2574                                  hw->aq.asq_last_status);
2575                         goto fail_msix_alloc;
2576                 }
2577                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
2578                 vsi->info.valid_sections = 0;
2579                 vsi->seid = ctxt.seid;
2580                 vsi->vsi_id = ctxt.vsi_number;
2581                 vsi->sib_vsi_list.vsi = vsi;
2582                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
2583                                 &vsi->sib_vsi_list, list);
2584         }
2585
2586         /* MAC/VLAN configuration */
2587         ret = i40e_vsi_add_mac(vsi, &broadcast);
2588         if (ret != I40E_SUCCESS) {
2589                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter\n");
2590                 goto fail_msix_alloc;
2591         }
2592
2593         /* Get VSI BW information */
2594         i40e_vsi_dump_bw_config(vsi);
2595         return vsi;
2596 fail_msix_alloc:
2597         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
2598 fail_queue_alloc:
2599         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
2600 fail_mem:
2601         rte_free(vsi);
2602         return NULL;
2603 }
2604
2605 /* Configure vlan stripping on or off */
2606 int
2607 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
2608 {
2609         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2610         struct i40e_vsi_context ctxt;
2611         uint8_t vlan_flags;
2612         int ret = I40E_SUCCESS;
2613
2614         /* Check if it has been already on or off */
2615         if (vsi->info.valid_sections &
2616                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
2617                 if (on) {
2618                         if ((vsi->info.port_vlan_flags &
2619                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
2620                                 return 0; /* already on */
2621                 } else {
2622                         if ((vsi->info.port_vlan_flags &
2623                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2624                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
2625                                 return 0; /* already off */
2626                 }
2627         }
2628
2629         if (on)
2630                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2631         else
2632                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2633         vsi->info.valid_sections =
2634                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2635         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
2636         vsi->info.port_vlan_flags |= vlan_flags;
2637         ctxt.seid = vsi->seid;
2638         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2639         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2640         if (ret)
2641                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping\n",
2642                                                 on ? "enable" : "disable");
2643
2644         return ret;
2645 }
2646
2647 static int
2648 i40e_dev_init_vlan(struct rte_eth_dev *dev)
2649 {
2650         struct rte_eth_dev_data *data = dev->data;
2651         int ret;
2652
2653         /* Apply vlan offload setting */
2654         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
2655
2656         /* Apply double-vlan setting, not implemented yet */
2657
2658         /* Apply pvid setting */
2659         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
2660                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
2661         if (ret)
2662                 PMD_DRV_LOG(INFO, "Failed to update VSI params\n");
2663
2664         return ret;
2665 }
2666
2667 static int
2668 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
2669 {
2670         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2671
2672         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
2673 }
2674
2675 static int
2676 i40e_update_flow_control(struct i40e_hw *hw)
2677 {
2678 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
2679         struct i40e_link_status link_status;
2680         uint32_t rxfc = 0, txfc = 0, reg;
2681         uint8_t an_info;
2682         int ret;
2683
2684         memset(&link_status, 0, sizeof(link_status));
2685         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
2686         if (ret != I40E_SUCCESS) {
2687                 PMD_DRV_LOG(ERR, "Failed to get link status information\n");
2688                 goto write_reg; /* Disable flow control */
2689         }
2690
2691         an_info = hw->phy.link_info.an_info;
2692         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
2693                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed\n");
2694                 ret = I40E_ERR_NOT_READY;
2695                 goto write_reg; /* Disable flow control */
2696         }
2697         /**
2698          * If link auto negotiation is enabled, flow control needs to
2699          * be configured according to it
2700          */
2701         switch (an_info & I40E_LINK_PAUSE_RXTX) {
2702         case I40E_LINK_PAUSE_RXTX:
2703                 rxfc = 1;
2704                 txfc = 1;
2705                 hw->fc.current_mode = I40E_FC_FULL;
2706                 break;
2707         case I40E_AQ_LINK_PAUSE_RX:
2708                 rxfc = 1;
2709                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2710                 break;
2711         case I40E_AQ_LINK_PAUSE_TX:
2712                 txfc = 1;
2713                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2714                 break;
2715         default:
2716                 hw->fc.current_mode = I40E_FC_NONE;
2717                 break;
2718         }
2719
2720 write_reg:
2721         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
2722                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
2723         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2724         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
2725         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
2726         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
2727
2728         return ret;
2729 }
2730
2731 /* PF setup */
2732 static int
2733 i40e_pf_setup(struct i40e_pf *pf)
2734 {
2735         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2736         struct i40e_filter_control_settings settings;
2737         struct rte_eth_dev_data *dev_data = pf->dev_data;
2738         struct i40e_vsi *vsi;
2739         int ret;
2740
2741         /* Clear all stats counters */
2742         pf->offset_loaded = FALSE;
2743         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
2744         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
2745
2746         ret = i40e_pf_get_switch_config(pf);
2747         if (ret != I40E_SUCCESS) {
2748                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
2749                 return ret;
2750         }
2751
2752         /* VSI setup */
2753         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
2754         if (!vsi) {
2755                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
2756                 return I40E_ERR_NOT_READY;
2757         }
2758         pf->main_vsi = vsi;
2759         dev_data->nb_rx_queues = vsi->nb_qps;
2760         dev_data->nb_tx_queues = vsi->nb_qps;
2761
2762         /* Configure filter control */
2763         memset(&settings, 0, sizeof(settings));
2764         settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
2765         /* Enable ethtype and macvlan filters */
2766         settings.enable_ethtype = TRUE;
2767         settings.enable_macvlan = TRUE;
2768         ret = i40e_set_filter_control(hw, &settings);
2769         if (ret)
2770                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2771                                                                 ret);
2772
2773         /* Update flow control according to the auto negotiation */
2774         i40e_update_flow_control(hw);
2775
2776         return I40E_SUCCESS;
2777 }
2778
2779 int
2780 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2781 {
2782         uint32_t reg;
2783         uint16_t j;
2784
2785         /**
2786          * Set or clear TX Queue Disable flags,
2787          * which is required by hardware.
2788          */
2789         i40e_pre_tx_queue_cfg(hw, q_idx, on);
2790         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
2791
2792         /* Wait until the request is finished */
2793         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2794                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2795                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2796                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2797                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
2798                                                         & 0x1))) {
2799                         break;
2800                 }
2801         }
2802         if (on) {
2803                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
2804                         return I40E_SUCCESS; /* already on, skip next steps */
2805
2806                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
2807                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
2808         } else {
2809                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
2810                         return I40E_SUCCESS; /* already off, skip next steps */
2811                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
2812         }
2813         /* Write the register */
2814         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
2815         /* Check the result */
2816         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2817                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2818                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2819                 if (on) {
2820                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
2821                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
2822                                 break;
2823                 } else {
2824                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
2825                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
2826                                 break;
2827                 }
2828         }
2829         /* Check if it is timeout */
2830         if (j >= I40E_CHK_Q_ENA_COUNT) {
2831                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]\n",
2832                         (on ? "enable" : "disable"), q_idx);
2833                 return I40E_ERR_TIMEOUT;
2834         }
2835
2836         return I40E_SUCCESS;
2837 }
2838
2839 /* Swith on or off the tx queues */
2840 static int
2841 i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on)
2842 {
2843         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
2844         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2845         struct i40e_tx_queue *txq;
2846         uint16_t i, pf_q;
2847         int ret;
2848
2849         pf_q = vsi->base_queue;
2850         for (i = 0; i < dev_data->nb_tx_queues; i++, pf_q++) {
2851                 txq = dev_data->tx_queues[i];
2852                 if (!txq->q_set)
2853                         continue; /* Queue not configured */
2854                 ret = i40e_switch_tx_queue(hw, pf_q, on);
2855                 if ( ret != I40E_SUCCESS)
2856                         return ret;
2857         }
2858
2859         return I40E_SUCCESS;
2860 }
2861
2862 int
2863 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2864 {
2865         uint32_t reg;
2866         uint16_t j;
2867
2868         /* Wait until the request is finished */
2869         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2870                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2871                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
2872                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2873                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
2874                         break;
2875         }
2876
2877         if (on) {
2878                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
2879                         return I40E_SUCCESS; /* Already on, skip next steps */
2880                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
2881         } else {
2882                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
2883                         return I40E_SUCCESS; /* Already off, skip next steps */
2884                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
2885         }
2886
2887         /* Write the register */
2888         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
2889         /* Check the result */
2890         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2891                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2892                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
2893                 if (on) {
2894                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
2895                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
2896                                 break;
2897                 } else {
2898                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
2899                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
2900                                 break;
2901                 }
2902         }
2903
2904         /* Check if it is timeout */
2905         if (j >= I40E_CHK_Q_ENA_COUNT) {
2906                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]\n",
2907                         (on ? "enable" : "disable"), q_idx);
2908                 return I40E_ERR_TIMEOUT;
2909         }
2910
2911         return I40E_SUCCESS;
2912 }
2913 /* Switch on or off the rx queues */
2914 static int
2915 i40e_vsi_switch_rx_queues(struct i40e_vsi *vsi, bool on)
2916 {
2917         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
2918         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2919         struct i40e_rx_queue *rxq;
2920         uint16_t i, pf_q;
2921         int ret;
2922
2923         pf_q = vsi->base_queue;
2924         for (i = 0; i < dev_data->nb_rx_queues; i++, pf_q++) {
2925                 rxq = dev_data->rx_queues[i];
2926                 if (!rxq->q_set)
2927                         continue; /* Queue not configured */
2928                 ret = i40e_switch_rx_queue(hw, pf_q, on);
2929                 if ( ret != I40E_SUCCESS)
2930                         return ret;
2931         }
2932
2933         return I40E_SUCCESS;
2934 }
2935
2936 /* Switch on or off all the rx/tx queues */
2937 int
2938 i40e_vsi_switch_queues(struct i40e_vsi *vsi, bool on)
2939 {
2940         int ret;
2941
2942         if (on) {
2943                 /* enable rx queues before enabling tx queues */
2944                 ret = i40e_vsi_switch_rx_queues(vsi, on);
2945                 if (ret) {
2946                         PMD_DRV_LOG(ERR, "Failed to switch rx queues\n");
2947                         return ret;
2948                 }
2949                 ret = i40e_vsi_switch_tx_queues(vsi, on);
2950         } else {
2951                 /* Stop tx queues before stopping rx queues */
2952                 ret = i40e_vsi_switch_tx_queues(vsi, on);
2953                 if (ret) {
2954                         PMD_DRV_LOG(ERR, "Failed to switch tx queues\n");
2955                         return ret;
2956                 }
2957                 ret = i40e_vsi_switch_rx_queues(vsi, on);
2958         }
2959
2960         return ret;
2961 }
2962
2963 /* Initialize VSI for TX */
2964 static int
2965 i40e_vsi_tx_init(struct i40e_vsi *vsi)
2966 {
2967         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2968         struct rte_eth_dev_data *data = pf->dev_data;
2969         uint16_t i;
2970         uint32_t ret = I40E_SUCCESS;
2971
2972         for (i = 0; i < data->nb_tx_queues; i++) {
2973                 ret = i40e_tx_queue_init(data->tx_queues[i]);
2974                 if (ret != I40E_SUCCESS)
2975                         break;
2976         }
2977
2978         return ret;
2979 }
2980
2981 /* Initialize VSI for RX */
2982 static int
2983 i40e_vsi_rx_init(struct i40e_vsi *vsi)
2984 {
2985         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2986         struct rte_eth_dev_data *data = pf->dev_data;
2987         int ret = I40E_SUCCESS;
2988         uint16_t i;
2989
2990         i40e_pf_config_mq_rx(pf);
2991         for (i = 0; i < data->nb_rx_queues; i++) {
2992                 ret = i40e_rx_queue_init(data->rx_queues[i]);
2993                 if (ret != I40E_SUCCESS) {
2994                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
2995                                         "initialization\n");
2996                         break;
2997                 }
2998         }
2999
3000         return ret;
3001 }
3002
3003 /* Initialize VSI */
3004 static int
3005 i40e_vsi_init(struct i40e_vsi *vsi)
3006 {
3007         int err;
3008
3009         err = i40e_vsi_tx_init(vsi);
3010         if (err) {
3011                 PMD_DRV_LOG(ERR, "Failed to do vsi TX initialization\n");
3012                 return err;
3013         }
3014         err = i40e_vsi_rx_init(vsi);
3015         if (err) {
3016                 PMD_DRV_LOG(ERR, "Failed to do vsi RX initialization\n");
3017                 return err;
3018         }
3019
3020         return err;
3021 }
3022
3023 static void
3024 i40e_stat_update_32(struct i40e_hw *hw,
3025                    uint32_t reg,
3026                    bool offset_loaded,
3027                    uint64_t *offset,
3028                    uint64_t *stat)
3029 {
3030         uint64_t new_data;
3031
3032         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3033         if (!offset_loaded)
3034                 *offset = new_data;
3035
3036         if (new_data >= *offset)
3037                 *stat = (uint64_t)(new_data - *offset);
3038         else
3039                 *stat = (uint64_t)((new_data +
3040                         ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3041 }
3042
3043 static void
3044 i40e_stat_update_48(struct i40e_hw *hw,
3045                    uint32_t hireg,
3046                    uint32_t loreg,
3047                    bool offset_loaded,
3048                    uint64_t *offset,
3049                    uint64_t *stat)
3050 {
3051         uint64_t new_data;
3052
3053         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3054         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3055                         I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3056
3057         if (!offset_loaded)
3058                 *offset = new_data;
3059
3060         if (new_data >= *offset)
3061                 *stat = new_data - *offset;
3062         else
3063                 *stat = (uint64_t)((new_data +
3064                         ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3065
3066         *stat &= I40E_48_BIT_MASK;
3067 }
3068
3069 /* Disable IRQ0 */
3070 void
3071 i40e_pf_disable_irq0(struct i40e_hw *hw)
3072 {
3073         /* Disable all interrupt types */
3074         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3075         I40E_WRITE_FLUSH(hw);
3076 }
3077
3078 /* Enable IRQ0 */
3079 void
3080 i40e_pf_enable_irq0(struct i40e_hw *hw)
3081 {
3082         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3083                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3084                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3085                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3086         I40E_WRITE_FLUSH(hw);
3087 }
3088
3089 static void
3090 i40e_pf_config_irq0(struct i40e_hw *hw)
3091 {
3092         uint32_t enable;
3093
3094         /* read pending request and disable first */
3095         i40e_pf_disable_irq0(hw);
3096         /**
3097          * Enable all interrupt error options to detect possible errors,
3098          * other informative int are ignored
3099          */
3100         enable = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3101                  I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3102                  I40E_PFINT_ICR0_ENA_GRST_MASK |
3103                  I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3104                  I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK |
3105                  I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3106                  I40E_PFINT_ICR0_ENA_VFLR_MASK |
3107                  I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3108
3109         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3110         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3111                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3112
3113         /* Link no queues with irq0 */
3114         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3115                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3116 }
3117
3118 static void
3119 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3120 {
3121         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3122         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3123         int i;
3124         uint16_t abs_vf_id;
3125         uint32_t index, offset, val;
3126
3127         if (!pf->vfs)
3128                 return;
3129         /**
3130          * Try to find which VF trigger a reset, use absolute VF id to access
3131          * since the reg is global register.
3132          */
3133         for (i = 0; i < pf->vf_num; i++) {
3134                 abs_vf_id = hw->func_caps.vf_base_id + i;
3135                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3136                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3137                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3138                 /* VFR event occured */
3139                 if (val & (0x1 << offset)) {
3140                         int ret;
3141
3142                         /* Clear the event first */
3143                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3144                                                         (0x1 << offset));
3145                         PMD_DRV_LOG(INFO, "VF %u reset occured\n", abs_vf_id);
3146                         /**
3147                          * Only notify a VF reset event occured,
3148                          * don't trigger another SW reset
3149                          */
3150                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3151                         if (ret != I40E_SUCCESS)
3152                                 PMD_DRV_LOG(ERR, "Failed to do VF reset\n");
3153                 }
3154         }
3155 }
3156
3157 static void
3158 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3159 {
3160         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3161         struct i40e_arq_event_info info;
3162         uint16_t pending, opcode;
3163         int ret;
3164
3165         info.msg_size = I40E_AQ_BUF_SZ;
3166         info.msg_buf = rte_zmalloc("msg_buffer", I40E_AQ_BUF_SZ, 0);
3167         if (!info.msg_buf) {
3168                 PMD_DRV_LOG(ERR, "Failed to allocate mem\n");
3169                 return;
3170         }
3171
3172         pending = 1;
3173         while (pending) {
3174                 ret = i40e_clean_arq_element(hw, &info, &pending);
3175
3176                 if (ret != I40E_SUCCESS) {
3177                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3178                                 "aq_err: %u\n", hw->aq.asq_last_status);
3179                         break;
3180                 }
3181                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3182
3183                 switch (opcode) {
3184                 case i40e_aqc_opc_send_msg_to_pf:
3185                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3186                         i40e_pf_host_handle_vf_msg(dev,
3187                                         rte_le_to_cpu_16(info.desc.retval),
3188                                         rte_le_to_cpu_32(info.desc.cookie_high),
3189                                         rte_le_to_cpu_32(info.desc.cookie_low),
3190                                         info.msg_buf,
3191                                         info.msg_size);
3192                         break;
3193                 default:
3194                         PMD_DRV_LOG(ERR, "Request %u is not supported yet\n",
3195                                 opcode);
3196                         break;
3197                 }
3198                 /* Reset the buffer after processing one */
3199                 info.msg_size = I40E_AQ_BUF_SZ;
3200         }
3201         rte_free(info.msg_buf);
3202 }
3203
3204 /**
3205  * Interrupt handler triggered by NIC  for handling
3206  * specific interrupt.
3207  *
3208  * @param handle
3209  *  Pointer to interrupt handle.
3210  * @param param
3211  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3212  *
3213  * @return
3214  *  void
3215  */
3216 static void
3217 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3218                            void *param)
3219 {
3220         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3221         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3222         uint32_t cause, enable;
3223
3224         i40e_pf_disable_irq0(hw);
3225
3226         cause = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3227         enable = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
3228
3229         /* Shared IRQ case, return */
3230         if (!(cause & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3231                 PMD_DRV_LOG(INFO, "Port%d INT0:share IRQ case, "
3232                         "no INT event to process\n", hw->pf_id);
3233                 goto done;
3234         }
3235
3236         if (cause & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3237                 PMD_DRV_LOG(INFO, "INT:Link status changed\n");
3238                 i40e_dev_link_update(dev, 0);
3239         }
3240
3241         if (cause & I40E_PFINT_ICR0_ECC_ERR_MASK)
3242                 PMD_DRV_LOG(INFO, "INT:Unrecoverable ECC Error\n");
3243
3244         if (cause & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3245                 PMD_DRV_LOG(INFO, "INT:Malicious programming detected\n");
3246
3247         if (cause & I40E_PFINT_ICR0_GRST_MASK)
3248                 PMD_DRV_LOG(INFO, "INT:Global Resets Requested\n");
3249
3250         if (cause & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3251                 PMD_DRV_LOG(INFO, "INT:PCI EXCEPTION occured\n");
3252
3253         if (cause & I40E_PFINT_ICR0_HMC_ERR_MASK)
3254                 PMD_DRV_LOG(INFO, "INT:HMC error occured\n");
3255
3256         /* Add processing func to deal with VF reset vent */
3257         if (cause & I40E_PFINT_ICR0_VFLR_MASK) {
3258                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3259                 i40e_dev_handle_vfr_event(dev);
3260         }
3261         /* Find admin queue event */
3262         if (cause & I40E_PFINT_ICR0_ADMINQ_MASK) {
3263                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3264                 i40e_dev_handle_aq_msg(dev);
3265         }
3266
3267 done:
3268         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3269         /* Re-enable interrupt from device side */
3270         i40e_pf_enable_irq0(hw);
3271         /* Re-enable interrupt from host side */
3272         rte_intr_enable(&(dev->pci_dev->intr_handle));
3273 }
3274
3275 static int
3276 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3277                          struct i40e_macvlan_filter *filter,
3278                          int total)
3279 {
3280         int ele_num, ele_buff_size;
3281         int num, actual_num, i;
3282         int ret = I40E_SUCCESS;
3283         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3284         struct i40e_aqc_add_macvlan_element_data *req_list;
3285
3286         if (filter == NULL  || total == 0)
3287                 return I40E_ERR_PARAM;
3288         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3289         ele_buff_size = hw->aq.asq_buf_size;
3290
3291         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3292         if (req_list == NULL) {
3293                 PMD_DRV_LOG(ERR, "Fail to allocate memory\n");
3294                 return I40E_ERR_NO_MEMORY;
3295         }
3296
3297         num = 0;
3298         do {
3299                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3300                 memset(req_list, 0, ele_buff_size);
3301
3302                 for (i = 0; i < actual_num; i++) {
3303                         (void)rte_memcpy(req_list[i].mac_addr,
3304                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3305                         req_list[i].vlan_tag =
3306                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3307                         req_list[i].flags = rte_cpu_to_le_16(\
3308                                 I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
3309                         req_list[i].queue_number = 0;
3310                 }
3311
3312                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3313                                                 actual_num, NULL);
3314                 if (ret != I40E_SUCCESS) {
3315                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter\n");
3316                         goto DONE;
3317                 }
3318                 num += actual_num;
3319         } while (num < total);
3320
3321 DONE:
3322         rte_free(req_list);
3323         return ret;
3324 }
3325
3326 static int
3327 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3328                             struct i40e_macvlan_filter *filter,
3329                             int total)
3330 {
3331         int ele_num, ele_buff_size;
3332         int num, actual_num, i;
3333         int ret = I40E_SUCCESS;
3334         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3335         struct i40e_aqc_remove_macvlan_element_data *req_list;
3336
3337         if (filter == NULL  || total == 0)
3338                 return I40E_ERR_PARAM;
3339
3340         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3341         ele_buff_size = hw->aq.asq_buf_size;
3342
3343         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3344         if (req_list == NULL) {
3345                 PMD_DRV_LOG(ERR, "Fail to allocate memory\n");
3346                 return I40E_ERR_NO_MEMORY;
3347         }
3348
3349         num = 0;
3350         do {
3351                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3352                 memset(req_list, 0, ele_buff_size);
3353
3354                 for (i = 0; i < actual_num; i++) {
3355                         (void)rte_memcpy(req_list[i].mac_addr,
3356                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3357                         req_list[i].vlan_tag =
3358                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3359                         req_list[i].flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3360                 }
3361
3362                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
3363                                                 actual_num, NULL);
3364                 if (ret != I40E_SUCCESS) {
3365                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter\n");
3366                         goto DONE;
3367                 }
3368                 num += actual_num;
3369         } while (num < total);
3370
3371 DONE:
3372         rte_free(req_list);
3373         return ret;
3374 }
3375
3376 /* Find out specific MAC filter */
3377 static struct i40e_mac_filter *
3378 i40e_find_mac_filter(struct i40e_vsi *vsi,
3379                          struct ether_addr *macaddr)
3380 {
3381         struct i40e_mac_filter *f;
3382
3383         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3384                 if (is_same_ether_addr(macaddr, &(f->macaddr)))
3385                         return f;
3386         }
3387
3388         return NULL;
3389 }
3390
3391 static bool
3392 i40e_find_vlan_filter(struct i40e_vsi *vsi,
3393                          uint16_t vlan_id)
3394 {
3395         uint32_t vid_idx, vid_bit;
3396
3397         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3398         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3399
3400         if (vsi->vfta[vid_idx] & vid_bit)
3401                 return 1;
3402         else
3403                 return 0;
3404 }
3405
3406 static void
3407 i40e_set_vlan_filter(struct i40e_vsi *vsi,
3408                          uint16_t vlan_id, bool on)
3409 {
3410         uint32_t vid_idx, vid_bit;
3411
3412 #define UINT32_BIT_MASK      0x1F
3413 #define VALID_VLAN_BIT_MASK  0xFFF
3414         /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
3415          *  element first, then find the bits it belongs to
3416          */
3417         vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
3418                   sizeof(uint32_t));
3419         vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
3420
3421         if (on)
3422                 vsi->vfta[vid_idx] |= vid_bit;
3423         else
3424                 vsi->vfta[vid_idx] &= ~vid_bit;
3425 }
3426
3427 /**
3428  * Find all vlan options for specific mac addr,
3429  * return with actual vlan found.
3430  */
3431 static inline int
3432 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
3433                            struct i40e_macvlan_filter *mv_f,
3434                            int num, struct ether_addr *addr)
3435 {
3436         int i;
3437         uint32_t j, k;
3438
3439         /**
3440          * Not to use i40e_find_vlan_filter to decrease the loop time,
3441          * although the code looks complex.
3442           */
3443         if (num < vsi->vlan_num)
3444                 return I40E_ERR_PARAM;
3445
3446         i = 0;
3447         for (j = 0; j < I40E_VFTA_SIZE; j++) {
3448                 if (vsi->vfta[j]) {
3449                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
3450                                 if (vsi->vfta[j] & (1 << k)) {
3451                                         if (i > num - 1) {
3452                                                 PMD_DRV_LOG(ERR, "vlan number "
3453                                                                 "not match\n");
3454                                                 return I40E_ERR_PARAM;
3455                                         }
3456                                         (void)rte_memcpy(&mv_f[i].macaddr,
3457                                                         addr, ETH_ADDR_LEN);
3458                                         mv_f[i].vlan_id =
3459                                                 j * I40E_UINT32_BIT_SIZE + k;
3460                                         i++;
3461                                 }
3462                         }
3463                 }
3464         }
3465         return I40E_SUCCESS;
3466 }
3467
3468 static inline int
3469 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
3470                            struct i40e_macvlan_filter *mv_f,
3471                            int num,
3472                            uint16_t vlan)
3473 {
3474         int i = 0;
3475         struct i40e_mac_filter *f;
3476
3477         if (num < vsi->mac_num)
3478                 return I40E_ERR_PARAM;
3479
3480         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3481                 if (i > num - 1) {
3482                         PMD_DRV_LOG(ERR, "buffer number not match\n");
3483                         return I40E_ERR_PARAM;
3484                 }
3485                 (void)rte_memcpy(&mv_f[i].macaddr, &f->macaddr, ETH_ADDR_LEN);
3486                 mv_f[i].vlan_id = vlan;
3487                 i++;
3488         }
3489
3490         return I40E_SUCCESS;
3491 }
3492
3493 static int
3494 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
3495 {
3496         int i, num;
3497         struct i40e_mac_filter *f;
3498         struct i40e_macvlan_filter *mv_f;
3499         int ret = I40E_SUCCESS;
3500
3501         if (vsi == NULL || vsi->mac_num == 0)
3502                 return I40E_ERR_PARAM;
3503
3504         /* Case that no vlan is set */
3505         if (vsi->vlan_num == 0)
3506                 num = vsi->mac_num;
3507         else
3508                 num = vsi->mac_num * vsi->vlan_num;
3509
3510         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
3511         if (mv_f == NULL) {
3512                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3513                 return I40E_ERR_NO_MEMORY;
3514         }
3515
3516         i = 0;
3517         if (vsi->vlan_num == 0) {
3518                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3519                         (void)rte_memcpy(&mv_f[i].macaddr,
3520                                 &f->macaddr, ETH_ADDR_LEN);
3521                         mv_f[i].vlan_id = 0;
3522                         i++;
3523                 }
3524         } else {
3525                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3526                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
3527                                         vsi->vlan_num, &f->macaddr);
3528                         if (ret != I40E_SUCCESS)
3529                                 goto DONE;
3530                         i += vsi->vlan_num;
3531                 }
3532         }
3533
3534         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
3535 DONE:
3536         rte_free(mv_f);
3537
3538         return ret;
3539 }
3540
3541 int
3542 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3543 {
3544         struct i40e_macvlan_filter *mv_f;
3545         int mac_num;
3546         int ret = I40E_SUCCESS;
3547
3548         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
3549                 return I40E_ERR_PARAM;
3550
3551         /* If it's already set, just return */
3552         if (i40e_find_vlan_filter(vsi,vlan))
3553                 return I40E_SUCCESS;
3554
3555         mac_num = vsi->mac_num;
3556
3557         if (mac_num == 0) {
3558                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr\n");
3559                 return I40E_ERR_PARAM;
3560         }
3561
3562         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3563
3564         if (mv_f == NULL) {
3565                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3566                 return I40E_ERR_NO_MEMORY;
3567         }
3568
3569         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3570
3571         if (ret != I40E_SUCCESS)
3572                 goto DONE;
3573
3574         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3575
3576         if (ret != I40E_SUCCESS)
3577                 goto DONE;
3578
3579         i40e_set_vlan_filter(vsi, vlan, 1);
3580
3581         vsi->vlan_num++;
3582         ret = I40E_SUCCESS;
3583 DONE:
3584         rte_free(mv_f);
3585         return ret;
3586 }
3587
3588 int
3589 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3590 {
3591         struct i40e_macvlan_filter *mv_f;
3592         int mac_num;
3593         int ret = I40E_SUCCESS;
3594
3595         /**
3596          * Vlan 0 is the generic filter for untagged packets
3597          * and can't be removed.
3598          */
3599         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
3600                 return I40E_ERR_PARAM;
3601
3602         /* If can't find it, just return */
3603         if (!i40e_find_vlan_filter(vsi, vlan))
3604                 return I40E_ERR_PARAM;
3605
3606         mac_num = vsi->mac_num;
3607
3608         if (mac_num == 0) {
3609                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr\n");
3610                 return I40E_ERR_PARAM;
3611         }
3612
3613         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3614
3615         if (mv_f == NULL) {
3616                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3617                 return I40E_ERR_NO_MEMORY;
3618         }
3619
3620         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3621
3622         if (ret != I40E_SUCCESS)
3623                 goto DONE;
3624
3625         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
3626
3627         if (ret != I40E_SUCCESS)
3628                 goto DONE;
3629
3630         /* This is last vlan to remove, replace all mac filter with vlan 0 */
3631         if (vsi->vlan_num == 1) {
3632                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
3633                 if (ret != I40E_SUCCESS)
3634                         goto DONE;
3635
3636                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3637                 if (ret != I40E_SUCCESS)
3638                         goto DONE;
3639         }
3640
3641         i40e_set_vlan_filter(vsi, vlan, 0);
3642
3643         vsi->vlan_num--;
3644         ret = I40E_SUCCESS;
3645 DONE:
3646         rte_free(mv_f);
3647         return ret;
3648 }
3649
3650 int
3651 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3652 {
3653         struct i40e_mac_filter *f;
3654         struct i40e_macvlan_filter *mv_f;
3655         int vlan_num;
3656         int ret = I40E_SUCCESS;
3657
3658         /* If it's add and we've config it, return */
3659         f = i40e_find_mac_filter(vsi, addr);
3660         if (f != NULL)
3661                 return I40E_SUCCESS;
3662
3663         /**
3664          * If vlan_num is 0, that's the first time to add mac,
3665          * set mask for vlan_id 0.
3666          */
3667         if (vsi->vlan_num == 0) {
3668                 i40e_set_vlan_filter(vsi, 0, 1);
3669                 vsi->vlan_num = 1;
3670         }
3671
3672         vlan_num = vsi->vlan_num;
3673
3674         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3675         if (mv_f == NULL) {
3676                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3677                 return I40E_ERR_NO_MEMORY;
3678         }
3679
3680         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3681         if (ret != I40E_SUCCESS)
3682                 goto DONE;
3683
3684         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
3685         if (ret != I40E_SUCCESS)
3686                 goto DONE;
3687
3688         /* Add the mac addr into mac list */
3689         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3690         if (f == NULL) {
3691                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3692                 ret = I40E_ERR_NO_MEMORY;
3693                 goto DONE;
3694         }
3695         (void)rte_memcpy(&f->macaddr, addr, ETH_ADDR_LEN);
3696         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3697         vsi->mac_num++;
3698
3699         ret = I40E_SUCCESS;
3700 DONE:
3701         rte_free(mv_f);
3702
3703         return ret;
3704 }
3705
3706 int
3707 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3708 {
3709         struct i40e_mac_filter *f;
3710         struct i40e_macvlan_filter *mv_f;
3711         int vlan_num;
3712         int ret = I40E_SUCCESS;
3713
3714         /* Can't find it, return an error */
3715         f = i40e_find_mac_filter(vsi, addr);
3716         if (f == NULL)
3717                 return I40E_ERR_PARAM;
3718
3719         vlan_num = vsi->vlan_num;
3720         if (vlan_num == 0) {
3721                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
3722                 return I40E_ERR_PARAM;
3723         }
3724         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3725         if (mv_f == NULL) {
3726                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3727                 return I40E_ERR_NO_MEMORY;
3728         }
3729
3730         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3731         if (ret != I40E_SUCCESS)
3732                 goto DONE;
3733
3734         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
3735         if (ret != I40E_SUCCESS)
3736                 goto DONE;
3737
3738         /* Remove the mac addr into mac list */
3739         TAILQ_REMOVE(&vsi->mac_list, f, next);
3740         rte_free(f);
3741         vsi->mac_num--;
3742
3743         ret = I40E_SUCCESS;
3744 DONE:
3745         rte_free(mv_f);
3746         return ret;
3747 }
3748
3749 /* Configure hash enable flags for RSS */
3750 static uint64_t
3751 i40e_config_hena(uint64_t flags)
3752 {
3753         uint64_t hena = 0;
3754
3755         if (!flags)
3756                 return hena;
3757
3758         if (flags & ETH_RSS_NONF_IPV4_UDP)
3759                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3760         if (flags & ETH_RSS_NONF_IPV4_TCP)
3761                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3762         if (flags & ETH_RSS_NONF_IPV4_SCTP)
3763                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3764         if (flags & ETH_RSS_NONF_IPV4_OTHER)
3765                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3766         if (flags & ETH_RSS_FRAG_IPV4)
3767                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
3768         if (flags & ETH_RSS_NONF_IPV6_UDP)
3769                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3770         if (flags & ETH_RSS_NONF_IPV6_TCP)
3771                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3772         if (flags & ETH_RSS_NONF_IPV6_SCTP)
3773                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3774         if (flags & ETH_RSS_NONF_IPV6_OTHER)
3775                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
3776         if (flags & ETH_RSS_FRAG_IPV6)
3777                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
3778         if (flags & ETH_RSS_L2_PAYLOAD)
3779                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
3780
3781         return hena;
3782 }
3783
3784 /* Parse the hash enable flags */
3785 static uint64_t
3786 i40e_parse_hena(uint64_t flags)
3787 {
3788         uint64_t rss_hf = 0;
3789
3790         if (!flags)
3791                 return rss_hf;
3792
3793         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
3794                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
3795         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
3796                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
3797         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
3798                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
3799         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
3800                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
3801         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
3802                 rss_hf |= ETH_RSS_FRAG_IPV4;
3803         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
3804                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
3805         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
3806                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
3807         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
3808                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
3809         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
3810                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
3811         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
3812                 rss_hf |= ETH_RSS_FRAG_IPV6;
3813         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
3814                 rss_hf |= ETH_RSS_L2_PAYLOAD;
3815
3816         return rss_hf;
3817 }
3818
3819 /* Disable RSS */
3820 static void
3821 i40e_pf_disable_rss(struct i40e_pf *pf)
3822 {
3823         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3824         uint64_t hena;
3825
3826         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3827         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3828         hena &= ~I40E_RSS_HENA_ALL;
3829         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
3830         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
3831         I40E_WRITE_FLUSH(hw);
3832 }
3833
3834 static int
3835 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
3836 {
3837         uint32_t *hash_key;
3838         uint8_t hash_key_len;
3839         uint64_t rss_hf;
3840         uint16_t i;
3841         uint64_t hena;
3842
3843         hash_key = (uint32_t *)(rss_conf->rss_key);
3844         hash_key_len = rss_conf->rss_key_len;
3845         if (hash_key != NULL && hash_key_len >=
3846                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
3847                 /* Fill in RSS hash key */
3848                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
3849                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
3850         }
3851
3852         rss_hf = rss_conf->rss_hf;
3853         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3854         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3855         hena &= ~I40E_RSS_HENA_ALL;
3856         hena |= i40e_config_hena(rss_hf);
3857         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
3858         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
3859         I40E_WRITE_FLUSH(hw);
3860
3861         return 0;
3862 }
3863
3864 static int
3865 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
3866                          struct rte_eth_rss_conf *rss_conf)
3867 {
3868         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3869         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
3870         uint64_t hena;
3871
3872         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3873         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3874         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
3875                 if (rss_hf != 0) /* Enable RSS */
3876                         return -EINVAL;
3877                 return 0; /* Nothing to do */
3878         }
3879         /* RSS enabled */
3880         if (rss_hf == 0) /* Disable RSS */
3881                 return -EINVAL;
3882
3883         return i40e_hw_rss_hash_set(hw, rss_conf);
3884 }
3885
3886 static int
3887 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
3888                            struct rte_eth_rss_conf *rss_conf)
3889 {
3890         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3891         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
3892         uint64_t hena;
3893         uint16_t i;
3894
3895         if (hash_key != NULL) {
3896                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
3897                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
3898                 rss_conf->rss_key_len = i * sizeof(uint32_t);
3899         }
3900         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3901         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3902         rss_conf->rss_hf = i40e_parse_hena(hena);
3903
3904         return 0;
3905 }
3906
3907 /* Configure RSS */
3908 static int
3909 i40e_pf_config_rss(struct i40e_pf *pf)
3910 {
3911         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3912         struct rte_eth_rss_conf rss_conf;
3913         uint32_t i, lut = 0;
3914         uint16_t j, num = i40e_prev_power_of_2(pf->dev_data->nb_rx_queues);
3915
3916         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
3917                 if (j == num)
3918                         j = 0;
3919                 lut = (lut << 8) | (j & ((0x1 <<
3920                         hw->func_caps.rss_table_entry_width) - 1));
3921                 if ((i & 3) == 3)
3922                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
3923         }
3924
3925         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
3926         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
3927                 i40e_pf_disable_rss(pf);
3928                 return 0;
3929         }
3930         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
3931                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
3932                 /* Calculate the default hash key */
3933                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
3934                         rss_key_default[i] = (uint32_t)rte_rand();
3935                 rss_conf.rss_key = (uint8_t *)rss_key_default;
3936                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3937                                                         sizeof(uint32_t);
3938         }
3939
3940         return i40e_hw_rss_hash_set(hw, &rss_conf);
3941 }
3942
3943 static int
3944 i40e_pf_config_mq_rx(struct i40e_pf *pf)
3945 {
3946         if (!pf->dev_data->sriov.active) {
3947                 switch (pf->dev_data->dev_conf.rxmode.mq_mode) {
3948                 case ETH_MQ_RX_RSS:
3949                         i40e_pf_config_rss(pf);
3950                         break;
3951                 default:
3952                         i40e_pf_disable_rss(pf);
3953                         break;
3954                 }
3955         }
3956
3957         return 0;
3958 }