lib/librte_pmd_i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define I40E_MIN_RING_DESC     64
  61 #define I40E_MAX_RING_DESC     4096
  62 #define I40E_ALIGN             128
  63 #define DEFAULT_TX_RS_THRESH   32
  64 #define DEFAULT_TX_FREE_THRESH 32
  65 #define I40E_MAX_PKT_TYPE      256
  66
  67 #define I40E_VLAN_TAG_SIZE 4
  68 #define I40E_TX_MAX_BURST  32
  69
  70 #define I40E_DMA_MEM_ALIGN 4096
  71
  72 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  73                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  74
  75 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  76
  77 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
  78         (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
  79
  80 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
  81         ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
  82
  83 static const struct rte_memzone *
  84 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
  85                            const char *ring_name,
  86                            uint16_t queue_id,
  87                            uint32_t ring_size,
  88                            int socket_id);
  89 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  90                                       struct rte_mbuf **tx_pkts,
  91                                       uint16_t nb_pkts);
  92
  93 /* Translate the rx descriptor status to pkt flags */
  94 static inline uint64_t
  95 i40e_rxd_status_to_pkt_flags(uint64_t qword)
  96 {
  97         uint64_t flags;
  98
  99         /* Check if VLAN packet */
 100         flags = qword & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
 101                                                         PKT_RX_VLAN_PKT : 0;
 102
 103         /* Check if RSS_HASH */
 104         flags |= (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 105                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 106                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 107
 108         return flags;
 109 }
 110
 111 static inline uint64_t
 112 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 113 {
 114         uint64_t flags = 0;
 115         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 116
 117 #define I40E_RX_ERR_BITS 0x3f
 118         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 119                 return flags;
 120         /* If RXE bit set, all other status bits are meaningless */
 121         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 122                 flags |= PKT_RX_MAC_ERR;
 123                 return flags;
 124         }
 125
 126         /* If RECIPE bit set, all other status indications should be ignored */
 127         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
 128                 flags |= PKT_RX_RECIP_ERR;
 129                 return flags;
 130         }
 131         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
 132                 flags |= PKT_RX_HBUF_OVERFLOW;
 133         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 134                 flags |= PKT_RX_IP_CKSUM_BAD;
 135         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 136                 flags |= PKT_RX_L4_CKSUM_BAD;
 137         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 138                 flags |= PKT_RX_EIP_CKSUM_BAD;
 139         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
 140                 flags |= PKT_RX_OVERSIZE;
 141
 142         return flags;
 143 }
 144
 145 /* Translate pkt types to pkt flags */
 146 static inline uint64_t
 147 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
 148 {
 149         uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
 150                                         I40E_RXD_QW1_PTYPE_SHIFT);
 151         static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
 152                 0, /* PTYPE 0 */
 153                 0, /* PTYPE 1 */
 154                 0, /* PTYPE 2 */
 155                 0, /* PTYPE 3 */
 156                 0, /* PTYPE 4 */
 157                 0, /* PTYPE 5 */
 158                 0, /* PTYPE 6 */
 159                 0, /* PTYPE 7 */
 160                 0, /* PTYPE 8 */
 161                 0, /* PTYPE 9 */
 162                 0, /* PTYPE 10 */
 163                 0, /* PTYPE 11 */
 164                 0, /* PTYPE 12 */
 165                 0, /* PTYPE 13 */
 166                 0, /* PTYPE 14 */
 167                 0, /* PTYPE 15 */
 168                 0, /* PTYPE 16 */
 169                 0, /* PTYPE 17 */
 170                 0, /* PTYPE 18 */
 171                 0, /* PTYPE 19 */
 172                 0, /* PTYPE 20 */
 173                 0, /* PTYPE 21 */
 174                 PKT_RX_IPV4_HDR, /* PTYPE 22 */
 175                 PKT_RX_IPV4_HDR, /* PTYPE 23 */
 176                 PKT_RX_IPV4_HDR, /* PTYPE 24 */
 177                 0, /* PTYPE 25 */
 178                 PKT_RX_IPV4_HDR, /* PTYPE 26 */
 179                 PKT_RX_IPV4_HDR, /* PTYPE 27 */
 180                 PKT_RX_IPV4_HDR, /* PTYPE 28 */
 181                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
 182                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
 183                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
 184                 0, /* PTYPE 32 */
 185                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
 186                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
 187                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
 188                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
 189                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
 190                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
 191                 0, /* PTYPE 39 */
 192                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
 193                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
 194                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
 195                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
 196                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
 197                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
 198                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
 199                 0, /* PTYPE 47 */
 200                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
 201                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
 202                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
 203                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
 204                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
 205                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
 206                 0, /* PTYPE 54 */
 207                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
 208                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
 209                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
 210                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
 211                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 59 */
 212                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 60 */
 213                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 61 */
 214                 0, /* PTYPE 62 */
 215                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 63 */
 216                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 64 */
 217                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 65 */
 218                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 66 */
 219                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 67 */
 220                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 68 */
 221                 0, /* PTYPE 69 */
 222                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 70 */
 223                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 71 */
 224                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 72 */
 225                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 73 */
 226                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 74 */
 227                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 75 */
 228                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 76 */
 229                 0, /* PTYPE 77 */
 230                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 78 */
 231                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 79 */
 232                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 80 */
 233                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 81 */
 234                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 82 */
 235                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 83 */
 236                 0, /* PTYPE 84 */
 237                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 85 */
 238                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 86 */
 239                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
 240                 PKT_RX_IPV6_HDR, /* PTYPE 88 */
 241                 PKT_RX_IPV6_HDR, /* PTYPE 89 */
 242                 PKT_RX_IPV6_HDR, /* PTYPE 90 */
 243                 0, /* PTYPE 91 */
 244                 PKT_RX_IPV6_HDR, /* PTYPE 92 */
 245                 PKT_RX_IPV6_HDR, /* PTYPE 93 */
 246                 PKT_RX_IPV6_HDR, /* PTYPE 94 */
 247                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
 248                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
 249                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
 250                 0, /* PTYPE 98 */
 251                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
 252                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
 253                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
 254                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
 255                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
 256                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
 257                 0, /* PTYPE 105 */
 258                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
 259                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
 260                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
 261                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
 262                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
 263                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
 264                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
 265                 0, /* PTYPE 113 */
 266                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
 267                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
 268                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
 269                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
 270                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
 271                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
 272                 0, /* PTYPE 120 */
 273                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
 274                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
 275                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
 276                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
 277                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 125 */
 278                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 126 */
 279                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 127 */
 280                 0, /* PTYPE 128 */
 281                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 129 */
 282                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 130 */
 283                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 131 */
 284                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 132 */
 285                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 133 */
 286                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 134 */
 287                 0, /* PTYPE 135 */
 288                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 136 */
 289                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 137 */
 290                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 138 */
 291                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 139 */
 292                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 140 */
 293                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 141 */
 294                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 142 */
 295                 0, /* PTYPE 143 */
 296                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 144 */
 297                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 145 */
 298                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 146 */
 299                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 147 */
 300                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 148 */
 301                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 149 */
 302                 0, /* PTYPE 150 */
 303                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 151 */
 304                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 152 */
 305                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
 306                 0, /* PTYPE 154 */
 307                 0, /* PTYPE 155 */
 308                 0, /* PTYPE 156 */
 309                 0, /* PTYPE 157 */
 310                 0, /* PTYPE 158 */
 311                 0, /* PTYPE 159 */
 312                 0, /* PTYPE 160 */
 313                 0, /* PTYPE 161 */
 314                 0, /* PTYPE 162 */
 315                 0, /* PTYPE 163 */
 316                 0, /* PTYPE 164 */
 317                 0, /* PTYPE 165 */
 318                 0, /* PTYPE 166 */
 319                 0, /* PTYPE 167 */
 320                 0, /* PTYPE 168 */
 321                 0, /* PTYPE 169 */
 322                 0, /* PTYPE 170 */
 323                 0, /* PTYPE 171 */
 324                 0, /* PTYPE 172 */
 325                 0, /* PTYPE 173 */
 326                 0, /* PTYPE 174 */
 327                 0, /* PTYPE 175 */
 328                 0, /* PTYPE 176 */
 329                 0, /* PTYPE 177 */
 330                 0, /* PTYPE 178 */
 331                 0, /* PTYPE 179 */
 332                 0, /* PTYPE 180 */
 333                 0, /* PTYPE 181 */
 334                 0, /* PTYPE 182 */
 335                 0, /* PTYPE 183 */
 336                 0, /* PTYPE 184 */
 337                 0, /* PTYPE 185 */
 338                 0, /* PTYPE 186 */
 339                 0, /* PTYPE 187 */
 340                 0, /* PTYPE 188 */
 341                 0, /* PTYPE 189 */
 342                 0, /* PTYPE 190 */
 343                 0, /* PTYPE 191 */
 344                 0, /* PTYPE 192 */
 345                 0, /* PTYPE 193 */
 346                 0, /* PTYPE 194 */
 347                 0, /* PTYPE 195 */
 348                 0, /* PTYPE 196 */
 349                 0, /* PTYPE 197 */
 350                 0, /* PTYPE 198 */
 351                 0, /* PTYPE 199 */
 352                 0, /* PTYPE 200 */
 353                 0, /* PTYPE 201 */
 354                 0, /* PTYPE 202 */
 355                 0, /* PTYPE 203 */
 356                 0, /* PTYPE 204 */
 357                 0, /* PTYPE 205 */
 358                 0, /* PTYPE 206 */
 359                 0, /* PTYPE 207 */
 360                 0, /* PTYPE 208 */
 361                 0, /* PTYPE 209 */
 362                 0, /* PTYPE 210 */
 363                 0, /* PTYPE 211 */
 364                 0, /* PTYPE 212 */
 365                 0, /* PTYPE 213 */
 366                 0, /* PTYPE 214 */
 367                 0, /* PTYPE 215 */
 368                 0, /* PTYPE 216 */
 369                 0, /* PTYPE 217 */
 370                 0, /* PTYPE 218 */
 371                 0, /* PTYPE 219 */
 372                 0, /* PTYPE 220 */
 373                 0, /* PTYPE 221 */
 374                 0, /* PTYPE 222 */
 375                 0, /* PTYPE 223 */
 376                 0, /* PTYPE 224 */
 377                 0, /* PTYPE 225 */
 378                 0, /* PTYPE 226 */
 379                 0, /* PTYPE 227 */
 380                 0, /* PTYPE 228 */
 381                 0, /* PTYPE 229 */
 382                 0, /* PTYPE 230 */
 383                 0, /* PTYPE 231 */
 384                 0, /* PTYPE 232 */
 385                 0, /* PTYPE 233 */
 386                 0, /* PTYPE 234 */
 387                 0, /* PTYPE 235 */
 388                 0, /* PTYPE 236 */
 389                 0, /* PTYPE 237 */
 390                 0, /* PTYPE 238 */
 391                 0, /* PTYPE 239 */
 392                 0, /* PTYPE 240 */
 393                 0, /* PTYPE 241 */
 394                 0, /* PTYPE 242 */
 395                 0, /* PTYPE 243 */
 396                 0, /* PTYPE 244 */
 397                 0, /* PTYPE 245 */
 398                 0, /* PTYPE 246 */
 399                 0, /* PTYPE 247 */
 400                 0, /* PTYPE 248 */
 401                 0, /* PTYPE 249 */
 402                 0, /* PTYPE 250 */
 403                 0, /* PTYPE 251 */
 404                 0, /* PTYPE 252 */
 405                 0, /* PTYPE 253 */
 406                 0, /* PTYPE 254 */
 407                 0, /* PTYPE 255 */
 408         };
 409
 410         return ip_ptype_map[ptype];
 411 }
 412
 413 static inline void
 414 i40e_txd_enable_checksum(uint64_t ol_flags,
 415                         uint32_t *td_cmd,
 416                         uint32_t *td_offset,
 417                         uint8_t l2_len,
 418                         uint16_t l3_len,
 419                         uint8_t inner_l2_len,
 420                         uint16_t inner_l3_len,
 421                         uint32_t *cd_tunneling)
 422 {
 423         if (!l2_len) {
 424                 PMD_DRV_LOG(DEBUG, "L2 length set to 0");
 425                 return;
 426         }
 427         *td_offset |= (l2_len >> 1) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 428
 429         if (!l3_len) {
 430                 PMD_DRV_LOG(DEBUG, "L3 length set to 0");
 431                 return;
 432         }
 433
 434         /* VxLAN packet TX checksum offload */
 435         if (unlikely(ol_flags & PKT_TX_VXLAN_CKSUM)) {
 436                 uint8_t l4tun_len;
 437
 438                 l4tun_len = ETHER_VXLAN_HLEN + inner_l2_len;
 439
 440                 if (ol_flags & PKT_TX_IPV4_CSUM)
 441                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 442                 else if (ol_flags & PKT_TX_IPV6)
 443                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 444
 445                 /* Now set the ctx descriptor fields */
 446                 *cd_tunneling |= (l3_len >> 2) <<
 447                                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
 448                                 I40E_TXD_CTX_UDP_TUNNELING |
 449                                 (l4tun_len >> 1) <<
 450                                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 451
 452                 l3_len = inner_l3_len;
 453         }
 454
 455         /* Enable L3 checksum offloads */
 456         if (ol_flags & PKT_TX_IPV4_CSUM) {
 457                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 458                 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 459         } else if (ol_flags & PKT_TX_IPV4) {
 460                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 461                 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 462         } else if (ol_flags & PKT_TX_IPV6) {
 463                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 464                 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 465         }
 466
 467         /* Enable L4 checksum offloads */
 468         switch (ol_flags & PKT_TX_L4_MASK) {
 469         case PKT_TX_TCP_CKSUM:
 470                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 471                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 472                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 473                 break;
 474         case PKT_TX_SCTP_CKSUM:
 475                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 476                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 477                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 478                 break;
 479         case PKT_TX_UDP_CKSUM:
 480                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 481                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 482                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 483                 break;
 484         default:
 485                 break;
 486         }
 487 }
 488
 489 static inline struct rte_mbuf *
 490 rte_rxmbuf_alloc(struct rte_mempool *mp)
 491 {
 492         struct rte_mbuf *m;
 493
 494         m = __rte_mbuf_raw_alloc(mp);
 495         __rte_mbuf_sanity_check_raw(m, 0);
 496
 497         return m;
 498 }
 499
 500 /* Construct the tx flags */
 501 static inline uint64_t
 502 i40e_build_ctob(uint32_t td_cmd,
 503                 uint32_t td_offset,
 504                 unsigned int size,
 505                 uint32_t td_tag)
 506 {
 507         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 508                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 509                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 510                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 511                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 512 }
 513
 514 static inline int
 515 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 516 {
 517         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 518         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 519         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 520         uint16_t nb_tx_desc = txq->nb_tx_desc;
 521         uint16_t desc_to_clean_to;
 522         uint16_t nb_tx_to_clean;
 523
 524         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 525         if (desc_to_clean_to >= nb_tx_desc)
 526                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 527
 528         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 529         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
 530                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) {
 531                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 532                         "(port=%d queue=%d)", desc_to_clean_to,
 533                                 txq->port_id, txq->queue_id);
 534                 return -1;
 535         }
 536
 537         if (last_desc_cleaned > desc_to_clean_to)
 538                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 539                                                         desc_to_clean_to);
 540         else
 541                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 542                                         last_desc_cleaned);
 543
 544         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 545
 546         txq->last_desc_cleaned = desc_to_clean_to;
 547         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 548
 549         return 0;
 550 }
 551
 552 static inline int
 553 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 554 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 555 #else
 556 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 557 #endif
 558 {
 559         int ret = 0;
 560
 561 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 562         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 563                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 564                              "rxq->rx_free_thresh=%d, "
 565                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 566                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 567                 ret = -EINVAL;
 568         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 569                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 570                              "rxq->rx_free_thresh=%d, "
 571                              "rxq->nb_rx_desc=%d",
 572                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 573                 ret = -EINVAL;
 574         } else if (!(rxq->nb_rx_desc % rxq->rx_free_thresh) == 0) {
 575                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 576                              "rxq->nb_rx_desc=%d, "
 577                              "rxq->rx_free_thresh=%d",
 578                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 579                 ret = -EINVAL;
 580         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 581                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 582                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 583                              "rxq->nb_rx_desc=%d, "
 584                              "I40E_MAX_RING_DESC=%d, "
 585                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 586                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 587                              RTE_PMD_I40E_RX_MAX_BURST);
 588                 ret = -EINVAL;
 589         }
 590 #else
 591         ret = -EINVAL;
 592 #endif
 593
 594         return ret;
 595 }
 596
 597 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 598 #define I40E_LOOK_AHEAD 8
 599 #if (I40E_LOOK_AHEAD != 8)
 600 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 601 #endif
 602 static inline int
 603 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 604 {
 605         volatile union i40e_rx_desc *rxdp;
 606         struct i40e_rx_entry *rxep;
 607         struct rte_mbuf *mb;
 608         uint16_t pkt_len;
 609         uint64_t qword1;
 610         uint32_t rx_status;
 611         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 612         int32_t i, j, nb_rx = 0;
 613         uint64_t pkt_flags;
 614
 615         rxdp = &rxq->rx_ring[rxq->rx_tail];
 616         rxep = &rxq->sw_ring[rxq->rx_tail];
 617
 618         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 619         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 620                                 I40E_RXD_QW1_STATUS_SHIFT;
 621
 622         /* Make sure there is at least 1 packet to receive */
 623         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 624                 return 0;
 625
 626         /**
 627          * Scan LOOK_AHEAD descriptors at a time to determine which
 628          * descriptors reference packets that are ready to be received.
 629          */
 630         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 631                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 632                 /* Read desc statuses backwards to avoid race condition */
 633                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 634                         qword1 = rte_le_to_cpu_64(\
 635                                 rxdp[j].wb.qword1.status_error_len);
 636                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 637                                         I40E_RXD_QW1_STATUS_SHIFT;
 638                 }
 639
 640                 /* Compute how many status bits were set */
 641                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 642                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 643
 644                 nb_rx += nb_dd;
 645
 646                 /* Translate descriptor info to mbuf parameters */
 647                 for (j = 0; j < nb_dd; j++) {
 648                         mb = rxep[j].mbuf;
 649                         qword1 = rte_le_to_cpu_64(\
 650                                 rxdp[j].wb.qword1.status_error_len);
 651                         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 652                                                 I40E_RXD_QW1_STATUS_SHIFT;
 653                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 654                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 655                         mb->data_len = pkt_len;
 656                         mb->pkt_len = pkt_len;
 657                         mb->vlan_tci = rx_status &
 658                                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
 659                         rte_le_to_cpu_16(\
 660                                 rxdp[j].wb.qword0.lo_dword.l2tag1) : 0;
 661                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 662                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 663                         pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
 664                         mb->ol_flags = pkt_flags;
 665
 666                         mb->packet_type = (uint16_t)((qword1 &
 667                                         I40E_RXD_QW1_PTYPE_MASK) >>
 668                                         I40E_RXD_QW1_PTYPE_SHIFT);
 669                         if (pkt_flags & PKT_RX_RSS_HASH)
 670                                 mb->hash.rss = rte_le_to_cpu_32(\
 671                                         rxdp->wb.qword0.hi_dword.rss);
 672                 }
 673
 674                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 675                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 676
 677                 if (nb_dd != I40E_LOOK_AHEAD)
 678                         break;
 679         }
 680
 681         /* Clear software ring entries */
 682         for (i = 0; i < nb_rx; i++)
 683                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 684
 685         return nb_rx;
 686 }
 687
 688 static inline uint16_t
 689 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 690                         struct rte_mbuf **rx_pkts,
 691                         uint16_t nb_pkts)
 692 {
 693         uint16_t i;
 694         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 695
 696         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 697
 698         for (i = 0; i < nb_pkts; i++)
 699                 rx_pkts[i] = stage[i];
 700
 701         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 702         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 703
 704         return nb_pkts;
 705 }
 706
 707 static inline int
 708 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 709 {
 710         volatile union i40e_rx_desc *rxdp;
 711         struct i40e_rx_entry *rxep;
 712         struct rte_mbuf *mb;
 713         uint16_t alloc_idx, i;
 714         uint64_t dma_addr;
 715         int diag;
 716
 717         /* Allocate buffers in bulk */
 718         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 719                                 (rxq->rx_free_thresh - 1));
 720         rxep = &(rxq->sw_ring[alloc_idx]);
 721         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 722                                         rxq->rx_free_thresh);
 723         if (unlikely(diag != 0)) {
 724                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 725                 return -ENOMEM;
 726         }
 727
 728         rxdp = &rxq->rx_ring[alloc_idx];
 729         for (i = 0; i < rxq->rx_free_thresh; i++) {
 730                 mb = rxep[i].mbuf;
 731                 rte_mbuf_refcnt_set(mb, 1);
 732                 mb->next = NULL;
 733                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 734                 mb->nb_segs = 1;
 735                 mb->port = rxq->port_id;
 736                 dma_addr = rte_cpu_to_le_64(\
 737                         RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
 738                 rxdp[i].read.hdr_addr = dma_addr;
 739                 rxdp[i].read.pkt_addr = dma_addr;
 740         }
 741
 742         /* Update rx tail regsiter */
 743         rte_wmb();
 744         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 745
 746         rxq->rx_free_trigger =
 747                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 748         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 749                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 750
 751         return 0;
 752 }
 753
 754 static inline uint16_t
 755 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 756 {
 757         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 758         uint16_t nb_rx = 0;
 759
 760         if (!nb_pkts)
 761                 return 0;
 762
 763         if (rxq->rx_nb_avail)
 764                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 765
 766         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 767         rxq->rx_next_avail = 0;
 768         rxq->rx_nb_avail = nb_rx;
 769         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 770
 771         if (rxq->rx_tail > rxq->rx_free_trigger) {
 772                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 773                         uint16_t i, j;
 774
 775                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
 776                                    "port_id=%u, queue_id=%u",
 777                                    rxq->port_id, rxq->queue_id);
 778                         rxq->rx_nb_avail = 0;
 779                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 780                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 781                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 782
 783                         return 0;
 784                 }
 785         }
 786
 787         if (rxq->rx_tail >= rxq->nb_rx_desc)
 788                 rxq->rx_tail = 0;
 789
 790         if (rxq->rx_nb_avail)
 791                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 792
 793         return 0;
 794 }
 795
 796 static uint16_t
 797 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 798                           struct rte_mbuf **rx_pkts,
 799                           uint16_t nb_pkts)
 800 {
 801         uint16_t nb_rx = 0, n, count;
 802
 803         if (unlikely(nb_pkts == 0))
 804                 return 0;
 805
 806         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 807                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 808
 809         while (nb_pkts) {
 810                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 811                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 812                 nb_rx = (uint16_t)(nb_rx + count);
 813                 nb_pkts = (uint16_t)(nb_pkts - count);
 814                 if (count < n)
 815                         break;
 816         }
 817
 818         return nb_rx;
 819 }
 820 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 821
 822 uint16_t
 823 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 824 {
 825         struct i40e_rx_queue *rxq;
 826         volatile union i40e_rx_desc *rx_ring;
 827         volatile union i40e_rx_desc *rxdp;
 828         union i40e_rx_desc rxd;
 829         struct i40e_rx_entry *sw_ring;
 830         struct i40e_rx_entry *rxe;
 831         struct rte_mbuf *rxm;
 832         struct rte_mbuf *nmb;
 833         uint16_t nb_rx;
 834         uint32_t rx_status;
 835         uint64_t qword1;
 836         uint16_t rx_packet_len;
 837         uint16_t rx_id, nb_hold;
 838         uint64_t dma_addr;
 839         uint64_t pkt_flags;
 840
 841         nb_rx = 0;
 842         nb_hold = 0;
 843         rxq = rx_queue;
 844         rx_id = rxq->rx_tail;
 845         rx_ring = rxq->rx_ring;
 846         sw_ring = rxq->sw_ring;
 847
 848         while (nb_rx < nb_pkts) {
 849                 rxdp = &rx_ring[rx_id];
 850                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 851                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 852                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 853                 /* Check the DD bit first */
 854                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 855                         break;
 856
 857                 nmb = rte_rxmbuf_alloc(rxq->mp);
 858                 if (unlikely(!nmb))
 859                         break;
 860                 rxd = *rxdp;
 861
 862                 nb_hold++;
 863                 rxe = &sw_ring[rx_id];
 864                 rx_id++;
 865                 if (unlikely(rx_id == rxq->nb_rx_desc))
 866                         rx_id = 0;
 867
 868                 /* Prefetch next mbuf */
 869                 rte_prefetch0(sw_ring[rx_id].mbuf);
 870
 871                 /**
 872                  * When next RX descriptor is on a cache line boundary,
 873                  * prefetch the next 4 RX descriptors and next 8 pointers
 874                  * to mbufs.
 875                  */
 876                 if ((rx_id & 0x3) == 0) {
 877                         rte_prefetch0(&rx_ring[rx_id]);
 878                         rte_prefetch0(&sw_ring[rx_id]);
 879                 }
 880                 rxm = rxe->mbuf;
 881                 rxe->mbuf = nmb;
 882                 dma_addr =
 883                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
 884                 rxdp->read.hdr_addr = dma_addr;
 885                 rxdp->read.pkt_addr = dma_addr;
 886
 887                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 888                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 889
 890                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 891                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 892                 rxm->nb_segs = 1;
 893                 rxm->next = NULL;
 894                 rxm->pkt_len = rx_packet_len;
 895                 rxm->data_len = rx_packet_len;
 896                 rxm->port = rxq->port_id;
 897
 898                 rxm->vlan_tci = rx_status &
 899                         (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
 900                         rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
 901                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 902                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 903                 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
 904                 rxm->packet_type = (uint16_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >>
 905                                 I40E_RXD_QW1_PTYPE_SHIFT);
 906                 rxm->ol_flags = pkt_flags;
 907                 if (pkt_flags & PKT_RX_RSS_HASH)
 908                         rxm->hash.rss =
 909                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 910
 911                 rx_pkts[nb_rx++] = rxm;
 912         }
 913         rxq->rx_tail = rx_id;
 914
 915         /**
 916          * If the number of free RX descriptors is greater than the RX free
 917          * threshold of the queue, advance the receive tail register of queue.
 918          * Update that register with the value of the last processed RX
 919          * descriptor minus 1.
 920          */
 921         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 922         if (nb_hold > rxq->rx_free_thresh) {
 923                 rx_id = (uint16_t) ((rx_id == 0) ?
 924                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 925                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 926                 nb_hold = 0;
 927         }
 928         rxq->nb_rx_hold = nb_hold;
 929
 930         return nb_rx;
 931 }
 932
 933 uint16_t
 934 i40e_recv_scattered_pkts(void *rx_queue,
 935                          struct rte_mbuf **rx_pkts,
 936                          uint16_t nb_pkts)
 937 {
 938         struct i40e_rx_queue *rxq = rx_queue;
 939         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 940         volatile union i40e_rx_desc *rxdp;
 941         union i40e_rx_desc rxd;
 942         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 943         struct i40e_rx_entry *rxe;
 944         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 945         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 946         struct rte_mbuf *nmb, *rxm;
 947         uint16_t rx_id = rxq->rx_tail;
 948         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 949         uint32_t rx_status;
 950         uint64_t qword1;
 951         uint64_t dma_addr;
 952         uint64_t pkt_flags;
 953
 954         while (nb_rx < nb_pkts) {
 955                 rxdp = &rx_ring[rx_id];
 956                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 957                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 958                                         I40E_RXD_QW1_STATUS_SHIFT;
 959                 /* Check the DD bit */
 960                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 961                         break;
 962
 963                 nmb = rte_rxmbuf_alloc(rxq->mp);
 964                 if (unlikely(!nmb))
 965                         break;
 966                 rxd = *rxdp;
 967                 nb_hold++;
 968                 rxe = &sw_ring[rx_id];
 969                 rx_id++;
 970                 if (rx_id == rxq->nb_rx_desc)
 971                         rx_id = 0;
 972
 973                 /* Prefetch next mbuf */
 974                 rte_prefetch0(sw_ring[rx_id].mbuf);
 975
 976                 /**
 977                  * When next RX descriptor is on a cache line boundary,
 978                  * prefetch the next 4 RX descriptors and next 8 pointers
 979                  * to mbufs.
 980                  */
 981                 if ((rx_id & 0x3) == 0) {
 982                         rte_prefetch0(&rx_ring[rx_id]);
 983                         rte_prefetch0(&sw_ring[rx_id]);
 984                 }
 985
 986                 rxm = rxe->mbuf;
 987                 rxe->mbuf = nmb;
 988                 dma_addr =
 989                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
 990
 991                 /* Set data buffer address and data length of the mbuf */
 992                 rxdp->read.hdr_addr = dma_addr;
 993                 rxdp->read.pkt_addr = dma_addr;
 994                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 995                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 996                 rxm->data_len = rx_packet_len;
 997                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 998
 999                 /**
1000                  * If this is the first buffer of the received packet, set the
1001                  * pointer to the first mbuf of the packet and initialize its
1002                  * context. Otherwise, update the total length and the number
1003                  * of segments of the current scattered packet, and update the
1004                  * pointer to the last mbuf of the current packet.
1005                  */
1006                 if (!first_seg) {
1007                         first_seg = rxm;
1008                         first_seg->nb_segs = 1;
1009                         first_seg->pkt_len = rx_packet_len;
1010                 } else {
1011                         first_seg->pkt_len =
1012                                 (uint16_t)(first_seg->pkt_len +
1013                                                 rx_packet_len);
1014                         first_seg->nb_segs++;
1015                         last_seg->next = rxm;
1016                 }
1017
1018                 /**
1019                  * If this is not the last buffer of the received packet,
1020                  * update the pointer to the last mbuf of the current scattered
1021                  * packet and continue to parse the RX ring.
1022                  */
1023                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1024                         last_seg = rxm;
1025                         continue;
1026                 }
1027
1028                 /**
1029                  * This is the last buffer of the received packet. If the CRC
1030                  * is not stripped by the hardware:
1031                  *  - Subtract the CRC length from the total packet length.
1032                  *  - If the last buffer only contains the whole CRC or a part
1033                  *  of it, free the mbuf associated to the last buffer. If part
1034                  *  of the CRC is also contained in the previous mbuf, subtract
1035                  *  the length of that CRC part from the data length of the
1036                  *  previous mbuf.
1037                  */
1038                 rxm->next = NULL;
1039                 if (unlikely(rxq->crc_len > 0)) {
1040                         first_seg->pkt_len -= ETHER_CRC_LEN;
1041                         if (rx_packet_len <= ETHER_CRC_LEN) {
1042                                 rte_pktmbuf_free_seg(rxm);
1043                                 first_seg->nb_segs--;
1044                                 last_seg->data_len =
1045                                         (uint16_t)(last_seg->data_len -
1046                                         (ETHER_CRC_LEN - rx_packet_len));
1047                                 last_seg->next = NULL;
1048                         } else
1049                                 rxm->data_len = (uint16_t)(rx_packet_len -
1050                                                                 ETHER_CRC_LEN);
1051                 }
1052
1053                 first_seg->port = rxq->port_id;
1054                 first_seg->vlan_tci = (rx_status &
1055                         (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1056                         rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
1057                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1058                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1059                 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1060                 first_seg->packet_type = (uint16_t)((qword1 &
1061                                         I40E_RXD_QW1_PTYPE_MASK) >>
1062                                         I40E_RXD_QW1_PTYPE_SHIFT);
1063                 first_seg->ol_flags = pkt_flags;
1064                 if (pkt_flags & PKT_RX_RSS_HASH)
1065                         rxm->hash.rss =
1066                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1067
1068                 /* Prefetch data of first segment, if configured to do so. */
1069                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1070                         first_seg->data_off));
1071                 rx_pkts[nb_rx++] = first_seg;
1072                 first_seg = NULL;
1073         }
1074
1075         /* Record index of the next RX descriptor to probe. */
1076         rxq->rx_tail = rx_id;
1077         rxq->pkt_first_seg = first_seg;
1078         rxq->pkt_last_seg = last_seg;
1079
1080         /**
1081          * If the number of free RX descriptors is greater than the RX free
1082          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1083          * register. Update the RDT with the value of the last processed RX
1084          * descriptor minus 1, to guarantee that the RDT register is never
1085          * equal to the RDH register, which creates a "full" ring situtation
1086          * from the hardware point of view.
1087          */
1088         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1089         if (nb_hold > rxq->rx_free_thresh) {
1090                 rx_id = (uint16_t)(rx_id == 0 ?
1091                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1092                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1093                 nb_hold = 0;
1094         }
1095         rxq->nb_rx_hold = nb_hold;
1096
1097         return nb_rx;
1098 }
1099
1100 /* Check if the context descriptor is needed for TX offloading */
1101 static inline uint16_t
1102 i40e_calc_context_desc(uint64_t flags)
1103 {
1104         uint64_t mask = 0ULL;
1105
1106         if (flags | PKT_TX_VXLAN_CKSUM)
1107                 mask |= PKT_TX_VXLAN_CKSUM;
1108
1109 #ifdef RTE_LIBRTE_IEEE1588
1110         mask |= PKT_TX_IEEE1588_TMST;
1111 #endif
1112         if (flags & mask)
1113                 return 1;
1114
1115         return 0;
1116 }
1117
1118 uint16_t
1119 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1120 {
1121         struct i40e_tx_queue *txq;
1122         struct i40e_tx_entry *sw_ring;
1123         struct i40e_tx_entry *txe, *txn;
1124         volatile struct i40e_tx_desc *txd;
1125         volatile struct i40e_tx_desc *txr;
1126         struct rte_mbuf *tx_pkt;
1127         struct rte_mbuf *m_seg;
1128         uint32_t cd_tunneling_params;
1129         uint16_t tx_id;
1130         uint16_t nb_tx;
1131         uint32_t td_cmd;
1132         uint32_t td_offset;
1133         uint32_t tx_flags;
1134         uint32_t td_tag;
1135         uint64_t ol_flags;
1136         uint8_t l2_len;
1137         uint16_t l3_len;
1138         uint8_t inner_l2_len;
1139         uint16_t inner_l3_len;
1140         uint16_t nb_used;
1141         uint16_t nb_ctx;
1142         uint16_t tx_last;
1143         uint16_t slen;
1144         uint64_t buf_dma_addr;
1145
1146         txq = tx_queue;
1147         sw_ring = txq->sw_ring;
1148         txr = txq->tx_ring;
1149         tx_id = txq->tx_tail;
1150         txe = &sw_ring[tx_id];
1151
1152         /* Check if the descriptor ring needs to be cleaned. */
1153         if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh)
1154                 i40e_xmit_cleanup(txq);
1155
1156         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1157                 td_cmd = 0;
1158                 td_tag = 0;
1159                 td_offset = 0;
1160                 tx_flags = 0;
1161
1162                 tx_pkt = *tx_pkts++;
1163                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1164
1165                 ol_flags = tx_pkt->ol_flags;
1166                 l2_len = tx_pkt->l2_len;
1167                 inner_l2_len = tx_pkt->inner_l2_len;
1168                 l3_len = tx_pkt->l3_len;
1169                 inner_l3_len = tx_pkt->inner_l3_len;
1170
1171                 /* Calculate the number of context descriptors needed. */
1172                 nb_ctx = i40e_calc_context_desc(ol_flags);
1173
1174                 /**
1175                  * The number of descriptors that must be allocated for
1176                  * a packet equals to the number of the segments of that
1177                  * packet plus 1 context descriptor if needed.
1178                  */
1179                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1180                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1181
1182                 /* Circular ring */
1183                 if (tx_last >= txq->nb_tx_desc)
1184                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1185
1186                 if (nb_used > txq->nb_tx_free) {
1187                         if (i40e_xmit_cleanup(txq) != 0) {
1188                                 if (nb_tx == 0)
1189                                         return 0;
1190                                 goto end_of_tx;
1191                         }
1192                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1193                                 while (nb_used > txq->nb_tx_free) {
1194                                         if (i40e_xmit_cleanup(txq) != 0) {
1195                                                 if (nb_tx == 0)
1196                                                         return 0;
1197                                                 goto end_of_tx;
1198                                         }
1199                                 }
1200                         }
1201                 }
1202
1203                 /* Descriptor based VLAN insertion */
1204                 if (ol_flags & PKT_TX_VLAN_PKT) {
1205                         tx_flags |= tx_pkt->vlan_tci <<
1206                                         I40E_TX_FLAG_L2TAG1_SHIFT;
1207                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1208                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1209                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1210                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1211                 }
1212
1213                 /* Always enable CRC offload insertion */
1214                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1215
1216                 /* Enable checksum offloading */
1217                 cd_tunneling_params = 0;
1218                 i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1219                                                 l2_len, l3_len, inner_l2_len,
1220                                                 inner_l3_len,
1221                                                 &cd_tunneling_params);
1222
1223                 if (unlikely(nb_ctx)) {
1224                         /* Setup TX context descriptor if required */
1225                         volatile struct i40e_tx_context_desc *ctx_txd =
1226                                 (volatile struct i40e_tx_context_desc *)\
1227                                                         &txr[tx_id];
1228                         uint16_t cd_l2tag2 = 0;
1229                         uint64_t cd_type_cmd_tso_mss =
1230                                 I40E_TX_DESC_DTYPE_CONTEXT;
1231
1232                         txn = &sw_ring[txe->next_id];
1233                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1234                         if (txe->mbuf != NULL) {
1235                                 rte_pktmbuf_free_seg(txe->mbuf);
1236                                 txe->mbuf = NULL;
1237                         }
1238 #ifdef RTE_LIBRTE_IEEE1588
1239                         if (ol_flags & PKT_TX_IEEE1588_TMST)
1240                                 cd_type_cmd_tso_mss |=
1241                                         ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1242                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1243 #endif
1244                         ctx_txd->tunneling_params =
1245                                 rte_cpu_to_le_32(cd_tunneling_params);
1246                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1247                         ctx_txd->type_cmd_tso_mss =
1248                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1249                         txe->last_id = tx_last;
1250                         tx_id = txe->next_id;
1251                         txe = txn;
1252                 }
1253
1254                 m_seg = tx_pkt;
1255                 do {
1256                         txd = &txr[tx_id];
1257                         txn = &sw_ring[txe->next_id];
1258
1259                         if (txe->mbuf)
1260                                 rte_pktmbuf_free_seg(txe->mbuf);
1261                         txe->mbuf = m_seg;
1262
1263                         /* Setup TX Descriptor */
1264                         slen = m_seg->data_len;
1265                         buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1266                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1267                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1268                                                 td_offset, slen, td_tag);
1269                         txe->last_id = tx_last;
1270                         tx_id = txe->next_id;
1271                         txe = txn;
1272                         m_seg = m_seg->next;
1273                 } while (m_seg != NULL);
1274
1275                 /* The last packet data descriptor needs End Of Packet (EOP) */
1276                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1277                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1278                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1279
1280                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1281                         PMD_TX_FREE_LOG(DEBUG,
1282                                         "Setting RS bit on TXD id="
1283                                         "%4u (port=%d queue=%d)",
1284                                         tx_last, txq->port_id, txq->queue_id);
1285
1286                         td_cmd |= I40E_TX_DESC_CMD_RS;
1287
1288                         /* Update txq RS bit counters */
1289                         txq->nb_tx_used = 0;
1290                 }
1291
1292                 txd->cmd_type_offset_bsz |=
1293                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1294                                         I40E_TXD_QW1_CMD_SHIFT);
1295         }
1296
1297 end_of_tx:
1298         rte_wmb();
1299
1300         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1301                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1302                    (unsigned) tx_id, (unsigned) nb_tx);
1303
1304         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1305         txq->tx_tail = tx_id;
1306
1307         return nb_tx;
1308 }
1309
1310 static inline int __attribute__((always_inline))
1311 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1312 {
1313         struct i40e_tx_entry *txep;
1314         uint16_t i;
1315
1316         if (!(txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1317                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)))
1318                 return 0;
1319
1320         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1321
1322         for (i = 0; i < txq->tx_rs_thresh; i++)
1323                 rte_prefetch0((txep + i)->mbuf);
1324
1325         if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1326                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1327                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1328                         txep->mbuf = NULL;
1329                 }
1330         } else {
1331                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1332                         rte_pktmbuf_free_seg(txep->mbuf);
1333                         txep->mbuf = NULL;
1334                 }
1335         }
1336
1337         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1338         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1339         if (txq->tx_next_dd >= txq->nb_tx_desc)
1340                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1341
1342         return txq->tx_rs_thresh;
1343 }
1344
1345 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1346                      I40E_TX_DESC_CMD_EOP)
1347
1348 /* Populate 4 descriptors with data from 4 mbufs */
1349 static inline void
1350 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1351 {
1352         uint64_t dma_addr;
1353         uint32_t i;
1354
1355         for (i = 0; i < 4; i++, txdp++, pkts++) {
1356                 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1357                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1358                 txdp->cmd_type_offset_bsz =
1359                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1360                                         (*pkts)->data_len, 0);
1361         }
1362 }
1363
1364 /* Populate 1 descriptor with data from 1 mbuf */
1365 static inline void
1366 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1367 {
1368         uint64_t dma_addr;
1369
1370         dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1371         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1372         txdp->cmd_type_offset_bsz =
1373                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1374                                 (*pkts)->data_len, 0);
1375 }
1376
1377 /* Fill hardware descriptor ring with mbuf data */
1378 static inline void
1379 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1380                      struct rte_mbuf **pkts,
1381                      uint16_t nb_pkts)
1382 {
1383         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1384         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1385         const int N_PER_LOOP = 4;
1386         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1387         int mainpart, leftover;
1388         int i, j;
1389
1390         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1391         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1392         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1393                 for (j = 0; j < N_PER_LOOP; ++j) {
1394                         (txep + i + j)->mbuf = *(pkts + i + j);
1395                 }
1396                 tx4(txdp + i, pkts + i);
1397         }
1398         if (unlikely(leftover > 0)) {
1399                 for (i = 0; i < leftover; ++i) {
1400                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1401                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1402                 }
1403         }
1404 }
1405
1406 static inline uint16_t
1407 tx_xmit_pkts(struct i40e_tx_queue *txq,
1408              struct rte_mbuf **tx_pkts,
1409              uint16_t nb_pkts)
1410 {
1411         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1412         uint16_t n = 0;
1413
1414         /**
1415          * Begin scanning the H/W ring for done descriptors when the number
1416          * of available descriptors drops below tx_free_thresh. For each done
1417          * descriptor, free the associated buffer.
1418          */
1419         if (txq->nb_tx_free < txq->tx_free_thresh)
1420                 i40e_tx_free_bufs(txq);
1421
1422         /* Use available descriptor only */
1423         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1424         if (unlikely(!nb_pkts))
1425                 return 0;
1426
1427         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1428         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1429                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1430                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1431                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1432                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1433                                                 I40E_TXD_QW1_CMD_SHIFT);
1434                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1435                 txq->tx_tail = 0;
1436         }
1437
1438         /* Fill hardware descriptor ring with mbuf data */
1439         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1440         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1441
1442         /* Determin if RS bit needs to be set */
1443         if (txq->tx_tail > txq->tx_next_rs) {
1444                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1445                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1446                                                 I40E_TXD_QW1_CMD_SHIFT);
1447                 txq->tx_next_rs =
1448                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1449                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1450                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1451         }
1452
1453         if (txq->tx_tail >= txq->nb_tx_desc)
1454                 txq->tx_tail = 0;
1455
1456         /* Update the tx tail register */
1457         rte_wmb();
1458         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1459
1460         return nb_pkts;
1461 }
1462
1463 static uint16_t
1464 i40e_xmit_pkts_simple(void *tx_queue,
1465                       struct rte_mbuf **tx_pkts,
1466                       uint16_t nb_pkts)
1467 {
1468         uint16_t nb_tx = 0;
1469
1470         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1471                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1472                                                 tx_pkts, nb_pkts);
1473
1474         while (nb_pkts) {
1475                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1476                                                 I40E_TX_MAX_BURST);
1477
1478                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1479                                                 &tx_pkts[nb_tx], num);
1480                 nb_tx = (uint16_t)(nb_tx + ret);
1481                 nb_pkts = (uint16_t)(nb_pkts - ret);
1482                 if (ret < num)
1483                         break;
1484         }
1485
1486         return nb_tx;
1487 }
1488
1489 int
1490 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1491 {
1492         struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1493         struct i40e_rx_queue *rxq;
1494         int err = -1;
1495         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1496         uint16_t q_base = vsi->base_queue;
1497
1498         PMD_INIT_FUNC_TRACE();
1499
1500         if (rx_queue_id < dev->data->nb_rx_queues) {
1501                 rxq = dev->data->rx_queues[rx_queue_id];
1502
1503                 err = i40e_alloc_rx_queue_mbufs(rxq);
1504                 if (err) {
1505                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1506                         return err;
1507                 }
1508
1509                 rte_wmb();
1510
1511                 /* Init the RX tail regieter. */
1512                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1513
1514                 err = i40e_switch_rx_queue(hw, rx_queue_id + q_base, TRUE);
1515
1516                 if (err) {
1517                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1518                                     rx_queue_id);
1519
1520                         i40e_rx_queue_release_mbufs(rxq);
1521                         i40e_reset_rx_queue(rxq);
1522                 }
1523         }
1524
1525         return err;
1526 }
1527
1528 int
1529 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1530 {
1531         struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1532         struct i40e_rx_queue *rxq;
1533         int err;
1534         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1535         uint16_t q_base = vsi->base_queue;
1536
1537         if (rx_queue_id < dev->data->nb_rx_queues) {
1538                 rxq = dev->data->rx_queues[rx_queue_id];
1539
1540                 err = i40e_switch_rx_queue(hw, rx_queue_id + q_base, FALSE);
1541
1542                 if (err) {
1543                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1544                                     rx_queue_id);
1545                         return err;
1546                 }
1547                 i40e_rx_queue_release_mbufs(rxq);
1548                 i40e_reset_rx_queue(rxq);
1549         }
1550
1551         return 0;
1552 }
1553
1554 int
1555 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1556 {
1557         struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1558         int err = -1;
1559         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1560         uint16_t q_base = vsi->base_queue;
1561
1562         PMD_INIT_FUNC_TRACE();
1563
1564         if (tx_queue_id < dev->data->nb_tx_queues) {
1565                 err = i40e_switch_tx_queue(hw, tx_queue_id + q_base, TRUE);
1566                 if (err)
1567                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1568                                     tx_queue_id);
1569         }
1570
1571         return err;
1572 }
1573
1574 int
1575 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1576 {
1577         struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1578         struct i40e_tx_queue *txq;
1579         int err;
1580         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1581         uint16_t q_base = vsi->base_queue;
1582
1583         if (tx_queue_id < dev->data->nb_tx_queues) {
1584                 txq = dev->data->tx_queues[tx_queue_id];
1585
1586                 err = i40e_switch_tx_queue(hw, tx_queue_id + q_base, FALSE);
1587
1588                 if (err) {
1589                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1590                                     tx_queue_id);
1591                         return err;
1592                 }
1593
1594                 i40e_tx_queue_release_mbufs(txq);
1595                 i40e_reset_tx_queue(txq);
1596         }
1597
1598         return 0;
1599 }
1600
1601 int
1602 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1603                         uint16_t queue_idx,
1604                         uint16_t nb_desc,
1605                         unsigned int socket_id,
1606                         const struct rte_eth_rxconf *rx_conf,
1607                         struct rte_mempool *mp)
1608 {
1609         struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1610         struct i40e_rx_queue *rxq;
1611         const struct rte_memzone *rz;
1612         uint32_t ring_size;
1613         uint16_t len;
1614         int use_def_burst_func = 1;
1615
1616         if (!vsi || queue_idx >= vsi->nb_qps) {
1617                 PMD_DRV_LOG(ERR, "VSI not available or queue "
1618                             "index exceeds the maximum");
1619                 return I40E_ERR_PARAM;
1620         }
1621         if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1622                                         (nb_desc > I40E_MAX_RING_DESC) ||
1623                                         (nb_desc < I40E_MIN_RING_DESC)) {
1624                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1625                             "invalid", nb_desc);
1626                 return I40E_ERR_PARAM;
1627         }
1628
1629         /* Free memory if needed */
1630         if (dev->data->rx_queues[queue_idx]) {
1631                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1632                 dev->data->rx_queues[queue_idx] = NULL;
1633         }
1634
1635         /* Allocate the rx queue data structure */
1636         rxq = rte_zmalloc_socket("i40e rx queue",
1637                                  sizeof(struct i40e_rx_queue),
1638                                  CACHE_LINE_SIZE,
1639                                  socket_id);
1640         if (!rxq) {
1641                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1642                             "rx queue data structure");
1643                 return (-ENOMEM);
1644         }
1645         rxq->mp = mp;
1646         rxq->nb_rx_desc = nb_desc;
1647         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1648         rxq->queue_id = queue_idx;
1649         rxq->reg_idx = vsi->base_queue + queue_idx;
1650         rxq->port_id = dev->data->port_id;
1651         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1652                                                         0 : ETHER_CRC_LEN);
1653         rxq->drop_en = rx_conf->rx_drop_en;
1654         rxq->vsi = vsi;
1655         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1656
1657         /* Allocate the maximun number of RX ring hardware descriptor. */
1658         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1659         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1660         rz = i40e_ring_dma_zone_reserve(dev,
1661                                         "rx_ring",
1662                                         queue_idx,
1663                                         ring_size,
1664                                         socket_id);
1665         if (!rz) {
1666                 i40e_dev_rx_queue_release(rxq);
1667                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1668                 return (-ENOMEM);
1669         }
1670
1671         /* Zero all the descriptors in the ring. */
1672         memset(rz->addr, 0, ring_size);
1673
1674 #ifdef RTE_LIBRTE_XEN_DOM0
1675         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1676 #else
1677         rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1678 #endif
1679
1680         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1681
1682 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1683         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1684 #else
1685         len = nb_desc;
1686 #endif
1687
1688         /* Allocate the software ring. */
1689         rxq->sw_ring =
1690                 rte_zmalloc_socket("i40e rx sw ring",
1691                                    sizeof(struct i40e_rx_entry) * len,
1692                                    CACHE_LINE_SIZE,
1693                                    socket_id);
1694         if (!rxq->sw_ring) {
1695                 i40e_dev_rx_queue_release(rxq);
1696                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1697                 return (-ENOMEM);
1698         }
1699
1700         i40e_reset_rx_queue(rxq);
1701         rxq->q_set = TRUE;
1702         dev->data->rx_queues[queue_idx] = rxq;
1703
1704         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1705
1706         if (!use_def_burst_func && !dev->data->scattered_rx) {
1707 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1708                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1709                              "satisfied. Rx Burst Bulk Alloc function will be "
1710                              "used on port=%d, queue=%d.",
1711                              rxq->port_id, rxq->queue_id);
1712                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1713 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1714         } else {
1715                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1716                              "not satisfied, Scattered Rx is requested, "
1717                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1718                              "not enabled on port=%d, queue=%d.",
1719                              rxq->port_id, rxq->queue_id);
1720         }
1721
1722         return 0;
1723 }
1724
1725 void
1726 i40e_dev_rx_queue_release(void *rxq)
1727 {
1728         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1729
1730         if (!q) {
1731                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1732                 return;
1733         }
1734
1735         i40e_rx_queue_release_mbufs(q);
1736         rte_free(q->sw_ring);
1737         rte_free(q);
1738 }
1739
1740 uint32_t
1741 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1742 {
1743 #define I40E_RXQ_SCAN_INTERVAL 4
1744         volatile union i40e_rx_desc *rxdp;
1745         struct i40e_rx_queue *rxq;
1746         uint16_t desc = 0;
1747
1748         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1749                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1750                 return 0;
1751         }
1752
1753         rxq = dev->data->rx_queues[rx_queue_id];
1754         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1755         while ((desc < rxq->nb_rx_desc) &&
1756                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1757                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1758                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1759                 /**
1760                  * Check the DD bit of a rx descriptor of each 4 in a group,
1761                  * to avoid checking too frequently and downgrading performance
1762                  * too much.
1763                  */
1764                 desc += I40E_RXQ_SCAN_INTERVAL;
1765                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1766                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1767                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1768                                         desc - rxq->nb_rx_desc]);
1769         }
1770
1771         return desc;
1772 }
1773
1774 int
1775 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1776 {
1777         volatile union i40e_rx_desc *rxdp;
1778         struct i40e_rx_queue *rxq = rx_queue;
1779         uint16_t desc;
1780         int ret;
1781
1782         if (unlikely(offset >= rxq->nb_rx_desc)) {
1783                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1784                 return 0;
1785         }
1786
1787         desc = rxq->rx_tail + offset;
1788         if (desc >= rxq->nb_rx_desc)
1789                 desc -= rxq->nb_rx_desc;
1790
1791         rxdp = &(rxq->rx_ring[desc]);
1792
1793         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1794                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1795                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1796
1797         return ret;
1798 }
1799
1800 int
1801 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1802                         uint16_t queue_idx,
1803                         uint16_t nb_desc,
1804                         unsigned int socket_id,
1805                         const struct rte_eth_txconf *tx_conf)
1806 {
1807         struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1808         struct i40e_tx_queue *txq;
1809         const struct rte_memzone *tz;
1810         uint32_t ring_size;
1811         uint16_t tx_rs_thresh, tx_free_thresh;
1812
1813         if (!vsi || queue_idx >= vsi->nb_qps) {
1814                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1815                             "exceeds the maximum", queue_idx);
1816                 return I40E_ERR_PARAM;
1817         }
1818
1819         if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
1820                                         (nb_desc > I40E_MAX_RING_DESC) ||
1821                                         (nb_desc < I40E_MIN_RING_DESC)) {
1822                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1823                             "invalid", nb_desc);
1824                 return I40E_ERR_PARAM;
1825         }
1826
1827         /**
1828          * The following two parameters control the setting of the RS bit on
1829          * transmit descriptors. TX descriptors will have their RS bit set
1830          * after txq->tx_rs_thresh descriptors have been used. The TX
1831          * descriptor ring will be cleaned after txq->tx_free_thresh
1832          * descriptors are used or if the number of descriptors required to
1833          * transmit a packet is greater than the number of free TX descriptors.
1834          *
1835          * The following constraints must be satisfied:
1836          *  - tx_rs_thresh must be greater than 0.
1837          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1838          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1839          *  - tx_rs_thresh must be a divisor of the ring size.
1840          *  - tx_free_thresh must be greater than 0.
1841          *  - tx_free_thresh must be less than the size of the ring minus 3.
1842          *
1843          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1844          * race condition, hence the maximum threshold constraints. When set
1845          * to zero use default values.
1846          */
1847         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1848                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1849         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1850                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1851         if (tx_rs_thresh >= (nb_desc - 2)) {
1852                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1853                              "number of TX descriptors minus 2. "
1854                              "(tx_rs_thresh=%u port=%d queue=%d)",
1855                              (unsigned int)tx_rs_thresh,
1856                              (int)dev->data->port_id,
1857                              (int)queue_idx);
1858                 return I40E_ERR_PARAM;
1859         }
1860         if (tx_free_thresh >= (nb_desc - 3)) {
1861                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1862                              "tx_free_thresh must be less than the "
1863                              "number of TX descriptors minus 3. "
1864                              "(tx_free_thresh=%u port=%d queue=%d)",
1865                              (unsigned int)tx_free_thresh,
1866                              (int)dev->data->port_id,
1867                              (int)queue_idx);
1868                 return I40E_ERR_PARAM;
1869         }
1870         if (tx_rs_thresh > tx_free_thresh) {
1871                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1872                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1873                              " tx_rs_thresh=%u port=%d queue=%d)",
1874                              (unsigned int)tx_free_thresh,
1875                              (unsigned int)tx_rs_thresh,
1876                              (int)dev->data->port_id,
1877                              (int)queue_idx);
1878                 return I40E_ERR_PARAM;
1879         }
1880         if ((nb_desc % tx_rs_thresh) != 0) {
1881                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1882                              "number of TX descriptors. (tx_rs_thresh=%u"
1883                              " port=%d queue=%d)",
1884                              (unsigned int)tx_rs_thresh,
1885                              (int)dev->data->port_id,
1886                              (int)queue_idx);
1887                 return I40E_ERR_PARAM;
1888         }
1889         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1890                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1891                              "tx_rs_thresh is greater than 1. "
1892                              "(tx_rs_thresh=%u port=%d queue=%d)",
1893                              (unsigned int)tx_rs_thresh,
1894                              (int)dev->data->port_id,
1895                              (int)queue_idx);
1896                 return I40E_ERR_PARAM;
1897         }
1898
1899         /* Free memory if needed. */
1900         if (dev->data->tx_queues[queue_idx]) {
1901                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
1902                 dev->data->tx_queues[queue_idx] = NULL;
1903         }
1904
1905         /* Allocate the TX queue data structure. */
1906         txq = rte_zmalloc_socket("i40e tx queue",
1907                                   sizeof(struct i40e_tx_queue),
1908                                   CACHE_LINE_SIZE,
1909                                   socket_id);
1910         if (!txq) {
1911                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1912                             "tx queue structure");
1913                 return (-ENOMEM);
1914         }
1915
1916         /* Allocate TX hardware ring descriptors. */
1917         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
1918         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1919         tz = i40e_ring_dma_zone_reserve(dev,
1920                                         "tx_ring",
1921                                         queue_idx,
1922                                         ring_size,
1923                                         socket_id);
1924         if (!tz) {
1925                 i40e_dev_tx_queue_release(txq);
1926                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
1927                 return (-ENOMEM);
1928         }
1929
1930         txq->nb_tx_desc = nb_desc;
1931         txq->tx_rs_thresh = tx_rs_thresh;
1932         txq->tx_free_thresh = tx_free_thresh;
1933         txq->pthresh = tx_conf->tx_thresh.pthresh;
1934         txq->hthresh = tx_conf->tx_thresh.hthresh;
1935         txq->wthresh = tx_conf->tx_thresh.wthresh;
1936         txq->queue_id = queue_idx;
1937         txq->reg_idx = vsi->base_queue + queue_idx;
1938         txq->port_id = dev->data->port_id;
1939         txq->txq_flags = tx_conf->txq_flags;
1940         txq->vsi = vsi;
1941         txq->tx_deferred_start = tx_conf->tx_deferred_start;
1942
1943 #ifdef RTE_LIBRTE_XEN_DOM0
1944         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1945 #else
1946         txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
1947 #endif
1948         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
1949
1950         /* Allocate software ring */
1951         txq->sw_ring =
1952                 rte_zmalloc_socket("i40e tx sw ring",
1953                                    sizeof(struct i40e_tx_entry) * nb_desc,
1954                                    CACHE_LINE_SIZE,
1955                                    socket_id);
1956         if (!txq->sw_ring) {
1957                 i40e_dev_tx_queue_release(txq);
1958                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
1959                 return (-ENOMEM);
1960         }
1961
1962         i40e_reset_tx_queue(txq);
1963         txq->q_set = TRUE;
1964         dev->data->tx_queues[queue_idx] = txq;
1965
1966         /* Use a simple TX queue without offloads or multi segs if possible */
1967         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
1968                                 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
1969                 PMD_INIT_LOG(INFO, "Using simple tx path");
1970                 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
1971         } else {
1972                 PMD_INIT_LOG(INFO, "Using full-featured tx path");
1973                 dev->tx_pkt_burst = i40e_xmit_pkts;
1974         }
1975
1976         return 0;
1977 }
1978
1979 void
1980 i40e_dev_tx_queue_release(void *txq)
1981 {
1982         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
1983
1984         if (!q) {
1985                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1986                 return;
1987         }
1988
1989         i40e_tx_queue_release_mbufs(q);
1990         rte_free(q->sw_ring);
1991         rte_free(q);
1992 }
1993
1994 static const struct rte_memzone *
1995 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
1996                            const char *ring_name,
1997                            uint16_t queue_id,
1998                            uint32_t ring_size,
1999                            int socket_id)
2000 {
2001         char z_name[RTE_MEMZONE_NAMESIZE];
2002         const struct rte_memzone *mz;
2003
2004         snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2005                         dev->driver->pci_drv.name, ring_name,
2006                                 dev->data->port_id, queue_id);
2007         mz = rte_memzone_lookup(z_name);
2008         if (mz)
2009                 return mz;
2010
2011 #ifdef RTE_LIBRTE_XEN_DOM0
2012         return rte_memzone_reserve_bounded(z_name, ring_size,
2013                 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2014 #else
2015         return rte_memzone_reserve_aligned(z_name, ring_size,
2016                                 socket_id, 0, I40E_ALIGN);
2017 #endif
2018 }
2019
2020 void
2021 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2022 {
2023         uint16_t i;
2024
2025         if (!rxq || !rxq->sw_ring) {
2026                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2027                 return;
2028         }
2029
2030         for (i = 0; i < rxq->nb_rx_desc; i++) {
2031                 if (rxq->sw_ring[i].mbuf) {
2032                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2033                         rxq->sw_ring[i].mbuf = NULL;
2034                 }
2035         }
2036 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2037         if (rxq->rx_nb_avail == 0)
2038                 return;
2039         for (i = 0; i < rxq->rx_nb_avail; i++) {
2040                 struct rte_mbuf *mbuf;
2041
2042                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2043                 rte_pktmbuf_free_seg(mbuf);
2044         }
2045         rxq->rx_nb_avail = 0;
2046 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2047 }
2048
2049 void
2050 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2051 {
2052         unsigned i;
2053         uint16_t len;
2054
2055 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2056         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2057                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2058         else
2059 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2060                 len = rxq->nb_rx_desc;
2061
2062         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2063                 ((volatile char *)rxq->rx_ring)[i] = 0;
2064
2065 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2066         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2067         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2068                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2069
2070         rxq->rx_nb_avail = 0;
2071         rxq->rx_next_avail = 0;
2072         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2073 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2074         rxq->rx_tail = 0;
2075         rxq->nb_rx_hold = 0;
2076         rxq->pkt_first_seg = NULL;
2077         rxq->pkt_last_seg = NULL;
2078 }
2079
2080 void
2081 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2082 {
2083         uint16_t i;
2084
2085         if (!txq || !txq->sw_ring) {
2086                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2087                 return;
2088         }
2089
2090         for (i = 0; i < txq->nb_tx_desc; i++) {
2091                 if (txq->sw_ring[i].mbuf) {
2092                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2093                         txq->sw_ring[i].mbuf = NULL;
2094                 }
2095         }
2096 }
2097
2098 void
2099 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2100 {
2101         struct i40e_tx_entry *txe;
2102         uint16_t i, prev, size;
2103
2104         if (!txq) {
2105                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2106                 return;
2107         }
2108
2109         txe = txq->sw_ring;
2110         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2111         for (i = 0; i < size; i++)
2112                 ((volatile char *)txq->tx_ring)[i] = 0;
2113
2114         prev = (uint16_t)(txq->nb_tx_desc - 1);
2115         for (i = 0; i < txq->nb_tx_desc; i++) {
2116                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2117
2118                 txd->cmd_type_offset_bsz =
2119                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2120                 txe[i].mbuf =  NULL;
2121                 txe[i].last_id = i;
2122                 txe[prev].next_id = i;
2123                 prev = i;
2124         }
2125
2126         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2127         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2128
2129         txq->tx_tail = 0;
2130         txq->nb_tx_used = 0;
2131
2132         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2133         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2134 }
2135
2136 /* Init the TX queue in hardware */
2137 int
2138 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2139 {
2140         enum i40e_status_code err = I40E_SUCCESS;
2141         struct i40e_vsi *vsi = txq->vsi;
2142         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2143         uint16_t pf_q = txq->reg_idx;
2144         struct i40e_hmc_obj_txq tx_ctx;
2145         uint32_t qtx_ctl;
2146
2147         /* clear the context structure first */
2148         memset(&tx_ctx, 0, sizeof(tx_ctx));
2149         tx_ctx.new_context = 1;
2150         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2151         tx_ctx.qlen = txq->nb_tx_desc;
2152         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2153
2154         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2155         if (err != I40E_SUCCESS) {
2156                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2157                 return err;
2158         }
2159
2160         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2161         if (err != I40E_SUCCESS) {
2162                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2163                 return err;
2164         }
2165
2166         /* Now associate this queue with this PCI function */
2167         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2168         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2169                                         I40E_QTX_CTL_PF_INDX_MASK);
2170         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2171         I40E_WRITE_FLUSH(hw);
2172
2173         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2174
2175         return err;
2176 }
2177
2178 int
2179 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2180 {
2181         struct i40e_rx_entry *rxe = rxq->sw_ring;
2182         uint64_t dma_addr;
2183         uint16_t i;
2184
2185         for (i = 0; i < rxq->nb_rx_desc; i++) {
2186                 volatile union i40e_rx_desc *rxd;
2187                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2188
2189                 if (unlikely(!mbuf)) {
2190                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2191                         return -ENOMEM;
2192                 }
2193
2194                 rte_mbuf_refcnt_set(mbuf, 1);
2195                 mbuf->next = NULL;
2196                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2197                 mbuf->nb_segs = 1;
2198                 mbuf->port = rxq->port_id;
2199
2200                 dma_addr =
2201                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2202
2203                 rxd = &rxq->rx_ring[i];
2204                 rxd->read.pkt_addr = dma_addr;
2205                 rxd->read.hdr_addr = dma_addr;
2206 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2207                 rxd->read.rsvd1 = 0;
2208                 rxd->read.rsvd2 = 0;
2209 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2210
2211                 rxe[i].mbuf = mbuf;
2212         }
2213
2214         return 0;
2215 }
2216
2217 /*
2218  * Calculate the buffer length, and check the jumbo frame
2219  * and maximum packet length.
2220  */
2221 static int
2222 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2223 {
2224         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2225         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2226         struct rte_eth_dev_data *data = pf->dev_data;
2227         struct rte_pktmbuf_pool_private *mbp_priv =
2228                         rte_mempool_get_priv(rxq->mp);
2229         uint16_t buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2230                                                 RTE_PKTMBUF_HEADROOM);
2231         uint16_t len;
2232
2233         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2234                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2235         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2236                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2237                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2238                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2239                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2240                 rxq->hs_mode = i40e_header_split_enabled;
2241                 break;
2242         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2243         default:
2244                 rxq->rx_hdr_len = 0;
2245                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2246                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2247                 rxq->hs_mode = i40e_header_split_none;
2248                 break;
2249         }
2250
2251         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2252         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2253         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2254                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2255                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2256                         PMD_DRV_LOG(ERR, "maximum packet length must "
2257                                     "be larger than %u and smaller than %u,"
2258                                     "as jumbo frame is enabled",
2259                                     (uint32_t)ETHER_MAX_LEN,
2260                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2261                         return I40E_ERR_CONFIG;
2262                 }
2263         } else {
2264                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2265                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2266                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2267                                     "larger than %u and smaller than %u, "
2268                                     "as jumbo frame is disabled",
2269                                     (uint32_t)ETHER_MIN_LEN,
2270                                     (uint32_t)ETHER_MAX_LEN);
2271                         return I40E_ERR_CONFIG;
2272                 }
2273         }
2274
2275         return 0;
2276 }
2277
2278 /* Init the RX queue in hardware */
2279 int
2280 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2281 {
2282         int err = I40E_SUCCESS;
2283         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2284         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2285         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2286         uint16_t pf_q = rxq->reg_idx;
2287         uint16_t buf_size;
2288         struct i40e_hmc_obj_rxq rx_ctx;
2289         struct rte_pktmbuf_pool_private *mbp_priv;
2290
2291         err = i40e_rx_queue_config(rxq);
2292         if (err < 0) {
2293                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2294                 return err;
2295         }
2296
2297         /* Clear the context structure first */
2298         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2299         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2300         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2301
2302         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2303         rx_ctx.qlen = rxq->nb_rx_desc;
2304 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2305         rx_ctx.dsize = 1;
2306 #endif
2307         rx_ctx.dtype = rxq->hs_mode;
2308         if (rxq->hs_mode)
2309                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2310         else
2311                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2312         rx_ctx.rxmax = rxq->max_pkt_len;
2313         rx_ctx.tphrdesc_ena = 1;
2314         rx_ctx.tphwdesc_ena = 1;
2315         rx_ctx.tphdata_ena = 1;
2316         rx_ctx.tphhead_ena = 1;
2317         rx_ctx.lrxqthresh = 2;
2318         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2319         rx_ctx.l2tsel = 1;
2320         rx_ctx.showiv = 1;
2321         rx_ctx.prefena = 1;
2322
2323         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2324         if (err != I40E_SUCCESS) {
2325                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2326                 return err;
2327         }
2328         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2329         if (err != I40E_SUCCESS) {
2330                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2331                 return err;
2332         }
2333
2334         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2335
2336         mbp_priv = rte_mempool_get_priv(rxq->mp);
2337         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2338                                         RTE_PKTMBUF_HEADROOM);
2339
2340         /* Check if scattered RX needs to be used. */
2341         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2342                 dev_data->scattered_rx = 1;
2343                 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2344         }
2345
2346         /* Init the RX tail regieter. */
2347         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2348
2349         return 0;
2350 }
2351
2352 void
2353 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2354 {
2355         uint16_t i;
2356
2357         PMD_INIT_FUNC_TRACE();
2358
2359         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2360                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2361                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2362         }
2363
2364         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2365                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2366                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2367         }
2368 }