4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
54 #include "i40e_logs.h"
55 #include "i40e/i40e_prototype.h"
56 #include "i40e/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
60 #define I40E_MIN_RING_DESC 64
61 #define I40E_MAX_RING_DESC 4096
62 #define I40E_ALIGN 128
63 #define DEFAULT_TX_RS_THRESH 32
64 #define DEFAULT_TX_FREE_THRESH 32
65 #define I40E_MAX_PKT_TYPE 256
67 #define I40E_VLAN_TAG_SIZE 4
68 #define I40E_TX_MAX_BURST 32
70 #define I40E_DMA_MEM_ALIGN 4096
72 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
73 ETH_TXQ_FLAGS_NOOFFLOADS)
75 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
77 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
80 PKT_TX_OUTER_IP_CKSUM)
82 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
83 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
85 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
86 ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
88 static const struct rte_memzone *
89 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
90 const char *ring_name,
94 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
95 struct rte_mbuf **tx_pkts,
98 /* Translate the rx descriptor status to pkt flags */
99 static inline uint64_t
100 i40e_rxd_status_to_pkt_flags(uint64_t qword)
104 /* Check if VLAN packet */
105 flags = qword & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
108 /* Check if RSS_HASH */
109 flags |= (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
110 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
111 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
113 /* Check if FDIR Match */
114 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
120 static inline uint64_t
121 i40e_rxd_error_to_pkt_flags(uint64_t qword)
124 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
126 #define I40E_RX_ERR_BITS 0x3f
127 if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
129 /* If RXE bit set, all other status bits are meaningless */
130 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
131 flags |= PKT_RX_MAC_ERR;
135 /* If RECIPE bit set, all other status indications should be ignored */
136 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
137 flags |= PKT_RX_RECIP_ERR;
140 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
141 flags |= PKT_RX_HBUF_OVERFLOW;
142 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
143 flags |= PKT_RX_IP_CKSUM_BAD;
144 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
145 flags |= PKT_RX_L4_CKSUM_BAD;
146 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
147 flags |= PKT_RX_EIP_CKSUM_BAD;
148 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
149 flags |= PKT_RX_OVERSIZE;
154 /* Translate pkt types to pkt flags */
155 static inline uint64_t
156 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
158 uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
159 I40E_RXD_QW1_PTYPE_SHIFT);
160 static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
183 PKT_RX_IPV4_HDR, /* PTYPE 22 */
184 PKT_RX_IPV4_HDR, /* PTYPE 23 */
185 PKT_RX_IPV4_HDR, /* PTYPE 24 */
187 PKT_RX_IPV4_HDR, /* PTYPE 26 */
188 PKT_RX_IPV4_HDR, /* PTYPE 27 */
189 PKT_RX_IPV4_HDR, /* PTYPE 28 */
190 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
191 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
192 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
194 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
195 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
196 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
197 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
198 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
199 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
201 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
202 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
203 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
204 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
205 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
206 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
207 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
209 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
210 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
211 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
212 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
213 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
214 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
216 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
217 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
218 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
219 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
220 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 59 */
221 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 60 */
222 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 61 */
224 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 63 */
225 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 64 */
226 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 65 */
227 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 66 */
228 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 67 */
229 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 68 */
231 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 70 */
232 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 71 */
233 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 72 */
234 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 73 */
235 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 74 */
236 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 75 */
237 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 76 */
239 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 78 */
240 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 79 */
241 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 80 */
242 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 81 */
243 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 82 */
244 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 83 */
246 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 85 */
247 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 86 */
248 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
249 PKT_RX_IPV6_HDR, /* PTYPE 88 */
250 PKT_RX_IPV6_HDR, /* PTYPE 89 */
251 PKT_RX_IPV6_HDR, /* PTYPE 90 */
253 PKT_RX_IPV6_HDR, /* PTYPE 92 */
254 PKT_RX_IPV6_HDR, /* PTYPE 93 */
255 PKT_RX_IPV6_HDR, /* PTYPE 94 */
256 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
257 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
258 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
260 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
261 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
262 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
263 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
264 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
265 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
267 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
268 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
269 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
270 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
271 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
272 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
273 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
275 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
276 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
277 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
278 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
279 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
280 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
282 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
283 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
284 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
285 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
286 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 125 */
287 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 126 */
288 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 127 */
290 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 129 */
291 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 130 */
292 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 131 */
293 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 132 */
294 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 133 */
295 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 134 */
297 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 136 */
298 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 137 */
299 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 138 */
300 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 139 */
301 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 140 */
302 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 141 */
303 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 142 */
305 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 144 */
306 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 145 */
307 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 146 */
308 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 147 */
309 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 148 */
310 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 149 */
312 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 151 */
313 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 152 */
314 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
419 return ip_ptype_map[ptype];
422 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
423 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
424 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
425 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
426 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
428 static inline uint64_t
429 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
432 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
433 uint16_t flexbh, flexbl;
435 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
436 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
437 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
438 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
439 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
440 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
443 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
445 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
446 flags |= PKT_RX_FDIR_ID;
447 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
449 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
450 flags |= PKT_RX_FDIR_FLX;
452 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
454 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
455 flags |= PKT_RX_FDIR_FLX;
459 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
460 flags |= PKT_RX_FDIR_ID;
465 i40e_txd_enable_checksum(uint64_t ol_flags,
470 uint8_t outer_l2_len,
471 uint16_t outer_l3_len,
472 uint32_t *cd_tunneling)
475 PMD_DRV_LOG(DEBUG, "L2 length set to 0");
480 PMD_DRV_LOG(DEBUG, "L3 length set to 0");
484 /* UDP tunneling packet TX checksum offload */
485 if (unlikely(ol_flags & PKT_TX_OUTER_IP_CKSUM)) {
487 *td_offset |= (outer_l2_len >> 1)
488 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
490 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
491 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
492 else if (ol_flags & PKT_TX_OUTER_IPV4)
493 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
494 else if (ol_flags & PKT_TX_OUTER_IPV6)
495 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
497 /* Now set the ctx descriptor fields */
498 *cd_tunneling |= (outer_l3_len >> 2) <<
499 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
501 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
504 *td_offset |= (l2_len >> 1)
505 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
507 /* Enable L3 checksum offloads */
508 if (ol_flags & PKT_TX_IP_CKSUM) {
509 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
510 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
511 } else if (ol_flags & PKT_TX_IPV4) {
512 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
513 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
514 } else if (ol_flags & PKT_TX_IPV6) {
515 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
516 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
519 /* Enable L4 checksum offloads */
520 switch (ol_flags & PKT_TX_L4_MASK) {
521 case PKT_TX_TCP_CKSUM:
522 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
523 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
524 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
526 case PKT_TX_SCTP_CKSUM:
527 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
528 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
529 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
531 case PKT_TX_UDP_CKSUM:
532 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
533 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
534 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
541 static inline struct rte_mbuf *
542 rte_rxmbuf_alloc(struct rte_mempool *mp)
546 m = __rte_mbuf_raw_alloc(mp);
547 __rte_mbuf_sanity_check_raw(m, 0);
552 /* Construct the tx flags */
553 static inline uint64_t
554 i40e_build_ctob(uint32_t td_cmd,
559 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
560 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
561 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
562 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
563 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
567 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
569 struct i40e_tx_entry *sw_ring = txq->sw_ring;
570 volatile struct i40e_tx_desc *txd = txq->tx_ring;
571 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
572 uint16_t nb_tx_desc = txq->nb_tx_desc;
573 uint16_t desc_to_clean_to;
574 uint16_t nb_tx_to_clean;
576 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
577 if (desc_to_clean_to >= nb_tx_desc)
578 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
580 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
581 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
582 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) {
583 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
584 "(port=%d queue=%d)", desc_to_clean_to,
585 txq->port_id, txq->queue_id);
589 if (last_desc_cleaned > desc_to_clean_to)
590 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
593 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
596 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
598 txq->last_desc_cleaned = desc_to_clean_to;
599 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
605 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
606 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
608 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
613 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
614 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
615 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
616 "rxq->rx_free_thresh=%d, "
617 "RTE_PMD_I40E_RX_MAX_BURST=%d",
618 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
620 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
621 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
622 "rxq->rx_free_thresh=%d, "
623 "rxq->nb_rx_desc=%d",
624 rxq->rx_free_thresh, rxq->nb_rx_desc);
626 } else if (!(rxq->nb_rx_desc % rxq->rx_free_thresh) == 0) {
627 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
628 "rxq->nb_rx_desc=%d, "
629 "rxq->rx_free_thresh=%d",
630 rxq->nb_rx_desc, rxq->rx_free_thresh);
632 } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
633 RTE_PMD_I40E_RX_MAX_BURST))) {
634 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
635 "rxq->nb_rx_desc=%d, "
636 "I40E_MAX_RING_DESC=%d, "
637 "RTE_PMD_I40E_RX_MAX_BURST=%d",
638 rxq->nb_rx_desc, I40E_MAX_RING_DESC,
639 RTE_PMD_I40E_RX_MAX_BURST);
649 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
650 #define I40E_LOOK_AHEAD 8
651 #if (I40E_LOOK_AHEAD != 8)
652 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
655 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
657 volatile union i40e_rx_desc *rxdp;
658 struct i40e_rx_entry *rxep;
663 int32_t s[I40E_LOOK_AHEAD], nb_dd;
664 int32_t i, j, nb_rx = 0;
667 rxdp = &rxq->rx_ring[rxq->rx_tail];
668 rxep = &rxq->sw_ring[rxq->rx_tail];
670 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
671 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
672 I40E_RXD_QW1_STATUS_SHIFT;
674 /* Make sure there is at least 1 packet to receive */
675 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
679 * Scan LOOK_AHEAD descriptors at a time to determine which
680 * descriptors reference packets that are ready to be received.
682 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
683 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
684 /* Read desc statuses backwards to avoid race condition */
685 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
686 qword1 = rte_le_to_cpu_64(\
687 rxdp[j].wb.qword1.status_error_len);
688 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
689 I40E_RXD_QW1_STATUS_SHIFT;
692 /* Compute how many status bits were set */
693 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
694 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
698 /* Translate descriptor info to mbuf parameters */
699 for (j = 0; j < nb_dd; j++) {
701 qword1 = rte_le_to_cpu_64(\
702 rxdp[j].wb.qword1.status_error_len);
703 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
704 I40E_RXD_QW1_STATUS_SHIFT;
705 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
706 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
707 mb->data_len = pkt_len;
708 mb->pkt_len = pkt_len;
709 mb->vlan_tci = rx_status &
710 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
712 rxdp[j].wb.qword0.lo_dword.l2tag1) : 0;
713 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
714 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
715 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
717 mb->packet_type = (uint16_t)((qword1 &
718 I40E_RXD_QW1_PTYPE_MASK) >>
719 I40E_RXD_QW1_PTYPE_SHIFT);
720 if (pkt_flags & PKT_RX_RSS_HASH)
721 mb->hash.rss = rte_le_to_cpu_32(\
722 rxdp[j].wb.qword0.hi_dword.rss);
723 if (pkt_flags & PKT_RX_FDIR)
724 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
726 mb->ol_flags = pkt_flags;
729 for (j = 0; j < I40E_LOOK_AHEAD; j++)
730 rxq->rx_stage[i + j] = rxep[j].mbuf;
732 if (nb_dd != I40E_LOOK_AHEAD)
736 /* Clear software ring entries */
737 for (i = 0; i < nb_rx; i++)
738 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
743 static inline uint16_t
744 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
745 struct rte_mbuf **rx_pkts,
749 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
751 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
753 for (i = 0; i < nb_pkts; i++)
754 rx_pkts[i] = stage[i];
756 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
757 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
763 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
765 volatile union i40e_rx_desc *rxdp;
766 struct i40e_rx_entry *rxep;
768 uint16_t alloc_idx, i;
772 /* Allocate buffers in bulk */
773 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
774 (rxq->rx_free_thresh - 1));
775 rxep = &(rxq->sw_ring[alloc_idx]);
776 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
777 rxq->rx_free_thresh);
778 if (unlikely(diag != 0)) {
779 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
783 rxdp = &rxq->rx_ring[alloc_idx];
784 for (i = 0; i < rxq->rx_free_thresh; i++) {
786 rte_mbuf_refcnt_set(mb, 1);
788 mb->data_off = RTE_PKTMBUF_HEADROOM;
790 mb->port = rxq->port_id;
791 dma_addr = rte_cpu_to_le_64(\
792 RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
793 rxdp[i].read.hdr_addr = dma_addr;
794 rxdp[i].read.pkt_addr = dma_addr;
797 /* Update rx tail regsiter */
799 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
801 rxq->rx_free_trigger =
802 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
803 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
804 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
809 static inline uint16_t
810 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
812 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
818 if (rxq->rx_nb_avail)
819 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
821 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
822 rxq->rx_next_avail = 0;
823 rxq->rx_nb_avail = nb_rx;
824 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
826 if (rxq->rx_tail > rxq->rx_free_trigger) {
827 if (i40e_rx_alloc_bufs(rxq) != 0) {
830 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
831 "port_id=%u, queue_id=%u",
832 rxq->port_id, rxq->queue_id);
833 rxq->rx_nb_avail = 0;
834 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
835 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
836 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
842 if (rxq->rx_tail >= rxq->nb_rx_desc)
845 if (rxq->rx_nb_avail)
846 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
852 i40e_recv_pkts_bulk_alloc(void *rx_queue,
853 struct rte_mbuf **rx_pkts,
856 uint16_t nb_rx = 0, n, count;
858 if (unlikely(nb_pkts == 0))
861 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
862 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
865 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
866 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
867 nb_rx = (uint16_t)(nb_rx + count);
868 nb_pkts = (uint16_t)(nb_pkts - count);
875 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
878 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
880 struct i40e_rx_queue *rxq;
881 volatile union i40e_rx_desc *rx_ring;
882 volatile union i40e_rx_desc *rxdp;
883 union i40e_rx_desc rxd;
884 struct i40e_rx_entry *sw_ring;
885 struct i40e_rx_entry *rxe;
886 struct rte_mbuf *rxm;
887 struct rte_mbuf *nmb;
891 uint16_t rx_packet_len;
892 uint16_t rx_id, nb_hold;
899 rx_id = rxq->rx_tail;
900 rx_ring = rxq->rx_ring;
901 sw_ring = rxq->sw_ring;
903 while (nb_rx < nb_pkts) {
904 rxdp = &rx_ring[rx_id];
905 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
906 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
907 >> I40E_RXD_QW1_STATUS_SHIFT;
908 /* Check the DD bit first */
909 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
912 nmb = rte_rxmbuf_alloc(rxq->mp);
918 rxe = &sw_ring[rx_id];
920 if (unlikely(rx_id == rxq->nb_rx_desc))
923 /* Prefetch next mbuf */
924 rte_prefetch0(sw_ring[rx_id].mbuf);
927 * When next RX descriptor is on a cache line boundary,
928 * prefetch the next 4 RX descriptors and next 8 pointers
931 if ((rx_id & 0x3) == 0) {
932 rte_prefetch0(&rx_ring[rx_id]);
933 rte_prefetch0(&sw_ring[rx_id]);
938 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
939 rxdp->read.hdr_addr = dma_addr;
940 rxdp->read.pkt_addr = dma_addr;
942 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
943 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
945 rxm->data_off = RTE_PKTMBUF_HEADROOM;
946 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
949 rxm->pkt_len = rx_packet_len;
950 rxm->data_len = rx_packet_len;
951 rxm->port = rxq->port_id;
953 rxm->vlan_tci = rx_status &
954 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
955 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
956 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
957 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
958 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
959 rxm->packet_type = (uint16_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >>
960 I40E_RXD_QW1_PTYPE_SHIFT);
961 if (pkt_flags & PKT_RX_RSS_HASH)
963 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
964 if (pkt_flags & PKT_RX_FDIR)
965 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
967 rxm->ol_flags = pkt_flags;
969 rx_pkts[nb_rx++] = rxm;
971 rxq->rx_tail = rx_id;
974 * If the number of free RX descriptors is greater than the RX free
975 * threshold of the queue, advance the receive tail register of queue.
976 * Update that register with the value of the last processed RX
977 * descriptor minus 1.
979 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
980 if (nb_hold > rxq->rx_free_thresh) {
981 rx_id = (uint16_t) ((rx_id == 0) ?
982 (rxq->nb_rx_desc - 1) : (rx_id - 1));
983 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
986 rxq->nb_rx_hold = nb_hold;
992 i40e_recv_scattered_pkts(void *rx_queue,
993 struct rte_mbuf **rx_pkts,
996 struct i40e_rx_queue *rxq = rx_queue;
997 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
998 volatile union i40e_rx_desc *rxdp;
999 union i40e_rx_desc rxd;
1000 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1001 struct i40e_rx_entry *rxe;
1002 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1003 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1004 struct rte_mbuf *nmb, *rxm;
1005 uint16_t rx_id = rxq->rx_tail;
1006 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1012 while (nb_rx < nb_pkts) {
1013 rxdp = &rx_ring[rx_id];
1014 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1015 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1016 I40E_RXD_QW1_STATUS_SHIFT;
1017 /* Check the DD bit */
1018 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1021 nmb = rte_rxmbuf_alloc(rxq->mp);
1026 rxe = &sw_ring[rx_id];
1028 if (rx_id == rxq->nb_rx_desc)
1031 /* Prefetch next mbuf */
1032 rte_prefetch0(sw_ring[rx_id].mbuf);
1035 * When next RX descriptor is on a cache line boundary,
1036 * prefetch the next 4 RX descriptors and next 8 pointers
1039 if ((rx_id & 0x3) == 0) {
1040 rte_prefetch0(&rx_ring[rx_id]);
1041 rte_prefetch0(&sw_ring[rx_id]);
1047 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1049 /* Set data buffer address and data length of the mbuf */
1050 rxdp->read.hdr_addr = dma_addr;
1051 rxdp->read.pkt_addr = dma_addr;
1052 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1053 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1054 rxm->data_len = rx_packet_len;
1055 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1058 * If this is the first buffer of the received packet, set the
1059 * pointer to the first mbuf of the packet and initialize its
1060 * context. Otherwise, update the total length and the number
1061 * of segments of the current scattered packet, and update the
1062 * pointer to the last mbuf of the current packet.
1066 first_seg->nb_segs = 1;
1067 first_seg->pkt_len = rx_packet_len;
1069 first_seg->pkt_len =
1070 (uint16_t)(first_seg->pkt_len +
1072 first_seg->nb_segs++;
1073 last_seg->next = rxm;
1077 * If this is not the last buffer of the received packet,
1078 * update the pointer to the last mbuf of the current scattered
1079 * packet and continue to parse the RX ring.
1081 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1087 * This is the last buffer of the received packet. If the CRC
1088 * is not stripped by the hardware:
1089 * - Subtract the CRC length from the total packet length.
1090 * - If the last buffer only contains the whole CRC or a part
1091 * of it, free the mbuf associated to the last buffer. If part
1092 * of the CRC is also contained in the previous mbuf, subtract
1093 * the length of that CRC part from the data length of the
1097 if (unlikely(rxq->crc_len > 0)) {
1098 first_seg->pkt_len -= ETHER_CRC_LEN;
1099 if (rx_packet_len <= ETHER_CRC_LEN) {
1100 rte_pktmbuf_free_seg(rxm);
1101 first_seg->nb_segs--;
1102 last_seg->data_len =
1103 (uint16_t)(last_seg->data_len -
1104 (ETHER_CRC_LEN - rx_packet_len));
1105 last_seg->next = NULL;
1107 rxm->data_len = (uint16_t)(rx_packet_len -
1111 first_seg->port = rxq->port_id;
1112 first_seg->vlan_tci = (rx_status &
1113 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1114 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
1115 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1116 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1117 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1118 first_seg->packet_type = (uint16_t)((qword1 &
1119 I40E_RXD_QW1_PTYPE_MASK) >>
1120 I40E_RXD_QW1_PTYPE_SHIFT);
1121 if (pkt_flags & PKT_RX_RSS_HASH)
1123 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1124 if (pkt_flags & PKT_RX_FDIR)
1125 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1127 first_seg->ol_flags = pkt_flags;
1129 /* Prefetch data of first segment, if configured to do so. */
1130 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1131 first_seg->data_off));
1132 rx_pkts[nb_rx++] = first_seg;
1136 /* Record index of the next RX descriptor to probe. */
1137 rxq->rx_tail = rx_id;
1138 rxq->pkt_first_seg = first_seg;
1139 rxq->pkt_last_seg = last_seg;
1142 * If the number of free RX descriptors is greater than the RX free
1143 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1144 * register. Update the RDT with the value of the last processed RX
1145 * descriptor minus 1, to guarantee that the RDT register is never
1146 * equal to the RDH register, which creates a "full" ring situtation
1147 * from the hardware point of view.
1149 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1150 if (nb_hold > rxq->rx_free_thresh) {
1151 rx_id = (uint16_t)(rx_id == 0 ?
1152 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1153 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1156 rxq->nb_rx_hold = nb_hold;
1161 /* Check if the context descriptor is needed for TX offloading */
1162 static inline uint16_t
1163 i40e_calc_context_desc(uint64_t flags)
1165 uint64_t mask = 0ULL;
1167 mask |= PKT_TX_OUTER_IP_CKSUM;
1169 #ifdef RTE_LIBRTE_IEEE1588
1170 mask |= PKT_TX_IEEE1588_TMST;
1179 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1181 struct i40e_tx_queue *txq;
1182 struct i40e_tx_entry *sw_ring;
1183 struct i40e_tx_entry *txe, *txn;
1184 volatile struct i40e_tx_desc *txd;
1185 volatile struct i40e_tx_desc *txr;
1186 struct rte_mbuf *tx_pkt;
1187 struct rte_mbuf *m_seg;
1188 uint32_t cd_tunneling_params;
1198 uint8_t outer_l2_len;
1199 uint16_t outer_l3_len;
1204 uint64_t buf_dma_addr;
1207 sw_ring = txq->sw_ring;
1209 tx_id = txq->tx_tail;
1210 txe = &sw_ring[tx_id];
1212 /* Check if the descriptor ring needs to be cleaned. */
1213 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh)
1214 i40e_xmit_cleanup(txq);
1216 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1222 tx_pkt = *tx_pkts++;
1223 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1225 ol_flags = tx_pkt->ol_flags;
1226 l2_len = tx_pkt->l2_len;
1227 l3_len = tx_pkt->l3_len;
1228 outer_l2_len = tx_pkt->outer_l2_len;
1229 outer_l3_len = tx_pkt->outer_l3_len;
1231 /* Calculate the number of context descriptors needed. */
1232 nb_ctx = i40e_calc_context_desc(ol_flags);
1235 * The number of descriptors that must be allocated for
1236 * a packet equals to the number of the segments of that
1237 * packet plus 1 context descriptor if needed.
1239 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1240 tx_last = (uint16_t)(tx_id + nb_used - 1);
1243 if (tx_last >= txq->nb_tx_desc)
1244 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1246 if (nb_used > txq->nb_tx_free) {
1247 if (i40e_xmit_cleanup(txq) != 0) {
1252 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1253 while (nb_used > txq->nb_tx_free) {
1254 if (i40e_xmit_cleanup(txq) != 0) {
1263 /* Descriptor based VLAN insertion */
1264 if (ol_flags & PKT_TX_VLAN_PKT) {
1265 tx_flags |= tx_pkt->vlan_tci <<
1266 I40E_TX_FLAG_L2TAG1_SHIFT;
1267 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1268 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1269 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1270 I40E_TX_FLAG_L2TAG1_SHIFT;
1273 /* Always enable CRC offload insertion */
1274 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1276 /* Enable checksum offloading */
1277 cd_tunneling_params = 0;
1278 if (unlikely(ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)) {
1279 i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1280 l2_len, l3_len, outer_l2_len,
1282 &cd_tunneling_params);
1285 if (unlikely(nb_ctx)) {
1286 /* Setup TX context descriptor if required */
1287 volatile struct i40e_tx_context_desc *ctx_txd =
1288 (volatile struct i40e_tx_context_desc *)\
1290 uint16_t cd_l2tag2 = 0;
1291 uint64_t cd_type_cmd_tso_mss =
1292 I40E_TX_DESC_DTYPE_CONTEXT;
1294 txn = &sw_ring[txe->next_id];
1295 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1296 if (txe->mbuf != NULL) {
1297 rte_pktmbuf_free_seg(txe->mbuf);
1300 #ifdef RTE_LIBRTE_IEEE1588
1301 if (ol_flags & PKT_TX_IEEE1588_TMST)
1302 cd_type_cmd_tso_mss |=
1303 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1304 I40E_TXD_CTX_QW1_CMD_SHIFT);
1306 ctx_txd->tunneling_params =
1307 rte_cpu_to_le_32(cd_tunneling_params);
1308 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1309 ctx_txd->type_cmd_tso_mss =
1310 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1311 txe->last_id = tx_last;
1312 tx_id = txe->next_id;
1319 txn = &sw_ring[txe->next_id];
1322 rte_pktmbuf_free_seg(txe->mbuf);
1325 /* Setup TX Descriptor */
1326 slen = m_seg->data_len;
1327 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1328 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1329 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1330 td_offset, slen, td_tag);
1331 txe->last_id = tx_last;
1332 tx_id = txe->next_id;
1334 m_seg = m_seg->next;
1335 } while (m_seg != NULL);
1337 /* The last packet data descriptor needs End Of Packet (EOP) */
1338 td_cmd |= I40E_TX_DESC_CMD_EOP;
1339 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1340 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1342 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1343 PMD_TX_FREE_LOG(DEBUG,
1344 "Setting RS bit on TXD id="
1345 "%4u (port=%d queue=%d)",
1346 tx_last, txq->port_id, txq->queue_id);
1348 td_cmd |= I40E_TX_DESC_CMD_RS;
1350 /* Update txq RS bit counters */
1351 txq->nb_tx_used = 0;
1354 txd->cmd_type_offset_bsz |=
1355 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1356 I40E_TXD_QW1_CMD_SHIFT);
1362 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1363 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1364 (unsigned) tx_id, (unsigned) nb_tx);
1366 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1367 txq->tx_tail = tx_id;
1372 static inline int __attribute__((always_inline))
1373 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1375 struct i40e_tx_entry *txep;
1378 if (!(txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1379 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)))
1382 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1384 for (i = 0; i < txq->tx_rs_thresh; i++)
1385 rte_prefetch0((txep + i)->mbuf);
1387 if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1388 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1389 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1393 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1394 rte_pktmbuf_free_seg(txep->mbuf);
1399 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1400 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1401 if (txq->tx_next_dd >= txq->nb_tx_desc)
1402 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1404 return txq->tx_rs_thresh;
1407 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1408 I40E_TX_DESC_CMD_EOP)
1410 /* Populate 4 descriptors with data from 4 mbufs */
1412 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1417 for (i = 0; i < 4; i++, txdp++, pkts++) {
1418 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1419 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1420 txdp->cmd_type_offset_bsz =
1421 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1422 (*pkts)->data_len, 0);
1426 /* Populate 1 descriptor with data from 1 mbuf */
1428 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1432 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1433 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1434 txdp->cmd_type_offset_bsz =
1435 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1436 (*pkts)->data_len, 0);
1439 /* Fill hardware descriptor ring with mbuf data */
1441 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1442 struct rte_mbuf **pkts,
1445 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1446 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1447 const int N_PER_LOOP = 4;
1448 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1449 int mainpart, leftover;
1452 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1453 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1454 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1455 for (j = 0; j < N_PER_LOOP; ++j) {
1456 (txep + i + j)->mbuf = *(pkts + i + j);
1458 tx4(txdp + i, pkts + i);
1460 if (unlikely(leftover > 0)) {
1461 for (i = 0; i < leftover; ++i) {
1462 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1463 tx1(txdp + mainpart + i, pkts + mainpart + i);
1468 static inline uint16_t
1469 tx_xmit_pkts(struct i40e_tx_queue *txq,
1470 struct rte_mbuf **tx_pkts,
1473 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1477 * Begin scanning the H/W ring for done descriptors when the number
1478 * of available descriptors drops below tx_free_thresh. For each done
1479 * descriptor, free the associated buffer.
1481 if (txq->nb_tx_free < txq->tx_free_thresh)
1482 i40e_tx_free_bufs(txq);
1484 /* Use available descriptor only */
1485 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1486 if (unlikely(!nb_pkts))
1489 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1490 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1491 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1492 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1493 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1494 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1495 I40E_TXD_QW1_CMD_SHIFT);
1496 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1500 /* Fill hardware descriptor ring with mbuf data */
1501 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1502 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1504 /* Determin if RS bit needs to be set */
1505 if (txq->tx_tail > txq->tx_next_rs) {
1506 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1507 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1508 I40E_TXD_QW1_CMD_SHIFT);
1510 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1511 if (txq->tx_next_rs >= txq->nb_tx_desc)
1512 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1515 if (txq->tx_tail >= txq->nb_tx_desc)
1518 /* Update the tx tail register */
1520 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1526 i40e_xmit_pkts_simple(void *tx_queue,
1527 struct rte_mbuf **tx_pkts,
1532 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1533 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1537 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1540 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1541 &tx_pkts[nb_tx], num);
1542 nb_tx = (uint16_t)(nb_tx + ret);
1543 nb_pkts = (uint16_t)(nb_pkts - ret);
1552 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1553 * application used, which assume having sequential ones. But from driver's
1554 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1555 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1556 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1557 * use queue_idx from 0 to 95 to access queues, while real queue would be
1558 * different. This function will do a queue mapping to find VSI the queue
1561 static struct i40e_vsi*
1562 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1564 /* the queue in MAIN VSI range */
1565 if (queue_idx < pf->main_vsi->nb_qps)
1566 return pf->main_vsi;
1568 queue_idx -= pf->main_vsi->nb_qps;
1570 /* queue_idx is greater than VMDQ VSIs range */
1571 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1572 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1576 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1580 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1582 /* the queue in MAIN VSI range */
1583 if (queue_idx < pf->main_vsi->nb_qps)
1586 /* It's VMDQ queues */
1587 queue_idx -= pf->main_vsi->nb_qps;
1589 if (pf->nb_cfg_vmdq_vsi)
1590 return queue_idx % pf->vmdq_nb_qps;
1592 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1593 return (uint16_t)(-1);
1598 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1600 struct i40e_rx_queue *rxq;
1602 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1604 PMD_INIT_FUNC_TRACE();
1606 if (rx_queue_id < dev->data->nb_rx_queues) {
1607 rxq = dev->data->rx_queues[rx_queue_id];
1609 err = i40e_alloc_rx_queue_mbufs(rxq);
1611 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1617 /* Init the RX tail regieter. */
1618 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1620 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1623 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1626 i40e_rx_queue_release_mbufs(rxq);
1627 i40e_reset_rx_queue(rxq);
1635 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1637 struct i40e_rx_queue *rxq;
1639 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1641 if (rx_queue_id < dev->data->nb_rx_queues) {
1642 rxq = dev->data->rx_queues[rx_queue_id];
1645 * rx_queue_id is queue id aplication refers to, while
1646 * rxq->reg_idx is the real queue index.
1648 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1651 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1655 i40e_rx_queue_release_mbufs(rxq);
1656 i40e_reset_rx_queue(rxq);
1663 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1666 struct i40e_tx_queue *txq;
1667 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1669 PMD_INIT_FUNC_TRACE();
1671 if (tx_queue_id < dev->data->nb_tx_queues) {
1672 txq = dev->data->tx_queues[tx_queue_id];
1675 * tx_queue_id is queue id aplication refers to, while
1676 * rxq->reg_idx is the real queue index.
1678 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1680 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1688 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1690 struct i40e_tx_queue *txq;
1692 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1694 if (tx_queue_id < dev->data->nb_tx_queues) {
1695 txq = dev->data->tx_queues[tx_queue_id];
1698 * tx_queue_id is queue id aplication refers to, while
1699 * txq->reg_idx is the real queue index.
1701 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1704 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1709 i40e_tx_queue_release_mbufs(txq);
1710 i40e_reset_tx_queue(txq);
1717 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1720 unsigned int socket_id,
1721 const struct rte_eth_rxconf *rx_conf,
1722 struct rte_mempool *mp)
1724 struct i40e_vsi *vsi;
1725 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1727 struct i40e_rx_queue *rxq;
1728 const struct rte_memzone *rz;
1731 int use_def_burst_func = 1;
1733 if (hw->mac.type == I40E_MAC_VF) {
1734 struct i40e_vf *vf =
1735 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1738 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1741 PMD_DRV_LOG(ERR, "VSI not available or queue "
1742 "index exceeds the maximum");
1743 return I40E_ERR_PARAM;
1745 if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1746 (nb_desc > I40E_MAX_RING_DESC) ||
1747 (nb_desc < I40E_MIN_RING_DESC)) {
1748 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1749 "invalid", nb_desc);
1750 return I40E_ERR_PARAM;
1753 /* Free memory if needed */
1754 if (dev->data->rx_queues[queue_idx]) {
1755 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1756 dev->data->rx_queues[queue_idx] = NULL;
1759 /* Allocate the rx queue data structure */
1760 rxq = rte_zmalloc_socket("i40e rx queue",
1761 sizeof(struct i40e_rx_queue),
1762 RTE_CACHE_LINE_SIZE,
1765 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1766 "rx queue data structure");
1770 rxq->nb_rx_desc = nb_desc;
1771 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1772 rxq->queue_id = queue_idx;
1773 if (hw->mac.type == I40E_MAC_VF)
1774 rxq->reg_idx = queue_idx;
1775 else /* PF device */
1776 rxq->reg_idx = vsi->base_queue +
1777 i40e_get_queue_offset_by_qindex(pf, queue_idx);
1779 rxq->port_id = dev->data->port_id;
1780 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1782 rxq->drop_en = rx_conf->rx_drop_en;
1784 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1786 /* Allocate the maximun number of RX ring hardware descriptor. */
1787 ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1788 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1789 rz = i40e_ring_dma_zone_reserve(dev,
1795 i40e_dev_rx_queue_release(rxq);
1796 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1800 /* Zero all the descriptors in the ring. */
1801 memset(rz->addr, 0, ring_size);
1803 #ifdef RTE_LIBRTE_XEN_DOM0
1804 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1806 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1809 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1811 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1812 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1817 /* Allocate the software ring. */
1819 rte_zmalloc_socket("i40e rx sw ring",
1820 sizeof(struct i40e_rx_entry) * len,
1821 RTE_CACHE_LINE_SIZE,
1823 if (!rxq->sw_ring) {
1824 i40e_dev_rx_queue_release(rxq);
1825 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1829 i40e_reset_rx_queue(rxq);
1831 dev->data->rx_queues[queue_idx] = rxq;
1833 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1835 if (!use_def_burst_func && !dev->data->scattered_rx) {
1836 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1837 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1838 "satisfied. Rx Burst Bulk Alloc function will be "
1839 "used on port=%d, queue=%d.",
1840 rxq->port_id, rxq->queue_id);
1841 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1842 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1844 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1845 "not satisfied, Scattered Rx is requested, "
1846 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1847 "not enabled on port=%d, queue=%d.",
1848 rxq->port_id, rxq->queue_id);
1855 i40e_dev_rx_queue_release(void *rxq)
1857 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1860 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1864 i40e_rx_queue_release_mbufs(q);
1865 rte_free(q->sw_ring);
1870 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1872 #define I40E_RXQ_SCAN_INTERVAL 4
1873 volatile union i40e_rx_desc *rxdp;
1874 struct i40e_rx_queue *rxq;
1877 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1878 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1882 rxq = dev->data->rx_queues[rx_queue_id];
1883 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1884 while ((desc < rxq->nb_rx_desc) &&
1885 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1886 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1887 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1889 * Check the DD bit of a rx descriptor of each 4 in a group,
1890 * to avoid checking too frequently and downgrading performance
1893 desc += I40E_RXQ_SCAN_INTERVAL;
1894 rxdp += I40E_RXQ_SCAN_INTERVAL;
1895 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1896 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1897 desc - rxq->nb_rx_desc]);
1904 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1906 volatile union i40e_rx_desc *rxdp;
1907 struct i40e_rx_queue *rxq = rx_queue;
1911 if (unlikely(offset >= rxq->nb_rx_desc)) {
1912 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1916 desc = rxq->rx_tail + offset;
1917 if (desc >= rxq->nb_rx_desc)
1918 desc -= rxq->nb_rx_desc;
1920 rxdp = &(rxq->rx_ring[desc]);
1922 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1923 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1924 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1930 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1933 unsigned int socket_id,
1934 const struct rte_eth_txconf *tx_conf)
1936 struct i40e_vsi *vsi;
1937 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1939 struct i40e_tx_queue *txq;
1940 const struct rte_memzone *tz;
1942 uint16_t tx_rs_thresh, tx_free_thresh;
1944 if (hw->mac.type == I40E_MAC_VF) {
1945 struct i40e_vf *vf =
1946 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1949 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1952 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1953 "exceeds the maximum", queue_idx);
1954 return I40E_ERR_PARAM;
1957 if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
1958 (nb_desc > I40E_MAX_RING_DESC) ||
1959 (nb_desc < I40E_MIN_RING_DESC)) {
1960 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1961 "invalid", nb_desc);
1962 return I40E_ERR_PARAM;
1966 * The following two parameters control the setting of the RS bit on
1967 * transmit descriptors. TX descriptors will have their RS bit set
1968 * after txq->tx_rs_thresh descriptors have been used. The TX
1969 * descriptor ring will be cleaned after txq->tx_free_thresh
1970 * descriptors are used or if the number of descriptors required to
1971 * transmit a packet is greater than the number of free TX descriptors.
1973 * The following constraints must be satisfied:
1974 * - tx_rs_thresh must be greater than 0.
1975 * - tx_rs_thresh must be less than the size of the ring minus 2.
1976 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1977 * - tx_rs_thresh must be a divisor of the ring size.
1978 * - tx_free_thresh must be greater than 0.
1979 * - tx_free_thresh must be less than the size of the ring minus 3.
1981 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1982 * race condition, hence the maximum threshold constraints. When set
1983 * to zero use default values.
1985 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1986 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1987 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1988 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1989 if (tx_rs_thresh >= (nb_desc - 2)) {
1990 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1991 "number of TX descriptors minus 2. "
1992 "(tx_rs_thresh=%u port=%d queue=%d)",
1993 (unsigned int)tx_rs_thresh,
1994 (int)dev->data->port_id,
1996 return I40E_ERR_PARAM;
1998 if (tx_free_thresh >= (nb_desc - 3)) {
1999 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2000 "tx_free_thresh must be less than the "
2001 "number of TX descriptors minus 3. "
2002 "(tx_free_thresh=%u port=%d queue=%d)",
2003 (unsigned int)tx_free_thresh,
2004 (int)dev->data->port_id,
2006 return I40E_ERR_PARAM;
2008 if (tx_rs_thresh > tx_free_thresh) {
2009 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2010 "equal to tx_free_thresh. (tx_free_thresh=%u"
2011 " tx_rs_thresh=%u port=%d queue=%d)",
2012 (unsigned int)tx_free_thresh,
2013 (unsigned int)tx_rs_thresh,
2014 (int)dev->data->port_id,
2016 return I40E_ERR_PARAM;
2018 if ((nb_desc % tx_rs_thresh) != 0) {
2019 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2020 "number of TX descriptors. (tx_rs_thresh=%u"
2021 " port=%d queue=%d)",
2022 (unsigned int)tx_rs_thresh,
2023 (int)dev->data->port_id,
2025 return I40E_ERR_PARAM;
2027 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2028 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2029 "tx_rs_thresh is greater than 1. "
2030 "(tx_rs_thresh=%u port=%d queue=%d)",
2031 (unsigned int)tx_rs_thresh,
2032 (int)dev->data->port_id,
2034 return I40E_ERR_PARAM;
2037 /* Free memory if needed. */
2038 if (dev->data->tx_queues[queue_idx]) {
2039 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2040 dev->data->tx_queues[queue_idx] = NULL;
2043 /* Allocate the TX queue data structure. */
2044 txq = rte_zmalloc_socket("i40e tx queue",
2045 sizeof(struct i40e_tx_queue),
2046 RTE_CACHE_LINE_SIZE,
2049 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2050 "tx queue structure");
2054 /* Allocate TX hardware ring descriptors. */
2055 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2056 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2057 tz = i40e_ring_dma_zone_reserve(dev,
2063 i40e_dev_tx_queue_release(txq);
2064 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2068 txq->nb_tx_desc = nb_desc;
2069 txq->tx_rs_thresh = tx_rs_thresh;
2070 txq->tx_free_thresh = tx_free_thresh;
2071 txq->pthresh = tx_conf->tx_thresh.pthresh;
2072 txq->hthresh = tx_conf->tx_thresh.hthresh;
2073 txq->wthresh = tx_conf->tx_thresh.wthresh;
2074 txq->queue_id = queue_idx;
2075 if (hw->mac.type == I40E_MAC_VF)
2076 txq->reg_idx = queue_idx;
2077 else /* PF device */
2078 txq->reg_idx = vsi->base_queue +
2079 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2081 txq->port_id = dev->data->port_id;
2082 txq->txq_flags = tx_conf->txq_flags;
2084 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2086 #ifdef RTE_LIBRTE_XEN_DOM0
2087 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2089 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2091 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2093 /* Allocate software ring */
2095 rte_zmalloc_socket("i40e tx sw ring",
2096 sizeof(struct i40e_tx_entry) * nb_desc,
2097 RTE_CACHE_LINE_SIZE,
2099 if (!txq->sw_ring) {
2100 i40e_dev_tx_queue_release(txq);
2101 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2105 i40e_reset_tx_queue(txq);
2107 dev->data->tx_queues[queue_idx] = txq;
2109 /* Use a simple TX queue without offloads or multi segs if possible */
2110 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
2111 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
2112 PMD_INIT_LOG(INFO, "Using simple tx path");
2113 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2115 PMD_INIT_LOG(INFO, "Using full-featured tx path");
2116 dev->tx_pkt_burst = i40e_xmit_pkts;
2123 i40e_dev_tx_queue_release(void *txq)
2125 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2128 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2132 i40e_tx_queue_release_mbufs(q);
2133 rte_free(q->sw_ring);
2137 static const struct rte_memzone *
2138 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
2139 const char *ring_name,
2144 char z_name[RTE_MEMZONE_NAMESIZE];
2145 const struct rte_memzone *mz;
2147 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2148 dev->driver->pci_drv.name, ring_name,
2149 dev->data->port_id, queue_id);
2150 mz = rte_memzone_lookup(z_name);
2154 #ifdef RTE_LIBRTE_XEN_DOM0
2155 return rte_memzone_reserve_bounded(z_name, ring_size,
2156 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2158 return rte_memzone_reserve_aligned(z_name, ring_size,
2159 socket_id, 0, I40E_ALIGN);
2163 const struct rte_memzone *
2164 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2166 const struct rte_memzone *mz = NULL;
2168 mz = rte_memzone_lookup(name);
2171 #ifdef RTE_LIBRTE_XEN_DOM0
2172 mz = rte_memzone_reserve_bounded(name, len,
2173 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2175 mz = rte_memzone_reserve_aligned(name, len,
2176 socket_id, 0, I40E_ALIGN);
2182 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2186 if (!rxq || !rxq->sw_ring) {
2187 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2191 for (i = 0; i < rxq->nb_rx_desc; i++) {
2192 if (rxq->sw_ring[i].mbuf) {
2193 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2194 rxq->sw_ring[i].mbuf = NULL;
2197 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2198 if (rxq->rx_nb_avail == 0)
2200 for (i = 0; i < rxq->rx_nb_avail; i++) {
2201 struct rte_mbuf *mbuf;
2203 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2204 rte_pktmbuf_free_seg(mbuf);
2206 rxq->rx_nb_avail = 0;
2207 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2211 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2216 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2217 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2218 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2220 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2221 len = rxq->nb_rx_desc;
2223 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2224 ((volatile char *)rxq->rx_ring)[i] = 0;
2226 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2227 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2228 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2229 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2231 rxq->rx_nb_avail = 0;
2232 rxq->rx_next_avail = 0;
2233 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2234 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2236 rxq->nb_rx_hold = 0;
2237 rxq->pkt_first_seg = NULL;
2238 rxq->pkt_last_seg = NULL;
2242 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2246 if (!txq || !txq->sw_ring) {
2247 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2251 for (i = 0; i < txq->nb_tx_desc; i++) {
2252 if (txq->sw_ring[i].mbuf) {
2253 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2254 txq->sw_ring[i].mbuf = NULL;
2260 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2262 struct i40e_tx_entry *txe;
2263 uint16_t i, prev, size;
2266 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2271 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2272 for (i = 0; i < size; i++)
2273 ((volatile char *)txq->tx_ring)[i] = 0;
2275 prev = (uint16_t)(txq->nb_tx_desc - 1);
2276 for (i = 0; i < txq->nb_tx_desc; i++) {
2277 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2279 txd->cmd_type_offset_bsz =
2280 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2283 txe[prev].next_id = i;
2287 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2288 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2291 txq->nb_tx_used = 0;
2293 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2294 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2297 /* Init the TX queue in hardware */
2299 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2301 enum i40e_status_code err = I40E_SUCCESS;
2302 struct i40e_vsi *vsi = txq->vsi;
2303 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2304 uint16_t pf_q = txq->reg_idx;
2305 struct i40e_hmc_obj_txq tx_ctx;
2308 /* clear the context structure first */
2309 memset(&tx_ctx, 0, sizeof(tx_ctx));
2310 tx_ctx.new_context = 1;
2311 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2312 tx_ctx.qlen = txq->nb_tx_desc;
2313 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2314 if (vsi->type == I40E_VSI_FDIR)
2315 tx_ctx.fd_ena = TRUE;
2317 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2318 if (err != I40E_SUCCESS) {
2319 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2323 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2324 if (err != I40E_SUCCESS) {
2325 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2329 /* Now associate this queue with this PCI function */
2330 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2331 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2332 I40E_QTX_CTL_PF_INDX_MASK);
2333 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2334 I40E_WRITE_FLUSH(hw);
2336 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2342 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2344 struct i40e_rx_entry *rxe = rxq->sw_ring;
2348 for (i = 0; i < rxq->nb_rx_desc; i++) {
2349 volatile union i40e_rx_desc *rxd;
2350 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2352 if (unlikely(!mbuf)) {
2353 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2357 rte_mbuf_refcnt_set(mbuf, 1);
2359 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2361 mbuf->port = rxq->port_id;
2364 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2366 rxd = &rxq->rx_ring[i];
2367 rxd->read.pkt_addr = dma_addr;
2368 rxd->read.hdr_addr = dma_addr;
2369 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2370 rxd->read.rsvd1 = 0;
2371 rxd->read.rsvd2 = 0;
2372 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2381 * Calculate the buffer length, and check the jumbo frame
2382 * and maximum packet length.
2385 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2387 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2388 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2389 struct rte_eth_dev_data *data = pf->dev_data;
2390 struct rte_pktmbuf_pool_private *mbp_priv =
2391 rte_mempool_get_priv(rxq->mp);
2392 uint16_t buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2393 RTE_PKTMBUF_HEADROOM);
2396 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2397 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2398 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2399 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2400 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2401 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2402 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2403 rxq->hs_mode = i40e_header_split_enabled;
2405 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2407 rxq->rx_hdr_len = 0;
2408 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2409 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2410 rxq->hs_mode = i40e_header_split_none;
2414 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2415 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2416 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2417 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2418 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2419 PMD_DRV_LOG(ERR, "maximum packet length must "
2420 "be larger than %u and smaller than %u,"
2421 "as jumbo frame is enabled",
2422 (uint32_t)ETHER_MAX_LEN,
2423 (uint32_t)I40E_FRAME_SIZE_MAX);
2424 return I40E_ERR_CONFIG;
2427 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2428 rxq->max_pkt_len > ETHER_MAX_LEN) {
2429 PMD_DRV_LOG(ERR, "maximum packet length must be "
2430 "larger than %u and smaller than %u, "
2431 "as jumbo frame is disabled",
2432 (uint32_t)ETHER_MIN_LEN,
2433 (uint32_t)ETHER_MAX_LEN);
2434 return I40E_ERR_CONFIG;
2441 /* Init the RX queue in hardware */
2443 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2445 int err = I40E_SUCCESS;
2446 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2447 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2448 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2449 uint16_t pf_q = rxq->reg_idx;
2451 struct i40e_hmc_obj_rxq rx_ctx;
2452 struct rte_pktmbuf_pool_private *mbp_priv;
2454 err = i40e_rx_queue_config(rxq);
2456 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2460 /* Clear the context structure first */
2461 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2462 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2463 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2465 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2466 rx_ctx.qlen = rxq->nb_rx_desc;
2467 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2470 rx_ctx.dtype = rxq->hs_mode;
2472 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2474 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2475 rx_ctx.rxmax = rxq->max_pkt_len;
2476 rx_ctx.tphrdesc_ena = 1;
2477 rx_ctx.tphwdesc_ena = 1;
2478 rx_ctx.tphdata_ena = 1;
2479 rx_ctx.tphhead_ena = 1;
2480 rx_ctx.lrxqthresh = 2;
2481 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2486 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2487 if (err != I40E_SUCCESS) {
2488 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2491 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2492 if (err != I40E_SUCCESS) {
2493 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2497 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2499 mbp_priv = rte_mempool_get_priv(rxq->mp);
2500 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2501 RTE_PKTMBUF_HEADROOM);
2503 /* Check if scattered RX needs to be used. */
2504 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2505 dev_data->scattered_rx = 1;
2506 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2509 /* Init the RX tail regieter. */
2510 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2516 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2520 PMD_INIT_FUNC_TRACE();
2522 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2523 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2524 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2527 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2528 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2529 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2533 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2534 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2536 enum i40e_status_code
2537 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2539 struct i40e_tx_queue *txq;
2540 const struct rte_memzone *tz = NULL;
2542 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2545 PMD_DRV_LOG(ERR, "PF is not available");
2546 return I40E_ERR_BAD_PTR;
2549 /* Allocate the TX queue data structure. */
2550 txq = rte_zmalloc_socket("i40e fdir tx queue",
2551 sizeof(struct i40e_tx_queue),
2552 RTE_CACHE_LINE_SIZE,
2555 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2556 "tx queue structure.");
2557 return I40E_ERR_NO_MEMORY;
2560 /* Allocate TX hardware ring descriptors. */
2561 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2562 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2564 tz = i40e_ring_dma_zone_reserve(dev,
2570 i40e_dev_tx_queue_release(txq);
2571 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2572 return I40E_ERR_NO_MEMORY;
2575 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2576 txq->queue_id = I40E_FDIR_QUEUE_ID;
2577 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2578 txq->vsi = pf->fdir.fdir_vsi;
2580 #ifdef RTE_LIBRTE_XEN_DOM0
2581 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2583 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2585 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2587 * don't need to allocate software ring and reset for the fdir
2588 * program queue just set the queue has been configured.
2593 return I40E_SUCCESS;
2596 enum i40e_status_code
2597 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2599 struct i40e_rx_queue *rxq;
2600 const struct rte_memzone *rz = NULL;
2602 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2605 PMD_DRV_LOG(ERR, "PF is not available");
2606 return I40E_ERR_BAD_PTR;
2609 /* Allocate the RX queue data structure. */
2610 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2611 sizeof(struct i40e_rx_queue),
2612 RTE_CACHE_LINE_SIZE,
2615 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2616 "rx queue structure.");
2617 return I40E_ERR_NO_MEMORY;
2620 /* Allocate RX hardware ring descriptors. */
2621 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2622 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2624 rz = i40e_ring_dma_zone_reserve(dev,
2630 i40e_dev_rx_queue_release(rxq);
2631 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2632 return I40E_ERR_NO_MEMORY;
2635 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2636 rxq->queue_id = I40E_FDIR_QUEUE_ID;
2637 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2638 rxq->vsi = pf->fdir.fdir_vsi;
2640 #ifdef RTE_LIBRTE_XEN_DOM0
2641 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2643 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
2645 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2648 * Don't need to allocate software ring and reset for the fdir
2649 * rx queue, just set the queue has been configured.
2654 return I40E_SUCCESS;