1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
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18 this software without specific prior written permission.
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82598.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
39 #ident "$Id: ixgbe_82598.c,v 1.194 2012/03/28 00:54:08 jtkirshe Exp $"
41 #define IXGBE_82598_MAX_TX_QUEUES 32
42 #define IXGBE_82598_MAX_RX_QUEUES 64
43 #define IXGBE_82598_RAR_ENTRIES 16
44 #define IXGBE_82598_MC_TBL_SIZE 128
45 #define IXGBE_82598_VFT_TBL_SIZE 128
46 #define IXGBE_82598_RX_PB_SIZE 512
48 STATIC s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
49 ixgbe_link_speed *speed,
51 STATIC enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
53 bool autoneg_wait_to_complete);
54 STATIC s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
55 ixgbe_link_speed *speed, bool *link_up,
56 bool link_up_wait_to_complete);
57 STATIC s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
58 ixgbe_link_speed speed,
59 bool autoneg_wait_to_complete);
60 STATIC s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
61 ixgbe_link_speed speed,
62 bool autoneg_wait_to_complete);
63 STATIC s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
64 STATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
65 STATIC s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
66 STATIC void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
67 u32 headroom, int strategy);
70 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
71 * @hw: pointer to the HW structure
73 * The defaults for 82598 should be in the range of 50us to 50ms,
74 * however the hardware default for these parts is 500us to 1ms which is less
75 * than the 10ms recommended by the pci-e spec. To address this we need to
76 * increase the value to either 10ms to 250ms for capability version 1 config,
77 * or 16ms to 55ms for version 2.
79 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
81 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
84 /* only take action if timeout value is defaulted to 0 */
85 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
89 * if capababilities version is type 1 we can write the
90 * timeout of 10ms to 250ms through the GCR register
92 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
93 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
98 * for version 2 capabilities we need to write the config space
99 * directly in order to set the completion timeout value for
102 pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
103 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
104 IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
106 /* disable completion timeout resend */
107 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
108 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
112 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
113 * @hw: pointer to hardware structure
115 * Initialize the function pointers and assign the MAC type for 82598.
116 * Does not touch the hardware.
118 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
120 struct ixgbe_mac_info *mac = &hw->mac;
121 struct ixgbe_phy_info *phy = &hw->phy;
124 DEBUGFUNC("ixgbe_init_ops_82598");
126 ret_val = ixgbe_init_phy_ops_generic(hw);
127 ret_val = ixgbe_init_ops_generic(hw);
130 phy->ops.init = &ixgbe_init_phy_ops_82598;
133 mac->ops.start_hw = &ixgbe_start_hw_82598;
134 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_82598;
135 mac->ops.reset_hw = &ixgbe_reset_hw_82598;
136 mac->ops.get_media_type = &ixgbe_get_media_type_82598;
137 mac->ops.get_supported_physical_layer =
138 &ixgbe_get_supported_physical_layer_82598;
139 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
140 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
141 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598;
142 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82598;
144 /* RAR, Multicast, VLAN */
145 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
146 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;
147 mac->ops.set_vfta = &ixgbe_set_vfta_82598;
148 mac->ops.set_vlvf = NULL;
149 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598;
152 mac->ops.fc_enable = &ixgbe_fc_enable_82598;
154 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
155 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
156 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
157 mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE;
158 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
159 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
160 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
163 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
166 mac->ops.check_link = &ixgbe_check_mac_link_82598;
167 mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
168 mac->ops.flap_tx_laser = NULL;
169 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82598;
170 mac->ops.setup_rxpba = &ixgbe_set_rxpba_82598;
172 /* Manageability interface */
173 mac->ops.set_fw_drv_ver = NULL;
175 mac->ops.get_rtrup2tc = NULL;
181 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
182 * @hw: pointer to hardware structure
184 * Initialize any function pointers that were not able to be
185 * set during init_shared_code because the PHY/SFP type was
186 * not known. Perform the SFP init if necessary.
189 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
191 struct ixgbe_mac_info *mac = &hw->mac;
192 struct ixgbe_phy_info *phy = &hw->phy;
193 s32 ret_val = IXGBE_SUCCESS;
194 u16 list_offset, data_offset;
196 DEBUGFUNC("ixgbe_init_phy_ops_82598");
198 /* Identify the PHY */
199 phy->ops.identify(hw);
201 /* Overwrite the link function pointers if copper PHY */
202 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
203 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
204 mac->ops.get_link_capabilities =
205 &ixgbe_get_copper_link_capabilities_generic;
208 switch (hw->phy.type) {
210 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
211 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
212 phy->ops.get_firmware_version =
213 &ixgbe_get_phy_firmware_version_tnx;
216 phy->ops.reset = &ixgbe_reset_phy_nl;
218 /* Call SFP+ identify routine to get the SFP+ module type */
219 ret_val = phy->ops.identify_sfp(hw);
220 if (ret_val != IXGBE_SUCCESS)
222 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
223 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
227 /* Check to see if SFP+ module is supported */
228 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
231 if (ret_val != IXGBE_SUCCESS) {
232 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
245 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
246 * @hw: pointer to hardware structure
248 * Starts the hardware using the generic start_hw function.
249 * Disables relaxed ordering Then set pcie completion timeout
252 s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
256 s32 ret_val = IXGBE_SUCCESS;
258 DEBUGFUNC("ixgbe_start_hw_82598");
260 ret_val = ixgbe_start_hw_generic(hw);
262 /* Disable relaxed ordering */
263 for (i = 0; ((i < hw->mac.max_tx_queues) &&
264 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
265 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
266 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
267 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
270 for (i = 0; ((i < hw->mac.max_rx_queues) &&
271 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
272 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
273 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
274 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
275 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
278 /* set the completion timeout for interface */
279 if (ret_val == IXGBE_SUCCESS)
280 ixgbe_set_pcie_completion_timeout(hw);
286 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
287 * @hw: pointer to hardware structure
288 * @speed: pointer to link speed
289 * @autoneg: boolean auto-negotiation value
291 * Determines the link capabilities by reading the AUTOC register.
293 STATIC s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
294 ixgbe_link_speed *speed,
297 s32 status = IXGBE_SUCCESS;
300 DEBUGFUNC("ixgbe_get_link_capabilities_82598");
303 * Determine link capabilities based on the stored value of AUTOC,
304 * which represents EEPROM defaults. If AUTOC value has not been
305 * stored, use the current register value.
307 if (hw->mac.orig_link_settings_stored)
308 autoc = hw->mac.orig_autoc;
310 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
312 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
313 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
314 *speed = IXGBE_LINK_SPEED_1GB_FULL;
318 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
319 *speed = IXGBE_LINK_SPEED_10GB_FULL;
323 case IXGBE_AUTOC_LMS_1G_AN:
324 *speed = IXGBE_LINK_SPEED_1GB_FULL;
328 case IXGBE_AUTOC_LMS_KX4_AN:
329 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
330 *speed = IXGBE_LINK_SPEED_UNKNOWN;
331 if (autoc & IXGBE_AUTOC_KX4_SUPP)
332 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
333 if (autoc & IXGBE_AUTOC_KX_SUPP)
334 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
339 status = IXGBE_ERR_LINK_SETUP;
347 * ixgbe_get_media_type_82598 - Determines media type
348 * @hw: pointer to hardware structure
350 * Returns the media type (fiber, copper, backplane)
352 STATIC enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
354 enum ixgbe_media_type media_type;
356 DEBUGFUNC("ixgbe_get_media_type_82598");
358 /* Detect if there is a copper PHY attached. */
359 switch (hw->phy.type) {
360 case ixgbe_phy_cu_unknown:
362 media_type = ixgbe_media_type_copper;
368 /* Media type for I82598 is based on device ID */
369 switch (hw->device_id) {
370 case IXGBE_DEV_ID_82598:
371 case IXGBE_DEV_ID_82598_BX:
372 /* Default device ID is mezzanine card KX/KX4 */
373 media_type = ixgbe_media_type_backplane;
375 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
376 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
377 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
378 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
379 case IXGBE_DEV_ID_82598EB_XF_LR:
380 case IXGBE_DEV_ID_82598EB_SFP_LOM:
381 media_type = ixgbe_media_type_fiber;
383 case IXGBE_DEV_ID_82598EB_CX4:
384 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
385 media_type = ixgbe_media_type_cx4;
387 case IXGBE_DEV_ID_82598AT:
388 case IXGBE_DEV_ID_82598AT2:
389 media_type = ixgbe_media_type_copper;
392 media_type = ixgbe_media_type_unknown;
400 * ixgbe_fc_enable_82598 - Enable flow control
401 * @hw: pointer to hardware structure
403 * Enable flow control according to the current settings.
405 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
407 s32 ret_val = IXGBE_SUCCESS;
416 DEBUGFUNC("ixgbe_fc_enable_82598");
418 /* Validate the water mark configuration */
419 if (!hw->fc.pause_time) {
420 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
424 /* Low water mark of zero causes XOFF floods */
425 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
426 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
427 hw->fc.high_water[i]) {
428 if (!hw->fc.low_water[i] ||
429 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
430 DEBUGOUT("Invalid water mark configuration\n");
431 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
438 * On 82598 having Rx FC on causes resets while doing 1G
439 * so if it's on turn it off once we know link_speed. For
440 * more details see 82598 Specification update.
442 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
443 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
444 switch (hw->fc.requested_mode) {
446 hw->fc.requested_mode = ixgbe_fc_tx_pause;
448 case ixgbe_fc_rx_pause:
449 hw->fc.requested_mode = ixgbe_fc_none;
457 /* Negotiate the fc mode to use */
458 ixgbe_fc_autoneg(hw);
460 /* Disable any previous flow control settings */
461 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
462 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
464 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
465 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
468 * The possible values of fc.current_mode are:
469 * 0: Flow control is completely disabled
470 * 1: Rx flow control is enabled (we can receive pause frames,
471 * but not send pause frames).
472 * 2: Tx flow control is enabled (we can send pause frames but
473 * we do not support receiving pause frames).
474 * 3: Both Rx and Tx flow control (symmetric) are enabled.
477 switch (hw->fc.current_mode) {
480 * Flow control is disabled by software override or autoneg.
481 * The code below will actually disable it in the HW.
484 case ixgbe_fc_rx_pause:
486 * Rx Flow control is enabled and Tx Flow control is
487 * disabled by software override. Since there really
488 * isn't a way to advertise that we are capable of RX
489 * Pause ONLY, we will advertise that we support both
490 * symmetric and asymmetric Rx PAUSE. Later, we will
491 * disable the adapter's ability to send PAUSE frames.
493 fctrl_reg |= IXGBE_FCTRL_RFCE;
495 case ixgbe_fc_tx_pause:
497 * Tx Flow control is enabled, and Rx Flow control is
498 * disabled by software override.
500 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
503 /* Flow control (both Rx and Tx) is enabled by SW override. */
504 fctrl_reg |= IXGBE_FCTRL_RFCE;
505 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
508 DEBUGOUT("Flow control param set incorrectly\n");
509 ret_val = IXGBE_ERR_CONFIG;
514 /* Set 802.3x based flow control settings. */
515 fctrl_reg |= IXGBE_FCTRL_DPF;
516 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
517 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
519 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
520 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
521 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
522 hw->fc.high_water[i]) {
523 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
524 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
525 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
526 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
528 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
529 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
534 /* Configure pause time (2 TCs per register) */
535 reg = hw->fc.pause_time * 0x00010001;
536 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
537 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
539 /* Configure flow control refresh threshold value */
540 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
547 * ixgbe_start_mac_link_82598 - Configures MAC link settings
548 * @hw: pointer to hardware structure
550 * Configures link settings based on values in the ixgbe_hw struct.
551 * Restarts the link. Performs autonegotiation if needed.
553 STATIC s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
554 bool autoneg_wait_to_complete)
559 s32 status = IXGBE_SUCCESS;
561 DEBUGFUNC("ixgbe_start_mac_link_82598");
564 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
565 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
566 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
568 /* Only poll for autoneg to complete if specified to do so */
569 if (autoneg_wait_to_complete) {
570 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
571 IXGBE_AUTOC_LMS_KX4_AN ||
572 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
573 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
574 links_reg = 0; /* Just in case Autoneg time = 0 */
575 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
576 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
577 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
581 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
582 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
583 DEBUGOUT("Autonegotiation did not complete.\n");
588 /* Add delay to filter out noises during initial link setup */
595 * ixgbe_validate_link_ready - Function looks for phy link
596 * @hw: pointer to hardware structure
598 * Function indicates success when phy link is available. If phy is not ready
599 * within 5 seconds of MAC indicating link, the function returns error.
601 STATIC s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
606 if (hw->device_id != IXGBE_DEV_ID_82598AT2)
607 return IXGBE_SUCCESS;
610 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
611 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
612 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg);
614 if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) &&
615 (an_reg & IXGBE_MII_AUTONEG_LINK_UP))
621 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
622 DEBUGOUT("Link was indicated but link is down\n");
623 return IXGBE_ERR_LINK_SETUP;
626 return IXGBE_SUCCESS;
630 * ixgbe_check_mac_link_82598 - Get link/speed status
631 * @hw: pointer to hardware structure
632 * @speed: pointer to link speed
633 * @link_up: true is link is up, false otherwise
634 * @link_up_wait_to_complete: bool used to wait for link up or not
636 * Reads the links register to determine if link is up and the current speed
638 STATIC s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
639 ixgbe_link_speed *speed, bool *link_up,
640 bool link_up_wait_to_complete)
644 u16 link_reg, adapt_comp_reg;
646 DEBUGFUNC("ixgbe_check_mac_link_82598");
649 * SERDES PHY requires us to read link status from undocumented
650 * register 0xC79F. Bit 0 set indicates link is up/ready; clear
651 * indicates link down. OxC00C is read to check that the XAUI lanes
652 * are active. Bit 0 clear indicates active; set indicates inactive.
654 if (hw->phy.type == ixgbe_phy_nl) {
655 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
656 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
657 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
659 if (link_up_wait_to_complete) {
660 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
661 if ((link_reg & 1) &&
662 ((adapt_comp_reg & 1) == 0)) {
669 hw->phy.ops.read_reg(hw, 0xC79F,
672 hw->phy.ops.read_reg(hw, 0xC00C,
677 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
683 if (*link_up == false)
687 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
688 if (link_up_wait_to_complete) {
689 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
690 if (links_reg & IXGBE_LINKS_UP) {
697 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
700 if (links_reg & IXGBE_LINKS_UP)
706 if (links_reg & IXGBE_LINKS_SPEED)
707 *speed = IXGBE_LINK_SPEED_10GB_FULL;
709 *speed = IXGBE_LINK_SPEED_1GB_FULL;
711 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) &&
712 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))
716 return IXGBE_SUCCESS;
720 * ixgbe_setup_mac_link_82598 - Set MAC link speed
721 * @hw: pointer to hardware structure
722 * @speed: new link speed
723 * @autoneg_wait_to_complete: true when waiting for completion is needed
725 * Set the link speed in the AUTOC register and restarts link.
727 STATIC s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
728 ixgbe_link_speed speed,
729 bool autoneg_wait_to_complete)
731 bool autoneg = false;
732 s32 status = IXGBE_SUCCESS;
733 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
734 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
735 u32 autoc = curr_autoc;
736 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
738 DEBUGFUNC("ixgbe_setup_mac_link_82598");
740 /* Check to see if speed passed in is supported. */
741 ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
742 speed &= link_capabilities;
744 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
745 status = IXGBE_ERR_LINK_SETUP;
747 /* Set KX4/KX support according to speed requested */
748 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
749 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
750 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
751 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
752 autoc |= IXGBE_AUTOC_KX4_SUPP;
753 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
754 autoc |= IXGBE_AUTOC_KX_SUPP;
755 if (autoc != curr_autoc)
756 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
759 if (status == IXGBE_SUCCESS) {
761 * Setup and restart the link based on the new values in
762 * ixgbe_hw This will write the AUTOC register based on the new
765 status = ixgbe_start_mac_link_82598(hw,
766 autoneg_wait_to_complete);
774 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
775 * @hw: pointer to hardware structure
776 * @speed: new link speed
777 * @autoneg_wait_to_complete: true if waiting is needed to complete
779 * Sets the link speed in the AUTOC register in the MAC and restarts link.
781 STATIC s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
782 ixgbe_link_speed speed,
783 bool autoneg_wait_to_complete)
787 DEBUGFUNC("ixgbe_setup_copper_link_82598");
789 /* Setup the PHY according to input speed */
790 status = hw->phy.ops.setup_link_speed(hw, speed,
791 autoneg_wait_to_complete);
793 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
799 * ixgbe_reset_hw_82598 - Performs hardware reset
800 * @hw: pointer to hardware structure
802 * Resets the hardware by resetting the transmit and receive units, masks and
803 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
806 STATIC s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
808 s32 status = IXGBE_SUCCESS;
809 s32 phy_status = IXGBE_SUCCESS;
816 DEBUGFUNC("ixgbe_reset_hw_82598");
818 /* Call adapter stop to disable tx/rx and clear interrupts */
819 status = hw->mac.ops.stop_adapter(hw);
820 if (status != IXGBE_SUCCESS)
824 * Power up the Atlas Tx lanes if they are currently powered down.
825 * Atlas Tx lanes are powered down for MAC loopback tests, but
826 * they are not automatically restored on reset.
828 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
829 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
830 /* Enable Tx Atlas so packets can be transmitted again */
831 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
833 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
834 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
837 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
839 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
840 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
843 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
845 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
846 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
849 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
851 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
852 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
857 if (hw->phy.reset_disable == false) {
858 /* PHY ops must be identified and initialized prior to reset */
860 /* Init PHY and function pointers, perform SFP setup */
861 phy_status = hw->phy.ops.init(hw);
862 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
864 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
867 hw->phy.ops.reset(hw);
872 * Issue global reset to the MAC. This needs to be a SW reset.
873 * If link reset is used, it might reset the MAC when mng is using it
875 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
876 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
877 IXGBE_WRITE_FLUSH(hw);
879 /* Poll for reset bit to self-clear indicating reset is complete */
880 for (i = 0; i < 10; i++) {
882 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
883 if (!(ctrl & IXGBE_CTRL_RST))
886 if (ctrl & IXGBE_CTRL_RST) {
887 status = IXGBE_ERR_RESET_FAILED;
888 DEBUGOUT("Reset polling failed to complete.\n");
894 * Double resets are required for recovery from certain error
895 * conditions. Between resets, it is necessary to stall to allow time
896 * for any pending HW events to complete.
898 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
899 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
903 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
904 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
905 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
908 * Store the original AUTOC value if it has not been
909 * stored off yet. Otherwise restore the stored original
910 * AUTOC value since the reset operation sets back to deaults.
912 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
913 if (hw->mac.orig_link_settings_stored == false) {
914 hw->mac.orig_autoc = autoc;
915 hw->mac.orig_link_settings_stored = true;
916 } else if (autoc != hw->mac.orig_autoc) {
917 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
920 /* Store the permanent mac address */
921 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
924 * Store MAC address from RAR0, clear receive address registers, and
925 * clear the multicast table
927 hw->mac.ops.init_rx_addrs(hw);
930 if (phy_status != IXGBE_SUCCESS)
937 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
938 * @hw: pointer to hardware struct
939 * @rar: receive address register index to associate with a VMDq index
940 * @vmdq: VMDq set index
942 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
945 u32 rar_entries = hw->mac.num_rar_entries;
947 DEBUGFUNC("ixgbe_set_vmdq_82598");
949 /* Make sure we are using a valid rar index range */
950 if (rar >= rar_entries) {
951 DEBUGOUT1("RAR index %d is out of range.\n", rar);
952 return IXGBE_ERR_INVALID_ARGUMENT;
955 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
956 rar_high &= ~IXGBE_RAH_VIND_MASK;
957 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
958 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
959 return IXGBE_SUCCESS;
963 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
964 * @hw: pointer to hardware struct
965 * @rar: receive address register index to associate with a VMDq index
966 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
968 STATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
971 u32 rar_entries = hw->mac.num_rar_entries;
973 UNREFERENCED_1PARAMETER(vmdq);
975 /* Make sure we are using a valid rar index range */
976 if (rar >= rar_entries) {
977 DEBUGOUT1("RAR index %d is out of range.\n", rar);
978 return IXGBE_ERR_INVALID_ARGUMENT;
981 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
982 if (rar_high & IXGBE_RAH_VIND_MASK) {
983 rar_high &= ~IXGBE_RAH_VIND_MASK;
984 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
987 return IXGBE_SUCCESS;
991 * ixgbe_set_vfta_82598 - Set VLAN filter table
992 * @hw: pointer to hardware structure
993 * @vlan: VLAN id to write to VLAN filter
994 * @vind: VMDq output index that maps queue to VLAN id in VFTA
995 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
997 * Turn on/off specified VLAN in the VLAN filter table.
999 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1007 DEBUGFUNC("ixgbe_set_vfta_82598");
1010 return IXGBE_ERR_PARAM;
1012 /* Determine 32-bit word position in array */
1013 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
1015 /* Determine the location of the (VMD) queue index */
1016 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
1017 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
1019 /* Set the nibble for VMD queue index */
1020 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
1021 bits &= (~(0x0F << bitindex));
1022 bits |= (vind << bitindex);
1023 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
1025 /* Determine the location of the bit for this VLAN id */
1026 bitindex = vlan & 0x1F; /* lower five bits */
1028 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1030 /* Turn on this VLAN id */
1031 bits |= (1 << bitindex);
1033 /* Turn off this VLAN id */
1034 bits &= ~(1 << bitindex);
1035 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1037 return IXGBE_SUCCESS;
1041 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
1042 * @hw: pointer to hardware structure
1044 * Clears the VLAN filer table, and the VMDq index associated with the filter
1046 STATIC s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
1051 DEBUGFUNC("ixgbe_clear_vfta_82598");
1053 for (offset = 0; offset < hw->mac.vft_size; offset++)
1054 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1056 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
1057 for (offset = 0; offset < hw->mac.vft_size; offset++)
1058 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
1061 return IXGBE_SUCCESS;
1065 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
1066 * @hw: pointer to hardware structure
1067 * @reg: analog register to read
1070 * Performs read operation to Atlas analog register specified.
1072 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
1076 DEBUGFUNC("ixgbe_read_analog_reg8_82598");
1078 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
1079 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
1080 IXGBE_WRITE_FLUSH(hw);
1082 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
1083 *val = (u8)atlas_ctl;
1085 return IXGBE_SUCCESS;
1089 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
1090 * @hw: pointer to hardware structure
1091 * @reg: atlas register to write
1092 * @val: value to write
1094 * Performs write operation to Atlas analog register specified.
1096 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
1100 DEBUGFUNC("ixgbe_write_analog_reg8_82598");
1102 atlas_ctl = (reg << 8) | val;
1103 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1104 IXGBE_WRITE_FLUSH(hw);
1107 return IXGBE_SUCCESS;
1111 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1112 * @hw: pointer to hardware structure
1113 * @byte_offset: EEPROM byte offset to read
1114 * @eeprom_data: value read
1116 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1118 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1121 s32 status = IXGBE_SUCCESS;
1127 DEBUGFUNC("ixgbe_read_i2c_eeprom_82598");
1129 if (hw->phy.type == ixgbe_phy_nl) {
1131 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
1132 * 0xC30D. These registers are used to talk to the SFP+
1133 * module's EEPROM through the SDA/SCL (I2C) interface.
1135 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1136 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1137 hw->phy.ops.write_reg(hw,
1138 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1139 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1143 for (i = 0; i < 100; i++) {
1144 hw->phy.ops.read_reg(hw,
1145 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1146 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1148 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1149 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1154 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1155 DEBUGOUT("EEPROM read did not pass.\n");
1156 status = IXGBE_ERR_SFP_NOT_PRESENT;
1161 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1162 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1164 *eeprom_data = (u8)(sfp_data >> 8);
1166 status = IXGBE_ERR_PHY;
1175 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1176 * @hw: pointer to hardware structure
1178 * Determines physical layer capabilities of the current configuration.
1180 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1182 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1183 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1184 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1185 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1186 u16 ext_ability = 0;
1188 DEBUGFUNC("ixgbe_get_supported_physical_layer_82598");
1190 hw->phy.ops.identify(hw);
1192 /* Copper PHY must be checked before AUTOC LMS to determine correct
1193 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1194 switch (hw->phy.type) {
1196 case ixgbe_phy_cu_unknown:
1197 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1198 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1199 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1200 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1201 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1202 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1203 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1204 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1210 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1211 case IXGBE_AUTOC_LMS_1G_AN:
1212 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1213 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1214 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1216 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1218 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1219 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1220 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1221 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1222 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1224 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1226 case IXGBE_AUTOC_LMS_KX4_AN:
1227 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1228 if (autoc & IXGBE_AUTOC_KX_SUPP)
1229 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1230 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1231 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1237 if (hw->phy.type == ixgbe_phy_nl) {
1238 hw->phy.ops.identify_sfp(hw);
1240 switch (hw->phy.sfp_type) {
1241 case ixgbe_sfp_type_da_cu:
1242 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1244 case ixgbe_sfp_type_sr:
1245 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1247 case ixgbe_sfp_type_lr:
1248 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1251 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1256 switch (hw->device_id) {
1257 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1258 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1260 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1261 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1262 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1263 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1265 case IXGBE_DEV_ID_82598EB_XF_LR:
1266 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1273 return physical_layer;
1277 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1279 * @hw: pointer to the HW structure
1281 * Calls common function and corrects issue with some single port devices
1282 * that enable LAN1 but not LAN0.
1284 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
1286 struct ixgbe_bus_info *bus = &hw->bus;
1290 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie_82598");
1292 ixgbe_set_lan_id_multi_port_pcie(hw);
1294 /* check if LAN0 is disabled */
1295 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
1296 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
1298 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
1300 /* if LAN0 is completely disabled force function to 0 */
1301 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
1302 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
1303 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
1311 * ixgbe_enable_relaxed_ordering_82598 - enable relaxed ordering
1312 * @hw: pointer to hardware structure
1315 void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw)
1320 DEBUGFUNC("ixgbe_enable_relaxed_ordering_82598");
1322 /* Enable relaxed ordering */
1323 for (i = 0; ((i < hw->mac.max_tx_queues) &&
1324 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1325 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
1326 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
1327 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
1330 for (i = 0; ((i < hw->mac.max_rx_queues) &&
1331 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1332 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
1333 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
1334 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
1335 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
1341 * ixgbe_set_rxpba_82598 - Initialize RX packet buffer
1342 * @hw: pointer to hardware structure
1343 * @num_pb: number of packet buffers to allocate
1344 * @headroom: reserve n KB of headroom
1345 * @strategy: packet buffer allocation strategy
1347 STATIC void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
1348 u32 headroom, int strategy)
1350 u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
1352 UNREFERENCED_1PARAMETER(headroom);
1357 /* Setup Rx packet buffer sizes */
1359 case PBA_STRATEGY_WEIGHTED:
1360 /* Setup the first four at 80KB */
1361 rxpktsize = IXGBE_RXPBSIZE_80KB;
1363 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1364 /* Setup the last four at 48KB...don't re-init i */
1365 rxpktsize = IXGBE_RXPBSIZE_48KB;
1367 case PBA_STRATEGY_EQUAL:
1369 /* Divide the remaining Rx packet buffer evenly among the TCs */
1370 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1371 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1375 /* Setup Tx packet buffer sizes */
1376 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1377 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
1383 * ixgbe_enable_rx_dma_82598 - Enable the Rx DMA unit
1384 * @hw: pointer to hardware structure
1385 * @regval: register value to write to RXCTRL
1387 * Enables the Rx DMA unit
1389 s32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval)
1391 DEBUGFUNC("ixgbe_enable_rx_dma_82598");
1393 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1395 return IXGBE_SUCCESS;