lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37
  38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  50                                           u8 *sff8472_data);
  51
  52 /**
  53  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54  * @hw: pointer to the hardware structure
  55  * @byte: byte to send
  56  *
  57  * Returns an error code on error.
  58  */
  59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60 {
  61         s32 status;
  62
  63         status = ixgbe_clock_out_i2c_byte(hw, byte);
  64         if (status)
  65                 return status;
  66         return ixgbe_get_i2c_ack(hw);
  67 }
  68
  69 /**
  70  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71  * @hw: pointer to the hardware structure
  72  * @byte: pointer to a u8 to receive the byte
  73  *
  74  * Returns an error code on error.
  75  */
  76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77 {
  78         s32 status;
  79
  80         status = ixgbe_clock_in_i2c_byte(hw, byte);
  81         if (status)
  82                 return status;
  83         /* ACK */
  84         return ixgbe_clock_out_i2c_bit(hw, false);
  85 }
  86
  87 /**
  88  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  89  * @add1 - addend 1
  90  * @add2 - addend 2
  91  *
  92  * Returns one's complement 8-bit sum.
  93  */
  94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95 {
  96         u16 sum = add1 + add2;
  97
  98         sum = (sum & 0xFF) + (sum >> 8);
  99         return sum & 0xFF;
 100 }
 101
 102 /**
 103  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 104  * @hw: pointer to the hardware structure
 105  * @addr: I2C bus address to read from
 106  * @reg: I2C device register to read from
 107  * @val: pointer to location to receive read value
 108  *
 109  * Returns an error code on error.
 110  */
 111 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 112                                            u16 reg, u16 *val)
 113 {
 114         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 115         int max_retry = 10;
 116         int retry = 0;
 117         u8 csum_byte;
 118         u8 high_bits;
 119         u8 low_bits;
 120         u8 reg_high;
 121         u8 csum;
 122
 123         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 124         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 125         csum = ~csum;
 126         do {
 127                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 128                         return IXGBE_ERR_SWFW_SYNC;
 129                 ixgbe_i2c_start(hw);
 130                 /* Device Address and write indication */
 131                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 132                         goto fail;
 133                 /* Write bits 14:8 */
 134                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 135                         goto fail;
 136                 /* Write bits 7:0 */
 137                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 138                         goto fail;
 139                 /* Write csum */
 140                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 141                         goto fail;
 142                 /* Re-start condition */
 143                 ixgbe_i2c_start(hw);
 144                 /* Device Address and read indication */
 145                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 146                         goto fail;
 147                 /* Get upper bits */
 148                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 149                         goto fail;
 150                 /* Get low bits */
 151                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 152                         goto fail;
 153                 /* Get csum */
 154                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 155                         goto fail;
 156                 /* NACK */
 157                 if (ixgbe_clock_out_i2c_bit(hw, false))
 158                         goto fail;
 159                 ixgbe_i2c_stop(hw);
 160                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 161                 *val = (high_bits << 8) | low_bits;
 162                 return 0;
 163
 164 fail:
 165                 ixgbe_i2c_bus_clear(hw);
 166                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 167                 retry++;
 168                 if (retry < max_retry)
 169                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 170                 else
 171                         DEBUGOUT("I2C byte read combined error.\n");
 172         } while (retry < max_retry);
 173
 174         return IXGBE_ERR_I2C;
 175 }
 176
 177 /**
 178  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 179  * @hw: pointer to the hardware structure
 180  * @addr: I2C bus address to write to
 181  * @reg: I2C device register to write to
 182  * @val: value to write
 183  *
 184  * Returns an error code on error.
 185  */
 186 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 187                                             u8 addr, u16 reg, u16 val)
 188 {
 189         int max_retry = 1;
 190         int retry = 0;
 191         u8 reg_high;
 192         u8 csum;
 193
 194         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 195         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 196         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 197         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 198         csum = ~csum;
 199         do {
 200                 ixgbe_i2c_start(hw);
 201                 /* Device Address and write indication */
 202                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 203                         goto fail;
 204                 /* Write bits 14:8 */
 205                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 206                         goto fail;
 207                 /* Write bits 7:0 */
 208                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 209                         goto fail;
 210                 /* Write data 15:8 */
 211                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 212                         goto fail;
 213                 /* Write data 7:0 */
 214                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 215                         goto fail;
 216                 /* Write csum */
 217                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 218                         goto fail;
 219                 ixgbe_i2c_stop(hw);
 220                 return 0;
 221
 222 fail:
 223                 ixgbe_i2c_bus_clear(hw);
 224                 retry++;
 225                 if (retry < max_retry)
 226                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 227                 else
 228                         DEBUGOUT("I2C byte write combined error.\n");
 229         } while (retry < max_retry);
 230
 231         return IXGBE_ERR_I2C;
 232 }
 233
 234 /**
 235  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 236  *  @hw: pointer to the hardware structure
 237  *
 238  *  Initialize the function pointers.
 239  **/
 240 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 241 {
 242         struct ixgbe_phy_info *phy = &hw->phy;
 243
 244         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 245
 246         /* PHY */
 247         phy->ops.identify = ixgbe_identify_phy_generic;
 248         phy->ops.reset = ixgbe_reset_phy_generic;
 249         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 250         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 251         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 252         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 253         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 254         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 255         phy->ops.check_link = NULL;
 256         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 257         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 258         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 259         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 260         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 261         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 262         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 263         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 264         phy->sfp_type = ixgbe_sfp_type_unknown;
 265         phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic;
 266         phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic;
 267         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 268         return IXGBE_SUCCESS;
 269 }
 270
 271 /**
 272  *  ixgbe_identify_phy_generic - Get physical layer module
 273  *  @hw: pointer to hardware structure
 274  *
 275  *  Determines the physical layer module found on the current adapter.
 276  **/
 277 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 278 {
 279         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 280         u32 phy_addr;
 281         u16 ext_ability = 0;
 282
 283         DEBUGFUNC("ixgbe_identify_phy_generic");
 284
 285         if (!hw->phy.phy_semaphore_mask) {
 286                 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
 287                                                 IXGBE_STATUS_LAN_ID_1;
 288                 if (hw->phy.lan_id)
 289                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 290                 else
 291                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 292         }
 293
 294         if (hw->phy.type == ixgbe_phy_unknown) {
 295                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 296                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 297                                 hw->phy.addr = phy_addr;
 298                                 ixgbe_get_phy_id(hw);
 299                                 hw->phy.type =
 300                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 301
 302                                 if (hw->phy.type == ixgbe_phy_unknown) {
 303                                         hw->phy.ops.read_reg(hw,
 304                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 305                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 306                                                   &ext_ability);
 307                                         if (ext_ability &
 308                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 309                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 310                                                 hw->phy.type =
 311                                                          ixgbe_phy_cu_unknown;
 312                                         else
 313                                                 hw->phy.type =
 314                                                          ixgbe_phy_generic;
 315                                 }
 316
 317                                 status = IXGBE_SUCCESS;
 318                                 break;
 319                         }
 320                 }
 321
 322                 /* Certain media types do not have a phy so an address will not
 323                  * be found and the code will take this path.  Caller has to
 324                  * decide if it is an error or not.
 325                  */
 326                 if (status != IXGBE_SUCCESS) {
 327                         hw->phy.addr = 0;
 328                 }
 329         } else {
 330                 status = IXGBE_SUCCESS;
 331         }
 332
 333         return status;
 334 }
 335
 336 /**
 337  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 338  * @hw: pointer to the hardware structure
 339  *
 340  * This function checks the MMNGC.MNG_VETO bit to see if there are
 341  * any constraints on link from manageability.  For MAC's that don't
 342  * have this bit just return faluse since the link can not be blocked
 343  * via this method.
 344  **/
 345 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 346 {
 347         u32 mmngc;
 348
 349         DEBUGFUNC("ixgbe_check_reset_blocked");
 350
 351         /* If we don't have this bit, it can't be blocking */
 352         if (hw->mac.type == ixgbe_mac_82598EB)
 353                 return false;
 354
 355         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 356         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 357                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 358                               "MNG_VETO bit detected.\n");
 359                 return true;
 360         }
 361
 362         return false;
 363 }
 364
 365 /**
 366  *  ixgbe_validate_phy_addr - Determines phy address is valid
 367  *  @hw: pointer to hardware structure
 368  *
 369  **/
 370 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 371 {
 372         u16 phy_id = 0;
 373         bool valid = false;
 374
 375         DEBUGFUNC("ixgbe_validate_phy_addr");
 376
 377         hw->phy.addr = phy_addr;
 378         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 379                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 380
 381         if (phy_id != 0xFFFF && phy_id != 0x0)
 382                 valid = true;
 383
 384         return valid;
 385 }
 386
 387 /**
 388  *  ixgbe_get_phy_id - Get the phy type
 389  *  @hw: pointer to hardware structure
 390  *
 391  **/
 392 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 393 {
 394         u32 status;
 395         u16 phy_id_high = 0;
 396         u16 phy_id_low = 0;
 397
 398         DEBUGFUNC("ixgbe_get_phy_id");
 399
 400         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 401                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 402                                       &phy_id_high);
 403
 404         if (status == IXGBE_SUCCESS) {
 405                 hw->phy.id = (u32)(phy_id_high << 16);
 406                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 407                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 408                                               &phy_id_low);
 409                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 410                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 411         }
 412         return status;
 413 }
 414
 415 /**
 416  *  ixgbe_get_phy_type_from_id - Get the phy type
 417  *  @hw: pointer to hardware structure
 418  *
 419  **/
 420 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 421 {
 422         enum ixgbe_phy_type phy_type;
 423
 424         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 425
 426         switch (phy_id) {
 427         case TN1010_PHY_ID:
 428                 phy_type = ixgbe_phy_tn;
 429                 break;
 430         case X550_PHY_ID:
 431         case X540_PHY_ID:
 432                 phy_type = ixgbe_phy_aq;
 433                 break;
 434         case QT2022_PHY_ID:
 435                 phy_type = ixgbe_phy_qt;
 436                 break;
 437         case ATH_PHY_ID:
 438                 phy_type = ixgbe_phy_nl;
 439                 break;
 440         default:
 441                 phy_type = ixgbe_phy_unknown;
 442                 break;
 443         }
 444
 445         DEBUGOUT1("phy type found is %d\n", phy_type);
 446         return phy_type;
 447 }
 448
 449 /**
 450  *  ixgbe_reset_phy_generic - Performs a PHY reset
 451  *  @hw: pointer to hardware structure
 452  **/
 453 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 454 {
 455         u32 i;
 456         u16 ctrl = 0;
 457         s32 status = IXGBE_SUCCESS;
 458
 459         DEBUGFUNC("ixgbe_reset_phy_generic");
 460
 461         if (hw->phy.type == ixgbe_phy_unknown)
 462                 status = ixgbe_identify_phy_generic(hw);
 463
 464         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 465                 goto out;
 466
 467         /* Don't reset PHY if it's shut down due to overtemp. */
 468         if (!hw->phy.reset_if_overtemp &&
 469             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 470                 goto out;
 471
 472         /* Blocked by MNG FW so bail */
 473         if (ixgbe_check_reset_blocked(hw))
 474                 goto out;
 475
 476         /*
 477          * Perform soft PHY reset to the PHY_XS.
 478          * This will cause a soft reset to the PHY
 479          */
 480         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 481                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 482                               IXGBE_MDIO_PHY_XS_RESET);
 483
 484         /*
 485          * Poll for reset bit to self-clear indicating reset is complete.
 486          * Some PHYs could take up to 3 seconds to complete and need about
 487          * 1.7 usec delay after the reset is complete.
 488          */
 489         for (i = 0; i < 30; i++) {
 490                 msec_delay(100);
 491                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 492                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 493                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 494                         usec_delay(2);
 495                         break;
 496                 }
 497         }
 498
 499         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 500                 status = IXGBE_ERR_RESET_FAILED;
 501                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 502                              "PHY reset polling failed to complete.\n");
 503         }
 504
 505 out:
 506         return status;
 507 }
 508
 509 /**
 510  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 511  *  the SWFW lock
 512  *  @hw: pointer to hardware structure
 513  *  @reg_addr: 32 bit address of PHY register to read
 514  *  @phy_data: Pointer to read data from PHY register
 515  **/
 516 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 517                        u16 *phy_data)
 518 {
 519         u32 i, data, command;
 520
 521         /* Setup and write the address cycle command */
 522         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 523                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 524                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 525                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 526
 527         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 528
 529         /*
 530          * Check every 10 usec to see if the address cycle completed.
 531          * The MDI Command bit will clear when the operation is
 532          * complete
 533          */
 534         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 535                 usec_delay(10);
 536
 537                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 538                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 539                                 break;
 540         }
 541
 542
 543         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 544                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 545                 return IXGBE_ERR_PHY;
 546         }
 547
 548         /*
 549          * Address cycle complete, setup and write the read
 550          * command
 551          */
 552         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 553                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 554                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 555                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 556
 557         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 558
 559         /*
 560          * Check every 10 usec to see if the address cycle
 561          * completed. The MDI Command bit will clear when the
 562          * operation is complete
 563          */
 564         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 565                 usec_delay(10);
 566
 567                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 568                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 569                         break;
 570         }
 571
 572         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 573                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 574                 return IXGBE_ERR_PHY;
 575         }
 576
 577         /*
 578          * Read operation is complete.  Get the data
 579          * from MSRWD
 580          */
 581         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 582         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 583         *phy_data = (u16)(data);
 584
 585         return IXGBE_SUCCESS;
 586 }
 587
 588 /**
 589  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 590  *  using the SWFW lock - this function is needed in most cases
 591  *  @hw: pointer to hardware structure
 592  *  @reg_addr: 32 bit address of PHY register to read
 593  *  @phy_data: Pointer to read data from PHY register
 594  **/
 595 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 596                                u32 device_type, u16 *phy_data)
 597 {
 598         s32 status;
 599         u32 gssr = hw->phy.phy_semaphore_mask;
 600
 601         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 602
 603         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 604                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 605                                                 phy_data);
 606                 hw->mac.ops.release_swfw_sync(hw, gssr);
 607         } else {
 608                 status = IXGBE_ERR_SWFW_SYNC;
 609         }
 610
 611         return status;
 612 }
 613
 614 /**
 615  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 616  *  without SWFW lock
 617  *  @hw: pointer to hardware structure
 618  *  @reg_addr: 32 bit PHY register to write
 619  *  @device_type: 5 bit device type
 620  *  @phy_data: Data to write to the PHY register
 621  **/
 622 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 623                                 u32 device_type, u16 phy_data)
 624 {
 625         u32 i, command;
 626
 627         /* Put the data in the MDI single read and write data register*/
 628         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 629
 630         /* Setup and write the address cycle command */
 631         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 632                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 633                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 634                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 635
 636         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 637
 638         /*
 639          * Check every 10 usec to see if the address cycle completed.
 640          * The MDI Command bit will clear when the operation is
 641          * complete
 642          */
 643         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 644                 usec_delay(10);
 645
 646                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 647                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 648                         break;
 649         }
 650
 651         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 652                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 653                 return IXGBE_ERR_PHY;
 654         }
 655
 656         /*
 657          * Address cycle complete, setup and write the write
 658          * command
 659          */
 660         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 661                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 662                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 663                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 664
 665         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 666
 667         /*
 668          * Check every 10 usec to see if the address cycle
 669          * completed. The MDI Command bit will clear when the
 670          * operation is complete
 671          */
 672         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 673                 usec_delay(10);
 674
 675                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 676                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 677                         break;
 678         }
 679
 680         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 681                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 682                 return IXGBE_ERR_PHY;
 683         }
 684
 685         return IXGBE_SUCCESS;
 686 }
 687
 688 /**
 689  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 690  *  using SWFW lock- this function is needed in most cases
 691  *  @hw: pointer to hardware structure
 692  *  @reg_addr: 32 bit PHY register to write
 693  *  @device_type: 5 bit device type
 694  *  @phy_data: Data to write to the PHY register
 695  **/
 696 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 697                                 u32 device_type, u16 phy_data)
 698 {
 699         s32 status;
 700         u32 gssr = hw->phy.phy_semaphore_mask;
 701
 702         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 703
 704         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 705                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 706                                                  phy_data);
 707                 hw->mac.ops.release_swfw_sync(hw, gssr);
 708         } else {
 709                 status = IXGBE_ERR_SWFW_SYNC;
 710         }
 711
 712         return status;
 713 }
 714
 715 /**
 716  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 717  *  @hw: pointer to hardware structure
 718  *
 719  *  Restart auto-negotiation and PHY and waits for completion.
 720  **/
 721 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 722 {
 723         s32 status = IXGBE_SUCCESS;
 724         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 725         bool autoneg = false;
 726         ixgbe_link_speed speed;
 727
 728         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 729
 730         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 731
 732         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 733                 /* Set or unset auto-negotiation 10G advertisement */
 734                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 735                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 736                                      &autoneg_reg);
 737
 738                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 739                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 740                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 741
 742                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 743                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 744                                       autoneg_reg);
 745         }
 746
 747         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 748                 /* Set or unset auto-negotiation 1G advertisement */
 749                 hw->phy.ops.read_reg(hw,
 750                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 751                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 752                                      &autoneg_reg);
 753
 754                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 755                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 756                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 757
 758                 hw->phy.ops.write_reg(hw,
 759                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 760                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 761                                       autoneg_reg);
 762         }
 763
 764         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 765                 /* Set or unset auto-negotiation 100M advertisement */
 766                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 767                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 768                                      &autoneg_reg);
 769
 770                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 771                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 772                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 773                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 774
 775                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 776                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 777                                       autoneg_reg);
 778         }
 779
 780         /* Blocked by MNG FW so don't reset PHY */
 781         if (ixgbe_check_reset_blocked(hw))
 782                 return status;
 783
 784         /* Restart PHY auto-negotiation. */
 785         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 786                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 787
 788         autoneg_reg |= IXGBE_MII_RESTART;
 789
 790         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 791                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 792
 793         return status;
 794 }
 795
 796 /**
 797  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 798  *  @hw: pointer to hardware structure
 799  *  @speed: new link speed
 800  **/
 801 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 802                                        ixgbe_link_speed speed,
 803                                        bool autoneg_wait_to_complete)
 804 {
 805         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 806
 807         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 808
 809         /*
 810          * Clear autoneg_advertised and set new values based on input link
 811          * speed.
 812          */
 813         hw->phy.autoneg_advertised = 0;
 814
 815         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 816                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 817
 818         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 819                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 820
 821         if (speed & IXGBE_LINK_SPEED_100_FULL)
 822                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 823
 824         /* Setup link based on the new speed settings */
 825         hw->phy.ops.setup_link(hw);
 826
 827         return IXGBE_SUCCESS;
 828 }
 829
 830 /**
 831  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 832  *  @hw: pointer to hardware structure
 833  *  @speed: pointer to link speed
 834  *  @autoneg: boolean auto-negotiation value
 835  *
 836  *  Determines the link capabilities by reading the AUTOC register.
 837  **/
 838 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 839                                                ixgbe_link_speed *speed,
 840                                                bool *autoneg)
 841 {
 842         s32 status;
 843         u16 speed_ability;
 844
 845         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 846
 847         *speed = 0;
 848         *autoneg = true;
 849
 850         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 851                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 852                                       &speed_ability);
 853
 854         if (status == IXGBE_SUCCESS) {
 855                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 856                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 857                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 858                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 859                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 860                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 861         }
 862
 863         return status;
 864 }
 865
 866 /**
 867  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 868  *  @hw: pointer to hardware structure
 869  *
 870  *  Reads the VS1 register to determine if link is up and the current speed for
 871  *  the PHY.
 872  **/
 873 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 874                              bool *link_up)
 875 {
 876         s32 status = IXGBE_SUCCESS;
 877         u32 time_out;
 878         u32 max_time_out = 10;
 879         u16 phy_link = 0;
 880         u16 phy_speed = 0;
 881         u16 phy_data = 0;
 882
 883         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 884
 885         /* Initialize speed and link to default case */
 886         *link_up = false;
 887         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 888
 889         /*
 890          * Check current speed and link status of the PHY register.
 891          * This is a vendor specific register and may have to
 892          * be changed for other copper PHYs.
 893          */
 894         for (time_out = 0; time_out < max_time_out; time_out++) {
 895                 usec_delay(10);
 896                 status = hw->phy.ops.read_reg(hw,
 897                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 898                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 899                                         &phy_data);
 900                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 901                 phy_speed = phy_data &
 902                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 903                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 904                         *link_up = true;
 905                         if (phy_speed ==
 906                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 907                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 908                         break;
 909                 }
 910         }
 911
 912         return status;
 913 }
 914
 915 /**
 916  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
 917  *      @hw: pointer to hardware structure
 918  *
 919  *      Restart auto-negotiation and PHY and waits for completion.
 920  **/
 921 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 922 {
 923         s32 status = IXGBE_SUCCESS;
 924         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 925         bool autoneg = false;
 926         ixgbe_link_speed speed;
 927
 928         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
 929
 930         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 931
 932         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 933                 /* Set or unset auto-negotiation 10G advertisement */
 934                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 935                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 936                                      &autoneg_reg);
 937
 938                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 939                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 940                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 941
 942                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 943                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 944                                       autoneg_reg);
 945         }
 946
 947         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 948                 /* Set or unset auto-negotiation 1G advertisement */
 949                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 950                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 951                                      &autoneg_reg);
 952
 953                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 954                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 955                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 956
 957                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 958                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 959                                       autoneg_reg);
 960         }
 961
 962         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 963                 /* Set or unset auto-negotiation 100M advertisement */
 964                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 965                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 966                                      &autoneg_reg);
 967
 968                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
 969                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 970                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 971
 972                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 973                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 974                                       autoneg_reg);
 975         }
 976
 977         /* Blocked by MNG FW so don't reset PHY */
 978         if (ixgbe_check_reset_blocked(hw))
 979                 return status;
 980
 981         /* Restart PHY auto-negotiation. */
 982         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 983                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 984
 985         autoneg_reg |= IXGBE_MII_RESTART;
 986
 987         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 988                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 989
 990         return status;
 991 }
 992
 993 /**
 994  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 995  *  @hw: pointer to hardware structure
 996  *  @firmware_version: pointer to the PHY Firmware Version
 997  **/
 998 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 999                                        u16 *firmware_version)
1000 {
1001         s32 status;
1002
1003         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1004
1005         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1006                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1007                                       firmware_version);
1008
1009         return status;
1010 }
1011
1012 /**
1013  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1014  *  @hw: pointer to hardware structure
1015  *  @firmware_version: pointer to the PHY Firmware Version
1016  **/
1017 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1018                                            u16 *firmware_version)
1019 {
1020         s32 status;
1021
1022         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1023
1024         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1025                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1026                                       firmware_version);
1027
1028         return status;
1029 }
1030
1031 /**
1032  *  ixgbe_reset_phy_nl - Performs a PHY reset
1033  *  @hw: pointer to hardware structure
1034  **/
1035 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1036 {
1037         u16 phy_offset, control, eword, edata, block_crc;
1038         bool end_data = false;
1039         u16 list_offset, data_offset;
1040         u16 phy_data = 0;
1041         s32 ret_val = IXGBE_SUCCESS;
1042         u32 i;
1043
1044         DEBUGFUNC("ixgbe_reset_phy_nl");
1045
1046         /* Blocked by MNG FW so bail */
1047         if (ixgbe_check_reset_blocked(hw))
1048                 goto out;
1049
1050         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1051                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1052
1053         /* reset the PHY and poll for completion */
1054         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1055                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1056                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1057
1058         for (i = 0; i < 100; i++) {
1059                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1060                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1061                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1062                         break;
1063                 msec_delay(10);
1064         }
1065
1066         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1067                 DEBUGOUT("PHY reset did not complete.\n");
1068                 ret_val = IXGBE_ERR_PHY;
1069                 goto out;
1070         }
1071
1072         /* Get init offsets */
1073         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1074                                                       &data_offset);
1075         if (ret_val != IXGBE_SUCCESS)
1076                 goto out;
1077
1078         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1079         data_offset++;
1080         while (!end_data) {
1081                 /*
1082                  * Read control word from PHY init contents offset
1083                  */
1084                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1085                 if (ret_val)
1086                         goto err_eeprom;
1087                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1088                            IXGBE_CONTROL_SHIFT_NL;
1089                 edata = eword & IXGBE_DATA_MASK_NL;
1090                 switch (control) {
1091                 case IXGBE_DELAY_NL:
1092                         data_offset++;
1093                         DEBUGOUT1("DELAY: %d MS\n", edata);
1094                         msec_delay(edata);
1095                         break;
1096                 case IXGBE_DATA_NL:
1097                         DEBUGOUT("DATA:\n");
1098                         data_offset++;
1099                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1100                                                       &phy_offset);
1101                         if (ret_val)
1102                                 goto err_eeprom;
1103                         data_offset++;
1104                         for (i = 0; i < edata; i++) {
1105                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1106                                                               &eword);
1107                                 if (ret_val)
1108                                         goto err_eeprom;
1109                                 hw->phy.ops.write_reg(hw, phy_offset,
1110                                                       IXGBE_TWINAX_DEV, eword);
1111                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1112                                           phy_offset);
1113                                 data_offset++;
1114                                 phy_offset++;
1115                         }
1116                         break;
1117                 case IXGBE_CONTROL_NL:
1118                         data_offset++;
1119                         DEBUGOUT("CONTROL:\n");
1120                         if (edata == IXGBE_CONTROL_EOL_NL) {
1121                                 DEBUGOUT("EOL\n");
1122                                 end_data = true;
1123                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1124                                 DEBUGOUT("SOL\n");
1125                         } else {
1126                                 DEBUGOUT("Bad control value\n");
1127                                 ret_val = IXGBE_ERR_PHY;
1128                                 goto out;
1129                         }
1130                         break;
1131                 default:
1132                         DEBUGOUT("Bad control type\n");
1133                         ret_val = IXGBE_ERR_PHY;
1134                         goto out;
1135                 }
1136         }
1137
1138 out:
1139         return ret_val;
1140
1141 err_eeprom:
1142         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1143                       "eeprom read at offset %d failed", data_offset);
1144         return IXGBE_ERR_PHY;
1145 }
1146
1147 /**
1148  *  ixgbe_identify_module_generic - Identifies module type
1149  *  @hw: pointer to hardware structure
1150  *
1151  *  Determines HW type and calls appropriate function.
1152  **/
1153 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1154 {
1155         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1156
1157         DEBUGFUNC("ixgbe_identify_module_generic");
1158
1159         switch (hw->mac.ops.get_media_type(hw)) {
1160         case ixgbe_media_type_fiber:
1161                 status = ixgbe_identify_sfp_module_generic(hw);
1162                 break;
1163
1164         case ixgbe_media_type_fiber_qsfp:
1165                 status = ixgbe_identify_qsfp_module_generic(hw);
1166                 break;
1167
1168         default:
1169                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1170                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1171                 break;
1172         }
1173
1174         return status;
1175 }
1176
1177 /**
1178  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1179  *  @hw: pointer to hardware structure
1180  *
1181  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1182  **/
1183 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1184 {
1185         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1186         u32 vendor_oui = 0;
1187         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1188         u8 identifier = 0;
1189         u8 comp_codes_1g = 0;
1190         u8 comp_codes_10g = 0;
1191         u8 oui_bytes[3] = {0, 0, 0};
1192         u8 cable_tech = 0;
1193         u8 cable_spec = 0;
1194         u16 enforce_sfp = 0;
1195
1196         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1197
1198         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1199                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1200                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1201                 goto out;
1202         }
1203
1204         /* LAN ID is needed for I2C access */
1205         hw->mac.ops.set_lan_id(hw);
1206
1207         status = hw->phy.ops.read_i2c_eeprom(hw,
1208                                              IXGBE_SFF_IDENTIFIER,
1209                                              &identifier);
1210
1211         if (status != IXGBE_SUCCESS)
1212                 goto err_read_i2c_eeprom;
1213
1214         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1215                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1216                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1217         } else {
1218                 status = hw->phy.ops.read_i2c_eeprom(hw,
1219                                                      IXGBE_SFF_1GBE_COMP_CODES,
1220                                                      &comp_codes_1g);
1221
1222                 if (status != IXGBE_SUCCESS)
1223                         goto err_read_i2c_eeprom;
1224
1225                 status = hw->phy.ops.read_i2c_eeprom(hw,
1226                                                      IXGBE_SFF_10GBE_COMP_CODES,
1227                                                      &comp_codes_10g);
1228
1229                 if (status != IXGBE_SUCCESS)
1230                         goto err_read_i2c_eeprom;
1231                 status = hw->phy.ops.read_i2c_eeprom(hw,
1232                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1233                                                      &cable_tech);
1234
1235                 if (status != IXGBE_SUCCESS)
1236                         goto err_read_i2c_eeprom;
1237
1238                  /* ID Module
1239                   * =========
1240                   * 0   SFP_DA_CU
1241                   * 1   SFP_SR
1242                   * 2   SFP_LR
1243                   * 3   SFP_DA_CORE0 - 82599-specific
1244                   * 4   SFP_DA_CORE1 - 82599-specific
1245                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1246                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1247                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1248                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1249                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1250                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1251                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1252                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1253                   */
1254                 if (hw->mac.type == ixgbe_mac_82598EB) {
1255                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1256                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1257                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1258                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1259                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1260                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1261                         else
1262                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1263                 } else {
1264                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1265                                 if (hw->bus.lan_id == 0)
1266                                         hw->phy.sfp_type =
1267                                                      ixgbe_sfp_type_da_cu_core0;
1268                                 else
1269                                         hw->phy.sfp_type =
1270                                                      ixgbe_sfp_type_da_cu_core1;
1271                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1272                                 hw->phy.ops.read_i2c_eeprom(
1273                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1274                                                 &cable_spec);
1275                                 if (cable_spec &
1276                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1277                                         if (hw->bus.lan_id == 0)
1278                                                 hw->phy.sfp_type =
1279                                                 ixgbe_sfp_type_da_act_lmt_core0;
1280                                         else
1281                                                 hw->phy.sfp_type =
1282                                                 ixgbe_sfp_type_da_act_lmt_core1;
1283                                 } else {
1284                                         hw->phy.sfp_type =
1285                                                         ixgbe_sfp_type_unknown;
1286                                 }
1287                         } else if (comp_codes_10g &
1288                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1289                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1290                                 if (hw->bus.lan_id == 0)
1291                                         hw->phy.sfp_type =
1292                                                       ixgbe_sfp_type_srlr_core0;
1293                                 else
1294                                         hw->phy.sfp_type =
1295                                                       ixgbe_sfp_type_srlr_core1;
1296                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1297                                 if (hw->bus.lan_id == 0)
1298                                         hw->phy.sfp_type =
1299                                                 ixgbe_sfp_type_1g_cu_core0;
1300                                 else
1301                                         hw->phy.sfp_type =
1302                                                 ixgbe_sfp_type_1g_cu_core1;
1303                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1304                                 if (hw->bus.lan_id == 0)
1305                                         hw->phy.sfp_type =
1306                                                 ixgbe_sfp_type_1g_sx_core0;
1307                                 else
1308                                         hw->phy.sfp_type =
1309                                                 ixgbe_sfp_type_1g_sx_core1;
1310                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1311                                 if (hw->bus.lan_id == 0)
1312                                         hw->phy.sfp_type =
1313                                                 ixgbe_sfp_type_1g_lx_core0;
1314                                 else
1315                                         hw->phy.sfp_type =
1316                                                 ixgbe_sfp_type_1g_lx_core1;
1317                         } else {
1318                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1319                         }
1320                 }
1321
1322                 if (hw->phy.sfp_type != stored_sfp_type)
1323                         hw->phy.sfp_setup_needed = true;
1324
1325                 /* Determine if the SFP+ PHY is dual speed or not. */
1326                 hw->phy.multispeed_fiber = false;
1327                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1328                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1329                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1330                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1331                         hw->phy.multispeed_fiber = true;
1332
1333                 /* Determine PHY vendor */
1334                 if (hw->phy.type != ixgbe_phy_nl) {
1335                         hw->phy.id = identifier;
1336                         status = hw->phy.ops.read_i2c_eeprom(hw,
1337                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1338                                                     &oui_bytes[0]);
1339
1340                         if (status != IXGBE_SUCCESS)
1341                                 goto err_read_i2c_eeprom;
1342
1343                         status = hw->phy.ops.read_i2c_eeprom(hw,
1344                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1345                                                     &oui_bytes[1]);
1346
1347                         if (status != IXGBE_SUCCESS)
1348                                 goto err_read_i2c_eeprom;
1349
1350                         status = hw->phy.ops.read_i2c_eeprom(hw,
1351                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1352                                                     &oui_bytes[2]);
1353
1354                         if (status != IXGBE_SUCCESS)
1355                                 goto err_read_i2c_eeprom;
1356
1357                         vendor_oui =
1358                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1359                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1360                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1361
1362                         switch (vendor_oui) {
1363                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1364                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1365                                         hw->phy.type =
1366                                                     ixgbe_phy_sfp_passive_tyco;
1367                                 break;
1368                         case IXGBE_SFF_VENDOR_OUI_FTL:
1369                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1370                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1371                                 else
1372                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1373                                 break;
1374                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1375                                 hw->phy.type = ixgbe_phy_sfp_avago;
1376                                 break;
1377                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1378                                 hw->phy.type = ixgbe_phy_sfp_intel;
1379                                 break;
1380                         default:
1381                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1382                                         hw->phy.type =
1383                                                  ixgbe_phy_sfp_passive_unknown;
1384                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1385                                         hw->phy.type =
1386                                                 ixgbe_phy_sfp_active_unknown;
1387                                 else
1388                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1389                                 break;
1390                         }
1391                 }
1392
1393                 /* Allow any DA cable vendor */
1394                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1395                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1396                         status = IXGBE_SUCCESS;
1397                         goto out;
1398                 }
1399
1400                 /* Verify supported 1G SFP modules */
1401                 if (comp_codes_10g == 0 &&
1402                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1403                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1404                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1405                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1406                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1407                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1408                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1409                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1410                         goto out;
1411                 }
1412
1413                 /* Anything else 82598-based is supported */
1414                 if (hw->mac.type == ixgbe_mac_82598EB) {
1415                         status = IXGBE_SUCCESS;
1416                         goto out;
1417                 }
1418
1419                 ixgbe_get_device_caps(hw, &enforce_sfp);
1420                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1421                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1422                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1423                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1424                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1425                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1426                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1427                         /* Make sure we're a supported PHY type */
1428                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1429                                 status = IXGBE_SUCCESS;
1430                         } else {
1431                                 if (hw->allow_unsupported_sfp == true) {
1432                                         EWARN(hw, "WARNING: Intel (R) Network "
1433                                               "Connections are quality tested "
1434                                               "using Intel (R) Ethernet Optics."
1435                                               " Using untested modules is not "
1436                                               "supported and may cause unstable"
1437                                               " operation or damage to the "
1438                                               "module or the adapter. Intel "
1439                                               "Corporation is not responsible "
1440                                               "for any harm caused by using "
1441                                               "untested modules.\n", status);
1442                                         status = IXGBE_SUCCESS;
1443                                 } else {
1444                                         DEBUGOUT("SFP+ module not supported\n");
1445                                         hw->phy.type =
1446                                                 ixgbe_phy_sfp_unsupported;
1447                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1448                                 }
1449                         }
1450                 } else {
1451                         status = IXGBE_SUCCESS;
1452                 }
1453         }
1454
1455 out:
1456         return status;
1457
1458 err_read_i2c_eeprom:
1459         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1460         if (hw->phy.type != ixgbe_phy_nl) {
1461                 hw->phy.id = 0;
1462                 hw->phy.type = ixgbe_phy_unknown;
1463         }
1464         return IXGBE_ERR_SFP_NOT_PRESENT;
1465 }
1466
1467 /**
1468  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1469  *  @hw: pointer to hardware structure
1470  *
1471  *  Determines physical layer capabilities of the current SFP.
1472  */
1473 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1474 {
1475         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1476         u8 comp_codes_10g = 0;
1477         u8 comp_codes_1g = 0;
1478
1479         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1480
1481         hw->phy.ops.identify_sfp(hw);
1482         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1483                 return physical_layer;
1484
1485         switch (hw->phy.type) {
1486         case ixgbe_phy_sfp_passive_tyco:
1487         case ixgbe_phy_sfp_passive_unknown:
1488         case ixgbe_phy_qsfp_passive_unknown:
1489                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1490                 break;
1491         case ixgbe_phy_sfp_ftl_active:
1492         case ixgbe_phy_sfp_active_unknown:
1493         case ixgbe_phy_qsfp_active_unknown:
1494                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1495                 break;
1496         case ixgbe_phy_sfp_avago:
1497         case ixgbe_phy_sfp_ftl:
1498         case ixgbe_phy_sfp_intel:
1499         case ixgbe_phy_sfp_unknown:
1500                 hw->phy.ops.read_i2c_eeprom(hw,
1501                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1502                 hw->phy.ops.read_i2c_eeprom(hw,
1503                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1504                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1505                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1506                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1507                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1508                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1509                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1510                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1511                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1512                 break;
1513         case ixgbe_phy_qsfp_intel:
1514         case ixgbe_phy_qsfp_unknown:
1515                 hw->phy.ops.read_i2c_eeprom(hw,
1516                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1517                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1518                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1519                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1520                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1521                 break;
1522         default:
1523                 break;
1524         }
1525
1526         return physical_layer;
1527 }
1528
1529 /**
1530  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1531  *  @hw: pointer to hardware structure
1532  *
1533  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1534  **/
1535 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1536 {
1537         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1538         u32 vendor_oui = 0;
1539         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1540         u8 identifier = 0;
1541         u8 comp_codes_1g = 0;
1542         u8 comp_codes_10g = 0;
1543         u8 oui_bytes[3] = {0, 0, 0};
1544         u16 enforce_sfp = 0;
1545         u8 connector = 0;
1546         u8 cable_length = 0;
1547         u8 device_tech = 0;
1548         bool active_cable = false;
1549
1550         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1551
1552         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1553                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1554                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1555                 goto out;
1556         }
1557
1558         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1559                                              &identifier);
1560
1561         if (status != IXGBE_SUCCESS)
1562                 goto err_read_i2c_eeprom;
1563
1564         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1565                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1566                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1567                 goto out;
1568         }
1569
1570         hw->phy.id = identifier;
1571
1572         /* LAN ID is needed for sfp_type determination */
1573         hw->mac.ops.set_lan_id(hw);
1574
1575         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1576                                              &comp_codes_10g);
1577
1578         if (status != IXGBE_SUCCESS)
1579                 goto err_read_i2c_eeprom;
1580
1581         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1582                                              &comp_codes_1g);
1583
1584         if (status != IXGBE_SUCCESS)
1585                 goto err_read_i2c_eeprom;
1586
1587         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1588                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1589                 if (hw->bus.lan_id == 0)
1590                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1591                 else
1592                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1593         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1594                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1595                 if (hw->bus.lan_id == 0)
1596                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1597                 else
1598                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1599         } else {
1600                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1601                         active_cable = true;
1602
1603                 if (!active_cable) {
1604                         /* check for active DA cables that pre-date
1605                          * SFF-8436 v3.6 */
1606                         hw->phy.ops.read_i2c_eeprom(hw,
1607                                         IXGBE_SFF_QSFP_CONNECTOR,
1608                                         &connector);
1609
1610                         hw->phy.ops.read_i2c_eeprom(hw,
1611                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1612                                         &cable_length);
1613
1614                         hw->phy.ops.read_i2c_eeprom(hw,
1615                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1616                                         &device_tech);
1617
1618                         if ((connector ==
1619                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1620                             (cable_length > 0) &&
1621                             ((device_tech >> 4) ==
1622                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1623                                 active_cable = true;
1624                 }
1625
1626                 if (active_cable) {
1627                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1628                         if (hw->bus.lan_id == 0)
1629                                 hw->phy.sfp_type =
1630                                                 ixgbe_sfp_type_da_act_lmt_core0;
1631                         else
1632                                 hw->phy.sfp_type =
1633                                                 ixgbe_sfp_type_da_act_lmt_core1;
1634                 } else {
1635                         /* unsupported module type */
1636                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1637                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1638                         goto out;
1639                 }
1640         }
1641
1642         if (hw->phy.sfp_type != stored_sfp_type)
1643                 hw->phy.sfp_setup_needed = true;
1644
1645         /* Determine if the QSFP+ PHY is dual speed or not. */
1646         hw->phy.multispeed_fiber = false;
1647         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1648            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1649            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1650            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1651                 hw->phy.multispeed_fiber = true;
1652
1653         /* Determine PHY vendor for optical modules */
1654         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1655                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1656                 status = hw->phy.ops.read_i2c_eeprom(hw,
1657                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1658                                             &oui_bytes[0]);
1659
1660                 if (status != IXGBE_SUCCESS)
1661                         goto err_read_i2c_eeprom;
1662
1663                 status = hw->phy.ops.read_i2c_eeprom(hw,
1664                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1665                                             &oui_bytes[1]);
1666
1667                 if (status != IXGBE_SUCCESS)
1668                         goto err_read_i2c_eeprom;
1669
1670                 status = hw->phy.ops.read_i2c_eeprom(hw,
1671                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1672                                             &oui_bytes[2]);
1673
1674                 if (status != IXGBE_SUCCESS)
1675                         goto err_read_i2c_eeprom;
1676
1677                 vendor_oui =
1678                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1679                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1680                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1681
1682                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1683                         hw->phy.type = ixgbe_phy_qsfp_intel;
1684                 else
1685                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1686
1687                 ixgbe_get_device_caps(hw, &enforce_sfp);
1688                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1689                         /* Make sure we're a supported PHY type */
1690                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1691                                 status = IXGBE_SUCCESS;
1692                         } else {
1693                                 if (hw->allow_unsupported_sfp == true) {
1694                                         EWARN(hw, "WARNING: Intel (R) Network "
1695                                               "Connections are quality tested "
1696                                               "using Intel (R) Ethernet Optics."
1697                                               " Using untested modules is not "
1698                                               "supported and may cause unstable"
1699                                               " operation or damage to the "
1700                                               "module or the adapter. Intel "
1701                                               "Corporation is not responsible "
1702                                               "for any harm caused by using "
1703                                               "untested modules.\n", status);
1704                                         status = IXGBE_SUCCESS;
1705                                 } else {
1706                                         DEBUGOUT("QSFP module not supported\n");
1707                                         hw->phy.type =
1708                                                 ixgbe_phy_sfp_unsupported;
1709                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1710                                 }
1711                         }
1712                 } else {
1713                         status = IXGBE_SUCCESS;
1714                 }
1715         }
1716
1717 out:
1718         return status;
1719
1720 err_read_i2c_eeprom:
1721         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1722         hw->phy.id = 0;
1723         hw->phy.type = ixgbe_phy_unknown;
1724
1725         return IXGBE_ERR_SFP_NOT_PRESENT;
1726 }
1727
1728
1729 /**
1730  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1731  *  @hw: pointer to hardware structure
1732  *  @list_offset: offset to the SFP ID list
1733  *  @data_offset: offset to the SFP data block
1734  *
1735  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1736  *  so it returns the offsets to the phy init sequence block.
1737  **/
1738 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1739                                         u16 *list_offset,
1740                                         u16 *data_offset)
1741 {
1742         u16 sfp_id;
1743         u16 sfp_type = hw->phy.sfp_type;
1744
1745         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1746
1747         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1748                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1749
1750         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1751                 return IXGBE_ERR_SFP_NOT_PRESENT;
1752
1753         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1754             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1755                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1756
1757         /*
1758          * Limiting active cables and 1G Phys must be initialized as
1759          * SR modules
1760          */
1761         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1762             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1763             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1764             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1765                 sfp_type = ixgbe_sfp_type_srlr_core0;
1766         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1767                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1768                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1769                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1770                 sfp_type = ixgbe_sfp_type_srlr_core1;
1771
1772         /* Read offset to PHY init contents */
1773         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1774                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1775                               "eeprom read at offset %d failed",
1776                               IXGBE_PHY_INIT_OFFSET_NL);
1777                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1778         }
1779
1780         if ((!*list_offset) || (*list_offset == 0xFFFF))
1781                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1782
1783         /* Shift offset to first ID word */
1784         (*list_offset)++;
1785
1786         /*
1787          * Find the matching SFP ID in the EEPROM
1788          * and program the init sequence
1789          */
1790         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1791                 goto err_phy;
1792
1793         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1794                 if (sfp_id == sfp_type) {
1795                         (*list_offset)++;
1796                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1797                                 goto err_phy;
1798                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1799                                 DEBUGOUT("SFP+ module not supported\n");
1800                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1801                         } else {
1802                                 break;
1803                         }
1804                 } else {
1805                         (*list_offset) += 2;
1806                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1807                                 goto err_phy;
1808                 }
1809         }
1810
1811         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1812                 DEBUGOUT("No matching SFP+ module found\n");
1813                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1814         }
1815
1816         return IXGBE_SUCCESS;
1817
1818 err_phy:
1819         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1820                       "eeprom read at offset %d failed", *list_offset);
1821         return IXGBE_ERR_PHY;
1822 }
1823
1824 /**
1825  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1826  *  @hw: pointer to hardware structure
1827  *  @byte_offset: EEPROM byte offset to read
1828  *  @eeprom_data: value read
1829  *
1830  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1831  **/
1832 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1833                                   u8 *eeprom_data)
1834 {
1835         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1836
1837         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1838                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1839                                          eeprom_data);
1840 }
1841
1842 /**
1843  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1844  *  @hw: pointer to hardware structure
1845  *  @byte_offset: byte offset at address 0xA2
1846  *  @eeprom_data: value read
1847  *
1848  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1849  **/
1850 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1851                                           u8 *sff8472_data)
1852 {
1853         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1854                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1855                                          sff8472_data);
1856 }
1857
1858 /**
1859  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1860  *  @hw: pointer to hardware structure
1861  *  @byte_offset: EEPROM byte offset to write
1862  *  @eeprom_data: value to write
1863  *
1864  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1865  **/
1866 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1867                                    u8 eeprom_data)
1868 {
1869         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1870
1871         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1872                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1873                                           eeprom_data);
1874 }
1875
1876 /**
1877  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1878  * @hw: pointer to hardware structure
1879  * @offset: eeprom offset to be read
1880  * @addr: I2C address to be read
1881  */
1882 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1883 {
1884         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1885             offset == IXGBE_SFF_IDENTIFIER &&
1886             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1887                 return true;
1888         return false;
1889 }
1890
1891 /**
1892  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1893  *  @hw: pointer to hardware structure
1894  *  @byte_offset: byte offset to read
1895  *  @data: value read
1896  *
1897  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1898  *  a specified device address.
1899  **/
1900 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1901                                 u8 dev_addr, u8 *data)
1902 {
1903         s32 status;
1904         u32 max_retry = 10;
1905         u32 retry = 0;
1906         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1907         bool nack = 1;
1908         *data = 0;
1909
1910         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1911
1912         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
1913                 max_retry = IXGBE_SFP_DETECT_RETRIES;
1914
1915         do {
1916                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1917                         return IXGBE_ERR_SWFW_SYNC;
1918
1919                 ixgbe_i2c_start(hw);
1920
1921                 /* Device Address and write indication */
1922                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1923                 if (status != IXGBE_SUCCESS)
1924                         goto fail;
1925
1926                 status = ixgbe_get_i2c_ack(hw);
1927                 if (status != IXGBE_SUCCESS)
1928                         goto fail;
1929
1930                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1931                 if (status != IXGBE_SUCCESS)
1932                         goto fail;
1933
1934                 status = ixgbe_get_i2c_ack(hw);
1935                 if (status != IXGBE_SUCCESS)
1936                         goto fail;
1937
1938                 ixgbe_i2c_start(hw);
1939
1940                 /* Device Address and read indication */
1941                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1942                 if (status != IXGBE_SUCCESS)
1943                         goto fail;
1944
1945                 status = ixgbe_get_i2c_ack(hw);
1946                 if (status != IXGBE_SUCCESS)
1947                         goto fail;
1948
1949                 status = ixgbe_clock_in_i2c_byte(hw, data);
1950                 if (status != IXGBE_SUCCESS)
1951                         goto fail;
1952
1953                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1954                 if (status != IXGBE_SUCCESS)
1955                         goto fail;
1956
1957                 ixgbe_i2c_stop(hw);
1958                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1959                 return IXGBE_SUCCESS;
1960
1961 fail:
1962                 ixgbe_i2c_bus_clear(hw);
1963                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1964                 msec_delay(100);
1965                 retry++;
1966                 if (retry < max_retry)
1967                         DEBUGOUT("I2C byte read error - Retrying.\n");
1968                 else
1969                         DEBUGOUT("I2C byte read error.\n");
1970
1971         } while (retry < max_retry);
1972
1973         return status;
1974 }
1975
1976 /**
1977  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1978  *  @hw: pointer to hardware structure
1979  *  @byte_offset: byte offset to write
1980  *  @data: value to write
1981  *
1982  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1983  *  a specified device address.
1984  **/
1985 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1986                                  u8 dev_addr, u8 data)
1987 {
1988         s32 status = IXGBE_SUCCESS;
1989         u32 max_retry = 1;
1990         u32 retry = 0;
1991         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1992
1993         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1994
1995         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1996                 status = IXGBE_ERR_SWFW_SYNC;
1997                 goto write_byte_out;
1998         }
1999
2000         do {
2001                 ixgbe_i2c_start(hw);
2002
2003                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2004                 if (status != IXGBE_SUCCESS)
2005                         goto fail;
2006
2007                 status = ixgbe_get_i2c_ack(hw);
2008                 if (status != IXGBE_SUCCESS)
2009                         goto fail;
2010
2011                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2012                 if (status != IXGBE_SUCCESS)
2013                         goto fail;
2014
2015                 status = ixgbe_get_i2c_ack(hw);
2016                 if (status != IXGBE_SUCCESS)
2017                         goto fail;
2018
2019                 status = ixgbe_clock_out_i2c_byte(hw, data);
2020                 if (status != IXGBE_SUCCESS)
2021                         goto fail;
2022
2023                 status = ixgbe_get_i2c_ack(hw);
2024                 if (status != IXGBE_SUCCESS)
2025                         goto fail;
2026
2027                 ixgbe_i2c_stop(hw);
2028                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2029                 return IXGBE_SUCCESS;
2030
2031 fail:
2032                 ixgbe_i2c_bus_clear(hw);
2033                 retry++;
2034                 if (retry < max_retry)
2035                         DEBUGOUT("I2C byte write error - Retrying.\n");
2036                 else
2037                         DEBUGOUT("I2C byte write error.\n");
2038         } while (retry < max_retry);
2039
2040         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2041
2042 write_byte_out:
2043         return status;
2044 }
2045
2046 /**
2047  *  ixgbe_i2c_start - Sets I2C start condition
2048  *  @hw: pointer to hardware structure
2049  *
2050  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2051  *  Set bit-bang mode on X550 hardware.
2052  **/
2053 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2054 {
2055         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2056
2057         DEBUGFUNC("ixgbe_i2c_start");
2058
2059         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2060
2061         /* Start condition must begin with data and clock high */
2062         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2063         ixgbe_raise_i2c_clk(hw, &i2cctl);
2064
2065         /* Setup time for start condition (4.7us) */
2066         usec_delay(IXGBE_I2C_T_SU_STA);
2067
2068         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2069
2070         /* Hold time for start condition (4us) */
2071         usec_delay(IXGBE_I2C_T_HD_STA);
2072
2073         ixgbe_lower_i2c_clk(hw, &i2cctl);
2074
2075         /* Minimum low period of clock is 4.7 us */
2076         usec_delay(IXGBE_I2C_T_LOW);
2077
2078 }
2079
2080 /**
2081  *  ixgbe_i2c_stop - Sets I2C stop condition
2082  *  @hw: pointer to hardware structure
2083  *
2084  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2085  *  Disables bit-bang mode and negates data output enable on X550
2086  *  hardware.
2087  **/
2088 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2089 {
2090         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2091         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2092         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2093         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2094
2095         DEBUGFUNC("ixgbe_i2c_stop");
2096
2097         /* Stop condition must begin with data low and clock high */
2098         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2099         ixgbe_raise_i2c_clk(hw, &i2cctl);
2100
2101         /* Setup time for stop condition (4us) */
2102         usec_delay(IXGBE_I2C_T_SU_STO);
2103
2104         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2105
2106         /* bus free time between stop and start (4.7us)*/
2107         usec_delay(IXGBE_I2C_T_BUF);
2108
2109         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2110                 i2cctl &= ~bb_en_bit;
2111                 i2cctl |= data_oe_bit | clk_oe_bit;
2112                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2113                 IXGBE_WRITE_FLUSH(hw);
2114         }
2115 }
2116
2117 /**
2118  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2119  *  @hw: pointer to hardware structure
2120  *  @data: data byte to clock in
2121  *
2122  *  Clocks in one byte data via I2C data/clock
2123  **/
2124 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2125 {
2126         s32 i;
2127         bool bit = 0;
2128
2129         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2130
2131         *data = 0;
2132         for (i = 7; i >= 0; i--) {
2133                 ixgbe_clock_in_i2c_bit(hw, &bit);
2134                 *data |= bit << i;
2135         }
2136
2137         return IXGBE_SUCCESS;
2138 }
2139
2140 /**
2141  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2142  *  @hw: pointer to hardware structure
2143  *  @data: data byte clocked out
2144  *
2145  *  Clocks out one byte data via I2C data/clock
2146  **/
2147 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2148 {
2149         s32 status = IXGBE_SUCCESS;
2150         s32 i;
2151         u32 i2cctl;
2152         bool bit;
2153
2154         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2155
2156         for (i = 7; i >= 0; i--) {
2157                 bit = (data >> i) & 0x1;
2158                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2159
2160                 if (status != IXGBE_SUCCESS)
2161                         break;
2162         }
2163
2164         /* Release SDA line (set high) */
2165         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2166         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2167         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2168         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2169         IXGBE_WRITE_FLUSH(hw);
2170
2171         return status;
2172 }
2173
2174 /**
2175  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2176  *  @hw: pointer to hardware structure
2177  *
2178  *  Clocks in/out one bit via I2C data/clock
2179  **/
2180 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2181 {
2182         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2183         s32 status = IXGBE_SUCCESS;
2184         u32 i = 0;
2185         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2186         u32 timeout = 10;
2187         bool ack = 1;
2188
2189         DEBUGFUNC("ixgbe_get_i2c_ack");
2190
2191         if (data_oe_bit) {
2192                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2193                 i2cctl |= data_oe_bit;
2194                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2195                 IXGBE_WRITE_FLUSH(hw);
2196         }
2197         ixgbe_raise_i2c_clk(hw, &i2cctl);
2198
2199         /* Minimum high period of clock is 4us */
2200         usec_delay(IXGBE_I2C_T_HIGH);
2201
2202         /* Poll for ACK.  Note that ACK in I2C spec is
2203          * transition from 1 to 0 */
2204         for (i = 0; i < timeout; i++) {
2205                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2206                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2207
2208                 usec_delay(1);
2209                 if (!ack)
2210                         break;
2211         }
2212
2213         if (ack) {
2214                 DEBUGOUT("I2C ack was not received.\n");
2215                 status = IXGBE_ERR_I2C;
2216         }
2217
2218         ixgbe_lower_i2c_clk(hw, &i2cctl);
2219
2220         /* Minimum low period of clock is 4.7 us */
2221         usec_delay(IXGBE_I2C_T_LOW);
2222
2223         return status;
2224 }
2225
2226 /**
2227  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2228  *  @hw: pointer to hardware structure
2229  *  @data: read data value
2230  *
2231  *  Clocks in one bit via I2C data/clock
2232  **/
2233 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2234 {
2235         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2236         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2237
2238         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2239
2240         if (data_oe_bit) {
2241                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2242                 i2cctl |= data_oe_bit;
2243                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2244                 IXGBE_WRITE_FLUSH(hw);
2245         }
2246         ixgbe_raise_i2c_clk(hw, &i2cctl);
2247
2248         /* Minimum high period of clock is 4us */
2249         usec_delay(IXGBE_I2C_T_HIGH);
2250
2251         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2252         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2253
2254         ixgbe_lower_i2c_clk(hw, &i2cctl);
2255
2256         /* Minimum low period of clock is 4.7 us */
2257         usec_delay(IXGBE_I2C_T_LOW);
2258
2259         return IXGBE_SUCCESS;
2260 }
2261
2262 /**
2263  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2264  *  @hw: pointer to hardware structure
2265  *  @data: data value to write
2266  *
2267  *  Clocks out one bit via I2C data/clock
2268  **/
2269 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2270 {
2271         s32 status;
2272         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2273
2274         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2275
2276         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2277         if (status == IXGBE_SUCCESS) {
2278                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2279
2280                 /* Minimum high period of clock is 4us */
2281                 usec_delay(IXGBE_I2C_T_HIGH);
2282
2283                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2284
2285                 /* Minimum low period of clock is 4.7 us.
2286                  * This also takes care of the data hold time.
2287                  */
2288                 usec_delay(IXGBE_I2C_T_LOW);
2289         } else {
2290                 status = IXGBE_ERR_I2C;
2291                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2292                              "I2C data was not set to %X\n", data);
2293         }
2294
2295         return status;
2296 }
2297
2298 /**
2299  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2300  *  @hw: pointer to hardware structure
2301  *  @i2cctl: Current value of I2CCTL register
2302  *
2303  *  Raises the I2C clock line '0'->'1'
2304  *  Negates the I2C clock output enable on X550 hardware.
2305  **/
2306 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2307 {
2308         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2309         u32 i = 0;
2310         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2311         u32 i2cctl_r = 0;
2312
2313         DEBUGFUNC("ixgbe_raise_i2c_clk");
2314
2315         if (clk_oe_bit) {
2316                 *i2cctl |= clk_oe_bit;
2317                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2318         }
2319
2320         for (i = 0; i < timeout; i++) {
2321                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2322
2323                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2324                 IXGBE_WRITE_FLUSH(hw);
2325                 /* SCL rise time (1000ns) */
2326                 usec_delay(IXGBE_I2C_T_RISE);
2327
2328                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2329                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2330                         break;
2331         }
2332 }
2333
2334 /**
2335  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2336  *  @hw: pointer to hardware structure
2337  *  @i2cctl: Current value of I2CCTL register
2338  *
2339  *  Lowers the I2C clock line '1'->'0'
2340  *  Asserts the I2C clock output enable on X550 hardware.
2341  **/
2342 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2343 {
2344         DEBUGFUNC("ixgbe_lower_i2c_clk");
2345
2346         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2347         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2348
2349         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2350         IXGBE_WRITE_FLUSH(hw);
2351
2352         /* SCL fall time (300ns) */
2353         usec_delay(IXGBE_I2C_T_FALL);
2354 }
2355
2356 /**
2357  *  ixgbe_set_i2c_data - Sets the I2C data bit
2358  *  @hw: pointer to hardware structure
2359  *  @i2cctl: Current value of I2CCTL register
2360  *  @data: I2C data value (0 or 1) to set
2361  *
2362  *  Sets the I2C data bit
2363  *  Asserts the I2C data output enable on X550 hardware.
2364  **/
2365 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2366 {
2367         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2368         s32 status = IXGBE_SUCCESS;
2369
2370         DEBUGFUNC("ixgbe_set_i2c_data");
2371
2372         if (data)
2373                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2374         else
2375                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2376         *i2cctl &= ~data_oe_bit;
2377
2378         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2379         IXGBE_WRITE_FLUSH(hw);
2380
2381         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2382         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2383
2384         if (!data)      /* Can't verify data in this case */
2385                 return IXGBE_SUCCESS;
2386         if (data_oe_bit) {
2387                 *i2cctl |= data_oe_bit;
2388                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2389                 IXGBE_WRITE_FLUSH(hw);
2390         }
2391
2392         /* Verify data was set correctly */
2393         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2394         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2395                 status = IXGBE_ERR_I2C;
2396                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2397                              "Error - I2C data was not set to %X.\n",
2398                              data);
2399         }
2400
2401         return status;
2402 }
2403
2404 /**
2405  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2406  *  @hw: pointer to hardware structure
2407  *  @i2cctl: Current value of I2CCTL register
2408  *
2409  *  Returns the I2C data bit value
2410  *  Negates the I2C data output enable on X550 hardware.
2411  **/
2412 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2413 {
2414         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2415         bool data;
2416
2417         DEBUGFUNC("ixgbe_get_i2c_data");
2418
2419         if (data_oe_bit) {
2420                 *i2cctl |= data_oe_bit;
2421                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2422                 IXGBE_WRITE_FLUSH(hw);
2423                 usec_delay(IXGBE_I2C_T_FALL);
2424         }
2425
2426         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2427                 data = 1;
2428         else
2429                 data = 0;
2430
2431         return data;
2432 }
2433
2434 /**
2435  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2436  *  @hw: pointer to hardware structure
2437  *
2438  *  Clears the I2C bus by sending nine clock pulses.
2439  *  Used when data line is stuck low.
2440  **/
2441 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2442 {
2443         u32 i2cctl;
2444         u32 i;
2445
2446         DEBUGFUNC("ixgbe_i2c_bus_clear");
2447
2448         ixgbe_i2c_start(hw);
2449         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2450
2451         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2452
2453         for (i = 0; i < 9; i++) {
2454                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2455
2456                 /* Min high period of clock is 4us */
2457                 usec_delay(IXGBE_I2C_T_HIGH);
2458
2459                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2460
2461                 /* Min low period of clock is 4.7us*/
2462                 usec_delay(IXGBE_I2C_T_LOW);
2463         }
2464
2465         ixgbe_i2c_start(hw);
2466
2467         /* Put the i2c bus back to default state */
2468         ixgbe_i2c_stop(hw);
2469 }
2470
2471 /**
2472  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2473  *  @hw: pointer to hardware structure
2474  *
2475  *  Checks if the LASI temp alarm status was triggered due to overtemp
2476  **/
2477 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2478 {
2479         s32 status = IXGBE_SUCCESS;
2480         u16 phy_data = 0;
2481
2482         DEBUGFUNC("ixgbe_tn_check_overtemp");
2483
2484         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2485                 goto out;
2486
2487         /* Check that the LASI temp alarm status was triggered */
2488         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2489                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2490
2491         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2492                 goto out;
2493
2494         status = IXGBE_ERR_OVERTEMP;
2495         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2496 out:
2497         return status;
2498 }