lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37
  38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  50                                           u8 *sff8472_data);
  51
  52 /**
  53  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54  * @hw: pointer to the hardware structure
  55  * @byte: byte to send
  56  *
  57  * Returns an error code on error.
  58  */
  59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60 {
  61         s32 status;
  62
  63         status = ixgbe_clock_out_i2c_byte(hw, byte);
  64         if (status)
  65                 return status;
  66         return ixgbe_get_i2c_ack(hw);
  67 }
  68
  69 /**
  70  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71  * @hw: pointer to the hardware structure
  72  * @byte: pointer to a u8 to receive the byte
  73  *
  74  * Returns an error code on error.
  75  */
  76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77 {
  78         s32 status;
  79
  80         status = ixgbe_clock_in_i2c_byte(hw, byte);
  81         if (status)
  82                 return status;
  83         /* ACK */
  84         return ixgbe_clock_out_i2c_bit(hw, false);
  85 }
  86
  87 /**
  88  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  89  * @add1 - addend 1
  90  * @add2 - addend 2
  91  *
  92  * Returns one's complement 8-bit sum.
  93  */
  94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95 {
  96         u16 sum = add1 + add2;
  97
  98         sum = (sum & 0xFF) + (sum >> 8);
  99         return sum & 0xFF;
 100 }
 101
 102 /**
 103  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 104  * @hw: pointer to the hardware structure
 105  * @addr: I2C bus address to read from
 106  * @reg: I2C device register to read from
 107  * @val: pointer to location to receive read value
 108  *
 109  * Returns an error code on error.
 110  */
 111 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 112                                            u16 reg, u16 *val)
 113 {
 114         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 115         int max_retry = 10;
 116         int retry = 0;
 117         u8 csum_byte;
 118         u8 high_bits;
 119         u8 low_bits;
 120         u8 reg_high;
 121         u8 csum;
 122
 123         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 124         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 125         csum = ~csum;
 126         do {
 127                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 128                         return IXGBE_ERR_SWFW_SYNC;
 129                 ixgbe_i2c_start(hw);
 130                 /* Device Address and write indication */
 131                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 132                         goto fail;
 133                 /* Write bits 14:8 */
 134                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 135                         goto fail;
 136                 /* Write bits 7:0 */
 137                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 138                         goto fail;
 139                 /* Write csum */
 140                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 141                         goto fail;
 142                 /* Re-start condition */
 143                 ixgbe_i2c_start(hw);
 144                 /* Device Address and read indication */
 145                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 146                         goto fail;
 147                 /* Get upper bits */
 148                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 149                         goto fail;
 150                 /* Get low bits */
 151                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 152                         goto fail;
 153                 /* Get csum */
 154                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 155                         goto fail;
 156                 /* NACK */
 157                 if (ixgbe_clock_out_i2c_bit(hw, false))
 158                         goto fail;
 159                 ixgbe_i2c_stop(hw);
 160                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 161                 *val = (high_bits << 8) | low_bits;
 162                 return 0;
 163
 164 fail:
 165                 ixgbe_i2c_bus_clear(hw);
 166                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 167                 retry++;
 168                 if (retry < max_retry)
 169                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 170                 else
 171                         DEBUGOUT("I2C byte read combined error.\n");
 172         } while (retry < max_retry);
 173
 174         return IXGBE_ERR_I2C;
 175 }
 176
 177 /**
 178  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 179  * @hw: pointer to the hardware structure
 180  * @addr: I2C bus address to write to
 181  * @reg: I2C device register to write to
 182  * @val: value to write
 183  *
 184  * Returns an error code on error.
 185  */
 186 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 187                                             u8 addr, u16 reg, u16 val)
 188 {
 189         int max_retry = 1;
 190         int retry = 0;
 191         u8 reg_high;
 192         u8 csum;
 193
 194         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 195         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 196         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 197         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 198         csum = ~csum;
 199         do {
 200                 ixgbe_i2c_start(hw);
 201                 /* Device Address and write indication */
 202                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 203                         goto fail;
 204                 /* Write bits 14:8 */
 205                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 206                         goto fail;
 207                 /* Write bits 7:0 */
 208                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 209                         goto fail;
 210                 /* Write data 15:8 */
 211                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 212                         goto fail;
 213                 /* Write data 7:0 */
 214                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 215                         goto fail;
 216                 /* Write csum */
 217                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 218                         goto fail;
 219                 ixgbe_i2c_stop(hw);
 220                 return 0;
 221
 222 fail:
 223                 ixgbe_i2c_bus_clear(hw);
 224                 retry++;
 225                 if (retry < max_retry)
 226                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 227                 else
 228                         DEBUGOUT("I2C byte write combined error.\n");
 229         } while (retry < max_retry);
 230
 231         return IXGBE_ERR_I2C;
 232 }
 233
 234 /**
 235  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 236  *  @hw: pointer to the hardware structure
 237  *
 238  *  Initialize the function pointers.
 239  **/
 240 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 241 {
 242         struct ixgbe_phy_info *phy = &hw->phy;
 243
 244         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 245
 246         /* PHY */
 247         phy->ops.identify = ixgbe_identify_phy_generic;
 248         phy->ops.reset = ixgbe_reset_phy_generic;
 249         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 250         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 251         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 252         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 253         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 254         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 255         phy->ops.check_link = NULL;
 256         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 257         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 258         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 259         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 260         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 261         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 262         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 263         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 264         phy->sfp_type = ixgbe_sfp_type_unknown;
 265         phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic;
 266         phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic;
 267         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 268         return IXGBE_SUCCESS;
 269 }
 270
 271 /**
 272  *  ixgbe_identify_phy_generic - Get physical layer module
 273  *  @hw: pointer to hardware structure
 274  *
 275  *  Determines the physical layer module found on the current adapter.
 276  **/
 277 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 278 {
 279         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 280         u32 phy_addr;
 281         u16 ext_ability = 0;
 282
 283         DEBUGFUNC("ixgbe_identify_phy_generic");
 284
 285         if (!hw->phy.phy_semaphore_mask) {
 286                 if (hw->bus.lan_id)
 287                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 288                 else
 289                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 290         }
 291
 292         if (hw->phy.type == ixgbe_phy_unknown) {
 293                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 294                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 295                                 hw->phy.addr = phy_addr;
 296                                 ixgbe_get_phy_id(hw);
 297                                 hw->phy.type =
 298                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 299
 300                                 if (hw->phy.type == ixgbe_phy_unknown) {
 301                                         hw->phy.ops.read_reg(hw,
 302                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 303                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 304                                                   &ext_ability);
 305                                         if (ext_ability &
 306                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 307                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 308                                                 hw->phy.type =
 309                                                          ixgbe_phy_cu_unknown;
 310                                         else
 311                                                 hw->phy.type =
 312                                                          ixgbe_phy_generic;
 313                                 }
 314
 315                                 status = IXGBE_SUCCESS;
 316                                 break;
 317                         }
 318                 }
 319
 320                 /* Certain media types do not have a phy so an address will not
 321                  * be found and the code will take this path.  Caller has to
 322                  * decide if it is an error or not.
 323                  */
 324                 if (status != IXGBE_SUCCESS) {
 325                         hw->phy.addr = 0;
 326                 }
 327         } else {
 328                 status = IXGBE_SUCCESS;
 329         }
 330
 331         return status;
 332 }
 333
 334 /**
 335  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 336  * @hw: pointer to the hardware structure
 337  *
 338  * This function checks the MMNGC.MNG_VETO bit to see if there are
 339  * any constraints on link from manageability.  For MAC's that don't
 340  * have this bit just return faluse since the link can not be blocked
 341  * via this method.
 342  **/
 343 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 344 {
 345         u32 mmngc;
 346
 347         DEBUGFUNC("ixgbe_check_reset_blocked");
 348
 349         /* If we don't have this bit, it can't be blocking */
 350         if (hw->mac.type == ixgbe_mac_82598EB)
 351                 return false;
 352
 353         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 354         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 355                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 356                               "MNG_VETO bit detected.\n");
 357                 return true;
 358         }
 359
 360         return false;
 361 }
 362
 363 /**
 364  *  ixgbe_validate_phy_addr - Determines phy address is valid
 365  *  @hw: pointer to hardware structure
 366  *
 367  **/
 368 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 369 {
 370         u16 phy_id = 0;
 371         bool valid = false;
 372
 373         DEBUGFUNC("ixgbe_validate_phy_addr");
 374
 375         hw->phy.addr = phy_addr;
 376         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 377                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 378
 379         if (phy_id != 0xFFFF && phy_id != 0x0)
 380                 valid = true;
 381
 382         return valid;
 383 }
 384
 385 /**
 386  *  ixgbe_get_phy_id - Get the phy type
 387  *  @hw: pointer to hardware structure
 388  *
 389  **/
 390 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 391 {
 392         u32 status;
 393         u16 phy_id_high = 0;
 394         u16 phy_id_low = 0;
 395
 396         DEBUGFUNC("ixgbe_get_phy_id");
 397
 398         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 399                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 400                                       &phy_id_high);
 401
 402         if (status == IXGBE_SUCCESS) {
 403                 hw->phy.id = (u32)(phy_id_high << 16);
 404                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 405                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 406                                               &phy_id_low);
 407                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 408                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 409         }
 410         return status;
 411 }
 412
 413 /**
 414  *  ixgbe_get_phy_type_from_id - Get the phy type
 415  *  @hw: pointer to hardware structure
 416  *
 417  **/
 418 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 419 {
 420         enum ixgbe_phy_type phy_type;
 421
 422         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 423
 424         switch (phy_id) {
 425         case TN1010_PHY_ID:
 426                 phy_type = ixgbe_phy_tn;
 427                 break;
 428         case X550_PHY_ID:
 429         case X540_PHY_ID:
 430                 phy_type = ixgbe_phy_aq;
 431                 break;
 432         case QT2022_PHY_ID:
 433                 phy_type = ixgbe_phy_qt;
 434                 break;
 435         case ATH_PHY_ID:
 436                 phy_type = ixgbe_phy_nl;
 437                 break;
 438         default:
 439                 phy_type = ixgbe_phy_unknown;
 440                 break;
 441         }
 442
 443         DEBUGOUT1("phy type found is %d\n", phy_type);
 444         return phy_type;
 445 }
 446
 447 /**
 448  *  ixgbe_reset_phy_generic - Performs a PHY reset
 449  *  @hw: pointer to hardware structure
 450  **/
 451 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 452 {
 453         u32 i;
 454         u16 ctrl = 0;
 455         s32 status = IXGBE_SUCCESS;
 456
 457         DEBUGFUNC("ixgbe_reset_phy_generic");
 458
 459         if (hw->phy.type == ixgbe_phy_unknown)
 460                 status = ixgbe_identify_phy_generic(hw);
 461
 462         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 463                 goto out;
 464
 465         /* Don't reset PHY if it's shut down due to overtemp. */
 466         if (!hw->phy.reset_if_overtemp &&
 467             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 468                 goto out;
 469
 470         /* Blocked by MNG FW so bail */
 471         if (ixgbe_check_reset_blocked(hw))
 472                 goto out;
 473
 474         /*
 475          * Perform soft PHY reset to the PHY_XS.
 476          * This will cause a soft reset to the PHY
 477          */
 478         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 479                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 480                               IXGBE_MDIO_PHY_XS_RESET);
 481
 482         /*
 483          * Poll for reset bit to self-clear indicating reset is complete.
 484          * Some PHYs could take up to 3 seconds to complete and need about
 485          * 1.7 usec delay after the reset is complete.
 486          */
 487         for (i = 0; i < 30; i++) {
 488                 msec_delay(100);
 489                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 490                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 491                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 492                         usec_delay(2);
 493                         break;
 494                 }
 495         }
 496
 497         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 498                 status = IXGBE_ERR_RESET_FAILED;
 499                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 500                              "PHY reset polling failed to complete.\n");
 501         }
 502
 503 out:
 504         return status;
 505 }
 506
 507 /**
 508  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 509  *  the SWFW lock
 510  *  @hw: pointer to hardware structure
 511  *  @reg_addr: 32 bit address of PHY register to read
 512  *  @phy_data: Pointer to read data from PHY register
 513  **/
 514 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 515                        u16 *phy_data)
 516 {
 517         u32 i, data, command;
 518
 519         /* Setup and write the address cycle command */
 520         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 521                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 522                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 523                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 524
 525         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 526
 527         /*
 528          * Check every 10 usec to see if the address cycle completed.
 529          * The MDI Command bit will clear when the operation is
 530          * complete
 531          */
 532         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 533                 usec_delay(10);
 534
 535                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 536                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 537                                 break;
 538         }
 539
 540
 541         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 542                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 543                 return IXGBE_ERR_PHY;
 544         }
 545
 546         /*
 547          * Address cycle complete, setup and write the read
 548          * command
 549          */
 550         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 551                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 552                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 553                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 554
 555         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 556
 557         /*
 558          * Check every 10 usec to see if the address cycle
 559          * completed. The MDI Command bit will clear when the
 560          * operation is complete
 561          */
 562         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 563                 usec_delay(10);
 564
 565                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 566                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 567                         break;
 568         }
 569
 570         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 571                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 572                 return IXGBE_ERR_PHY;
 573         }
 574
 575         /*
 576          * Read operation is complete.  Get the data
 577          * from MSRWD
 578          */
 579         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 580         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 581         *phy_data = (u16)(data);
 582
 583         return IXGBE_SUCCESS;
 584 }
 585
 586 /**
 587  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 588  *  using the SWFW lock - this function is needed in most cases
 589  *  @hw: pointer to hardware structure
 590  *  @reg_addr: 32 bit address of PHY register to read
 591  *  @phy_data: Pointer to read data from PHY register
 592  **/
 593 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 594                                u32 device_type, u16 *phy_data)
 595 {
 596         s32 status;
 597         u32 gssr = hw->phy.phy_semaphore_mask;
 598
 599         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 600
 601         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 602                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 603                                                 phy_data);
 604                 hw->mac.ops.release_swfw_sync(hw, gssr);
 605         } else {
 606                 status = IXGBE_ERR_SWFW_SYNC;
 607         }
 608
 609         return status;
 610 }
 611
 612 /**
 613  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 614  *  without SWFW lock
 615  *  @hw: pointer to hardware structure
 616  *  @reg_addr: 32 bit PHY register to write
 617  *  @device_type: 5 bit device type
 618  *  @phy_data: Data to write to the PHY register
 619  **/
 620 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 621                                 u32 device_type, u16 phy_data)
 622 {
 623         u32 i, command;
 624
 625         /* Put the data in the MDI single read and write data register*/
 626         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 627
 628         /* Setup and write the address cycle command */
 629         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 630                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 631                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 632                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 633
 634         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 635
 636         /*
 637          * Check every 10 usec to see if the address cycle completed.
 638          * The MDI Command bit will clear when the operation is
 639          * complete
 640          */
 641         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 642                 usec_delay(10);
 643
 644                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 645                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 646                         break;
 647         }
 648
 649         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 650                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 651                 return IXGBE_ERR_PHY;
 652         }
 653
 654         /*
 655          * Address cycle complete, setup and write the write
 656          * command
 657          */
 658         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 659                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 660                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 661                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 662
 663         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 664
 665         /*
 666          * Check every 10 usec to see if the address cycle
 667          * completed. The MDI Command bit will clear when the
 668          * operation is complete
 669          */
 670         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 671                 usec_delay(10);
 672
 673                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 674                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 675                         break;
 676         }
 677
 678         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 679                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 680                 return IXGBE_ERR_PHY;
 681         }
 682
 683         return IXGBE_SUCCESS;
 684 }
 685
 686 /**
 687  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 688  *  using SWFW lock- this function is needed in most cases
 689  *  @hw: pointer to hardware structure
 690  *  @reg_addr: 32 bit PHY register to write
 691  *  @device_type: 5 bit device type
 692  *  @phy_data: Data to write to the PHY register
 693  **/
 694 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 695                                 u32 device_type, u16 phy_data)
 696 {
 697         s32 status;
 698         u32 gssr = hw->phy.phy_semaphore_mask;
 699
 700         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 701
 702         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 703                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 704                                                  phy_data);
 705                 hw->mac.ops.release_swfw_sync(hw, gssr);
 706         } else {
 707                 status = IXGBE_ERR_SWFW_SYNC;
 708         }
 709
 710         return status;
 711 }
 712
 713 /**
 714  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 715  *  @hw: pointer to hardware structure
 716  *
 717  *  Restart auto-negotiation and PHY and waits for completion.
 718  **/
 719 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 720 {
 721         s32 status = IXGBE_SUCCESS;
 722         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 723         bool autoneg = false;
 724         ixgbe_link_speed speed;
 725
 726         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 727
 728         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 729
 730         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 731                 /* Set or unset auto-negotiation 10G advertisement */
 732                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 733                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 734                                      &autoneg_reg);
 735
 736                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 737                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 738                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 739
 740                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 741                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 742                                       autoneg_reg);
 743         }
 744
 745         if (hw->mac.type == ixgbe_mac_X550) {
 746                 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
 747                         /* Set or unset auto-negotiation 1G advertisement */
 748                         hw->phy.ops.read_reg(hw,
 749                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 750                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 751                                 &autoneg_reg);
 752
 753                         autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 754                         if (hw->phy.autoneg_advertised &
 755                              IXGBE_LINK_SPEED_5GB_FULL)
 756                                 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 757
 758                         hw->phy.ops.write_reg(hw,
 759                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 760                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 761                                 autoneg_reg);
 762                 }
 763
 764                 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
 765                         /* Set or unset auto-negotiation 1G advertisement */
 766                         hw->phy.ops.read_reg(hw,
 767                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 768                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 769                                 &autoneg_reg);
 770
 771                         autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 772                         if (hw->phy.autoneg_advertised &
 773                             IXGBE_LINK_SPEED_2_5GB_FULL)
 774                                 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 775
 776                         hw->phy.ops.write_reg(hw,
 777                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 778                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 779                                 autoneg_reg);
 780                 }
 781         }
 782
 783         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 784                 /* Set or unset auto-negotiation 1G advertisement */
 785                 hw->phy.ops.read_reg(hw,
 786                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 787                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 788                                      &autoneg_reg);
 789
 790                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 791                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 792                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 793
 794                 hw->phy.ops.write_reg(hw,
 795                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 796                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 797                                       autoneg_reg);
 798         }
 799
 800         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 801                 /* Set or unset auto-negotiation 100M advertisement */
 802                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 803                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 804                                      &autoneg_reg);
 805
 806                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 807                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 808                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 809                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 810
 811                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 812                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 813                                       autoneg_reg);
 814         }
 815
 816         /* Blocked by MNG FW so don't reset PHY */
 817         if (ixgbe_check_reset_blocked(hw))
 818                 return status;
 819
 820         /* Restart PHY auto-negotiation. */
 821         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 822                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 823
 824         autoneg_reg |= IXGBE_MII_RESTART;
 825
 826         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 827                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 828
 829         return status;
 830 }
 831
 832 /**
 833  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 834  *  @hw: pointer to hardware structure
 835  *  @speed: new link speed
 836  **/
 837 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 838                                        ixgbe_link_speed speed,
 839                                        bool autoneg_wait_to_complete)
 840 {
 841         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 842
 843         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 844
 845         /*
 846          * Clear autoneg_advertised and set new values based on input link
 847          * speed.
 848          */
 849         hw->phy.autoneg_advertised = 0;
 850
 851         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 852                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 853
 854         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 855                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 856
 857         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 858                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 859
 860         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 861                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 862
 863         if (speed & IXGBE_LINK_SPEED_100_FULL)
 864                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 865
 866         /* Setup link based on the new speed settings */
 867         hw->phy.ops.setup_link(hw);
 868
 869         return IXGBE_SUCCESS;
 870 }
 871
 872 /**
 873  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 874  *  @hw: pointer to hardware structure
 875  *  @speed: pointer to link speed
 876  *  @autoneg: boolean auto-negotiation value
 877  *
 878  *  Determines the supported link capabilities by reading the PHY auto
 879  *  negotiation register.
 880  **/
 881 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 882                                                ixgbe_link_speed *speed,
 883                                                bool *autoneg)
 884 {
 885         s32 status;
 886         u16 speed_ability;
 887
 888         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 889
 890         *speed = 0;
 891         *autoneg = true;
 892
 893         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 894                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 895                                       &speed_ability);
 896
 897         if (status == IXGBE_SUCCESS) {
 898                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 899                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 900                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 901                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 902                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 903                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 904         }
 905
 906         /* Internal PHY does not support 100 Mbps */
 907         if (hw->mac.type == ixgbe_mac_X550EM_x)
 908                 *speed &= ~IXGBE_LINK_SPEED_100_FULL;
 909
 910         if (hw->mac.type == ixgbe_mac_X550) {
 911                 *speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
 912                 *speed |= IXGBE_LINK_SPEED_5GB_FULL;
 913         }
 914
 915         return status;
 916 }
 917
 918 /**
 919  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 920  *  @hw: pointer to hardware structure
 921  *
 922  *  Reads the VS1 register to determine if link is up and the current speed for
 923  *  the PHY.
 924  **/
 925 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 926                              bool *link_up)
 927 {
 928         s32 status = IXGBE_SUCCESS;
 929         u32 time_out;
 930         u32 max_time_out = 10;
 931         u16 phy_link = 0;
 932         u16 phy_speed = 0;
 933         u16 phy_data = 0;
 934
 935         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 936
 937         /* Initialize speed and link to default case */
 938         *link_up = false;
 939         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 940
 941         /*
 942          * Check current speed and link status of the PHY register.
 943          * This is a vendor specific register and may have to
 944          * be changed for other copper PHYs.
 945          */
 946         for (time_out = 0; time_out < max_time_out; time_out++) {
 947                 usec_delay(10);
 948                 status = hw->phy.ops.read_reg(hw,
 949                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 950                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 951                                         &phy_data);
 952                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 953                 phy_speed = phy_data &
 954                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 955                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 956                         *link_up = true;
 957                         if (phy_speed ==
 958                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 959                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 960                         break;
 961                 }
 962         }
 963
 964         return status;
 965 }
 966
 967 /**
 968  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
 969  *      @hw: pointer to hardware structure
 970  *
 971  *      Restart auto-negotiation and PHY and waits for completion.
 972  **/
 973 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 974 {
 975         s32 status = IXGBE_SUCCESS;
 976         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 977         bool autoneg = false;
 978         ixgbe_link_speed speed;
 979
 980         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
 981
 982         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 983
 984         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 985                 /* Set or unset auto-negotiation 10G advertisement */
 986                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 987                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 988                                      &autoneg_reg);
 989
 990                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 991                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 992                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 993
 994                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 995                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 996                                       autoneg_reg);
 997         }
 998
 999         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1000                 /* Set or unset auto-negotiation 1G advertisement */
1001                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1002                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1003                                      &autoneg_reg);
1004
1005                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1006                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1007                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1008
1009                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1010                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1011                                       autoneg_reg);
1012         }
1013
1014         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1015                 /* Set or unset auto-negotiation 100M advertisement */
1016                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1017                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1018                                      &autoneg_reg);
1019
1020                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1021                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1022                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1023
1024                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1025                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1026                                       autoneg_reg);
1027         }
1028
1029         /* Blocked by MNG FW so don't reset PHY */
1030         if (ixgbe_check_reset_blocked(hw))
1031                 return status;
1032
1033         /* Restart PHY auto-negotiation. */
1034         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1035                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1036
1037         autoneg_reg |= IXGBE_MII_RESTART;
1038
1039         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1040                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1041
1042         return status;
1043 }
1044
1045 /**
1046  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1047  *  @hw: pointer to hardware structure
1048  *  @firmware_version: pointer to the PHY Firmware Version
1049  **/
1050 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1051                                        u16 *firmware_version)
1052 {
1053         s32 status;
1054
1055         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1056
1057         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1058                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1059                                       firmware_version);
1060
1061         return status;
1062 }
1063
1064 /**
1065  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1066  *  @hw: pointer to hardware structure
1067  *  @firmware_version: pointer to the PHY Firmware Version
1068  **/
1069 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1070                                            u16 *firmware_version)
1071 {
1072         s32 status;
1073
1074         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1075
1076         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1077                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1078                                       firmware_version);
1079
1080         return status;
1081 }
1082
1083 /**
1084  *  ixgbe_reset_phy_nl - Performs a PHY reset
1085  *  @hw: pointer to hardware structure
1086  **/
1087 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1088 {
1089         u16 phy_offset, control, eword, edata, block_crc;
1090         bool end_data = false;
1091         u16 list_offset, data_offset;
1092         u16 phy_data = 0;
1093         s32 ret_val = IXGBE_SUCCESS;
1094         u32 i;
1095
1096         DEBUGFUNC("ixgbe_reset_phy_nl");
1097
1098         /* Blocked by MNG FW so bail */
1099         if (ixgbe_check_reset_blocked(hw))
1100                 goto out;
1101
1102         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1103                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1104
1105         /* reset the PHY and poll for completion */
1106         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1107                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1108                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1109
1110         for (i = 0; i < 100; i++) {
1111                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1112                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1113                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1114                         break;
1115                 msec_delay(10);
1116         }
1117
1118         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1119                 DEBUGOUT("PHY reset did not complete.\n");
1120                 ret_val = IXGBE_ERR_PHY;
1121                 goto out;
1122         }
1123
1124         /* Get init offsets */
1125         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1126                                                       &data_offset);
1127         if (ret_val != IXGBE_SUCCESS)
1128                 goto out;
1129
1130         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1131         data_offset++;
1132         while (!end_data) {
1133                 /*
1134                  * Read control word from PHY init contents offset
1135                  */
1136                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1137                 if (ret_val)
1138                         goto err_eeprom;
1139                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1140                            IXGBE_CONTROL_SHIFT_NL;
1141                 edata = eword & IXGBE_DATA_MASK_NL;
1142                 switch (control) {
1143                 case IXGBE_DELAY_NL:
1144                         data_offset++;
1145                         DEBUGOUT1("DELAY: %d MS\n", edata);
1146                         msec_delay(edata);
1147                         break;
1148                 case IXGBE_DATA_NL:
1149                         DEBUGOUT("DATA:\n");
1150                         data_offset++;
1151                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1152                                                       &phy_offset);
1153                         if (ret_val)
1154                                 goto err_eeprom;
1155                         data_offset++;
1156                         for (i = 0; i < edata; i++) {
1157                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1158                                                               &eword);
1159                                 if (ret_val)
1160                                         goto err_eeprom;
1161                                 hw->phy.ops.write_reg(hw, phy_offset,
1162                                                       IXGBE_TWINAX_DEV, eword);
1163                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1164                                           phy_offset);
1165                                 data_offset++;
1166                                 phy_offset++;
1167                         }
1168                         break;
1169                 case IXGBE_CONTROL_NL:
1170                         data_offset++;
1171                         DEBUGOUT("CONTROL:\n");
1172                         if (edata == IXGBE_CONTROL_EOL_NL) {
1173                                 DEBUGOUT("EOL\n");
1174                                 end_data = true;
1175                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1176                                 DEBUGOUT("SOL\n");
1177                         } else {
1178                                 DEBUGOUT("Bad control value\n");
1179                                 ret_val = IXGBE_ERR_PHY;
1180                                 goto out;
1181                         }
1182                         break;
1183                 default:
1184                         DEBUGOUT("Bad control type\n");
1185                         ret_val = IXGBE_ERR_PHY;
1186                         goto out;
1187                 }
1188         }
1189
1190 out:
1191         return ret_val;
1192
1193 err_eeprom:
1194         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1195                       "eeprom read at offset %d failed", data_offset);
1196         return IXGBE_ERR_PHY;
1197 }
1198
1199 /**
1200  *  ixgbe_identify_module_generic - Identifies module type
1201  *  @hw: pointer to hardware structure
1202  *
1203  *  Determines HW type and calls appropriate function.
1204  **/
1205 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1206 {
1207         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1208
1209         DEBUGFUNC("ixgbe_identify_module_generic");
1210
1211         switch (hw->mac.ops.get_media_type(hw)) {
1212         case ixgbe_media_type_fiber:
1213                 status = ixgbe_identify_sfp_module_generic(hw);
1214                 break;
1215
1216         case ixgbe_media_type_fiber_qsfp:
1217                 status = ixgbe_identify_qsfp_module_generic(hw);
1218                 break;
1219
1220         default:
1221                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1222                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1223                 break;
1224         }
1225
1226         return status;
1227 }
1228
1229 /**
1230  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1231  *  @hw: pointer to hardware structure
1232  *
1233  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1234  **/
1235 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1236 {
1237         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1238         u32 vendor_oui = 0;
1239         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1240         u8 identifier = 0;
1241         u8 comp_codes_1g = 0;
1242         u8 comp_codes_10g = 0;
1243         u8 oui_bytes[3] = {0, 0, 0};
1244         u8 cable_tech = 0;
1245         u8 cable_spec = 0;
1246         u16 enforce_sfp = 0;
1247
1248         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1249
1250         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1251                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1252                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1253                 goto out;
1254         }
1255
1256         /* LAN ID is needed for I2C access */
1257         hw->mac.ops.set_lan_id(hw);
1258
1259         status = hw->phy.ops.read_i2c_eeprom(hw,
1260                                              IXGBE_SFF_IDENTIFIER,
1261                                              &identifier);
1262
1263         if (status != IXGBE_SUCCESS)
1264                 goto err_read_i2c_eeprom;
1265
1266         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1267                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1268                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1269         } else {
1270                 status = hw->phy.ops.read_i2c_eeprom(hw,
1271                                                      IXGBE_SFF_1GBE_COMP_CODES,
1272                                                      &comp_codes_1g);
1273
1274                 if (status != IXGBE_SUCCESS)
1275                         goto err_read_i2c_eeprom;
1276
1277                 status = hw->phy.ops.read_i2c_eeprom(hw,
1278                                                      IXGBE_SFF_10GBE_COMP_CODES,
1279                                                      &comp_codes_10g);
1280
1281                 if (status != IXGBE_SUCCESS)
1282                         goto err_read_i2c_eeprom;
1283                 status = hw->phy.ops.read_i2c_eeprom(hw,
1284                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1285                                                      &cable_tech);
1286
1287                 if (status != IXGBE_SUCCESS)
1288                         goto err_read_i2c_eeprom;
1289
1290                  /* ID Module
1291                   * =========
1292                   * 0   SFP_DA_CU
1293                   * 1   SFP_SR
1294                   * 2   SFP_LR
1295                   * 3   SFP_DA_CORE0 - 82599-specific
1296                   * 4   SFP_DA_CORE1 - 82599-specific
1297                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1298                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1299                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1300                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1301                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1302                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1303                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1304                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1305                   */
1306                 if (hw->mac.type == ixgbe_mac_82598EB) {
1307                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1308                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1309                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1310                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1311                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1312                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1313                         else
1314                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1315                 } else {
1316                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1317                                 if (hw->bus.lan_id == 0)
1318                                         hw->phy.sfp_type =
1319                                                      ixgbe_sfp_type_da_cu_core0;
1320                                 else
1321                                         hw->phy.sfp_type =
1322                                                      ixgbe_sfp_type_da_cu_core1;
1323                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1324                                 hw->phy.ops.read_i2c_eeprom(
1325                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1326                                                 &cable_spec);
1327                                 if (cable_spec &
1328                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1329                                         if (hw->bus.lan_id == 0)
1330                                                 hw->phy.sfp_type =
1331                                                 ixgbe_sfp_type_da_act_lmt_core0;
1332                                         else
1333                                                 hw->phy.sfp_type =
1334                                                 ixgbe_sfp_type_da_act_lmt_core1;
1335                                 } else {
1336                                         hw->phy.sfp_type =
1337                                                         ixgbe_sfp_type_unknown;
1338                                 }
1339                         } else if (comp_codes_10g &
1340                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1341                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1342                                 if (hw->bus.lan_id == 0)
1343                                         hw->phy.sfp_type =
1344                                                       ixgbe_sfp_type_srlr_core0;
1345                                 else
1346                                         hw->phy.sfp_type =
1347                                                       ixgbe_sfp_type_srlr_core1;
1348                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1349                                 if (hw->bus.lan_id == 0)
1350                                         hw->phy.sfp_type =
1351                                                 ixgbe_sfp_type_1g_cu_core0;
1352                                 else
1353                                         hw->phy.sfp_type =
1354                                                 ixgbe_sfp_type_1g_cu_core1;
1355                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1356                                 if (hw->bus.lan_id == 0)
1357                                         hw->phy.sfp_type =
1358                                                 ixgbe_sfp_type_1g_sx_core0;
1359                                 else
1360                                         hw->phy.sfp_type =
1361                                                 ixgbe_sfp_type_1g_sx_core1;
1362                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1363                                 if (hw->bus.lan_id == 0)
1364                                         hw->phy.sfp_type =
1365                                                 ixgbe_sfp_type_1g_lx_core0;
1366                                 else
1367                                         hw->phy.sfp_type =
1368                                                 ixgbe_sfp_type_1g_lx_core1;
1369                         } else {
1370                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1371                         }
1372                 }
1373
1374                 if (hw->phy.sfp_type != stored_sfp_type)
1375                         hw->phy.sfp_setup_needed = true;
1376
1377                 /* Determine if the SFP+ PHY is dual speed or not. */
1378                 hw->phy.multispeed_fiber = false;
1379                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1380                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1381                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1382                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1383                         hw->phy.multispeed_fiber = true;
1384
1385                 /* Determine PHY vendor */
1386                 if (hw->phy.type != ixgbe_phy_nl) {
1387                         hw->phy.id = identifier;
1388                         status = hw->phy.ops.read_i2c_eeprom(hw,
1389                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1390                                                     &oui_bytes[0]);
1391
1392                         if (status != IXGBE_SUCCESS)
1393                                 goto err_read_i2c_eeprom;
1394
1395                         status = hw->phy.ops.read_i2c_eeprom(hw,
1396                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1397                                                     &oui_bytes[1]);
1398
1399                         if (status != IXGBE_SUCCESS)
1400                                 goto err_read_i2c_eeprom;
1401
1402                         status = hw->phy.ops.read_i2c_eeprom(hw,
1403                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1404                                                     &oui_bytes[2]);
1405
1406                         if (status != IXGBE_SUCCESS)
1407                                 goto err_read_i2c_eeprom;
1408
1409                         vendor_oui =
1410                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1411                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1412                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1413
1414                         switch (vendor_oui) {
1415                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1416                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1417                                         hw->phy.type =
1418                                                     ixgbe_phy_sfp_passive_tyco;
1419                                 break;
1420                         case IXGBE_SFF_VENDOR_OUI_FTL:
1421                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1422                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1423                                 else
1424                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1425                                 break;
1426                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1427                                 hw->phy.type = ixgbe_phy_sfp_avago;
1428                                 break;
1429                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1430                                 hw->phy.type = ixgbe_phy_sfp_intel;
1431                                 break;
1432                         default:
1433                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1434                                         hw->phy.type =
1435                                                  ixgbe_phy_sfp_passive_unknown;
1436                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1437                                         hw->phy.type =
1438                                                 ixgbe_phy_sfp_active_unknown;
1439                                 else
1440                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1441                                 break;
1442                         }
1443                 }
1444
1445                 /* Allow any DA cable vendor */
1446                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1447                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1448                         status = IXGBE_SUCCESS;
1449                         goto out;
1450                 }
1451
1452                 /* Verify supported 1G SFP modules */
1453                 if (comp_codes_10g == 0 &&
1454                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1455                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1456                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1457                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1458                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1459                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1460                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1461                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1462                         goto out;
1463                 }
1464
1465                 /* Anything else 82598-based is supported */
1466                 if (hw->mac.type == ixgbe_mac_82598EB) {
1467                         status = IXGBE_SUCCESS;
1468                         goto out;
1469                 }
1470
1471                 ixgbe_get_device_caps(hw, &enforce_sfp);
1472                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1473                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1474                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1475                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1476                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1477                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1478                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1479                         /* Make sure we're a supported PHY type */
1480                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1481                                 status = IXGBE_SUCCESS;
1482                         } else {
1483                                 if (hw->allow_unsupported_sfp == true) {
1484                                         EWARN(hw, "WARNING: Intel (R) Network "
1485                                               "Connections are quality tested "
1486                                               "using Intel (R) Ethernet Optics."
1487                                               " Using untested modules is not "
1488                                               "supported and may cause unstable"
1489                                               " operation or damage to the "
1490                                               "module or the adapter. Intel "
1491                                               "Corporation is not responsible "
1492                                               "for any harm caused by using "
1493                                               "untested modules.\n", status);
1494                                         status = IXGBE_SUCCESS;
1495                                 } else {
1496                                         DEBUGOUT("SFP+ module not supported\n");
1497                                         hw->phy.type =
1498                                                 ixgbe_phy_sfp_unsupported;
1499                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1500                                 }
1501                         }
1502                 } else {
1503                         status = IXGBE_SUCCESS;
1504                 }
1505         }
1506
1507 out:
1508         return status;
1509
1510 err_read_i2c_eeprom:
1511         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1512         if (hw->phy.type != ixgbe_phy_nl) {
1513                 hw->phy.id = 0;
1514                 hw->phy.type = ixgbe_phy_unknown;
1515         }
1516         return IXGBE_ERR_SFP_NOT_PRESENT;
1517 }
1518
1519 /**
1520  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1521  *  @hw: pointer to hardware structure
1522  *
1523  *  Determines physical layer capabilities of the current SFP.
1524  */
1525 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1526 {
1527         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1528         u8 comp_codes_10g = 0;
1529         u8 comp_codes_1g = 0;
1530
1531         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1532
1533         hw->phy.ops.identify_sfp(hw);
1534         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1535                 return physical_layer;
1536
1537         switch (hw->phy.type) {
1538         case ixgbe_phy_sfp_passive_tyco:
1539         case ixgbe_phy_sfp_passive_unknown:
1540         case ixgbe_phy_qsfp_passive_unknown:
1541                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1542                 break;
1543         case ixgbe_phy_sfp_ftl_active:
1544         case ixgbe_phy_sfp_active_unknown:
1545         case ixgbe_phy_qsfp_active_unknown:
1546                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1547                 break;
1548         case ixgbe_phy_sfp_avago:
1549         case ixgbe_phy_sfp_ftl:
1550         case ixgbe_phy_sfp_intel:
1551         case ixgbe_phy_sfp_unknown:
1552                 hw->phy.ops.read_i2c_eeprom(hw,
1553                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1554                 hw->phy.ops.read_i2c_eeprom(hw,
1555                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1556                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1557                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1558                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1559                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1560                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1561                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1562                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1563                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1564                 break;
1565         case ixgbe_phy_qsfp_intel:
1566         case ixgbe_phy_qsfp_unknown:
1567                 hw->phy.ops.read_i2c_eeprom(hw,
1568                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1569                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1570                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1571                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1572                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1573                 break;
1574         default:
1575                 break;
1576         }
1577
1578         return physical_layer;
1579 }
1580
1581 /**
1582  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1583  *  @hw: pointer to hardware structure
1584  *
1585  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1586  **/
1587 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1588 {
1589         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1590         u32 vendor_oui = 0;
1591         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1592         u8 identifier = 0;
1593         u8 comp_codes_1g = 0;
1594         u8 comp_codes_10g = 0;
1595         u8 oui_bytes[3] = {0, 0, 0};
1596         u16 enforce_sfp = 0;
1597         u8 connector = 0;
1598         u8 cable_length = 0;
1599         u8 device_tech = 0;
1600         bool active_cable = false;
1601
1602         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1603
1604         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1605                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1606                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1607                 goto out;
1608         }
1609
1610         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1611                                              &identifier);
1612
1613         if (status != IXGBE_SUCCESS)
1614                 goto err_read_i2c_eeprom;
1615
1616         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1617                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1618                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1619                 goto out;
1620         }
1621
1622         hw->phy.id = identifier;
1623
1624         /* LAN ID is needed for sfp_type determination */
1625         hw->mac.ops.set_lan_id(hw);
1626
1627         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1628                                              &comp_codes_10g);
1629
1630         if (status != IXGBE_SUCCESS)
1631                 goto err_read_i2c_eeprom;
1632
1633         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1634                                              &comp_codes_1g);
1635
1636         if (status != IXGBE_SUCCESS)
1637                 goto err_read_i2c_eeprom;
1638
1639         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1640                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1641                 if (hw->bus.lan_id == 0)
1642                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1643                 else
1644                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1645         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1646                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1647                 if (hw->bus.lan_id == 0)
1648                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1649                 else
1650                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1651         } else {
1652                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1653                         active_cable = true;
1654
1655                 if (!active_cable) {
1656                         /* check for active DA cables that pre-date
1657                          * SFF-8436 v3.6 */
1658                         hw->phy.ops.read_i2c_eeprom(hw,
1659                                         IXGBE_SFF_QSFP_CONNECTOR,
1660                                         &connector);
1661
1662                         hw->phy.ops.read_i2c_eeprom(hw,
1663                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1664                                         &cable_length);
1665
1666                         hw->phy.ops.read_i2c_eeprom(hw,
1667                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1668                                         &device_tech);
1669
1670                         if ((connector ==
1671                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1672                             (cable_length > 0) &&
1673                             ((device_tech >> 4) ==
1674                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1675                                 active_cable = true;
1676                 }
1677
1678                 if (active_cable) {
1679                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1680                         if (hw->bus.lan_id == 0)
1681                                 hw->phy.sfp_type =
1682                                                 ixgbe_sfp_type_da_act_lmt_core0;
1683                         else
1684                                 hw->phy.sfp_type =
1685                                                 ixgbe_sfp_type_da_act_lmt_core1;
1686                 } else {
1687                         /* unsupported module type */
1688                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1689                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1690                         goto out;
1691                 }
1692         }
1693
1694         if (hw->phy.sfp_type != stored_sfp_type)
1695                 hw->phy.sfp_setup_needed = true;
1696
1697         /* Determine if the QSFP+ PHY is dual speed or not. */
1698         hw->phy.multispeed_fiber = false;
1699         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1700            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1701            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1702            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1703                 hw->phy.multispeed_fiber = true;
1704
1705         /* Determine PHY vendor for optical modules */
1706         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1707                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1708                 status = hw->phy.ops.read_i2c_eeprom(hw,
1709                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1710                                             &oui_bytes[0]);
1711
1712                 if (status != IXGBE_SUCCESS)
1713                         goto err_read_i2c_eeprom;
1714
1715                 status = hw->phy.ops.read_i2c_eeprom(hw,
1716                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1717                                             &oui_bytes[1]);
1718
1719                 if (status != IXGBE_SUCCESS)
1720                         goto err_read_i2c_eeprom;
1721
1722                 status = hw->phy.ops.read_i2c_eeprom(hw,
1723                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1724                                             &oui_bytes[2]);
1725
1726                 if (status != IXGBE_SUCCESS)
1727                         goto err_read_i2c_eeprom;
1728
1729                 vendor_oui =
1730                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1731                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1732                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1733
1734                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1735                         hw->phy.type = ixgbe_phy_qsfp_intel;
1736                 else
1737                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1738
1739                 ixgbe_get_device_caps(hw, &enforce_sfp);
1740                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1741                         /* Make sure we're a supported PHY type */
1742                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1743                                 status = IXGBE_SUCCESS;
1744                         } else {
1745                                 if (hw->allow_unsupported_sfp == true) {
1746                                         EWARN(hw, "WARNING: Intel (R) Network "
1747                                               "Connections are quality tested "
1748                                               "using Intel (R) Ethernet Optics."
1749                                               " Using untested modules is not "
1750                                               "supported and may cause unstable"
1751                                               " operation or damage to the "
1752                                               "module or the adapter. Intel "
1753                                               "Corporation is not responsible "
1754                                               "for any harm caused by using "
1755                                               "untested modules.\n", status);
1756                                         status = IXGBE_SUCCESS;
1757                                 } else {
1758                                         DEBUGOUT("QSFP module not supported\n");
1759                                         hw->phy.type =
1760                                                 ixgbe_phy_sfp_unsupported;
1761                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1762                                 }
1763                         }
1764                 } else {
1765                         status = IXGBE_SUCCESS;
1766                 }
1767         }
1768
1769 out:
1770         return status;
1771
1772 err_read_i2c_eeprom:
1773         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1774         hw->phy.id = 0;
1775         hw->phy.type = ixgbe_phy_unknown;
1776
1777         return IXGBE_ERR_SFP_NOT_PRESENT;
1778 }
1779
1780
1781 /**
1782  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1783  *  @hw: pointer to hardware structure
1784  *  @list_offset: offset to the SFP ID list
1785  *  @data_offset: offset to the SFP data block
1786  *
1787  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1788  *  so it returns the offsets to the phy init sequence block.
1789  **/
1790 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1791                                         u16 *list_offset,
1792                                         u16 *data_offset)
1793 {
1794         u16 sfp_id;
1795         u16 sfp_type = hw->phy.sfp_type;
1796
1797         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1798
1799         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1800                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1801
1802         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1803                 return IXGBE_ERR_SFP_NOT_PRESENT;
1804
1805         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1806             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1807                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1808
1809         /*
1810          * Limiting active cables and 1G Phys must be initialized as
1811          * SR modules
1812          */
1813         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1814             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1815             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1816             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1817                 sfp_type = ixgbe_sfp_type_srlr_core0;
1818         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1819                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1820                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1821                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1822                 sfp_type = ixgbe_sfp_type_srlr_core1;
1823
1824         /* Read offset to PHY init contents */
1825         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1826                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1827                               "eeprom read at offset %d failed",
1828                               IXGBE_PHY_INIT_OFFSET_NL);
1829                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1830         }
1831
1832         if ((!*list_offset) || (*list_offset == 0xFFFF))
1833                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1834
1835         /* Shift offset to first ID word */
1836         (*list_offset)++;
1837
1838         /*
1839          * Find the matching SFP ID in the EEPROM
1840          * and program the init sequence
1841          */
1842         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1843                 goto err_phy;
1844
1845         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1846                 if (sfp_id == sfp_type) {
1847                         (*list_offset)++;
1848                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1849                                 goto err_phy;
1850                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1851                                 DEBUGOUT("SFP+ module not supported\n");
1852                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1853                         } else {
1854                                 break;
1855                         }
1856                 } else {
1857                         (*list_offset) += 2;
1858                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1859                                 goto err_phy;
1860                 }
1861         }
1862
1863         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1864                 DEBUGOUT("No matching SFP+ module found\n");
1865                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1866         }
1867
1868         return IXGBE_SUCCESS;
1869
1870 err_phy:
1871         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1872                       "eeprom read at offset %d failed", *list_offset);
1873         return IXGBE_ERR_PHY;
1874 }
1875
1876 /**
1877  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1878  *  @hw: pointer to hardware structure
1879  *  @byte_offset: EEPROM byte offset to read
1880  *  @eeprom_data: value read
1881  *
1882  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1883  **/
1884 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1885                                   u8 *eeprom_data)
1886 {
1887         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1888
1889         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1890                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1891                                          eeprom_data);
1892 }
1893
1894 /**
1895  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1896  *  @hw: pointer to hardware structure
1897  *  @byte_offset: byte offset at address 0xA2
1898  *  @eeprom_data: value read
1899  *
1900  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1901  **/
1902 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1903                                           u8 *sff8472_data)
1904 {
1905         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1906                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1907                                          sff8472_data);
1908 }
1909
1910 /**
1911  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1912  *  @hw: pointer to hardware structure
1913  *  @byte_offset: EEPROM byte offset to write
1914  *  @eeprom_data: value to write
1915  *
1916  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1917  **/
1918 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1919                                    u8 eeprom_data)
1920 {
1921         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1922
1923         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1924                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1925                                           eeprom_data);
1926 }
1927
1928 /**
1929  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1930  * @hw: pointer to hardware structure
1931  * @offset: eeprom offset to be read
1932  * @addr: I2C address to be read
1933  */
1934 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1935 {
1936         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1937             offset == IXGBE_SFF_IDENTIFIER &&
1938             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1939                 return true;
1940         return false;
1941 }
1942
1943 /**
1944  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1945  *  @hw: pointer to hardware structure
1946  *  @byte_offset: byte offset to read
1947  *  @data: value read
1948  *
1949  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1950  *  a specified device address.
1951  **/
1952 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1953                                 u8 dev_addr, u8 *data)
1954 {
1955         s32 status;
1956         u32 max_retry = 10;
1957         u32 retry = 0;
1958         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1959         bool nack = 1;
1960         *data = 0;
1961
1962         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1963
1964         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
1965                 max_retry = IXGBE_SFP_DETECT_RETRIES;
1966
1967         do {
1968                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1969                         return IXGBE_ERR_SWFW_SYNC;
1970
1971                 ixgbe_i2c_start(hw);
1972
1973                 /* Device Address and write indication */
1974                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1975                 if (status != IXGBE_SUCCESS)
1976                         goto fail;
1977
1978                 status = ixgbe_get_i2c_ack(hw);
1979                 if (status != IXGBE_SUCCESS)
1980                         goto fail;
1981
1982                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1983                 if (status != IXGBE_SUCCESS)
1984                         goto fail;
1985
1986                 status = ixgbe_get_i2c_ack(hw);
1987                 if (status != IXGBE_SUCCESS)
1988                         goto fail;
1989
1990                 ixgbe_i2c_start(hw);
1991
1992                 /* Device Address and read indication */
1993                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1994                 if (status != IXGBE_SUCCESS)
1995                         goto fail;
1996
1997                 status = ixgbe_get_i2c_ack(hw);
1998                 if (status != IXGBE_SUCCESS)
1999                         goto fail;
2000
2001                 status = ixgbe_clock_in_i2c_byte(hw, data);
2002                 if (status != IXGBE_SUCCESS)
2003                         goto fail;
2004
2005                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2006                 if (status != IXGBE_SUCCESS)
2007                         goto fail;
2008
2009                 ixgbe_i2c_stop(hw);
2010                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2011                 return IXGBE_SUCCESS;
2012
2013 fail:
2014                 ixgbe_i2c_bus_clear(hw);
2015                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2016                 msec_delay(100);
2017                 retry++;
2018                 if (retry < max_retry)
2019                         DEBUGOUT("I2C byte read error - Retrying.\n");
2020                 else
2021                         DEBUGOUT("I2C byte read error.\n");
2022
2023         } while (retry < max_retry);
2024
2025         return status;
2026 }
2027
2028 /**
2029  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2030  *  @hw: pointer to hardware structure
2031  *  @byte_offset: byte offset to write
2032  *  @data: value to write
2033  *
2034  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2035  *  a specified device address.
2036  **/
2037 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2038                                  u8 dev_addr, u8 data)
2039 {
2040         s32 status = IXGBE_SUCCESS;
2041         u32 max_retry = 1;
2042         u32 retry = 0;
2043         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2044
2045         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2046
2047         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
2048                 status = IXGBE_ERR_SWFW_SYNC;
2049                 goto write_byte_out;
2050         }
2051
2052         do {
2053                 ixgbe_i2c_start(hw);
2054
2055                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2056                 if (status != IXGBE_SUCCESS)
2057                         goto fail;
2058
2059                 status = ixgbe_get_i2c_ack(hw);
2060                 if (status != IXGBE_SUCCESS)
2061                         goto fail;
2062
2063                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2064                 if (status != IXGBE_SUCCESS)
2065                         goto fail;
2066
2067                 status = ixgbe_get_i2c_ack(hw);
2068                 if (status != IXGBE_SUCCESS)
2069                         goto fail;
2070
2071                 status = ixgbe_clock_out_i2c_byte(hw, data);
2072                 if (status != IXGBE_SUCCESS)
2073                         goto fail;
2074
2075                 status = ixgbe_get_i2c_ack(hw);
2076                 if (status != IXGBE_SUCCESS)
2077                         goto fail;
2078
2079                 ixgbe_i2c_stop(hw);
2080                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2081                 return IXGBE_SUCCESS;
2082
2083 fail:
2084                 ixgbe_i2c_bus_clear(hw);
2085                 retry++;
2086                 if (retry < max_retry)
2087                         DEBUGOUT("I2C byte write error - Retrying.\n");
2088                 else
2089                         DEBUGOUT("I2C byte write error.\n");
2090         } while (retry < max_retry);
2091
2092         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2093
2094 write_byte_out:
2095         return status;
2096 }
2097
2098 /**
2099  *  ixgbe_i2c_start - Sets I2C start condition
2100  *  @hw: pointer to hardware structure
2101  *
2102  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2103  *  Set bit-bang mode on X550 hardware.
2104  **/
2105 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2106 {
2107         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2108
2109         DEBUGFUNC("ixgbe_i2c_start");
2110
2111         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2112
2113         /* Start condition must begin with data and clock high */
2114         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2115         ixgbe_raise_i2c_clk(hw, &i2cctl);
2116
2117         /* Setup time for start condition (4.7us) */
2118         usec_delay(IXGBE_I2C_T_SU_STA);
2119
2120         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2121
2122         /* Hold time for start condition (4us) */
2123         usec_delay(IXGBE_I2C_T_HD_STA);
2124
2125         ixgbe_lower_i2c_clk(hw, &i2cctl);
2126
2127         /* Minimum low period of clock is 4.7 us */
2128         usec_delay(IXGBE_I2C_T_LOW);
2129
2130 }
2131
2132 /**
2133  *  ixgbe_i2c_stop - Sets I2C stop condition
2134  *  @hw: pointer to hardware structure
2135  *
2136  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2137  *  Disables bit-bang mode and negates data output enable on X550
2138  *  hardware.
2139  **/
2140 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2141 {
2142         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2143         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2144         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2145         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2146
2147         DEBUGFUNC("ixgbe_i2c_stop");
2148
2149         /* Stop condition must begin with data low and clock high */
2150         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2151         ixgbe_raise_i2c_clk(hw, &i2cctl);
2152
2153         /* Setup time for stop condition (4us) */
2154         usec_delay(IXGBE_I2C_T_SU_STO);
2155
2156         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2157
2158         /* bus free time between stop and start (4.7us)*/
2159         usec_delay(IXGBE_I2C_T_BUF);
2160
2161         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2162                 i2cctl &= ~bb_en_bit;
2163                 i2cctl |= data_oe_bit | clk_oe_bit;
2164                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2165                 IXGBE_WRITE_FLUSH(hw);
2166         }
2167 }
2168
2169 /**
2170  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2171  *  @hw: pointer to hardware structure
2172  *  @data: data byte to clock in
2173  *
2174  *  Clocks in one byte data via I2C data/clock
2175  **/
2176 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2177 {
2178         s32 i;
2179         bool bit = 0;
2180
2181         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2182
2183         *data = 0;
2184         for (i = 7; i >= 0; i--) {
2185                 ixgbe_clock_in_i2c_bit(hw, &bit);
2186                 *data |= bit << i;
2187         }
2188
2189         return IXGBE_SUCCESS;
2190 }
2191
2192 /**
2193  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2194  *  @hw: pointer to hardware structure
2195  *  @data: data byte clocked out
2196  *
2197  *  Clocks out one byte data via I2C data/clock
2198  **/
2199 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2200 {
2201         s32 status = IXGBE_SUCCESS;
2202         s32 i;
2203         u32 i2cctl;
2204         bool bit;
2205
2206         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2207
2208         for (i = 7; i >= 0; i--) {
2209                 bit = (data >> i) & 0x1;
2210                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2211
2212                 if (status != IXGBE_SUCCESS)
2213                         break;
2214         }
2215
2216         /* Release SDA line (set high) */
2217         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2218         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2219         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2220         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2221         IXGBE_WRITE_FLUSH(hw);
2222
2223         return status;
2224 }
2225
2226 /**
2227  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2228  *  @hw: pointer to hardware structure
2229  *
2230  *  Clocks in/out one bit via I2C data/clock
2231  **/
2232 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2233 {
2234         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2235         s32 status = IXGBE_SUCCESS;
2236         u32 i = 0;
2237         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2238         u32 timeout = 10;
2239         bool ack = 1;
2240
2241         DEBUGFUNC("ixgbe_get_i2c_ack");
2242
2243         if (data_oe_bit) {
2244                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2245                 i2cctl |= data_oe_bit;
2246                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2247                 IXGBE_WRITE_FLUSH(hw);
2248         }
2249         ixgbe_raise_i2c_clk(hw, &i2cctl);
2250
2251         /* Minimum high period of clock is 4us */
2252         usec_delay(IXGBE_I2C_T_HIGH);
2253
2254         /* Poll for ACK.  Note that ACK in I2C spec is
2255          * transition from 1 to 0 */
2256         for (i = 0; i < timeout; i++) {
2257                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2258                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2259
2260                 usec_delay(1);
2261                 if (!ack)
2262                         break;
2263         }
2264
2265         if (ack) {
2266                 DEBUGOUT("I2C ack was not received.\n");
2267                 status = IXGBE_ERR_I2C;
2268         }
2269
2270         ixgbe_lower_i2c_clk(hw, &i2cctl);
2271
2272         /* Minimum low period of clock is 4.7 us */
2273         usec_delay(IXGBE_I2C_T_LOW);
2274
2275         return status;
2276 }
2277
2278 /**
2279  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2280  *  @hw: pointer to hardware structure
2281  *  @data: read data value
2282  *
2283  *  Clocks in one bit via I2C data/clock
2284  **/
2285 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2286 {
2287         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2288         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2289
2290         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2291
2292         if (data_oe_bit) {
2293                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2294                 i2cctl |= data_oe_bit;
2295                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2296                 IXGBE_WRITE_FLUSH(hw);
2297         }
2298         ixgbe_raise_i2c_clk(hw, &i2cctl);
2299
2300         /* Minimum high period of clock is 4us */
2301         usec_delay(IXGBE_I2C_T_HIGH);
2302
2303         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2304         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2305
2306         ixgbe_lower_i2c_clk(hw, &i2cctl);
2307
2308         /* Minimum low period of clock is 4.7 us */
2309         usec_delay(IXGBE_I2C_T_LOW);
2310
2311         return IXGBE_SUCCESS;
2312 }
2313
2314 /**
2315  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2316  *  @hw: pointer to hardware structure
2317  *  @data: data value to write
2318  *
2319  *  Clocks out one bit via I2C data/clock
2320  **/
2321 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2322 {
2323         s32 status;
2324         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2325
2326         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2327
2328         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2329         if (status == IXGBE_SUCCESS) {
2330                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2331
2332                 /* Minimum high period of clock is 4us */
2333                 usec_delay(IXGBE_I2C_T_HIGH);
2334
2335                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2336
2337                 /* Minimum low period of clock is 4.7 us.
2338                  * This also takes care of the data hold time.
2339                  */
2340                 usec_delay(IXGBE_I2C_T_LOW);
2341         } else {
2342                 status = IXGBE_ERR_I2C;
2343                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2344                              "I2C data was not set to %X\n", data);
2345         }
2346
2347         return status;
2348 }
2349
2350 /**
2351  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2352  *  @hw: pointer to hardware structure
2353  *  @i2cctl: Current value of I2CCTL register
2354  *
2355  *  Raises the I2C clock line '0'->'1'
2356  *  Negates the I2C clock output enable on X550 hardware.
2357  **/
2358 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2359 {
2360         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2361         u32 i = 0;
2362         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2363         u32 i2cctl_r = 0;
2364
2365         DEBUGFUNC("ixgbe_raise_i2c_clk");
2366
2367         if (clk_oe_bit) {
2368                 *i2cctl |= clk_oe_bit;
2369                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2370         }
2371
2372         for (i = 0; i < timeout; i++) {
2373                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2374
2375                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2376                 IXGBE_WRITE_FLUSH(hw);
2377                 /* SCL rise time (1000ns) */
2378                 usec_delay(IXGBE_I2C_T_RISE);
2379
2380                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2381                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2382                         break;
2383         }
2384 }
2385
2386 /**
2387  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2388  *  @hw: pointer to hardware structure
2389  *  @i2cctl: Current value of I2CCTL register
2390  *
2391  *  Lowers the I2C clock line '1'->'0'
2392  *  Asserts the I2C clock output enable on X550 hardware.
2393  **/
2394 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2395 {
2396         DEBUGFUNC("ixgbe_lower_i2c_clk");
2397
2398         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2399         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2400
2401         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2402         IXGBE_WRITE_FLUSH(hw);
2403
2404         /* SCL fall time (300ns) */
2405         usec_delay(IXGBE_I2C_T_FALL);
2406 }
2407
2408 /**
2409  *  ixgbe_set_i2c_data - Sets the I2C data bit
2410  *  @hw: pointer to hardware structure
2411  *  @i2cctl: Current value of I2CCTL register
2412  *  @data: I2C data value (0 or 1) to set
2413  *
2414  *  Sets the I2C data bit
2415  *  Asserts the I2C data output enable on X550 hardware.
2416  **/
2417 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2418 {
2419         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2420         s32 status = IXGBE_SUCCESS;
2421
2422         DEBUGFUNC("ixgbe_set_i2c_data");
2423
2424         if (data)
2425                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2426         else
2427                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2428         *i2cctl &= ~data_oe_bit;
2429
2430         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2431         IXGBE_WRITE_FLUSH(hw);
2432
2433         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2434         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2435
2436         if (!data)      /* Can't verify data in this case */
2437                 return IXGBE_SUCCESS;
2438         if (data_oe_bit) {
2439                 *i2cctl |= data_oe_bit;
2440                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2441                 IXGBE_WRITE_FLUSH(hw);
2442         }
2443
2444         /* Verify data was set correctly */
2445         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2446         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2447                 status = IXGBE_ERR_I2C;
2448                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2449                              "Error - I2C data was not set to %X.\n",
2450                              data);
2451         }
2452
2453         return status;
2454 }
2455
2456 /**
2457  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2458  *  @hw: pointer to hardware structure
2459  *  @i2cctl: Current value of I2CCTL register
2460  *
2461  *  Returns the I2C data bit value
2462  *  Negates the I2C data output enable on X550 hardware.
2463  **/
2464 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2465 {
2466         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2467         bool data;
2468
2469         DEBUGFUNC("ixgbe_get_i2c_data");
2470
2471         if (data_oe_bit) {
2472                 *i2cctl |= data_oe_bit;
2473                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2474                 IXGBE_WRITE_FLUSH(hw);
2475                 usec_delay(IXGBE_I2C_T_FALL);
2476         }
2477
2478         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2479                 data = 1;
2480         else
2481                 data = 0;
2482
2483         return data;
2484 }
2485
2486 /**
2487  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2488  *  @hw: pointer to hardware structure
2489  *
2490  *  Clears the I2C bus by sending nine clock pulses.
2491  *  Used when data line is stuck low.
2492  **/
2493 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2494 {
2495         u32 i2cctl;
2496         u32 i;
2497
2498         DEBUGFUNC("ixgbe_i2c_bus_clear");
2499
2500         ixgbe_i2c_start(hw);
2501         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2502
2503         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2504
2505         for (i = 0; i < 9; i++) {
2506                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2507
2508                 /* Min high period of clock is 4us */
2509                 usec_delay(IXGBE_I2C_T_HIGH);
2510
2511                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2512
2513                 /* Min low period of clock is 4.7us*/
2514                 usec_delay(IXGBE_I2C_T_LOW);
2515         }
2516
2517         ixgbe_i2c_start(hw);
2518
2519         /* Put the i2c bus back to default state */
2520         ixgbe_i2c_stop(hw);
2521 }
2522
2523 /**
2524  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2525  *  @hw: pointer to hardware structure
2526  *
2527  *  Checks if the LASI temp alarm status was triggered due to overtemp
2528  **/
2529 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2530 {
2531         s32 status = IXGBE_SUCCESS;
2532         u16 phy_data = 0;
2533
2534         DEBUGFUNC("ixgbe_tn_check_overtemp");
2535
2536         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2537                 goto out;
2538
2539         /* Check that the LASI temp alarm status was triggered */
2540         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2541                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2542
2543         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2544                 goto out;
2545
2546         status = IXGBE_ERR_OVERTEMP;
2547         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2548 out:
2549         return status;
2550 }
2551
2552 /**
2553  * ixgbe_set_copper_phy_power - Control power for copper phy
2554  * @hw: pointer to hardware structure
2555  * @on: true for on, false for off
2556  */
2557 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2558 {
2559         u32 status;
2560         u16 reg;
2561
2562         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2563                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2564                                       &reg);
2565         if (status)
2566                 return status;
2567
2568         if (on) {
2569                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2570         } else {
2571                 if (ixgbe_check_reset_blocked(hw))
2572                         return 0;
2573                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2574         }
2575
2576         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2577                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2578                                        reg);
2579         return status;
2580 }