lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x540.h"
  35 #include "ixgbe_type.h"
  36 #include "ixgbe_api.h"
  37 #include "ixgbe_common.h"
  38 #include "ixgbe_phy.h"
  39
  40 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw);
  41 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
  42                                       ixgbe_link_speed *speed,
  43                                       bool *autoneg);
  44 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw);
  45 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
  46                                ixgbe_link_speed speed,
  47                                bool autoneg, bool link_up_wait_to_complete);
  48 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw);
  49 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw);
  50 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw);
  51
  52 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw);
  53 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data);
  54 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
  55                                 u16 offset, u16 words, u16 *data);
  56 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data);
  57 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
  58                                  u16 offset, u16 words, u16 *data);
  59 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw);
  60 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, u16 *checksum_val);
  61 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw);
  62
  63 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
  64 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
  65
  66 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
  67 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
  68 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
  69 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
  70
  71 /**
  72  *  ixgbe_init_ops_X540 - Inits func ptrs and MAC type
  73  *  @hw: pointer to hardware structure
  74  *
  75  *  Initialize the function pointers and assign the MAC type for 82599.
  76  *  Does not touch the hardware.
  77  **/
  78 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
  79 {
  80         struct ixgbe_mac_info *mac = &hw->mac;
  81         struct ixgbe_phy_info *phy = &hw->phy;
  82         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  83         s32 ret_val;
  84
  85         DEBUGFUNC("ixgbe_init_ops_X540");
  86
  87         ret_val = ixgbe_init_phy_ops_generic(hw);
  88         ret_val = ixgbe_init_ops_generic(hw);
  89
  90
  91         /* EEPROM */
  92         eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
  93         eeprom->ops.read = &ixgbe_read_eerd_X540;
  94         eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
  95         eeprom->ops.write = &ixgbe_write_eewr_X540;
  96         eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
  97         eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
  98         eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
  99         eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
 100
 101         /* PHY */
 102         phy->ops.init = &ixgbe_init_phy_ops_generic;
 103         phy->ops.reset = NULL;
 104
 105         /* MAC */
 106         mac->ops.reset_hw = &ixgbe_reset_hw_X540;
 107         mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
 108         mac->ops.get_media_type = &ixgbe_get_media_type_X540;
 109         mac->ops.get_supported_physical_layer =
 110                                     &ixgbe_get_supported_physical_layer_X540;
 111         mac->ops.read_analog_reg8 = NULL;
 112         mac->ops.write_analog_reg8 = NULL;
 113         mac->ops.start_hw = &ixgbe_start_hw_X540;
 114         mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
 115         mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
 116         mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
 117         mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
 118         mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
 119         mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
 120         mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
 121
 122         /* RAR, Multicast, VLAN */
 123         mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
 124         mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
 125         mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
 126         mac->rar_highwater = 1;
 127         mac->ops.set_vfta = &ixgbe_set_vfta_generic;
 128         mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
 129         mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
 130         mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
 131         mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
 132
 133         /* Link */
 134         mac->ops.get_link_capabilities =
 135                                 &ixgbe_get_copper_link_capabilities_generic;
 136         mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
 137         mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
 138         mac->ops.check_link = &ixgbe_check_mac_link_generic;
 139
 140
 141         mac->mcft_size        = 128;
 142         mac->vft_size         = 128;
 143         mac->num_rar_entries  = 128;
 144         mac->rx_pb_size       = 384;
 145         mac->max_tx_queues    = 128;
 146         mac->max_rx_queues    = 128;
 147         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
 148
 149         /*
 150          * FWSM register
 151          * ARC supported; valid only if manageability features are
 152          * enabled.
 153          */
 154         mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
 155                                    IXGBE_FWSM_MODE_MASK) ? true : false;
 156
 157         hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
 158
 159         /* LEDs */
 160         mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
 161         mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
 162
 163         /* Manageability interface */
 164         mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
 165
 166         return ret_val;
 167 }
 168
 169 /**
 170  *  ixgbe_get_link_capabilities_X540 - Determines link capabilities
 171  *  @hw: pointer to hardware structure
 172  *  @speed: pointer to link speed
 173  *  @autoneg: true when autoneg or autotry is enabled
 174  *
 175  *  Determines the link capabilities by reading the AUTOC register.
 176  **/
 177 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
 178                                      ixgbe_link_speed *speed,
 179                                      bool *autoneg)
 180 {
 181         ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
 182
 183         return IXGBE_SUCCESS;
 184 }
 185
 186 /**
 187  *  ixgbe_get_media_type_X540 - Get media type
 188  *  @hw: pointer to hardware structure
 189  *
 190  *  Returns the media type (fiber, copper, backplane)
 191  **/
 192 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
 193 {
 194         UNREFERENCED_1PARAMETER(hw);
 195         return ixgbe_media_type_copper;
 196 }
 197
 198 /**
 199  *  ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
 200  *  @hw: pointer to hardware structure
 201  *  @speed: new link speed
 202  *  @autoneg: true if autonegotiation enabled
 203  *  @autoneg_wait_to_complete: true when waiting for completion is needed
 204  **/
 205 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
 206                                      ixgbe_link_speed speed, bool autoneg,
 207                                      bool autoneg_wait_to_complete)
 208 {
 209         DEBUGFUNC("ixgbe_setup_mac_link_X540");
 210         return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 211                                             autoneg_wait_to_complete);
 212 }
 213
 214 /**
 215  *  ixgbe_reset_hw_X540 - Perform hardware reset
 216  *  @hw: pointer to hardware structure
 217  *
 218  *  Resets the hardware by resetting the transmit and receive units, masks
 219  *  and clears all interrupts, and perform a reset.
 220  **/
 221 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
 222 {
 223         s32 status;
 224         u32 ctrl, i;
 225
 226         DEBUGFUNC("ixgbe_reset_hw_X540");
 227
 228         /* Call adapter stop to disable tx/rx and clear interrupts */
 229         status = hw->mac.ops.stop_adapter(hw);
 230         if (status != IXGBE_SUCCESS)
 231                 goto reset_hw_out;
 232
 233         /* flush pending Tx transactions */
 234         ixgbe_clear_tx_pending(hw);
 235
 236 mac_reset_top:
 237         ctrl = IXGBE_CTRL_RST;
 238         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
 239         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
 240         IXGBE_WRITE_FLUSH(hw);
 241
 242         /* Poll for reset bit to self-clear indicating reset is complete */
 243         for (i = 0; i < 10; i++) {
 244                 usec_delay(1);
 245                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 246                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
 247                         break;
 248         }
 249
 250         if (ctrl & IXGBE_CTRL_RST_MASK) {
 251                 status = IXGBE_ERR_RESET_FAILED;
 252                 DEBUGOUT("Reset polling failed to complete.\n");
 253         }
 254         msec_delay(100);
 255
 256         /*
 257          * Double resets are required for recovery from certain error
 258          * conditions.  Between resets, it is necessary to stall to allow time
 259          * for any pending HW events to complete.
 260          */
 261         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
 262                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
 263                 goto mac_reset_top;
 264         }
 265
 266         /* Set the Rx packet buffer size. */
 267         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
 268
 269         /* Store the permanent mac address */
 270         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 271
 272         /*
 273          * Store MAC address from RAR0, clear receive address registers, and
 274          * clear the multicast table.  Also reset num_rar_entries to 128,
 275          * since we modify this value when programming the SAN MAC address.
 276          */
 277         hw->mac.num_rar_entries = 128;
 278         hw->mac.ops.init_rx_addrs(hw);
 279
 280         /* Store the permanent SAN mac address */
 281         hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
 282
 283         /* Add the SAN MAC address to the RAR only if it's a valid address */
 284         if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
 285                 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
 286                                     hw->mac.san_addr, 0, IXGBE_RAH_AV);
 287
 288                 /* Reserve the last RAR for the SAN MAC address */
 289                 hw->mac.num_rar_entries--;
 290         }
 291
 292         /* Store the alternative WWNN/WWPN prefix */
 293         hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
 294                                        &hw->mac.wwpn_prefix);
 295
 296 reset_hw_out:
 297         return status;
 298 }
 299
 300 /**
 301  *  ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
 302  *  @hw: pointer to hardware structure
 303  *
 304  *  Starts the hardware using the generic start_hw function
 305  *  and the generation start_hw function.
 306  *  Then performs revision-specific operations, if any.
 307  **/
 308 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
 309 {
 310         s32 ret_val = IXGBE_SUCCESS;
 311
 312         DEBUGFUNC("ixgbe_start_hw_X540");
 313
 314         ret_val = ixgbe_start_hw_generic(hw);
 315         if (ret_val != IXGBE_SUCCESS)
 316                 goto out;
 317
 318         ret_val = ixgbe_start_hw_gen2(hw);
 319
 320 out:
 321         return ret_val;
 322 }
 323
 324 /**
 325  *  ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
 326  *  @hw: pointer to hardware structure
 327  *
 328  *  Determines physical layer capabilities of the current configuration.
 329  **/
 330 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
 331 {
 332         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
 333         u16 ext_ability = 0;
 334
 335         DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
 336
 337         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 338         IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 339         if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
 340                 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
 341         if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
 342                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
 343         if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
 344                 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
 345
 346         return physical_layer;
 347 }
 348
 349 /**
 350  *  ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
 351  *  @hw: pointer to hardware structure
 352  *
 353  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 354  *  ixgbe_hw struct in order to set up EEPROM access.
 355  **/
 356 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
 357 {
 358         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 359         u32 eec;
 360         u16 eeprom_size;
 361
 362         DEBUGFUNC("ixgbe_init_eeprom_params_X540");
 363
 364         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 365                 eeprom->semaphore_delay = 10;
 366                 eeprom->type = ixgbe_flash;
 367
 368                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 369                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 370                                     IXGBE_EEC_SIZE_SHIFT);
 371                 eeprom->word_size = 1 << (eeprom_size +
 372                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 373
 374                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 375                           eeprom->type, eeprom->word_size);
 376         }
 377
 378         return IXGBE_SUCCESS;
 379 }
 380
 381 /**
 382  *  ixgbe_read_eerd_X540- Read EEPROM word using EERD
 383  *  @hw: pointer to hardware structure
 384  *  @offset: offset of  word in the EEPROM to read
 385  *  @data: word read from the EEPROM
 386  *
 387  *  Reads a 16 bit word from the EEPROM using the EERD register.
 388  **/
 389 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
 390 {
 391         s32 status = IXGBE_SUCCESS;
 392
 393         DEBUGFUNC("ixgbe_read_eerd_X540");
 394         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 395             IXGBE_SUCCESS)
 396                 status = ixgbe_read_eerd_generic(hw, offset, data);
 397         else
 398                 status = IXGBE_ERR_SWFW_SYNC;
 399
 400         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 401         return status;
 402 }
 403
 404 /**
 405  *  ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
 406  *  @hw: pointer to hardware structure
 407  *  @offset: offset of  word in the EEPROM to read
 408  *  @words: number of words
 409  *  @data: word(s) read from the EEPROM
 410  *
 411  *  Reads a 16 bit word(s) from the EEPROM using the EERD register.
 412  **/
 413 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
 414                                 u16 offset, u16 words, u16 *data)
 415 {
 416         s32 status = IXGBE_SUCCESS;
 417
 418         DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
 419         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 420             IXGBE_SUCCESS)
 421                 status = ixgbe_read_eerd_buffer_generic(hw, offset,
 422                                                         words, data);
 423         else
 424                 status = IXGBE_ERR_SWFW_SYNC;
 425
 426         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 427         return status;
 428 }
 429
 430 /**
 431  *  ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
 432  *  @hw: pointer to hardware structure
 433  *  @offset: offset of  word in the EEPROM to write
 434  *  @data: word write to the EEPROM
 435  *
 436  *  Write a 16 bit word to the EEPROM using the EEWR register.
 437  **/
 438 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
 439 {
 440         s32 status = IXGBE_SUCCESS;
 441
 442         DEBUGFUNC("ixgbe_write_eewr_X540");
 443         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 444             IXGBE_SUCCESS)
 445                 status = ixgbe_write_eewr_generic(hw, offset, data);
 446         else
 447                 status = IXGBE_ERR_SWFW_SYNC;
 448
 449         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 450         return status;
 451 }
 452
 453 /**
 454  *  ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
 455  *  @hw: pointer to hardware structure
 456  *  @offset: offset of  word in the EEPROM to write
 457  *  @words: number of words
 458  *  @data: word(s) write to the EEPROM
 459  *
 460  *  Write a 16 bit word(s) to the EEPROM using the EEWR register.
 461  **/
 462 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
 463                                  u16 offset, u16 words, u16 *data)
 464 {
 465         s32 status = IXGBE_SUCCESS;
 466
 467         DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
 468         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 469             IXGBE_SUCCESS)
 470                 status = ixgbe_write_eewr_buffer_generic(hw, offset,
 471                                                          words, data);
 472         else
 473                 status = IXGBE_ERR_SWFW_SYNC;
 474
 475         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 476         return status;
 477 }
 478
 479 /**
 480  *  ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
 481  *
 482  *  This function does not use synchronization for EERD and EEWR. It can
 483  *  be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
 484  *
 485  *  @hw: pointer to hardware structure
 486  **/
 487 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
 488 {
 489         u16 i;
 490         u16 j;
 491         u16 checksum = 0;
 492         u16 length = 0;
 493         u16 pointer = 0;
 494         u16 word = 0;
 495
 496         /*
 497          * Do not use hw->eeprom.ops.read because we do not want to take
 498          * the synchronization semaphores here. Instead use
 499          * ixgbe_read_eerd_generic
 500          */
 501
 502         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
 503
 504         /* Include 0x0-0x3F in the checksum */
 505         for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
 506                 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
 507                         DEBUGOUT("EEPROM read failed\n");
 508                         break;
 509                 }
 510                 checksum += word;
 511         }
 512
 513         /*
 514          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 515          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 516          */
 517         for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
 518                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 519                         continue;
 520
 521                 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
 522                         DEBUGOUT("EEPROM read failed\n");
 523                         break;
 524                 }
 525
 526                 /* Skip pointer section if the pointer is invalid. */
 527                 if (pointer == 0xFFFF || pointer == 0 ||
 528                     pointer >= hw->eeprom.word_size)
 529                         continue;
 530
 531                 if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
 532                     IXGBE_SUCCESS) {
 533                         DEBUGOUT("EEPROM read failed\n");
 534                         break;
 535                 }
 536
 537                 /* Skip pointer section if length is invalid. */
 538                 if (length == 0xFFFF || length == 0 ||
 539                     (pointer + length) >= hw->eeprom.word_size)
 540                         continue;
 541
 542                 for (j = pointer+1; j <= pointer+length; j++) {
 543                         if (ixgbe_read_eerd_generic(hw, j, &word) !=
 544                             IXGBE_SUCCESS) {
 545                                 DEBUGOUT("EEPROM read failed\n");
 546                                 break;
 547                         }
 548                         checksum += word;
 549                 }
 550         }
 551
 552         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 553
 554         return checksum;
 555 }
 556
 557 /**
 558  *  ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
 559  *  @hw: pointer to hardware structure
 560  *  @checksum_val: calculated checksum
 561  *
 562  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 563  *  caller does not need checksum_val, the value can be NULL.
 564  **/
 565 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
 566                                         u16 *checksum_val)
 567 {
 568         s32 status;
 569         u16 checksum;
 570         u16 read_checksum = 0;
 571
 572         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
 573
 574         /*
 575          * Read the first word from the EEPROM. If this times out or fails, do
 576          * not continue or we could be in for a very long wait while every
 577          * EEPROM read fails
 578          */
 579         status = hw->eeprom.ops.read(hw, 0, &checksum);
 580
 581         if (status != IXGBE_SUCCESS) {
 582                 DEBUGOUT("EEPROM read failed\n");
 583                 goto out;
 584         }
 585
 586         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 587             IXGBE_SUCCESS) {
 588                 checksum = hw->eeprom.ops.calc_checksum(hw);
 589
 590                 /*
 591                  * Do not use hw->eeprom.ops.read because we do not want to take
 592                  * the synchronization semaphores twice here.
 593                 */
 594                 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
 595                                         &read_checksum);
 596
 597                 /*
 598                  * Verify read checksum from EEPROM is the same as
 599                  * calculated checksum
 600                  */
 601                 if (read_checksum != checksum)
 602                         status = IXGBE_ERR_EEPROM_CHECKSUM;
 603
 604                 /* If the user cares, return the calculated checksum */
 605                 if (checksum_val)
 606                         *checksum_val = checksum;
 607         } else {
 608                 status = IXGBE_ERR_SWFW_SYNC;
 609         }
 610
 611         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 612 out:
 613         return status;
 614 }
 615
 616 /**
 617  * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
 618  * @hw: pointer to hardware structure
 619  *
 620  * After writing EEPROM to shadow RAM using EEWR register, software calculates
 621  * checksum and updates the EEPROM and instructs the hardware to update
 622  * the flash.
 623  **/
 624 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
 625 {
 626         s32 status;
 627         u16 checksum;
 628
 629         DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
 630
 631         /*
 632          * Read the first word from the EEPROM. If this times out or fails, do
 633          * not continue or we could be in for a very long wait while every
 634          * EEPROM read fails
 635          */
 636         status = hw->eeprom.ops.read(hw, 0, &checksum);
 637
 638         if (status != IXGBE_SUCCESS)
 639                 DEBUGOUT("EEPROM read failed\n");
 640
 641         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 642             IXGBE_SUCCESS) {
 643                 checksum = hw->eeprom.ops.calc_checksum(hw);
 644
 645                 /*
 646                  * Do not use hw->eeprom.ops.write because we do not want to
 647                  * take the synchronization semaphores twice here.
 648                 */
 649                 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
 650                                                   checksum);
 651
 652         if (status == IXGBE_SUCCESS)
 653                 status = ixgbe_update_flash_X540(hw);
 654         else
 655                 status = IXGBE_ERR_SWFW_SYNC;
 656         }
 657
 658         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 659
 660         return status;
 661 }
 662
 663 /**
 664  *  ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
 665  *  @hw: pointer to hardware structure
 666  *
 667  *  Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
 668  *  EEPROM from shadow RAM to the flash device.
 669  **/
 670 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
 671 {
 672         u32 flup;
 673         s32 status = IXGBE_ERR_EEPROM;
 674
 675         DEBUGFUNC("ixgbe_update_flash_X540");
 676
 677         status = ixgbe_poll_flash_update_done_X540(hw);
 678         if (status == IXGBE_ERR_EEPROM) {
 679                 DEBUGOUT("Flash update time out\n");
 680                 goto out;
 681         }
 682
 683         flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
 684         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 685
 686         status = ixgbe_poll_flash_update_done_X540(hw);
 687         if (status == IXGBE_SUCCESS)
 688                 DEBUGOUT("Flash update complete\n");
 689         else
 690                 DEBUGOUT("Flash update time out\n");
 691
 692         if (hw->revision_id == 0) {
 693                 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
 694
 695                 if (flup & IXGBE_EEC_SEC1VAL) {
 696                         flup |= IXGBE_EEC_FLUP;
 697                         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 698                 }
 699
 700                 status = ixgbe_poll_flash_update_done_X540(hw);
 701                 if (status == IXGBE_SUCCESS)
 702                         DEBUGOUT("Flash update complete\n");
 703                 else
 704                         DEBUGOUT("Flash update time out\n");
 705         }
 706 out:
 707         return status;
 708 }
 709
 710 /**
 711  *  ixgbe_poll_flash_update_done_X540 - Poll flash update status
 712  *  @hw: pointer to hardware structure
 713  *
 714  *  Polls the FLUDONE (bit 26) of the EEC Register to determine when the
 715  *  flash update is done.
 716  **/
 717 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
 718 {
 719         u32 i;
 720         u32 reg;
 721         s32 status = IXGBE_ERR_EEPROM;
 722
 723         DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
 724
 725         for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
 726                 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
 727                 if (reg & IXGBE_EEC_FLUDONE) {
 728                         status = IXGBE_SUCCESS;
 729                         break;
 730                 }
 731                 usec_delay(5);
 732         }
 733         return status;
 734 }
 735
 736 /**
 737  *  ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
 738  *  @hw: pointer to hardware structure
 739  *  @mask: Mask to specify which semaphore to acquire
 740  *
 741  *  Acquires the SWFW semaphore thought the SW_FW_SYNC register for
 742  *  the specified function (CSR, PHY0, PHY1, NVM, Flash)
 743  **/
 744 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 745 {
 746         u32 swfw_sync;
 747         u32 swmask = mask;
 748         u32 fwmask = mask << 5;
 749         u32 hwmask = 0;
 750         u32 timeout = 200;
 751         u32 i;
 752         s32 ret_val = IXGBE_SUCCESS;
 753
 754         DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
 755
 756         if (swmask == IXGBE_GSSR_EEP_SM)
 757                 hwmask = IXGBE_GSSR_FLASH_SM;
 758
 759         /* SW only mask doesn't have FW bit pair */
 760         if (swmask == IXGBE_GSSR_SW_MNG_SM)
 761                 fwmask = 0;
 762
 763         for (i = 0; i < timeout; i++) {
 764                 /*
 765                  * SW NVM semaphore bit is used for access to all
 766                  * SW_FW_SYNC bits (not just NVM)
 767                  */
 768                 if (ixgbe_get_swfw_sync_semaphore(hw)) {
 769                         ret_val = IXGBE_ERR_SWFW_SYNC;
 770                         goto out;
 771                 }
 772
 773                 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 774                 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
 775                         swfw_sync |= swmask;
 776                         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 777                         ixgbe_release_swfw_sync_semaphore(hw);
 778                         msec_delay(5);
 779                         goto out;
 780                 } else {
 781                         /*
 782                          * Firmware currently using resource (fwmask), hardware
 783                          * currently using resource (hwmask), or other software
 784                          * thread currently using resource (swmask)
 785                          */
 786                         ixgbe_release_swfw_sync_semaphore(hw);
 787                         msec_delay(5);
 788                 }
 789         }
 790
 791         /* Failed to get SW only semaphore */
 792         if (swmask == IXGBE_GSSR_SW_MNG_SM) {
 793                 ret_val = IXGBE_ERR_SWFW_SYNC;
 794                 goto out;
 795         }
 796
 797         /* If the resource is not released by the FW/HW the SW can assume that
 798          * the FW/HW malfunctions. In that case the SW should sets the SW bit(s)
 799          * of the requested resource(s) while ignoring the corresponding FW/HW
 800          * bits in the SW_FW_SYNC register.
 801          */
 802         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 803         if (swfw_sync & (fwmask | hwmask)) {
 804                 if (ixgbe_get_swfw_sync_semaphore(hw)) {
 805                         ret_val = IXGBE_ERR_SWFW_SYNC;
 806                         goto out;
 807                 }
 808
 809                 swfw_sync |= swmask;
 810                 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 811                 ixgbe_release_swfw_sync_semaphore(hw);
 812                 msec_delay(5);
 813         }
 814
 815 out:
 816         return ret_val;
 817 }
 818
 819 /**
 820  *  ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
 821  *  @hw: pointer to hardware structure
 822  *  @mask: Mask to specify which semaphore to release
 823  *
 824  *  Releases the SWFW semaphore through the SW_FW_SYNC register
 825  *  for the specified function (CSR, PHY0, PHY1, EVM, Flash)
 826  **/
 827 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 828 {
 829         u32 swfw_sync;
 830         u32 swmask = mask;
 831
 832         DEBUGFUNC("ixgbe_release_swfw_sync_X540");
 833
 834         ixgbe_get_swfw_sync_semaphore(hw);
 835
 836         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 837         swfw_sync &= ~swmask;
 838         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 839
 840         ixgbe_release_swfw_sync_semaphore(hw);
 841         msec_delay(5);
 842 }
 843
 844 /**
 845  *  ixgbe_get_nvm_semaphore - Get hardware semaphore
 846  *  @hw: pointer to hardware structure
 847  *
 848  *  Sets the hardware semaphores so SW/FW can gain control of shared resources
 849  **/
 850 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
 851 {
 852         s32 status = IXGBE_ERR_EEPROM;
 853         u32 timeout = 2000;
 854         u32 i;
 855         u32 swsm;
 856
 857         DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
 858
 859         /* Get SMBI software semaphore between device drivers first */
 860         for (i = 0; i < timeout; i++) {
 861                 /*
 862                  * If the SMBI bit is 0 when we read it, then the bit will be
 863                  * set and we have the semaphore
 864                  */
 865                 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 866                 if (!(swsm & IXGBE_SWSM_SMBI)) {
 867                         status = IXGBE_SUCCESS;
 868                         break;
 869                 }
 870                 usec_delay(50);
 871         }
 872
 873         /* Now get the semaphore between SW/FW through the REGSMP bit */
 874         if (status == IXGBE_SUCCESS) {
 875                 for (i = 0; i < timeout; i++) {
 876                         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 877                         if (!(swsm & IXGBE_SWFW_REGSMP))
 878                                 break;
 879
 880                         usec_delay(50);
 881                 }
 882
 883                 /*
 884                  * Release semaphores and return error if SW NVM semaphore
 885                  * was not granted because we don't have access to the EEPROM
 886                  */
 887                 if (i >= timeout) {
 888                         DEBUGOUT("REGSMP Software NVM semaphore not "
 889                                  "granted.\n");
 890                         ixgbe_release_swfw_sync_semaphore(hw);
 891                         status = IXGBE_ERR_EEPROM;
 892                 }
 893         } else {
 894                 DEBUGOUT("Software semaphore SMBI between device drivers "
 895                          "not granted.\n");
 896         }
 897
 898         return status;
 899 }
 900
 901 /**
 902  *  ixgbe_release_nvm_semaphore - Release hardware semaphore
 903  *  @hw: pointer to hardware structure
 904  *
 905  *  This function clears hardware semaphore bits.
 906  **/
 907 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
 908 {
 909         u32 swsm;
 910
 911         DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
 912
 913         /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
 914
 915         swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 916         swsm &= ~IXGBE_SWSM_SMBI;
 917         IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
 918
 919         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 920         swsm &= ~IXGBE_SWFW_REGSMP;
 921         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
 922
 923         IXGBE_WRITE_FLUSH(hw);
 924 }
 925
 926 /**
 927  * ixgbe_blink_led_start_X540 - Blink LED based on index.
 928  * @hw: pointer to hardware structure
 929  * @index: led number to blink
 930  *
 931  * Devices that implement the version 2 interface:
 932  *   X540
 933  **/
 934 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
 935 {
 936         u32 macc_reg;
 937         u32 ledctl_reg;
 938
 939         DEBUGFUNC("ixgbe_blink_led_start_X540");
 940
 941         /*
 942          * In order for the blink bit in the LED control register
 943          * to work, link and speed must be forced in the MAC. We
 944          * will reverse this when we stop the blinking.
 945          */
 946         macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 947         macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
 948         IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 949
 950         /* Set the LED to LINK_UP + BLINK. */
 951         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 952         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 953         ledctl_reg |= IXGBE_LED_BLINK(index);
 954         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 955         IXGBE_WRITE_FLUSH(hw);
 956
 957         return IXGBE_SUCCESS;
 958 }
 959
 960 /**
 961  * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
 962  * @hw: pointer to hardware structure
 963  * @index: led number to stop blinking
 964  *
 965  * Devices that implement the version 2 interface:
 966  *   X540
 967  **/
 968 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
 969 {
 970         u32 macc_reg;
 971         u32 ledctl_reg;
 972
 973         DEBUGFUNC("ixgbe_blink_led_stop_X540");
 974
 975         /* Restore the LED to its default value. */
 976         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 977         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 978         ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
 979         ledctl_reg &= ~IXGBE_LED_BLINK(index);
 980         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 981
 982         /* Unforce link and speed in the MAC. */
 983         macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 984         macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
 985         IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 986         IXGBE_WRITE_FLUSH(hw);
 987
 988         return IXGBE_SUCCESS;
 989 }
 990
 991