lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 /**
  42  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  43  *  @hw: pointer to hardware structure
  44  *
  45  *  Initialize the function pointers and assign the MAC type for X550.
  46  *  Does not touch the hardware.
  47  **/
  48 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  49 {
  50         struct ixgbe_mac_info *mac = &hw->mac;
  51         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  52         s32 ret_val;
  53
  54         DEBUGFUNC("ixgbe_init_ops_X550");
  55
  56         ret_val = ixgbe_init_ops_X540(hw);
  57         mac->ops.dmac_config = &ixgbe_dmac_config_X550;
  58         mac->ops.dmac_config_tcs = &ixgbe_dmac_config_tcs_X550;
  59         mac->ops.dmac_update_tcs = &ixgbe_dmac_update_tcs_X550;
  60         mac->ops.setup_eee = &ixgbe_setup_eee_X550;
  61         mac->ops.set_source_address_pruning =
  62                         &ixgbe_set_source_address_pruning_X550;
  63         mac->ops.set_ethertype_anti_spoofing =
  64                         &ixgbe_set_ethertype_anti_spoofing_X550;
  65
  66         mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
  67         eeprom->ops.init_params = &ixgbe_init_eeprom_params_X550;
  68         eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X550;
  69         eeprom->ops.read = &ixgbe_read_ee_hostif_X550;
  70         eeprom->ops.read_buffer = &ixgbe_read_ee_hostif_buffer_X550;
  71         eeprom->ops.write = &ixgbe_write_ee_hostif_X550;
  72         eeprom->ops.write_buffer = &ixgbe_write_ee_hostif_buffer_X550;
  73         eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X550;
  74         eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X550;
  75
  76         mac->ops.disable_mdd = &ixgbe_disable_mdd_X550;
  77         mac->ops.enable_mdd = &ixgbe_enable_mdd_X550;
  78         mac->ops.mdd_event = &ixgbe_mdd_event_X550;
  79         mac->ops.restore_mdd_vf = &ixgbe_restore_mdd_vf_X550;
  80         mac->ops.disable_rx = &ixgbe_disable_rx_x550;
  81         return ret_val;
  82 }
  83
  84 /**
  85  * ixgbe_identify_phy_x550em - Get PHY type based on device id
  86  * @hw: pointer to hardware structure
  87  *
  88  * Returns error code
  89  */
  90 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
  91 {
  92         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  93
  94         switch (hw->device_id) {
  95         case IXGBE_DEV_ID_X550EM_X_SFP:
  96                 /* set up for CS4227 usage */
  97                 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
  98                                  IXGBE_STATUS_LAN_ID_1;
  99                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 100                 if (hw->phy.lan_id) {
 101
 102                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 103                         esdp |= IXGBE_ESDP_SDP1_DIR;
 104                 }
 105                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 106                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 107
 108                 return ixgbe_identify_module_generic(hw);
 109                 break;
 110         case IXGBE_DEV_ID_X550EM_X_KX4:
 111                 hw->phy.type = ixgbe_phy_x550em_kx4;
 112                 break;
 113         case IXGBE_DEV_ID_X550EM_X_KR:
 114         case IXGBE_DEV_ID_X550EM_X:
 115                 hw->phy.type = ixgbe_phy_x550em_kr;
 116                 break;
 117         default:
 118                 break;
 119         }
 120         return IXGBE_SUCCESS;
 121 }
 122
 123 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 124                                      u32 device_type, u16 *phy_data)
 125 {
 126         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 127         return IXGBE_NOT_IMPLEMENTED;
 128 }
 129
 130 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 131                                       u32 device_type, u16 phy_data)
 132 {
 133         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 134         return IXGBE_NOT_IMPLEMENTED;
 135 }
 136
 137 /**
 138 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 139 *  @hw: pointer to hardware structure
 140 *
 141 *  Initialize the function pointers and for MAC type X550EM.
 142 *  Does not touch the hardware.
 143 **/
 144 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 145 {
 146         struct ixgbe_mac_info *mac = &hw->mac;
 147         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 148         struct ixgbe_phy_info *phy = &hw->phy;
 149         s32 ret_val;
 150
 151         DEBUGFUNC("ixgbe_init_ops_X550EM");
 152
 153         /* Similar to X550 so start there. */
 154         ret_val = ixgbe_init_ops_X550(hw);
 155
 156         /* Since this function eventually calls
 157          * ixgbe_init_ops_540 by design, we are setting
 158          * the pointers to NULL explicitly here to overwrite
 159          * the values being set in the x540 function.
 160          */
 161         /* Thermal sensor not supported in x550EM */
 162         mac->ops.get_thermal_sensor_data = NULL;
 163         mac->ops.init_thermal_sensor_thresh = NULL;
 164         mac->thermal_sensor_enabled = false;
 165
 166         /* FCOE not supported in x550EM */
 167         mac->ops.get_san_mac_addr = NULL;
 168         mac->ops.set_san_mac_addr = NULL;
 169         mac->ops.get_wwn_prefix = NULL;
 170         mac->ops.get_fcoe_boot_status = NULL;
 171
 172         /* IPsec not supported in x550EM */
 173         mac->ops.disable_sec_rx_path = NULL;
 174         mac->ops.enable_sec_rx_path = NULL;
 175
 176         /* PCIe bus info not supported in X550EM */
 177         mac->ops.get_bus_info = NULL;
 178
 179         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 180         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 181         mac->ops.get_media_type = &ixgbe_get_media_type_X550em;
 182         mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_X550em;
 183         mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_X550em;
 184         mac->ops.reset_hw = &ixgbe_reset_hw_X550em;
 185         mac->ops.get_supported_physical_layer =
 186                                     &ixgbe_get_supported_physical_layer_X550em;
 187
 188         /* PHY */
 189         phy->ops.init = &ixgbe_init_phy_ops_X550em;
 190         phy->ops.identify = &ixgbe_identify_phy_x550em;
 191         phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
 192         phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
 193         phy->ops.setup_link = ixgbe_setup_kr_x550em;
 194
 195
 196         /* EEPROM */
 197         eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
 198         eeprom->ops.read = &ixgbe_read_ee_hostif_X550;
 199         eeprom->ops.read_buffer = &ixgbe_read_ee_hostif_buffer_X550;
 200         eeprom->ops.write = &ixgbe_write_ee_hostif_X550;
 201         eeprom->ops.write_buffer = &ixgbe_write_ee_hostif_buffer_X550;
 202         eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X550;
 203         eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X550;
 204         eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X550;
 205
 206         return ret_val;
 207 }
 208
 209 /**
 210  *  ixgbe_dmac_config_X550
 211  *  @hw: pointer to hardware structure
 212  *
 213  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 214  *  When disabling dmac, dmac enable dmac bit is cleared.
 215  **/
 216 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 217 {
 218         u32 reg, high_pri_tc;
 219
 220         DEBUGFUNC("ixgbe_dmac_config_X550");
 221
 222         /* Disable DMA coalescing before configuring */
 223         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 224         reg &= ~IXGBE_DMACR_DMAC_EN;
 225         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 226
 227         /* Disable DMA Coalescing if the watchdog timer is 0 */
 228         if (!hw->mac.dmac_config.watchdog_timer)
 229                 goto out;
 230
 231         ixgbe_dmac_config_tcs_X550(hw);
 232
 233         /* Configure DMA Coalescing Control Register */
 234         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 235
 236         /* Set the watchdog timer in units of 40.96 usec */
 237         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 238         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 239
 240         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 241         /* If fcoe is enabled, set high priority traffic class */
 242         if (hw->mac.dmac_config.fcoe_en) {
 243                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 244                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 245                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 246         }
 247         reg |= IXGBE_DMACR_EN_MNG_IND;
 248
 249         /* Enable DMA coalescing after configuration */
 250         reg |= IXGBE_DMACR_DMAC_EN;
 251         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 252
 253 out:
 254         return IXGBE_SUCCESS;
 255 }
 256
 257 /**
 258  *  ixgbe_dmac_config_tcs_X550
 259  *  @hw: pointer to hardware structure
 260  *
 261  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 262  *  be cleared before configuring.
 263  **/
 264 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 265 {
 266         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 267
 268         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 269
 270         /* Configure DMA coalescing enabled */
 271         switch (hw->mac.dmac_config.link_speed) {
 272         case IXGBE_LINK_SPEED_100_FULL:
 273                 pb_headroom = IXGBE_DMACRXT_100M;
 274                 break;
 275         case IXGBE_LINK_SPEED_1GB_FULL:
 276                 pb_headroom = IXGBE_DMACRXT_1G;
 277                 break;
 278         default:
 279                 pb_headroom = IXGBE_DMACRXT_10G;
 280                 break;
 281         }
 282
 283         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 284                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 285
 286         /* Set the per Rx packet buffer receive threshold */
 287         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 288                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 289                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 290
 291                 if (tc < hw->mac.dmac_config.num_tcs) {
 292                         /* Get Rx PB size */
 293                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 294                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 295                                 IXGBE_RXPBSIZE_SHIFT;
 296
 297                         /* Calculate receive buffer threshold in kilobytes */
 298                         if (rx_pb_size > pb_headroom)
 299                                 rx_pb_size = rx_pb_size - pb_headroom;
 300                         else
 301                                 rx_pb_size = 0;
 302
 303                         /* Minimum of MFS shall be set for DMCTH */
 304                         reg |= (rx_pb_size > maxframe_size_kb) ?
 305                                 rx_pb_size : maxframe_size_kb;
 306                 }
 307                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 308         }
 309         return IXGBE_SUCCESS;
 310 }
 311
 312 /**
 313  *  ixgbe_dmac_update_tcs_X550
 314  *  @hw: pointer to hardware structure
 315  *
 316  *  Disables dmac, updates per TC settings, and then enables dmac.
 317  **/
 318 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 319 {
 320         u32 reg;
 321
 322         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 323
 324         /* Disable DMA coalescing before configuring */
 325         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 326         reg &= ~IXGBE_DMACR_DMAC_EN;
 327         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 328
 329         ixgbe_dmac_config_tcs_X550(hw);
 330
 331         /* Enable DMA coalescing after configuration */
 332         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 333         reg |= IXGBE_DMACR_DMAC_EN;
 334         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 335
 336         return IXGBE_SUCCESS;
 337 }
 338
 339 /**
 340  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 341  *  @hw: pointer to hardware structure
 342  *
 343  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 344  *  ixgbe_hw struct in order to set up EEPROM access.
 345  **/
 346 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 347 {
 348         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 349         u32 eec;
 350         u16 eeprom_size;
 351
 352         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 353
 354         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 355                 eeprom->semaphore_delay = 10;
 356                 eeprom->type = ixgbe_flash;
 357
 358                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 359                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 360                                     IXGBE_EEC_SIZE_SHIFT);
 361                 eeprom->word_size = 1 << (eeprom_size +
 362                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 363
 364                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 365                           eeprom->type, eeprom->word_size);
 366         }
 367
 368         return IXGBE_SUCCESS;
 369 }
 370
 371 /**
 372  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 373  *  @hw: pointer to the HW structure
 374  *  @enable_eee: boolean flag to enable EEE
 375  *
 376  *  Enable/disable EEE based on enable_eee flag.
 377  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 378  *  are modified.
 379  *
 380  **/
 381 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 382 {
 383         u32 eeer;
 384         u16 autoneg_eee_reg;
 385         u32 link_reg;
 386         s32 status;
 387
 388         DEBUGFUNC("ixgbe_setup_eee_X550");
 389
 390         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 391         /* Enable or disable EEE per flag */
 392         if (enable_eee) {
 393                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 394
 395                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 396                         /* Advertise EEE capability */
 397                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 398                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 399
 400                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 401                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 402                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 403
 404                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 405                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 406                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
 407                            hw->device_id == IXGBE_DEV_ID_X550EM_X) {
 408                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 409                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 410                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 411                         if (status != IXGBE_SUCCESS)
 412                                 return status;
 413
 414                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 415                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 416
 417                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 418                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 419                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 420                         if (status != IXGBE_SUCCESS)
 421                                 return status;
 422                 }
 423         } else {
 424                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 425
 426                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 427                         /* Disable advertised EEE capability */
 428                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 429                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 430
 431                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 432                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 433                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 434
 435                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 436                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 437                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
 438                            hw->device_id == IXGBE_DEV_ID_X550EM_X) {
 439                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 440                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 441                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 442                         if (status != IXGBE_SUCCESS)
 443                                 return status;
 444
 445                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 446                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 447
 448                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 449                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 450                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 451                         if (status != IXGBE_SUCCESS)
 452                                 return status;
 453                 }
 454         }
 455         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 456
 457         return IXGBE_SUCCESS;
 458 }
 459
 460 /**
 461  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 462  * @hw: pointer to hardware structure
 463  * @enable: enable or disable source address pruning
 464  * @pool: Rx pool to set source address pruning for
 465  **/
 466 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 467                                            unsigned int pool)
 468 {
 469         u64 pfflp;
 470
 471         /* max rx pool is 63 */
 472         if (pool > 63)
 473                 return;
 474
 475         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 476         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 477
 478         if (enable)
 479                 pfflp |= (1ULL << pool);
 480         else
 481                 pfflp &= ~(1ULL << pool);
 482
 483         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 484         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 485 }
 486
 487 /**
 488  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 489  *  @hw: pointer to hardware structure
 490  *  @enable: enable or disable switch for Ethertype anti-spoofing
 491  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 492  *
 493  **/
 494 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 495                 bool enable, int vf)
 496 {
 497         int vf_target_reg = vf >> 3;
 498         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 499         u32 pfvfspoof;
 500
 501         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 502
 503         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 504         if (enable)
 505                 pfvfspoof |= (1 << vf_target_shift);
 506         else
 507                 pfvfspoof &= ~(1 << vf_target_shift);
 508
 509         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 510 }
 511
 512 /**
 513  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 514  *  device
 515  *  @hw: pointer to hardware structure
 516  *  @reg_addr: 32 bit PHY register to write
 517  *  @device_type: 3 bit device type
 518  *  @data: Data to write to the register
 519  **/
 520 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 521                             u32 device_type, u32 data)
 522 {
 523         u32 i, command, error;
 524
 525         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 526                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 527
 528         /* Write IOSF control register */
 529         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 530
 531         /* Write IOSF data register */
 532         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 533         /*
 534          * Check every 10 usec to see if the address cycle completed.
 535          * The SB IOSF BUSY bit will clear when the operation is
 536          * complete
 537          */
 538         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 539                 usec_delay(10);
 540
 541                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 542                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 543                         break;
 544         }
 545
 546         if ((command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) != 0) {
 547                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 548                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 549                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 550                               "Failed to write, error %x\n", error);
 551                 return IXGBE_ERR_PHY;
 552         }
 553
 554         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 555                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 556                 return IXGBE_ERR_PHY;
 557         }
 558
 559         return IXGBE_SUCCESS;
 560 }
 561
 562 /**
 563  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 564  *  device
 565  *  @hw: pointer to hardware structure
 566  *  @reg_addr: 32 bit PHY register to write
 567  *  @device_type: 3 bit device type
 568  *  @phy_data: Pointer to read data from the register
 569  **/
 570 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 571                            u32 device_type, u32 *data)
 572 {
 573         u32 i, command, error;
 574
 575         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 576                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 577
 578         /* Write IOSF control register */
 579         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 580
 581         /*
 582          * Check every 10 usec to see if the address cycle completed.
 583          * The SB IOSF BUSY bit will clear when the operation is
 584          * complete
 585          */
 586         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 587                 usec_delay(10);
 588
 589                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 590                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 591                         break;
 592         }
 593
 594         if ((command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) != 0) {
 595                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 596                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 597                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 598                                 "Failed to read, error %x\n", error);
 599                 return IXGBE_ERR_PHY;
 600         }
 601
 602         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 603                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 604                 return IXGBE_ERR_PHY;
 605         }
 606
 607         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 608
 609         return IXGBE_SUCCESS;
 610 }
 611
 612 /**
 613  *  ixgbe_disable_mdd_X550
 614  *  @hw: pointer to hardware structure
 615  *
 616  *  Disable malicious driver detection
 617  **/
 618 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 619 {
 620         u32 reg;
 621
 622         DEBUGFUNC("ixgbe_disable_mdd_X550");
 623
 624         /* Disable MDD for TX DMA and interrupt */
 625         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 626         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 627         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 628
 629         /* Disable MDD for RX and interrupt */
 630         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 631         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 632         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 633 }
 634
 635 /**
 636  *  ixgbe_enable_mdd_X550
 637  *  @hw: pointer to hardware structure
 638  *
 639  *  Enable malicious driver detection
 640  **/
 641 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 642 {
 643         u32 reg;
 644
 645         DEBUGFUNC("ixgbe_enable_mdd_X550");
 646
 647         /* Enable MDD for TX DMA and interrupt */
 648         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 649         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 650         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 651
 652         /* Enable MDD for RX and interrupt */
 653         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 654         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 655         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 656 }
 657
 658 /**
 659  *  ixgbe_restore_mdd_vf_X550
 660  *  @hw: pointer to hardware structure
 661  *  @vf: vf index
 662  *
 663  *  Restore VF that was disabled during malicious driver detection event
 664  **/
 665 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 666 {
 667         u32 idx, reg, num_qs, start_q, bitmask;
 668
 669         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 670
 671         /* Map VF to queues */
 672         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 673         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 674         case IXGBE_MRQC_VMDQRT8TCEN:
 675                 num_qs = 8;  /* 16 VFs / pools */
 676                 bitmask = 0x000000FF;
 677                 break;
 678         case IXGBE_MRQC_VMDQRSS32EN:
 679         case IXGBE_MRQC_VMDQRT4TCEN:
 680                 num_qs = 4;  /* 32 VFs / pools */
 681                 bitmask = 0x0000000F;
 682                 break;
 683         default:            /* 64 VFs / pools */
 684                 num_qs = 2;
 685                 bitmask = 0x00000003;
 686                 break;
 687         }
 688         start_q = vf * num_qs;
 689
 690         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 691         idx = start_q / 32;
 692         reg = 0;
 693         reg |= (bitmask << (start_q % 32));
 694         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 695         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 696 }
 697
 698 /**
 699  *  ixgbe_mdd_event_X550
 700  *  @hw: pointer to hardware structure
 701  *  @vf_bitmap: vf bitmap of malicious vfs
 702  *
 703  *  Handle malicious driver detection event.
 704  **/
 705 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 706 {
 707         u32 wqbr;
 708         u32 i, j, reg, q, shift, vf, idx;
 709
 710         DEBUGFUNC("ixgbe_mdd_event_X550");
 711
 712         /* figure out pool size for mapping to vf's */
 713         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 714         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 715         case IXGBE_MRQC_VMDQRT8TCEN:
 716                 shift = 3;  /* 16 VFs / pools */
 717                 break;
 718         case IXGBE_MRQC_VMDQRSS32EN:
 719         case IXGBE_MRQC_VMDQRT4TCEN:
 720                 shift = 2;  /* 32 VFs / pools */
 721                 break;
 722         default:
 723                 shift = 1;  /* 64 VFs / pools */
 724                 break;
 725         }
 726
 727         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 728         for (i = 0; i < 4; i++) {
 729                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 730                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 731
 732                 if (!wqbr)
 733                         continue;
 734
 735                 /* Get malicious queue */
 736                 for (j = 0; j < 32 && wqbr; j++) {
 737
 738                         if (!(wqbr & (1 << j)))
 739                                 continue;
 740
 741                         /* Get queue from bitmask */
 742                         q = j + (i * 32);
 743
 744                         /* Map queue to vf */
 745                         vf = (q >> shift);
 746
 747                         /* Set vf bit in vf_bitmap */
 748                         idx = vf / 32;
 749                         vf_bitmap[idx] |= (1 << (vf % 32));
 750                         wqbr &= ~(1 << j);
 751                 }
 752         }
 753 }
 754
 755 /**
 756  *  ixgbe_get_media_type_X550em - Get media type
 757  *  @hw: pointer to hardware structure
 758  *
 759  *  Returns the media type (fiber, copper, backplane)
 760  */
 761 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 762 {
 763         enum ixgbe_media_type media_type;
 764
 765         DEBUGFUNC("ixgbe_get_media_type_X550em");
 766
 767         /* Detect if there is a copper PHY attached. */
 768         switch (hw->device_id) {
 769         case IXGBE_DEV_ID_X550EM_X:
 770         case IXGBE_DEV_ID_X550EM_X_KR:
 771         case IXGBE_DEV_ID_X550EM_X_KX4:
 772                 media_type = ixgbe_media_type_backplane;
 773                 break;
 774         case IXGBE_DEV_ID_X550EM_X_SFP:
 775                 media_type = ixgbe_media_type_fiber;
 776                 break;
 777         default:
 778                 media_type = ixgbe_media_type_unknown;
 779                 break;
 780         }
 781         return media_type;
 782 }
 783
 784 /**
 785  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 786  *  @hw: pointer to hardware structure
 787  */
 788 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 789 {
 790         bool setup_linear;
 791         u16 reg_slice, edc_mode;
 792
 793         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
 794
 795         switch (hw->phy.sfp_type) {
 796         case ixgbe_sfp_type_unknown:
 797                 return IXGBE_SUCCESS;
 798         case ixgbe_sfp_type_not_present:
 799                 return IXGBE_ERR_SFP_NOT_PRESENT;
 800         case ixgbe_sfp_type_da_cu_core0:
 801         case ixgbe_sfp_type_da_cu_core1:
 802                 setup_linear = true;
 803                 break;
 804         case ixgbe_sfp_type_srlr_core0:
 805         case ixgbe_sfp_type_srlr_core1:
 806         case ixgbe_sfp_type_da_act_lmt_core0:
 807         case ixgbe_sfp_type_da_act_lmt_core1:
 808         case ixgbe_sfp_type_1g_sx_core0:
 809         case ixgbe_sfp_type_1g_sx_core1:
 810         case ixgbe_sfp_type_1g_lx_core0:
 811         case ixgbe_sfp_type_1g_lx_core1:
 812                 setup_linear = false;
 813                 break;
 814         default:
 815                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 816         }
 817
 818         ixgbe_init_mac_link_ops_X550em(hw);
 819         hw->phy.ops.reset = NULL;
 820
 821         /* The CS4227 slice address is the base address + the port-pair reg
 822          * offset. I.e. Slice 0 = 0x0000 and slice 1 = 0x1000.
 823          */
 824         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->phy.lan_id << 12);
 825
 826         if (setup_linear)
 827                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 828         else
 829                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 830
 831         /* Configure CS4227 for connection type. */
 832         return hw->phy.ops.write_i2c_combined(hw, IXGBE_CS4227,
 833                                               reg_slice, edc_mode);
 834 }
 835
 836 /**
 837  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
 838  *  @hw: pointer to hardware structure
 839  */
 840 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
 841 {
 842         struct ixgbe_mac_info *mac = &hw->mac;
 843
 844         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
 845
 846         /* CS4227 does not support autoneg, so disable the laser control
 847          * functions for SFP+ fiber
 848          */
 849          if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 850                 mac->ops.disable_tx_laser = NULL;
 851                 mac->ops.enable_tx_laser = NULL;
 852                 mac->ops.flap_tx_laser = NULL;
 853          }
 854 }
 855
 856 /**
 857  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
 858  *  @hw: pointer to hardware structure
 859  *  @speed: pointer to link speed
 860  *  @autoneg: true when autoneg or autotry is enabled
 861  */
 862 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
 863                                        ixgbe_link_speed *speed,
 864                                        bool *autoneg)
 865 {
 866         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
 867
 868         /* SFP */
 869         if (hw->phy.media_type == ixgbe_media_type_fiber) {
 870
 871                 /* CS4227 SFP must not enable auto-negotiation */
 872                 *autoneg = false;
 873
 874                 /* Check if 1G SFP module. */
 875                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
 876                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
 877                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
 878                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
 879                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
 880                         return IXGBE_SUCCESS;
 881                 }
 882
 883                 /* Link capabilities are based on SFP */
 884                 if (hw->phy.multispeed_fiber)
 885                         *speed |= IXGBE_LINK_SPEED_10GB_FULL |
 886                                   IXGBE_LINK_SPEED_1GB_FULL;
 887                 else
 888                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 889         } else {
 890                 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
 891                           IXGBE_LINK_SPEED_1GB_FULL;
 892                 *autoneg = true;
 893         }
 894
 895         return IXGBE_SUCCESS;
 896 }
 897
 898 /**
 899  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
 900  *  @hw: pointer to hardware structure
 901  *
 902  *  Initialize any function pointers that were not able to be
 903  *  set during init_shared_code because the PHY/SFP type was
 904  *  not known.  Perform the SFP init if necessary.
 905  */
 906 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
 907 {
 908         struct ixgbe_phy_info *phy = &hw->phy;
 909         s32 ret_val;
 910         u32 esdp;
 911
 912         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
 913
 914         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 915                 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 916                 phy->lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
 917                               IXGBE_STATUS_LAN_ID_1;
 918                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 919                 if (phy->lan_id) {
 920                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 921                         esdp |= IXGBE_ESDP_SDP1_DIR;
 922                 }
 923                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 924                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 925         }
 926
 927         /* Identify the PHY or SFP module */
 928         ret_val = phy->ops.identify(hw);
 929         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
 930                 return ret_val;
 931
 932         /* Setup function pointers based on detected SFP module and speeds */
 933         ixgbe_init_mac_link_ops_X550em(hw);
 934         if (phy->sfp_type != ixgbe_sfp_type_unknown)
 935                 phy->ops.reset = NULL;
 936
 937         /* Set functions pointers based on phy type */
 938         switch (hw->phy.type) {
 939         case ixgbe_phy_x550em_kr:
 940                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
 941                 break;
 942         default:
 943                 break;
 944         }
 945         return ret_val;
 946 }
 947
 948 /**
 949  *  ixgbe_reset_hw_X550em - Perform hardware reset
 950  *  @hw: pointer to hardware structure
 951  *
 952  *  Resets the hardware by resetting the transmit and receive units, masks
 953  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
 954  *  reset.
 955  */
 956 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
 957 {
 958         ixgbe_link_speed link_speed;
 959         s32 status;
 960         u32 ctrl = 0;
 961         u32 i;
 962         bool link_up = false;
 963
 964         DEBUGFUNC("ixgbe_reset_hw_X550em");
 965
 966         /* Call adapter stop to disable Tx/Rx and clear interrupts */
 967         status = hw->mac.ops.stop_adapter(hw);
 968         if (status != IXGBE_SUCCESS)
 969                 return status;
 970
 971         /* flush pending Tx transactions */
 972         ixgbe_clear_tx_pending(hw);
 973
 974         /* PHY ops must be identified and initialized prior to reset */
 975
 976         /* Identify PHY and related function pointers */
 977         status = hw->phy.ops.init(hw);
 978
 979         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 980                 return status;
 981
 982         /* Setup SFP module if there is one present. */
 983         if (hw->phy.sfp_setup_needed) {
 984                 status = hw->mac.ops.setup_sfp(hw);
 985                 hw->phy.sfp_setup_needed = false;
 986         }
 987
 988         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 989                 return status;
 990
 991         /* Reset PHY */
 992         if (!hw->phy.reset_disable && hw->phy.ops.reset)
 993                 hw->phy.ops.reset(hw);
 994
 995 mac_reset_top:
 996         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
 997          * If link reset is used when link is up, it might reset the PHY when
 998          * mng is using it.  If link is down or the flag to force full link
 999          * reset is set, then perform link reset.
1000          */
1001         ctrl = IXGBE_CTRL_LNK_RST;
1002         if (!hw->force_full_reset) {
1003                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1004                 if (link_up)
1005                         ctrl = IXGBE_CTRL_RST;
1006         }
1007
1008         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1009         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1010         IXGBE_WRITE_FLUSH(hw);
1011
1012         /* Poll for reset bit to self-clear meaning reset is complete */
1013         for (i = 0; i < 10; i++) {
1014                 usec_delay(1);
1015                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1016                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1017                         break;
1018         }
1019
1020         if (ctrl & IXGBE_CTRL_RST_MASK) {
1021                 status = IXGBE_ERR_RESET_FAILED;
1022                 DEBUGOUT("Reset polling failed to complete.\n");
1023         }
1024
1025         msec_delay(50);
1026
1027         /* Double resets are required for recovery from certain error
1028          * conditions.  Between resets, it is necessary to stall to
1029          * allow time for any pending HW events to complete.
1030          */
1031         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1032                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1033                 goto mac_reset_top;
1034         }
1035
1036         /* Store the permanent mac address */
1037         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1038
1039         /* Store MAC address from RAR0, clear receive address registers, and
1040          * clear the multicast table.  Also reset num_rar_entries to 128,
1041          * since we modify this value when programming the SAN MAC address.
1042          */
1043         hw->mac.num_rar_entries = 128;
1044         hw->mac.ops.init_rx_addrs(hw);
1045
1046         return status;
1047 }
1048
1049 /**
1050  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1051  *  @hw: pointer to hardware structure
1052  *
1053  *  Configures the integrated KR PHY.
1054  **/
1055 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1056 {
1057         s32 status;
1058         u32 reg_val;
1059
1060         status = ixgbe_read_iosf_sb_reg_x550(hw,
1061                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1062                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1063
1064         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1065         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ;
1066         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1067         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1068                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1069
1070         /* Advertise 10G support. */
1071         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1072                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1073
1074         /* Advertise 1G support. */
1075         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1076                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1077
1078         /* Restart auto-negotiation. */
1079         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1080         status = ixgbe_write_iosf_sb_reg_x550(hw,
1081                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1082                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1083
1084         return status;
1085 }
1086
1087 /**
1088  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI.
1089  *  @hw: pointer to hardware structure
1090  *
1091  *  Configures the integrated KR PHY to use iXFI mode.
1092  **/
1093 s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw)
1094 {
1095         s32 status;
1096         u32 reg_val;
1097
1098         /* Disable AN and force speed to 10G Serial. */
1099         status = ixgbe_read_iosf_sb_reg_x550(hw,
1100                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1101                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1102         if (status != IXGBE_SUCCESS)
1103                 return status;
1104         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1105         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1106         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1107         status = ixgbe_write_iosf_sb_reg_x550(hw,
1108                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1109                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1110         if (status != IXGBE_SUCCESS)
1111                 return status;
1112
1113         /* Disable training protocol FSM. */
1114         status = ixgbe_read_iosf_sb_reg_x550(hw,
1115                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1116                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1117         if (status != IXGBE_SUCCESS)
1118                 return status;
1119         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1120         status = ixgbe_write_iosf_sb_reg_x550(hw,
1121                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1122                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1123         if (status != IXGBE_SUCCESS)
1124                 return status;
1125
1126         /* Disable Flex from training TXFFE. */
1127         status = ixgbe_read_iosf_sb_reg_x550(hw,
1128                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),
1129                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1130         if (status != IXGBE_SUCCESS)
1131                 return status;
1132         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1133         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1134         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1135         status = ixgbe_write_iosf_sb_reg_x550(hw,
1136                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),
1137                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1138         if (status != IXGBE_SUCCESS)
1139                 return status;
1140         status = ixgbe_read_iosf_sb_reg_x550(hw,
1141                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),
1142                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1143         if (status != IXGBE_SUCCESS)
1144                 return status;
1145         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1146         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1147         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1148         status = ixgbe_write_iosf_sb_reg_x550(hw,
1149                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),
1150                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1151         if (status != IXGBE_SUCCESS)
1152                 return status;
1153
1154         /* Enable override for coefficients. */
1155         status = ixgbe_read_iosf_sb_reg_x550(hw,
1156                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),
1157                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1158         if (status != IXGBE_SUCCESS)
1159                 return status;
1160         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1161         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1162         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1163         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1164         status = ixgbe_write_iosf_sb_reg_x550(hw,
1165                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),
1166                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1167         if (status != IXGBE_SUCCESS)
1168                 return status;
1169
1170         /* Toggle port SW reset by AN reset. */
1171         status = ixgbe_read_iosf_sb_reg_x550(hw,
1172                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1173                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1174         if (status != IXGBE_SUCCESS)
1175                 return status;
1176         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1177         status = ixgbe_write_iosf_sb_reg_x550(hw,
1178                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1179                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1180
1181         return status;
1182 }
1183
1184 /**
1185  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1186  *  @hw: pointer to hardware structure
1187  *
1188  *  Configures the integrated KR PHY to use internal loopback mode.
1189  **/
1190 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1191 {
1192         s32 status;
1193         u32 reg_val;
1194
1195         /* Disable AN and force speed to 10G Serial. */
1196         status = ixgbe_read_iosf_sb_reg_x550(hw,
1197                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1198                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1199         if (status != IXGBE_SUCCESS)
1200                 return status;
1201         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1202         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1203         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1204         status = ixgbe_write_iosf_sb_reg_x550(hw,
1205                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1206                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1207         if (status != IXGBE_SUCCESS)
1208                 return status;
1209
1210         /* Set near-end loopback clocks. */
1211         status = ixgbe_read_iosf_sb_reg_x550(hw,
1212                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),
1213                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1214         if (status != IXGBE_SUCCESS)
1215                 return status;
1216         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1217         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1218         status = ixgbe_write_iosf_sb_reg_x550(hw,
1219                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),
1220                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1221         if (status != IXGBE_SUCCESS)
1222                 return status;
1223
1224         /* Set loopback enable. */
1225         status = ixgbe_read_iosf_sb_reg_x550(hw,
1226                 IXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),
1227                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1228         if (status != IXGBE_SUCCESS)
1229                 return status;
1230         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1231         status = ixgbe_write_iosf_sb_reg_x550(hw,
1232                 IXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),
1233                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1234         if (status != IXGBE_SUCCESS)
1235                 return status;
1236
1237         /* Training bypass. */
1238         status = ixgbe_read_iosf_sb_reg_x550(hw,
1239                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1240                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1241         if (status != IXGBE_SUCCESS)
1242                 return status;
1243         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1244         status = ixgbe_write_iosf_sb_reg_x550(hw,
1245                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1246                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1247
1248         return status;
1249 }
1250
1251 /**
1252  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1253  *  assuming that the semaphore is already obtained.
1254  *  @hw: pointer to hardware structure
1255  *  @offset: offset of  word in the EEPROM to read
1256  *  @data: word read from the EEPROM
1257  *
1258  *  Reads a 16 bit word from the EEPROM using the hostif.
1259  **/
1260 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1261                                    u16 *data)
1262 {
1263         s32 status;
1264         struct ixgbe_hic_read_shadow_ram buffer;
1265
1266         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1267         buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1268         buffer.hdr.buf_len1 = 0;
1269         buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1270         buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1271
1272         /* convert offset from words to bytes */
1273         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1274         /* one word */
1275         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1276
1277         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1278                                               sizeof(buffer), false);
1279
1280         if (status)
1281                 return status;
1282
1283         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1284                                           FW_NVM_DATA_OFFSET);
1285
1286         return 0;
1287 }
1288
1289 /**
1290  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1291  *  @hw: pointer to hardware structure
1292  *  @offset: offset of  word in the EEPROM to read
1293  *  @data: word read from the EEPROM
1294  *
1295  *  Reads a 16 bit word from the EEPROM using the hostif.
1296  **/
1297 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1298                               u16 *data)
1299 {
1300         s32 status = IXGBE_SUCCESS;
1301
1302         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1303
1304         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1305             IXGBE_SUCCESS) {
1306                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1307                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1308         } else {
1309                 status = IXGBE_ERR_SWFW_SYNC;
1310         }
1311
1312         return status;
1313 }
1314
1315 /**
1316  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1317  *  @hw: pointer to hardware structure
1318  *  @offset: offset of  word in the EEPROM to read
1319  *  @words: number of words
1320  *  @data: word(s) read from the EEPROM
1321  *
1322  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1323  **/
1324 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1325                                      u16 offset, u16 words, u16 *data)
1326 {
1327         struct ixgbe_hic_read_shadow_ram buffer;
1328         u32 current_word = 0;
1329         u16 words_to_read;
1330         s32 status;
1331         u32 i;
1332
1333         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1334
1335         /* Take semaphore for the entire operation. */
1336         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1337         if (status) {
1338                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1339                 return status;
1340         }
1341         while (words) {
1342                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1343                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1344                 else
1345                         words_to_read = words;
1346
1347                 buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1348                 buffer.hdr.buf_len1 = 0;
1349                 buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1350                 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1351
1352                 /* convert offset from words to bytes */
1353                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1354                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1355
1356                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1357                                                       sizeof(buffer), false);
1358
1359                 if (status) {
1360                         DEBUGOUT("Host interface command failed\n");
1361                         goto out;
1362                 }
1363
1364                 for (i = 0; i < words_to_read; i++) {
1365                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1366                                   2 * i;
1367                         u32 value = IXGBE_READ_REG(hw, reg);
1368
1369                         data[current_word] = (u16)(value & 0xffff);
1370                         current_word++;
1371                         i++;
1372                         if (i < words_to_read) {
1373                                 value >>= 16;
1374                                 data[current_word] = (u16)(value & 0xffff);
1375                                 current_word++;
1376                         }
1377                 }
1378                 words -= words_to_read;
1379         }
1380
1381 out:
1382         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1383         return status;
1384 }
1385
1386 /**
1387  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1388  *  @hw: pointer to hardware structure
1389  *  @offset: offset of  word in the EEPROM to write
1390  *  @data: word write to the EEPROM
1391  *
1392  *  Write a 16 bit word to the EEPROM using the hostif.
1393  **/
1394 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1395                                     u16 data)
1396 {
1397         s32 status;
1398         struct ixgbe_hic_write_shadow_ram buffer;
1399
1400         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1401
1402         buffer.hdr.cmd = FW_WRITE_SHADOW_RAM_CMD;
1403         buffer.hdr.buf_len1 = 0;
1404         buffer.hdr.buf_len2 = FW_WRITE_SHADOW_RAM_LEN;
1405         buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1406
1407          /* one word */
1408         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1409         buffer.data = data;
1410         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1411
1412         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1413                                               sizeof(buffer), false);
1414
1415         return status;
1416 }
1417
1418 /**
1419  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1420  *  @hw: pointer to hardware structure
1421  *  @offset: offset of  word in the EEPROM to write
1422  *  @data: word write to the EEPROM
1423  *
1424  *  Write a 16 bit word to the EEPROM using the hostif.
1425  **/
1426 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1427                                u16 data)
1428 {
1429         s32 status = IXGBE_SUCCESS;
1430
1431         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1432
1433         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1434             IXGBE_SUCCESS) {
1435                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1436                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1437         } else {
1438                 DEBUGOUT("write ee hostif failed to get semaphore");
1439                 status = IXGBE_ERR_SWFW_SYNC;
1440         }
1441
1442         return status;
1443 }
1444
1445 /**
1446  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1447  *  @hw: pointer to hardware structure
1448  *  @offset: offset of  word in the EEPROM to write
1449  *  @words: number of words
1450  *  @data: word(s) write to the EEPROM
1451  *
1452  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1453  **/
1454 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1455                                       u16 offset, u16 words, u16 *data)
1456 {
1457         s32 status = IXGBE_SUCCESS;
1458         u32 i = 0;
1459
1460         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1461
1462         /* Take semaphore for the entire operation. */
1463         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1464         if (status != IXGBE_SUCCESS) {
1465                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1466                 goto out;
1467         }
1468
1469         for (i = 0; i < words; i++) {
1470                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1471                                                          data[i]);
1472
1473                 if (status != IXGBE_SUCCESS) {
1474                         DEBUGOUT("Eeprom buffered write failed\n");
1475                         break;
1476                 }
1477         }
1478
1479         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1480 out:
1481
1482         return status;
1483 }
1484
1485 /**
1486  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1487  * @hw: pointer to hardware structure
1488  * @ptr: pointer offset in eeprom
1489  * @size: size of section pointed by ptr, if 0 first word will be used as size
1490  * @csum: address of checksum to update
1491  *
1492  * Returns error status for any failure
1493  */
1494 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1495                                    u16 size, u16 *csum)
1496 {
1497         u16 buf[256];
1498         s32 status;
1499         u16 length, bufsz, i, start;
1500
1501         bufsz = sizeof(buf) / sizeof(buf[0]);
1502
1503         /* Read a chunk at the pointer location */
1504         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1505         if (status) {
1506                 DEBUGOUT("Failed to read EEPROM image\n");
1507                 return status;
1508         }
1509
1510         if (size) {
1511                 start = 0;
1512                 length = size;
1513         } else {
1514                 start = 1;
1515                 length = buf[0];
1516
1517                 /* Skip pointer section if length is invalid. */
1518                 if (length == 0xFFFF || length == 0 ||
1519                     (ptr + length) >= hw->eeprom.word_size)
1520                         return IXGBE_SUCCESS;
1521         }
1522
1523         for (i = start; length; i++, length--) {
1524                 if (i == bufsz) {
1525                         ptr += bufsz;
1526                         i = 0;
1527                         if (length < bufsz)
1528                                 bufsz = length;
1529
1530                         /* Read a chunk at the pointer location */
1531                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1532                                                                   bufsz, buf);
1533                         if (status) {
1534                                 DEBUGOUT("Failed to read EEPROM image\n");
1535                                 return status;
1536                         }
1537                 }
1538                 *csum += buf[i];
1539         }
1540         return IXGBE_SUCCESS;
1541 }
1542
1543 /**
1544  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1545  *  @hw: pointer to hardware structure
1546  *
1547  *  Returns a negative error code on error, or the 16-bit checksum
1548  **/
1549 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1550 {
1551         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1552         s32 status;
1553         u16 checksum = 0;
1554         u16 pointer, i, size;
1555
1556         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
1557
1558         hw->eeprom.ops.init_params(hw);
1559
1560         /* Read pointer area */
1561         status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1562                                                   IXGBE_EEPROM_LAST_WORD + 1,
1563                                                   eeprom_ptrs);
1564         if (status) {
1565                 DEBUGOUT("Failed to read EEPROM image\n");
1566                 return status;
1567         }
1568
1569         /*
1570          * For X550 hardware include 0x0-0x41 in the checksum, skip the
1571          * checksum word itself
1572          */
1573         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1574                 if (i != IXGBE_EEPROM_CHECKSUM)
1575                         checksum += eeprom_ptrs[i];
1576
1577         /*
1578          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
1579          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1580          */
1581         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1582                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1583                         continue;
1584
1585                 pointer = eeprom_ptrs[i];
1586
1587                 /* Skip pointer section if the pointer is invalid. */
1588                 if (pointer == 0xFFFF || pointer == 0 ||
1589                     pointer >= hw->eeprom.word_size)
1590                         continue;
1591
1592                 switch (i) {
1593                 case IXGBE_PCIE_GENERAL_PTR:
1594                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1595                         break;
1596                 case IXGBE_PCIE_CONFIG0_PTR:
1597                 case IXGBE_PCIE_CONFIG1_PTR:
1598                         size = IXGBE_PCIE_CONFIG_SIZE;
1599                         break;
1600                 default:
1601                         size = 0;
1602                         break;
1603                 }
1604
1605                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum);
1606                 if (status)
1607                         return status;
1608         }
1609
1610         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1611
1612         return (s32)checksum;
1613 }
1614
1615 /**
1616  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1617  *  @hw: pointer to hardware structure
1618  *  @checksum_val: calculated checksum
1619  *
1620  *  Performs checksum calculation and validates the EEPROM checksum.  If the
1621  *  caller does not need checksum_val, the value can be NULL.
1622  **/
1623 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
1624                                         u16 *checksum_val)
1625 {
1626         s32 status;
1627         u16 checksum;
1628         u16 read_checksum = 0;
1629
1630         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
1631
1632         /* Read the first word from the EEPROM. If this times out or fails, do
1633          * not continue or we could be in for a very long wait while every
1634          * EEPROM read fails
1635          */
1636         status = hw->eeprom.ops.read(hw, 0, &checksum);
1637         if (status) {
1638                 DEBUGOUT("EEPROM read failed\n");
1639                 return status;
1640         }
1641
1642         status = hw->eeprom.ops.calc_checksum(hw);
1643         if (status < 0)
1644                 return status;
1645
1646         checksum = (u16)(status & 0xffff);
1647
1648         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1649                                            &read_checksum);
1650         if (status)
1651                 return status;
1652
1653         /* Verify read checksum from EEPROM is the same as
1654          * calculated checksum
1655          */
1656         if (read_checksum != checksum) {
1657                 status = IXGBE_ERR_EEPROM_CHECKSUM;
1658                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1659                              "Invalid EEPROM checksum");
1660         }
1661
1662         /* If the user cares, return the calculated checksum */
1663         if (checksum_val)
1664                 *checksum_val = checksum;
1665
1666         return status;
1667 }
1668
1669 /**
1670  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1671  * @hw: pointer to hardware structure
1672  *
1673  * After writing EEPROM to shadow RAM using EEWR register, software calculates
1674  * checksum and updates the EEPROM and instructs the hardware to update
1675  * the flash.
1676  **/
1677 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1678 {
1679         s32 status;
1680         u16 checksum = 0;
1681
1682         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
1683
1684         /* Read the first word from the EEPROM. If this times out or fails, do
1685          * not continue or we could be in for a very long wait while every
1686          * EEPROM read fails
1687          */
1688         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1689         if (status) {
1690                 DEBUGOUT("EEPROM read failed\n");
1691                 return status;
1692         }
1693
1694         status = ixgbe_calc_eeprom_checksum_X550(hw);
1695         if (status < 0)
1696                 return status;
1697
1698         checksum = (u16)(status & 0xffff);
1699
1700         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1701                                             checksum);
1702         if (status)
1703                 return status;
1704
1705         status = ixgbe_update_flash_X550(hw);
1706
1707         return status;
1708 }
1709
1710 /**
1711  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1712  *  @hw: pointer to hardware structure
1713  *
1714  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1715  **/
1716 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1717 {
1718         s32 status = IXGBE_SUCCESS;
1719         struct ixgbe_hic_hdr2 buffer;
1720
1721         DEBUGFUNC("ixgbe_update_flash_X550");
1722
1723         buffer.cmd = FW_SHADOW_RAM_DUMP_CMD;
1724         buffer.buf_len1 = 0;
1725         buffer.buf_len2 = FW_SHADOW_RAM_DUMP_LEN;
1726         buffer.checksum = FW_DEFAULT_CHECKSUM;
1727
1728         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1729                                               sizeof(buffer), false);
1730
1731         return status;
1732 }
1733
1734 /**
1735  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
1736  *  @hw: pointer to hardware structure
1737  *
1738  *  Determines physical layer capabilities of the current configuration.
1739  **/
1740 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
1741 {
1742         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1743
1744         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
1745
1746         hw->phy.ops.identify(hw);
1747
1748         switch (hw->phy.type) {
1749         case ixgbe_phy_x550em_kr:
1750                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
1751                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1752                 break;
1753         case ixgbe_phy_x550em_kx4:
1754                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1755                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1756                 break;
1757         default:
1758                 break;
1759         }
1760
1761         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
1762                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
1763
1764         return physical_layer;
1765 }
1766
1767 /**
1768  * ixgbe_disable_rx_x550 - Disable RX unit
1769  *
1770  * Enables the Rx DMA unit for x550
1771  **/
1772 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1773 {
1774         u32 rxctrl, pfdtxgswc;
1775         s32 status;
1776         struct ixgbe_hic_disable_rxen fw_cmd;
1777
1778         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
1779
1780         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1781         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1782                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1783                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1784                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1785                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1786                         hw->mac.set_lben = true;
1787                 } else {
1788                         hw->mac.set_lben = false;
1789                 }
1790
1791                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1792                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1793                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1794                 fw_cmd.port_number = hw->phy.lan_id;
1795
1796                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1797                                         sizeof(struct ixgbe_hic_disable_rxen),
1798                                         true);
1799
1800                 /* If we fail - disable RX using register write */
1801                 if (status) {
1802                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1803                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1804                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1805                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1806                         }
1807                 }
1808         }
1809 }