lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 /**
  42  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  43  *  @hw: pointer to hardware structure
  44  *
  45  *  Initialize the function pointers and assign the MAC type for X550.
  46  *  Does not touch the hardware.
  47  **/
  48 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  49 {
  50         struct ixgbe_mac_info *mac = &hw->mac;
  51         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  52         s32 ret_val;
  53
  54         DEBUGFUNC("ixgbe_init_ops_X550");
  55
  56         ret_val = ixgbe_init_ops_X540(hw);
  57         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  58         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  59         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  60         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  61         mac->ops.set_source_address_pruning =
  62                         ixgbe_set_source_address_pruning_X550;
  63         mac->ops.set_ethertype_anti_spoofing =
  64                         ixgbe_set_ethertype_anti_spoofing_X550;
  65
  66         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  67         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  68         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  69         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  70         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  71         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  72         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  73         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  74         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  75
  76         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  77         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  78         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  79         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  80         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  81         return ret_val;
  82 }
  83
  84 /**
  85  * ixgbe_identify_phy_x550em - Get PHY type based on device id
  86  * @hw: pointer to hardware structure
  87  *
  88  * Returns error code
  89  */
  90 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
  91 {
  92         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  93
  94         switch (hw->device_id) {
  95         case IXGBE_DEV_ID_X550EM_X_SFP:
  96                 /* set up for CS4227 usage */
  97                 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
  98                                  IXGBE_STATUS_LAN_ID_1;
  99                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 100                 if (hw->phy.lan_id) {
 101
 102                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 103                         esdp |= IXGBE_ESDP_SDP1_DIR;
 104                 }
 105                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 106                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 107
 108                 return ixgbe_identify_module_generic(hw);
 109                 break;
 110         case IXGBE_DEV_ID_X550EM_X_KX4:
 111                 hw->phy.type = ixgbe_phy_x550em_kx4;
 112                 break;
 113         case IXGBE_DEV_ID_X550EM_X_KR:
 114         case IXGBE_DEV_ID_X550EM_X:
 115                 hw->phy.type = ixgbe_phy_x550em_kr;
 116                 break;
 117         default:
 118                 break;
 119         }
 120         return IXGBE_SUCCESS;
 121 }
 122
 123 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 124                                      u32 device_type, u16 *phy_data)
 125 {
 126         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 127         return IXGBE_NOT_IMPLEMENTED;
 128 }
 129
 130 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 131                                       u32 device_type, u16 phy_data)
 132 {
 133         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 134         return IXGBE_NOT_IMPLEMENTED;
 135 }
 136
 137 /**
 138 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 139 *  @hw: pointer to hardware structure
 140 *
 141 *  Initialize the function pointers and for MAC type X550EM.
 142 *  Does not touch the hardware.
 143 **/
 144 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 145 {
 146         struct ixgbe_mac_info *mac = &hw->mac;
 147         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 148         struct ixgbe_phy_info *phy = &hw->phy;
 149         s32 ret_val;
 150
 151         DEBUGFUNC("ixgbe_init_ops_X550EM");
 152
 153         /* Similar to X550 so start there. */
 154         ret_val = ixgbe_init_ops_X550(hw);
 155
 156         /* Since this function eventually calls
 157          * ixgbe_init_ops_540 by design, we are setting
 158          * the pointers to NULL explicitly here to overwrite
 159          * the values being set in the x540 function.
 160          */
 161         /* Thermal sensor not supported in x550EM */
 162         mac->ops.get_thermal_sensor_data = NULL;
 163         mac->ops.init_thermal_sensor_thresh = NULL;
 164         mac->thermal_sensor_enabled = false;
 165
 166         /* FCOE not supported in x550EM */
 167         mac->ops.get_san_mac_addr = NULL;
 168         mac->ops.set_san_mac_addr = NULL;
 169         mac->ops.get_wwn_prefix = NULL;
 170         mac->ops.get_fcoe_boot_status = NULL;
 171
 172         /* IPsec not supported in x550EM */
 173         mac->ops.disable_sec_rx_path = NULL;
 174         mac->ops.enable_sec_rx_path = NULL;
 175
 176         /* X550EM bus type is internal*/
 177         hw->bus.type = ixgbe_bus_type_internal;
 178         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 179
 180         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 181         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 182         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 183         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 184         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 185         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 186         mac->ops.get_supported_physical_layer =
 187                                     ixgbe_get_supported_physical_layer_X550em;
 188
 189         /* PHY */
 190         phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
 191         phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
 192         phy->ops.init = ixgbe_init_phy_ops_X550em;
 193         phy->ops.identify = ixgbe_identify_phy_x550em;
 194         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 195                 phy->ops.set_phy_power = NULL;
 196
 197
 198         /* EEPROM */
 199         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 200         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 201         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 202         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 203         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 204         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 205         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 206         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 207
 208         return ret_val;
 209 }
 210
 211 /**
 212  *  ixgbe_dmac_config_X550
 213  *  @hw: pointer to hardware structure
 214  *
 215  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 216  *  When disabling dmac, dmac enable dmac bit is cleared.
 217  **/
 218 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 219 {
 220         u32 reg, high_pri_tc;
 221
 222         DEBUGFUNC("ixgbe_dmac_config_X550");
 223
 224         /* Disable DMA coalescing before configuring */
 225         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 226         reg &= ~IXGBE_DMACR_DMAC_EN;
 227         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 228
 229         /* Disable DMA Coalescing if the watchdog timer is 0 */
 230         if (!hw->mac.dmac_config.watchdog_timer)
 231                 goto out;
 232
 233         ixgbe_dmac_config_tcs_X550(hw);
 234
 235         /* Configure DMA Coalescing Control Register */
 236         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 237
 238         /* Set the watchdog timer in units of 40.96 usec */
 239         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 240         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 241
 242         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 243         /* If fcoe is enabled, set high priority traffic class */
 244         if (hw->mac.dmac_config.fcoe_en) {
 245                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 246                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 247                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 248         }
 249         reg |= IXGBE_DMACR_EN_MNG_IND;
 250
 251         /* Enable DMA coalescing after configuration */
 252         reg |= IXGBE_DMACR_DMAC_EN;
 253         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 254
 255 out:
 256         return IXGBE_SUCCESS;
 257 }
 258
 259 /**
 260  *  ixgbe_dmac_config_tcs_X550
 261  *  @hw: pointer to hardware structure
 262  *
 263  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 264  *  be cleared before configuring.
 265  **/
 266 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 267 {
 268         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 269
 270         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 271
 272         /* Configure DMA coalescing enabled */
 273         switch (hw->mac.dmac_config.link_speed) {
 274         case IXGBE_LINK_SPEED_100_FULL:
 275                 pb_headroom = IXGBE_DMACRXT_100M;
 276                 break;
 277         case IXGBE_LINK_SPEED_1GB_FULL:
 278                 pb_headroom = IXGBE_DMACRXT_1G;
 279                 break;
 280         default:
 281                 pb_headroom = IXGBE_DMACRXT_10G;
 282                 break;
 283         }
 284
 285         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 286                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 287
 288         /* Set the per Rx packet buffer receive threshold */
 289         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 290                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 291                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 292
 293                 if (tc < hw->mac.dmac_config.num_tcs) {
 294                         /* Get Rx PB size */
 295                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 296                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 297                                 IXGBE_RXPBSIZE_SHIFT;
 298
 299                         /* Calculate receive buffer threshold in kilobytes */
 300                         if (rx_pb_size > pb_headroom)
 301                                 rx_pb_size = rx_pb_size - pb_headroom;
 302                         else
 303                                 rx_pb_size = 0;
 304
 305                         /* Minimum of MFS shall be set for DMCTH */
 306                         reg |= (rx_pb_size > maxframe_size_kb) ?
 307                                 rx_pb_size : maxframe_size_kb;
 308                 }
 309                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 310         }
 311         return IXGBE_SUCCESS;
 312 }
 313
 314 /**
 315  *  ixgbe_dmac_update_tcs_X550
 316  *  @hw: pointer to hardware structure
 317  *
 318  *  Disables dmac, updates per TC settings, and then enables dmac.
 319  **/
 320 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 321 {
 322         u32 reg;
 323
 324         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 325
 326         /* Disable DMA coalescing before configuring */
 327         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 328         reg &= ~IXGBE_DMACR_DMAC_EN;
 329         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 330
 331         ixgbe_dmac_config_tcs_X550(hw);
 332
 333         /* Enable DMA coalescing after configuration */
 334         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 335         reg |= IXGBE_DMACR_DMAC_EN;
 336         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 337
 338         return IXGBE_SUCCESS;
 339 }
 340
 341 /**
 342  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 343  *  @hw: pointer to hardware structure
 344  *
 345  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 346  *  ixgbe_hw struct in order to set up EEPROM access.
 347  **/
 348 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 349 {
 350         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 351         u32 eec;
 352         u16 eeprom_size;
 353
 354         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 355
 356         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 357                 eeprom->semaphore_delay = 10;
 358                 eeprom->type = ixgbe_flash;
 359
 360                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 361                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 362                                     IXGBE_EEC_SIZE_SHIFT);
 363                 eeprom->word_size = 1 << (eeprom_size +
 364                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 365
 366                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 367                           eeprom->type, eeprom->word_size);
 368         }
 369
 370         return IXGBE_SUCCESS;
 371 }
 372
 373 /**
 374  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 375  *  @hw: pointer to the HW structure
 376  *  @enable_eee: boolean flag to enable EEE
 377  *
 378  *  Enable/disable EEE based on enable_eee flag.
 379  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 380  *  are modified.
 381  *
 382  **/
 383 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 384 {
 385         u32 eeer;
 386         u16 autoneg_eee_reg;
 387         u32 link_reg;
 388         s32 status;
 389
 390         DEBUGFUNC("ixgbe_setup_eee_X550");
 391
 392         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 393         /* Enable or disable EEE per flag */
 394         if (enable_eee) {
 395                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 396
 397                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 398                         /* Advertise EEE capability */
 399                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 400                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 401
 402                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 403                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 404                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 405
 406                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 407                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 408                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
 409                            hw->device_id == IXGBE_DEV_ID_X550EM_X) {
 410                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 411                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 412                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 413                         if (status != IXGBE_SUCCESS)
 414                                 return status;
 415
 416                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 417                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 418
 419                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 420                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 421                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 422                         if (status != IXGBE_SUCCESS)
 423                                 return status;
 424                 }
 425         } else {
 426                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 427
 428                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 429                         /* Disable advertised EEE capability */
 430                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 431                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 432
 433                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 434                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 435                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 436
 437                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 438                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 439                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
 440                            hw->device_id == IXGBE_DEV_ID_X550EM_X) {
 441                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 442                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 443                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 444                         if (status != IXGBE_SUCCESS)
 445                                 return status;
 446
 447                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 448                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 449
 450                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 451                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 452                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 453                         if (status != IXGBE_SUCCESS)
 454                                 return status;
 455                 }
 456         }
 457         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 458
 459         return IXGBE_SUCCESS;
 460 }
 461
 462 /**
 463  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 464  * @hw: pointer to hardware structure
 465  * @enable: enable or disable source address pruning
 466  * @pool: Rx pool to set source address pruning for
 467  **/
 468 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 469                                            unsigned int pool)
 470 {
 471         u64 pfflp;
 472
 473         /* max rx pool is 63 */
 474         if (pool > 63)
 475                 return;
 476
 477         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 478         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 479
 480         if (enable)
 481                 pfflp |= (1ULL << pool);
 482         else
 483                 pfflp &= ~(1ULL << pool);
 484
 485         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 486         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 487 }
 488
 489 /**
 490  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 491  *  @hw: pointer to hardware structure
 492  *  @enable: enable or disable switch for Ethertype anti-spoofing
 493  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 494  *
 495  **/
 496 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 497                 bool enable, int vf)
 498 {
 499         int vf_target_reg = vf >> 3;
 500         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 501         u32 pfvfspoof;
 502
 503         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 504
 505         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 506         if (enable)
 507                 pfvfspoof |= (1 << vf_target_shift);
 508         else
 509                 pfvfspoof &= ~(1 << vf_target_shift);
 510
 511         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 512 }
 513
 514 /**
 515  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 516  *  device
 517  *  @hw: pointer to hardware structure
 518  *  @reg_addr: 32 bit PHY register to write
 519  *  @device_type: 3 bit device type
 520  *  @data: Data to write to the register
 521  **/
 522 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 523                             u32 device_type, u32 data)
 524 {
 525         u32 i, command, error;
 526
 527         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 528                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 529
 530         /* Write IOSF control register */
 531         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 532
 533         /* Write IOSF data register */
 534         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 535         /*
 536          * Check every 10 usec to see if the address cycle completed.
 537          * The SB IOSF BUSY bit will clear when the operation is
 538          * complete
 539          */
 540         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 541                 usec_delay(10);
 542
 543                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 544                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 545                         break;
 546         }
 547
 548         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 549                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 550                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 551                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 552                               "Failed to write, error %x\n", error);
 553                 return IXGBE_ERR_PHY;
 554         }
 555
 556         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 557                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 558                 return IXGBE_ERR_PHY;
 559         }
 560
 561         return IXGBE_SUCCESS;
 562 }
 563
 564 /**
 565  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 566  *  device
 567  *  @hw: pointer to hardware structure
 568  *  @reg_addr: 32 bit PHY register to write
 569  *  @device_type: 3 bit device type
 570  *  @phy_data: Pointer to read data from the register
 571  **/
 572 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 573                            u32 device_type, u32 *data)
 574 {
 575         u32 i, command, error;
 576
 577         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 578                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 579
 580         /* Write IOSF control register */
 581         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 582
 583         /*
 584          * Check every 10 usec to see if the address cycle completed.
 585          * The SB IOSF BUSY bit will clear when the operation is
 586          * complete
 587          */
 588         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 589                 usec_delay(10);
 590
 591                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 592                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 593                         break;
 594         }
 595
 596         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 597                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 598                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 599                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 600                                 "Failed to read, error %x\n", error);
 601                 return IXGBE_ERR_PHY;
 602         }
 603
 604         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 605                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 606                 return IXGBE_ERR_PHY;
 607         }
 608
 609         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 610
 611         return IXGBE_SUCCESS;
 612 }
 613
 614 /**
 615  *  ixgbe_disable_mdd_X550
 616  *  @hw: pointer to hardware structure
 617  *
 618  *  Disable malicious driver detection
 619  **/
 620 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 621 {
 622         u32 reg;
 623
 624         DEBUGFUNC("ixgbe_disable_mdd_X550");
 625
 626         /* Disable MDD for TX DMA and interrupt */
 627         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 628         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 629         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 630
 631         /* Disable MDD for RX and interrupt */
 632         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 633         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 634         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 635 }
 636
 637 /**
 638  *  ixgbe_enable_mdd_X550
 639  *  @hw: pointer to hardware structure
 640  *
 641  *  Enable malicious driver detection
 642  **/
 643 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 644 {
 645         u32 reg;
 646
 647         DEBUGFUNC("ixgbe_enable_mdd_X550");
 648
 649         /* Enable MDD for TX DMA and interrupt */
 650         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 651         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 652         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 653
 654         /* Enable MDD for RX and interrupt */
 655         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 656         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 657         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 658 }
 659
 660 /**
 661  *  ixgbe_restore_mdd_vf_X550
 662  *  @hw: pointer to hardware structure
 663  *  @vf: vf index
 664  *
 665  *  Restore VF that was disabled during malicious driver detection event
 666  **/
 667 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 668 {
 669         u32 idx, reg, num_qs, start_q, bitmask;
 670
 671         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 672
 673         /* Map VF to queues */
 674         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 675         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 676         case IXGBE_MRQC_VMDQRT8TCEN:
 677                 num_qs = 8;  /* 16 VFs / pools */
 678                 bitmask = 0x000000FF;
 679                 break;
 680         case IXGBE_MRQC_VMDQRSS32EN:
 681         case IXGBE_MRQC_VMDQRT4TCEN:
 682                 num_qs = 4;  /* 32 VFs / pools */
 683                 bitmask = 0x0000000F;
 684                 break;
 685         default:            /* 64 VFs / pools */
 686                 num_qs = 2;
 687                 bitmask = 0x00000003;
 688                 break;
 689         }
 690         start_q = vf * num_qs;
 691
 692         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 693         idx = start_q / 32;
 694         reg = 0;
 695         reg |= (bitmask << (start_q % 32));
 696         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 697         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 698 }
 699
 700 /**
 701  *  ixgbe_mdd_event_X550
 702  *  @hw: pointer to hardware structure
 703  *  @vf_bitmap: vf bitmap of malicious vfs
 704  *
 705  *  Handle malicious driver detection event.
 706  **/
 707 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 708 {
 709         u32 wqbr;
 710         u32 i, j, reg, q, shift, vf, idx;
 711
 712         DEBUGFUNC("ixgbe_mdd_event_X550");
 713
 714         /* figure out pool size for mapping to vf's */
 715         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 716         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 717         case IXGBE_MRQC_VMDQRT8TCEN:
 718                 shift = 3;  /* 16 VFs / pools */
 719                 break;
 720         case IXGBE_MRQC_VMDQRSS32EN:
 721         case IXGBE_MRQC_VMDQRT4TCEN:
 722                 shift = 2;  /* 32 VFs / pools */
 723                 break;
 724         default:
 725                 shift = 1;  /* 64 VFs / pools */
 726                 break;
 727         }
 728
 729         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 730         for (i = 0; i < 4; i++) {
 731                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 732                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 733
 734                 if (!wqbr)
 735                         continue;
 736
 737                 /* Get malicious queue */
 738                 for (j = 0; j < 32 && wqbr; j++) {
 739
 740                         if (!(wqbr & (1 << j)))
 741                                 continue;
 742
 743                         /* Get queue from bitmask */
 744                         q = j + (i * 32);
 745
 746                         /* Map queue to vf */
 747                         vf = (q >> shift);
 748
 749                         /* Set vf bit in vf_bitmap */
 750                         idx = vf / 32;
 751                         vf_bitmap[idx] |= (1 << (vf % 32));
 752                         wqbr &= ~(1 << j);
 753                 }
 754         }
 755 }
 756
 757 /**
 758  *  ixgbe_get_media_type_X550em - Get media type
 759  *  @hw: pointer to hardware structure
 760  *
 761  *  Returns the media type (fiber, copper, backplane)
 762  */
 763 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 764 {
 765         enum ixgbe_media_type media_type;
 766
 767         DEBUGFUNC("ixgbe_get_media_type_X550em");
 768
 769         /* Detect if there is a copper PHY attached. */
 770         switch (hw->device_id) {
 771         case IXGBE_DEV_ID_X550EM_X:
 772         case IXGBE_DEV_ID_X550EM_X_KR:
 773         case IXGBE_DEV_ID_X550EM_X_KX4:
 774                 media_type = ixgbe_media_type_backplane;
 775                 break;
 776         case IXGBE_DEV_ID_X550EM_X_SFP:
 777                 media_type = ixgbe_media_type_fiber;
 778                 break;
 779         default:
 780                 media_type = ixgbe_media_type_unknown;
 781                 break;
 782         }
 783         return media_type;
 784 }
 785
 786 /**
 787  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 788  *  @hw: pointer to hardware structure
 789  */
 790 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 791 {
 792         bool setup_linear;
 793         u16 reg_slice, edc_mode;
 794         s32 ret_val;
 795
 796         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
 797
 798         switch (hw->phy.sfp_type) {
 799         case ixgbe_sfp_type_unknown:
 800                 return IXGBE_SUCCESS;
 801         case ixgbe_sfp_type_not_present:
 802                 return IXGBE_ERR_SFP_NOT_PRESENT;
 803         case ixgbe_sfp_type_da_cu_core0:
 804         case ixgbe_sfp_type_da_cu_core1:
 805                 setup_linear = true;
 806                 break;
 807         case ixgbe_sfp_type_srlr_core0:
 808         case ixgbe_sfp_type_srlr_core1:
 809         case ixgbe_sfp_type_da_act_lmt_core0:
 810         case ixgbe_sfp_type_da_act_lmt_core1:
 811         case ixgbe_sfp_type_1g_sx_core0:
 812         case ixgbe_sfp_type_1g_sx_core1:
 813         case ixgbe_sfp_type_1g_lx_core0:
 814         case ixgbe_sfp_type_1g_lx_core1:
 815                 setup_linear = false;
 816                 break;
 817         default:
 818                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 819         }
 820
 821         ixgbe_init_mac_link_ops_X550em(hw);
 822         hw->phy.ops.reset = NULL;
 823
 824         /* The CS4227 slice address is the base address + the port-pair reg
 825          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
 826          */
 827         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->phy.lan_id << 12);
 828
 829         if (setup_linear)
 830                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 831         else
 832                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 833
 834         /* Configure CS4227 for connection type. */
 835         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
 836                                            edc_mode);
 837
 838         if (ret_val != IXGBE_SUCCESS)
 839                 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
 840                                                    edc_mode);
 841
 842         return ret_val;
 843 }
 844
 845 /**
 846  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
 847  *  @hw: pointer to hardware structure
 848  */
 849 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
 850 {
 851         struct ixgbe_mac_info *mac = &hw->mac;
 852
 853         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
 854
 855         /* CS4227 does not support autoneg, so disable the laser control
 856          * functions for SFP+ fiber
 857          */
 858          if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 859                 mac->ops.disable_tx_laser = NULL;
 860                 mac->ops.enable_tx_laser = NULL;
 861                 mac->ops.flap_tx_laser = NULL;
 862          }
 863 }
 864
 865 /**
 866  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
 867  *  @hw: pointer to hardware structure
 868  *  @speed: pointer to link speed
 869  *  @autoneg: true when autoneg or autotry is enabled
 870  */
 871 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
 872                                        ixgbe_link_speed *speed,
 873                                        bool *autoneg)
 874 {
 875         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
 876
 877         /* SFP */
 878         if (hw->phy.media_type == ixgbe_media_type_fiber) {
 879
 880                 /* CS4227 SFP must not enable auto-negotiation */
 881                 *autoneg = false;
 882
 883                 /* Check if 1G SFP module. */
 884                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
 885                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
 886                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
 887                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
 888                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
 889                         return IXGBE_SUCCESS;
 890                 }
 891
 892                 /* Link capabilities are based on SFP */
 893                 if (hw->phy.multispeed_fiber)
 894                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
 895                                  IXGBE_LINK_SPEED_1GB_FULL;
 896                 else
 897                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 898         } else {
 899                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
 900                          IXGBE_LINK_SPEED_1GB_FULL;
 901                 *autoneg = true;
 902         }
 903
 904         return IXGBE_SUCCESS;
 905 }
 906
 907 /**
 908  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
 909  *  @hw: pointer to hardware structure
 910  *
 911  *  Initialize any function pointers that were not able to be
 912  *  set during init_shared_code because the PHY/SFP type was
 913  *  not known.  Perform the SFP init if necessary.
 914  */
 915 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
 916 {
 917         struct ixgbe_phy_info *phy = &hw->phy;
 918         s32 ret_val;
 919         u32 esdp;
 920
 921         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
 922
 923         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 924                 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 925                 phy->lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
 926                               IXGBE_STATUS_LAN_ID_1;
 927                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 928                 if (phy->lan_id) {
 929                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 930                         esdp |= IXGBE_ESDP_SDP1_DIR;
 931                 }
 932                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 933                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 934         }
 935
 936         /* Identify the PHY or SFP module */
 937         ret_val = phy->ops.identify(hw);
 938         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
 939                 return ret_val;
 940
 941         /* Setup function pointers based on detected SFP module and speeds */
 942         ixgbe_init_mac_link_ops_X550em(hw);
 943         if (phy->sfp_type != ixgbe_sfp_type_unknown)
 944                 phy->ops.reset = NULL;
 945
 946         /* Set functions pointers based on phy type */
 947         switch (hw->phy.type) {
 948         case ixgbe_phy_x550em_kr:
 949                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
 950                 break;
 951         default:
 952                 break;
 953         }
 954         return ret_val;
 955 }
 956
 957 /**
 958  *  ixgbe_reset_hw_X550em - Perform hardware reset
 959  *  @hw: pointer to hardware structure
 960  *
 961  *  Resets the hardware by resetting the transmit and receive units, masks
 962  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
 963  *  reset.
 964  */
 965 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
 966 {
 967         ixgbe_link_speed link_speed;
 968         s32 status;
 969         u32 ctrl = 0;
 970         u32 i;
 971         bool link_up = false;
 972
 973         DEBUGFUNC("ixgbe_reset_hw_X550em");
 974
 975         /* Call adapter stop to disable Tx/Rx and clear interrupts */
 976         status = hw->mac.ops.stop_adapter(hw);
 977         if (status != IXGBE_SUCCESS)
 978                 return status;
 979
 980         /* flush pending Tx transactions */
 981         ixgbe_clear_tx_pending(hw);
 982
 983         /* PHY ops must be identified and initialized prior to reset */
 984
 985         /* Identify PHY and related function pointers */
 986         status = hw->phy.ops.init(hw);
 987
 988         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 989                 return status;
 990
 991         /* Setup SFP module if there is one present. */
 992         if (hw->phy.sfp_setup_needed) {
 993                 status = hw->mac.ops.setup_sfp(hw);
 994                 hw->phy.sfp_setup_needed = false;
 995         }
 996
 997         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 998                 return status;
 999
1000         /* Reset PHY */
1001         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1002                 hw->phy.ops.reset(hw);
1003
1004 mac_reset_top:
1005         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1006          * If link reset is used when link is up, it might reset the PHY when
1007          * mng is using it.  If link is down or the flag to force full link
1008          * reset is set, then perform link reset.
1009          */
1010         ctrl = IXGBE_CTRL_LNK_RST;
1011         if (!hw->force_full_reset) {
1012                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1013                 if (link_up)
1014                         ctrl = IXGBE_CTRL_RST;
1015         }
1016
1017         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1018         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1019         IXGBE_WRITE_FLUSH(hw);
1020
1021         /* Poll for reset bit to self-clear meaning reset is complete */
1022         for (i = 0; i < 10; i++) {
1023                 usec_delay(1);
1024                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1025                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1026                         break;
1027         }
1028
1029         if (ctrl & IXGBE_CTRL_RST_MASK) {
1030                 status = IXGBE_ERR_RESET_FAILED;
1031                 DEBUGOUT("Reset polling failed to complete.\n");
1032         }
1033
1034         msec_delay(50);
1035
1036         /* Double resets are required for recovery from certain error
1037          * conditions.  Between resets, it is necessary to stall to
1038          * allow time for any pending HW events to complete.
1039          */
1040         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1041                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1042                 goto mac_reset_top;
1043         }
1044
1045         /* Store the permanent mac address */
1046         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1047
1048         /* Store MAC address from RAR0, clear receive address registers, and
1049          * clear the multicast table.  Also reset num_rar_entries to 128,
1050          * since we modify this value when programming the SAN MAC address.
1051          */
1052         hw->mac.num_rar_entries = 128;
1053         hw->mac.ops.init_rx_addrs(hw);
1054
1055         return status;
1056 }
1057
1058 /**
1059  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1060  *  @hw: pointer to hardware structure
1061  *
1062  *  Configures the integrated KR PHY.
1063  **/
1064 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1065 {
1066         s32 status;
1067         u32 reg_val;
1068
1069         status = ixgbe_read_iosf_sb_reg_x550(hw,
1070                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1071                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1072         if (status)
1073                 return status;
1074
1075         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1076         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ;
1077         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1078         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1079                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1080
1081         /* Advertise 10G support. */
1082         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1083                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1084
1085         /* Advertise 1G support. */
1086         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1087                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1088
1089         /* Restart auto-negotiation. */
1090         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1091         status = ixgbe_write_iosf_sb_reg_x550(hw,
1092                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1093                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1094
1095         return status;
1096 }
1097
1098 /**
1099  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI.
1100  *  @hw: pointer to hardware structure
1101  *
1102  *  Configures the integrated KR PHY to use iXFI mode.
1103  **/
1104 s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw)
1105 {
1106         s32 status;
1107         u32 reg_val;
1108
1109         /* Disable AN and force speed to 10G Serial. */
1110         status = ixgbe_read_iosf_sb_reg_x550(hw,
1111                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1112                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1113         if (status != IXGBE_SUCCESS)
1114                 return status;
1115         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1116         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1117         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1118         status = ixgbe_write_iosf_sb_reg_x550(hw,
1119                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1120                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1121         if (status != IXGBE_SUCCESS)
1122                 return status;
1123
1124         /* Disable training protocol FSM. */
1125         status = ixgbe_read_iosf_sb_reg_x550(hw,
1126                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1127                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1128         if (status != IXGBE_SUCCESS)
1129                 return status;
1130         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1131         status = ixgbe_write_iosf_sb_reg_x550(hw,
1132                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1133                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1134         if (status != IXGBE_SUCCESS)
1135                 return status;
1136
1137         /* Disable Flex from training TXFFE. */
1138         status = ixgbe_read_iosf_sb_reg_x550(hw,
1139                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),
1140                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1141         if (status != IXGBE_SUCCESS)
1142                 return status;
1143         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1144         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1145         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1146         status = ixgbe_write_iosf_sb_reg_x550(hw,
1147                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),
1148                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1149         if (status != IXGBE_SUCCESS)
1150                 return status;
1151         status = ixgbe_read_iosf_sb_reg_x550(hw,
1152                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),
1153                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1154         if (status != IXGBE_SUCCESS)
1155                 return status;
1156         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1157         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1158         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1159         status = ixgbe_write_iosf_sb_reg_x550(hw,
1160                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),
1161                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1162         if (status != IXGBE_SUCCESS)
1163                 return status;
1164
1165         /* Enable override for coefficients. */
1166         status = ixgbe_read_iosf_sb_reg_x550(hw,
1167                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),
1168                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1169         if (status != IXGBE_SUCCESS)
1170                 return status;
1171         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1172         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1173         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1174         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1175         status = ixgbe_write_iosf_sb_reg_x550(hw,
1176                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),
1177                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1178         if (status != IXGBE_SUCCESS)
1179                 return status;
1180
1181         /* Toggle port SW reset by AN reset. */
1182         status = ixgbe_read_iosf_sb_reg_x550(hw,
1183                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1184                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1185         if (status != IXGBE_SUCCESS)
1186                 return status;
1187         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1188         status = ixgbe_write_iosf_sb_reg_x550(hw,
1189                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1190                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1191
1192         return status;
1193 }
1194
1195 /**
1196  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1197  *  @hw: pointer to hardware structure
1198  *
1199  *  Configures the integrated KR PHY to use internal loopback mode.
1200  **/
1201 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1202 {
1203         s32 status;
1204         u32 reg_val;
1205
1206         /* Disable AN and force speed to 10G Serial. */
1207         status = ixgbe_read_iosf_sb_reg_x550(hw,
1208                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1209                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1210         if (status != IXGBE_SUCCESS)
1211                 return status;
1212         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1213         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1214         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1215         status = ixgbe_write_iosf_sb_reg_x550(hw,
1216                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1217                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1218         if (status != IXGBE_SUCCESS)
1219                 return status;
1220
1221         /* Set near-end loopback clocks. */
1222         status = ixgbe_read_iosf_sb_reg_x550(hw,
1223                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),
1224                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1225         if (status != IXGBE_SUCCESS)
1226                 return status;
1227         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1228         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1229         status = ixgbe_write_iosf_sb_reg_x550(hw,
1230                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),
1231                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1232         if (status != IXGBE_SUCCESS)
1233                 return status;
1234
1235         /* Set loopback enable. */
1236         status = ixgbe_read_iosf_sb_reg_x550(hw,
1237                 IXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),
1238                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1239         if (status != IXGBE_SUCCESS)
1240                 return status;
1241         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1242         status = ixgbe_write_iosf_sb_reg_x550(hw,
1243                 IXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),
1244                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1245         if (status != IXGBE_SUCCESS)
1246                 return status;
1247
1248         /* Training bypass. */
1249         status = ixgbe_read_iosf_sb_reg_x550(hw,
1250                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1251                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1252         if (status != IXGBE_SUCCESS)
1253                 return status;
1254         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1255         status = ixgbe_write_iosf_sb_reg_x550(hw,
1256                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1257                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1258
1259         return status;
1260 }
1261
1262 /**
1263  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1264  *  assuming that the semaphore is already obtained.
1265  *  @hw: pointer to hardware structure
1266  *  @offset: offset of  word in the EEPROM to read
1267  *  @data: word read from the EEPROM
1268  *
1269  *  Reads a 16 bit word from the EEPROM using the hostif.
1270  **/
1271 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1272                                    u16 *data)
1273 {
1274         s32 status;
1275         struct ixgbe_hic_read_shadow_ram buffer;
1276
1277         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1278         buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1279         buffer.hdr.buf_len1 = 0;
1280         buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1281         buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1282
1283         /* convert offset from words to bytes */
1284         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1285         /* one word */
1286         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1287
1288         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1289                                               sizeof(buffer), false);
1290
1291         if (status)
1292                 return status;
1293
1294         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1295                                           FW_NVM_DATA_OFFSET);
1296
1297         return 0;
1298 }
1299
1300 /**
1301  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1302  *  @hw: pointer to hardware structure
1303  *  @offset: offset of  word in the EEPROM to read
1304  *  @data: word read from the EEPROM
1305  *
1306  *  Reads a 16 bit word from the EEPROM using the hostif.
1307  **/
1308 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1309                               u16 *data)
1310 {
1311         s32 status = IXGBE_SUCCESS;
1312
1313         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1314
1315         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1316             IXGBE_SUCCESS) {
1317                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1318                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1319         } else {
1320                 status = IXGBE_ERR_SWFW_SYNC;
1321         }
1322
1323         return status;
1324 }
1325
1326 /**
1327  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1328  *  @hw: pointer to hardware structure
1329  *  @offset: offset of  word in the EEPROM to read
1330  *  @words: number of words
1331  *  @data: word(s) read from the EEPROM
1332  *
1333  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1334  **/
1335 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1336                                      u16 offset, u16 words, u16 *data)
1337 {
1338         struct ixgbe_hic_read_shadow_ram buffer;
1339         u32 current_word = 0;
1340         u16 words_to_read;
1341         s32 status;
1342         u32 i;
1343
1344         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1345
1346         /* Take semaphore for the entire operation. */
1347         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1348         if (status) {
1349                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1350                 return status;
1351         }
1352         while (words) {
1353                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1354                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1355                 else
1356                         words_to_read = words;
1357
1358                 buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1359                 buffer.hdr.buf_len1 = 0;
1360                 buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1361                 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1362
1363                 /* convert offset from words to bytes */
1364                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1365                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1366
1367                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1368                                                       sizeof(buffer), false);
1369
1370                 if (status) {
1371                         DEBUGOUT("Host interface command failed\n");
1372                         goto out;
1373                 }
1374
1375                 for (i = 0; i < words_to_read; i++) {
1376                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1377                                   2 * i;
1378                         u32 value = IXGBE_READ_REG(hw, reg);
1379
1380                         data[current_word] = (u16)(value & 0xffff);
1381                         current_word++;
1382                         i++;
1383                         if (i < words_to_read) {
1384                                 value >>= 16;
1385                                 data[current_word] = (u16)(value & 0xffff);
1386                                 current_word++;
1387                         }
1388                 }
1389                 words -= words_to_read;
1390         }
1391
1392 out:
1393         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1394         return status;
1395 }
1396
1397 /**
1398  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1399  *  @hw: pointer to hardware structure
1400  *  @offset: offset of  word in the EEPROM to write
1401  *  @data: word write to the EEPROM
1402  *
1403  *  Write a 16 bit word to the EEPROM using the hostif.
1404  **/
1405 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1406                                     u16 data)
1407 {
1408         s32 status;
1409         struct ixgbe_hic_write_shadow_ram buffer;
1410
1411         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1412
1413         buffer.hdr.cmd = FW_WRITE_SHADOW_RAM_CMD;
1414         buffer.hdr.buf_len1 = 0;
1415         buffer.hdr.buf_len2 = FW_WRITE_SHADOW_RAM_LEN;
1416         buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1417
1418          /* one word */
1419         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1420         buffer.data = data;
1421         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1422
1423         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1424                                               sizeof(buffer), false);
1425
1426         return status;
1427 }
1428
1429 /**
1430  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1431  *  @hw: pointer to hardware structure
1432  *  @offset: offset of  word in the EEPROM to write
1433  *  @data: word write to the EEPROM
1434  *
1435  *  Write a 16 bit word to the EEPROM using the hostif.
1436  **/
1437 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1438                                u16 data)
1439 {
1440         s32 status = IXGBE_SUCCESS;
1441
1442         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1443
1444         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1445             IXGBE_SUCCESS) {
1446                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1447                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1448         } else {
1449                 DEBUGOUT("write ee hostif failed to get semaphore");
1450                 status = IXGBE_ERR_SWFW_SYNC;
1451         }
1452
1453         return status;
1454 }
1455
1456 /**
1457  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1458  *  @hw: pointer to hardware structure
1459  *  @offset: offset of  word in the EEPROM to write
1460  *  @words: number of words
1461  *  @data: word(s) write to the EEPROM
1462  *
1463  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1464  **/
1465 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1466                                       u16 offset, u16 words, u16 *data)
1467 {
1468         s32 status = IXGBE_SUCCESS;
1469         u32 i = 0;
1470
1471         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1472
1473         /* Take semaphore for the entire operation. */
1474         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1475         if (status != IXGBE_SUCCESS) {
1476                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1477                 goto out;
1478         }
1479
1480         for (i = 0; i < words; i++) {
1481                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1482                                                          data[i]);
1483
1484                 if (status != IXGBE_SUCCESS) {
1485                         DEBUGOUT("Eeprom buffered write failed\n");
1486                         break;
1487                 }
1488         }
1489
1490         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1491 out:
1492
1493         return status;
1494 }
1495
1496 /**
1497  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1498  * @hw: pointer to hardware structure
1499  * @ptr: pointer offset in eeprom
1500  * @size: size of section pointed by ptr, if 0 first word will be used as size
1501  * @csum: address of checksum to update
1502  *
1503  * Returns error status for any failure
1504  */
1505 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1506                                    u16 size, u16 *csum)
1507 {
1508         u16 buf[256];
1509         s32 status;
1510         u16 length, bufsz, i, start;
1511
1512         bufsz = sizeof(buf) / sizeof(buf[0]);
1513
1514         /* Read a chunk at the pointer location */
1515         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1516         if (status) {
1517                 DEBUGOUT("Failed to read EEPROM image\n");
1518                 return status;
1519         }
1520
1521         if (size) {
1522                 start = 0;
1523                 length = size;
1524         } else {
1525                 start = 1;
1526                 length = buf[0];
1527
1528                 /* Skip pointer section if length is invalid. */
1529                 if (length == 0xFFFF || length == 0 ||
1530                     (ptr + length) >= hw->eeprom.word_size)
1531                         return IXGBE_SUCCESS;
1532         }
1533
1534         for (i = start; length; i++, length--) {
1535                 if (i == bufsz) {
1536                         ptr += bufsz;
1537                         i = 0;
1538                         if (length < bufsz)
1539                                 bufsz = length;
1540
1541                         /* Read a chunk at the pointer location */
1542                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1543                                                                   bufsz, buf);
1544                         if (status) {
1545                                 DEBUGOUT("Failed to read EEPROM image\n");
1546                                 return status;
1547                         }
1548                 }
1549                 *csum += buf[i];
1550         }
1551         return IXGBE_SUCCESS;
1552 }
1553
1554 /**
1555  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1556  *  @hw: pointer to hardware structure
1557  *
1558  *  Returns a negative error code on error, or the 16-bit checksum
1559  **/
1560 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1561 {
1562         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1563         s32 status;
1564         u16 checksum = 0;
1565         u16 pointer, i, size;
1566
1567         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
1568
1569         hw->eeprom.ops.init_params(hw);
1570
1571         /* Read pointer area */
1572         status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1573                                                   IXGBE_EEPROM_LAST_WORD + 1,
1574                                                   eeprom_ptrs);
1575         if (status) {
1576                 DEBUGOUT("Failed to read EEPROM image\n");
1577                 return status;
1578         }
1579
1580         /*
1581          * For X550 hardware include 0x0-0x41 in the checksum, skip the
1582          * checksum word itself
1583          */
1584         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1585                 if (i != IXGBE_EEPROM_CHECKSUM)
1586                         checksum += eeprom_ptrs[i];
1587
1588         /*
1589          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
1590          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1591          */
1592         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1593                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1594                         continue;
1595
1596                 pointer = eeprom_ptrs[i];
1597
1598                 /* Skip pointer section if the pointer is invalid. */
1599                 if (pointer == 0xFFFF || pointer == 0 ||
1600                     pointer >= hw->eeprom.word_size)
1601                         continue;
1602
1603                 switch (i) {
1604                 case IXGBE_PCIE_GENERAL_PTR:
1605                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1606                         break;
1607                 case IXGBE_PCIE_CONFIG0_PTR:
1608                 case IXGBE_PCIE_CONFIG1_PTR:
1609                         size = IXGBE_PCIE_CONFIG_SIZE;
1610                         break;
1611                 default:
1612                         size = 0;
1613                         break;
1614                 }
1615
1616                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum);
1617                 if (status)
1618                         return status;
1619         }
1620
1621         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1622
1623         return (s32)checksum;
1624 }
1625
1626 /**
1627  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1628  *  @hw: pointer to hardware structure
1629  *  @checksum_val: calculated checksum
1630  *
1631  *  Performs checksum calculation and validates the EEPROM checksum.  If the
1632  *  caller does not need checksum_val, the value can be NULL.
1633  **/
1634 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
1635 {
1636         s32 status;
1637         u16 checksum;
1638         u16 read_checksum = 0;
1639
1640         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
1641
1642         /* Read the first word from the EEPROM. If this times out or fails, do
1643          * not continue or we could be in for a very long wait while every
1644          * EEPROM read fails
1645          */
1646         status = hw->eeprom.ops.read(hw, 0, &checksum);
1647         if (status) {
1648                 DEBUGOUT("EEPROM read failed\n");
1649                 return status;
1650         }
1651
1652         status = hw->eeprom.ops.calc_checksum(hw);
1653         if (status < 0)
1654                 return status;
1655
1656         checksum = (u16)(status & 0xffff);
1657
1658         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1659                                            &read_checksum);
1660         if (status)
1661                 return status;
1662
1663         /* Verify read checksum from EEPROM is the same as
1664          * calculated checksum
1665          */
1666         if (read_checksum != checksum) {
1667                 status = IXGBE_ERR_EEPROM_CHECKSUM;
1668                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1669                              "Invalid EEPROM checksum");
1670         }
1671
1672         /* If the user cares, return the calculated checksum */
1673         if (checksum_val)
1674                 *checksum_val = checksum;
1675
1676         return status;
1677 }
1678
1679 /**
1680  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1681  * @hw: pointer to hardware structure
1682  *
1683  * After writing EEPROM to shadow RAM using EEWR register, software calculates
1684  * checksum and updates the EEPROM and instructs the hardware to update
1685  * the flash.
1686  **/
1687 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1688 {
1689         s32 status;
1690         u16 checksum = 0;
1691
1692         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
1693
1694         /* Read the first word from the EEPROM. If this times out or fails, do
1695          * not continue or we could be in for a very long wait while every
1696          * EEPROM read fails
1697          */
1698         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1699         if (status) {
1700                 DEBUGOUT("EEPROM read failed\n");
1701                 return status;
1702         }
1703
1704         status = ixgbe_calc_eeprom_checksum_X550(hw);
1705         if (status < 0)
1706                 return status;
1707
1708         checksum = (u16)(status & 0xffff);
1709
1710         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1711                                             checksum);
1712         if (status)
1713                 return status;
1714
1715         status = ixgbe_update_flash_X550(hw);
1716
1717         return status;
1718 }
1719
1720 /**
1721  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1722  *  @hw: pointer to hardware structure
1723  *
1724  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1725  **/
1726 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1727 {
1728         s32 status = IXGBE_SUCCESS;
1729         struct ixgbe_hic_hdr2 buffer;
1730
1731         DEBUGFUNC("ixgbe_update_flash_X550");
1732
1733         buffer.cmd = FW_SHADOW_RAM_DUMP_CMD;
1734         buffer.buf_len1 = 0;
1735         buffer.buf_len2 = FW_SHADOW_RAM_DUMP_LEN;
1736         buffer.checksum = FW_DEFAULT_CHECKSUM;
1737
1738         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1739                                               sizeof(buffer), false);
1740
1741         return status;
1742 }
1743
1744 /**
1745  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
1746  *  @hw: pointer to hardware structure
1747  *
1748  *  Determines physical layer capabilities of the current configuration.
1749  **/
1750 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
1751 {
1752         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1753
1754         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
1755
1756         hw->phy.ops.identify(hw);
1757
1758         switch (hw->phy.type) {
1759         case ixgbe_phy_x550em_kr:
1760                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
1761                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1762                 break;
1763         case ixgbe_phy_x550em_kx4:
1764                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1765                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1766                 break;
1767         default:
1768                 break;
1769         }
1770
1771         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
1772                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
1773
1774         return physical_layer;
1775 }
1776
1777 /**
1778  * ixgbe_get_bus_info_x550em - Set PCI bus info
1779  * @hw: pointer to hardware structure
1780  *
1781  * Sets bus link width and speed to unknown because X550em is
1782  * not a PCI device.
1783  **/
1784 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
1785 {
1786
1787         DEBUGFUNC("ixgbe_get_bus_info_x550em");
1788
1789         hw->bus.width = ixgbe_bus_width_unknown;
1790         hw->bus.speed = ixgbe_bus_speed_unknown;
1791
1792         return IXGBE_SUCCESS;
1793 }
1794
1795 /**
1796  * ixgbe_disable_rx_x550 - Disable RX unit
1797  *
1798  * Enables the Rx DMA unit for x550
1799  **/
1800 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1801 {
1802         u32 rxctrl, pfdtxgswc;
1803         s32 status;
1804         struct ixgbe_hic_disable_rxen fw_cmd;
1805
1806         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
1807
1808         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1809         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1810                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1811                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1812                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1813                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1814                         hw->mac.set_lben = true;
1815                 } else {
1816                         hw->mac.set_lben = false;
1817                 }
1818
1819                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1820                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1821                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1822                 fw_cmd.port_number = hw->phy.lan_id;
1823
1824                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1825                                         sizeof(struct ixgbe_hic_disable_rxen),
1826                                         true);
1827
1828                 /* If we fail - disable RX using register write */
1829                 if (status) {
1830                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1831                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1832                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1833                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1834                         }
1835                 }
1836         }
1837 }