lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 /**
  42  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  43  *  @hw: pointer to hardware structure
  44  *
  45  *  Initialize the function pointers and assign the MAC type for X550.
  46  *  Does not touch the hardware.
  47  **/
  48 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  49 {
  50         struct ixgbe_mac_info *mac = &hw->mac;
  51         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  52         s32 ret_val;
  53
  54         DEBUGFUNC("ixgbe_init_ops_X550");
  55
  56         ret_val = ixgbe_init_ops_X540(hw);
  57         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  58         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  59         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  60         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  61         mac->ops.set_source_address_pruning =
  62                         ixgbe_set_source_address_pruning_X550;
  63         mac->ops.set_ethertype_anti_spoofing =
  64                         ixgbe_set_ethertype_anti_spoofing_X550;
  65
  66         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  67         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  68         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  69         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  70         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  71         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  72         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  73         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  74         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  75
  76         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  77         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  78         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  79         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  80         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  81         return ret_val;
  82 }
  83
  84 /**
  85  * ixgbe_identify_phy_x550em - Get PHY type based on device id
  86  * @hw: pointer to hardware structure
  87  *
  88  * Returns error code
  89  */
  90 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
  91 {
  92         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  93
  94         switch (hw->device_id) {
  95         case IXGBE_DEV_ID_X550EM_X_SFP:
  96                 /* set up for CS4227 usage */
  97                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
  98                 if (hw->bus.lan_id) {
  99
 100                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 101                         esdp |= IXGBE_ESDP_SDP1_DIR;
 102                 }
 103                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 104                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 105
 106                 return ixgbe_identify_module_generic(hw);
 107                 break;
 108         case IXGBE_DEV_ID_X550EM_X_KX4:
 109                 hw->phy.type = ixgbe_phy_x550em_kx4;
 110                 break;
 111         case IXGBE_DEV_ID_X550EM_X_KR:
 112         case IXGBE_DEV_ID_X550EM_X:
 113                 hw->phy.type = ixgbe_phy_x550em_kr;
 114                 break;
 115         default:
 116                 break;
 117         }
 118         return IXGBE_SUCCESS;
 119 }
 120
 121 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 122                                      u32 device_type, u16 *phy_data)
 123 {
 124         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 125         return IXGBE_NOT_IMPLEMENTED;
 126 }
 127
 128 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 129                                       u32 device_type, u16 phy_data)
 130 {
 131         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 132         return IXGBE_NOT_IMPLEMENTED;
 133 }
 134
 135 /**
 136 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 137 *  @hw: pointer to hardware structure
 138 *
 139 *  Initialize the function pointers and for MAC type X550EM.
 140 *  Does not touch the hardware.
 141 **/
 142 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 143 {
 144         struct ixgbe_mac_info *mac = &hw->mac;
 145         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 146         struct ixgbe_phy_info *phy = &hw->phy;
 147         s32 ret_val;
 148
 149         DEBUGFUNC("ixgbe_init_ops_X550EM");
 150
 151         /* Similar to X550 so start there. */
 152         ret_val = ixgbe_init_ops_X550(hw);
 153
 154         /* Since this function eventually calls
 155          * ixgbe_init_ops_540 by design, we are setting
 156          * the pointers to NULL explicitly here to overwrite
 157          * the values being set in the x540 function.
 158          */
 159         /* Thermal sensor not supported in x550EM */
 160         mac->ops.get_thermal_sensor_data = NULL;
 161         mac->ops.init_thermal_sensor_thresh = NULL;
 162         mac->thermal_sensor_enabled = false;
 163
 164         /* FCOE not supported in x550EM */
 165         mac->ops.get_san_mac_addr = NULL;
 166         mac->ops.set_san_mac_addr = NULL;
 167         mac->ops.get_wwn_prefix = NULL;
 168         mac->ops.get_fcoe_boot_status = NULL;
 169
 170         /* IPsec not supported in x550EM */
 171         mac->ops.disable_sec_rx_path = NULL;
 172         mac->ops.enable_sec_rx_path = NULL;
 173
 174         /* X550EM bus type is internal*/
 175         hw->bus.type = ixgbe_bus_type_internal;
 176         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 177
 178         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 179         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 180         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 181         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 182         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 183         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 184         mac->ops.get_supported_physical_layer =
 185                                     ixgbe_get_supported_physical_layer_X550em;
 186
 187         /* PHY */
 188         phy->ops.init = ixgbe_init_phy_ops_X550em;
 189         phy->ops.identify = ixgbe_identify_phy_x550em;
 190         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 191                 phy->ops.set_phy_power = NULL;
 192
 193
 194         /* EEPROM */
 195         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 196         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 197         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 198         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 199         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 200         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 201         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 202         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 203
 204         return ret_val;
 205 }
 206
 207 /**
 208  *  ixgbe_dmac_config_X550
 209  *  @hw: pointer to hardware structure
 210  *
 211  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 212  *  When disabling dmac, dmac enable dmac bit is cleared.
 213  **/
 214 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 215 {
 216         u32 reg, high_pri_tc;
 217
 218         DEBUGFUNC("ixgbe_dmac_config_X550");
 219
 220         /* Disable DMA coalescing before configuring */
 221         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 222         reg &= ~IXGBE_DMACR_DMAC_EN;
 223         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 224
 225         /* Disable DMA Coalescing if the watchdog timer is 0 */
 226         if (!hw->mac.dmac_config.watchdog_timer)
 227                 goto out;
 228
 229         ixgbe_dmac_config_tcs_X550(hw);
 230
 231         /* Configure DMA Coalescing Control Register */
 232         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 233
 234         /* Set the watchdog timer in units of 40.96 usec */
 235         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 236         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 237
 238         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 239         /* If fcoe is enabled, set high priority traffic class */
 240         if (hw->mac.dmac_config.fcoe_en) {
 241                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 242                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 243                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 244         }
 245         reg |= IXGBE_DMACR_EN_MNG_IND;
 246
 247         /* Enable DMA coalescing after configuration */
 248         reg |= IXGBE_DMACR_DMAC_EN;
 249         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 250
 251 out:
 252         return IXGBE_SUCCESS;
 253 }
 254
 255 /**
 256  *  ixgbe_dmac_config_tcs_X550
 257  *  @hw: pointer to hardware structure
 258  *
 259  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 260  *  be cleared before configuring.
 261  **/
 262 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 263 {
 264         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 265
 266         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 267
 268         /* Configure DMA coalescing enabled */
 269         switch (hw->mac.dmac_config.link_speed) {
 270         case IXGBE_LINK_SPEED_100_FULL:
 271                 pb_headroom = IXGBE_DMACRXT_100M;
 272                 break;
 273         case IXGBE_LINK_SPEED_1GB_FULL:
 274                 pb_headroom = IXGBE_DMACRXT_1G;
 275                 break;
 276         default:
 277                 pb_headroom = IXGBE_DMACRXT_10G;
 278                 break;
 279         }
 280
 281         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 282                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 283
 284         /* Set the per Rx packet buffer receive threshold */
 285         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 286                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 287                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 288
 289                 if (tc < hw->mac.dmac_config.num_tcs) {
 290                         /* Get Rx PB size */
 291                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 292                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 293                                 IXGBE_RXPBSIZE_SHIFT;
 294
 295                         /* Calculate receive buffer threshold in kilobytes */
 296                         if (rx_pb_size > pb_headroom)
 297                                 rx_pb_size = rx_pb_size - pb_headroom;
 298                         else
 299                                 rx_pb_size = 0;
 300
 301                         /* Minimum of MFS shall be set for DMCTH */
 302                         reg |= (rx_pb_size > maxframe_size_kb) ?
 303                                 rx_pb_size : maxframe_size_kb;
 304                 }
 305                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 306         }
 307         return IXGBE_SUCCESS;
 308 }
 309
 310 /**
 311  *  ixgbe_dmac_update_tcs_X550
 312  *  @hw: pointer to hardware structure
 313  *
 314  *  Disables dmac, updates per TC settings, and then enables dmac.
 315  **/
 316 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 317 {
 318         u32 reg;
 319
 320         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 321
 322         /* Disable DMA coalescing before configuring */
 323         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 324         reg &= ~IXGBE_DMACR_DMAC_EN;
 325         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 326
 327         ixgbe_dmac_config_tcs_X550(hw);
 328
 329         /* Enable DMA coalescing after configuration */
 330         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 331         reg |= IXGBE_DMACR_DMAC_EN;
 332         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 333
 334         return IXGBE_SUCCESS;
 335 }
 336
 337 /**
 338  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 339  *  @hw: pointer to hardware structure
 340  *
 341  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 342  *  ixgbe_hw struct in order to set up EEPROM access.
 343  **/
 344 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 345 {
 346         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 347         u32 eec;
 348         u16 eeprom_size;
 349
 350         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 351
 352         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 353                 eeprom->semaphore_delay = 10;
 354                 eeprom->type = ixgbe_flash;
 355
 356                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 357                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 358                                     IXGBE_EEC_SIZE_SHIFT);
 359                 eeprom->word_size = 1 << (eeprom_size +
 360                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 361
 362                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 363                           eeprom->type, eeprom->word_size);
 364         }
 365
 366         return IXGBE_SUCCESS;
 367 }
 368
 369 /**
 370  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 371  *  @hw: pointer to the HW structure
 372  *  @enable_eee: boolean flag to enable EEE
 373  *
 374  *  Enable/disable EEE based on enable_eee flag.
 375  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 376  *  are modified.
 377  *
 378  **/
 379 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 380 {
 381         u32 eeer;
 382         u16 autoneg_eee_reg;
 383         u32 link_reg;
 384         s32 status;
 385
 386         DEBUGFUNC("ixgbe_setup_eee_X550");
 387
 388         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 389         /* Enable or disable EEE per flag */
 390         if (enable_eee) {
 391                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 392
 393                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 394                         /* Advertise EEE capability */
 395                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 396                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 397
 398                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 399                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 400                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 401
 402                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 403                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 404                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
 405                            hw->device_id == IXGBE_DEV_ID_X550EM_X) {
 406                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 407                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 408                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 409                         if (status != IXGBE_SUCCESS)
 410                                 return status;
 411
 412                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 413                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 414
 415                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 416                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 417                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 418                         if (status != IXGBE_SUCCESS)
 419                                 return status;
 420                 }
 421         } else {
 422                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 423
 424                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 425                         /* Disable advertised EEE capability */
 426                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 427                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 428
 429                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 430                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 431                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 432
 433                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 434                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 435                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
 436                            hw->device_id == IXGBE_DEV_ID_X550EM_X) {
 437                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 438                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 439                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 440                         if (status != IXGBE_SUCCESS)
 441                                 return status;
 442
 443                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 444                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 445
 446                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 447                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 448                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 449                         if (status != IXGBE_SUCCESS)
 450                                 return status;
 451                 }
 452         }
 453         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 454
 455         return IXGBE_SUCCESS;
 456 }
 457
 458 /**
 459  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 460  * @hw: pointer to hardware structure
 461  * @enable: enable or disable source address pruning
 462  * @pool: Rx pool to set source address pruning for
 463  **/
 464 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 465                                            unsigned int pool)
 466 {
 467         u64 pfflp;
 468
 469         /* max rx pool is 63 */
 470         if (pool > 63)
 471                 return;
 472
 473         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 474         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 475
 476         if (enable)
 477                 pfflp |= (1ULL << pool);
 478         else
 479                 pfflp &= ~(1ULL << pool);
 480
 481         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 482         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 483 }
 484
 485 /**
 486  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 487  *  @hw: pointer to hardware structure
 488  *  @enable: enable or disable switch for Ethertype anti-spoofing
 489  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 490  *
 491  **/
 492 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 493                 bool enable, int vf)
 494 {
 495         int vf_target_reg = vf >> 3;
 496         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 497         u32 pfvfspoof;
 498
 499         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 500
 501         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 502         if (enable)
 503                 pfvfspoof |= (1 << vf_target_shift);
 504         else
 505                 pfvfspoof &= ~(1 << vf_target_shift);
 506
 507         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 508 }
 509
 510 /**
 511  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 512  *  device
 513  *  @hw: pointer to hardware structure
 514  *  @reg_addr: 32 bit PHY register to write
 515  *  @device_type: 3 bit device type
 516  *  @data: Data to write to the register
 517  **/
 518 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 519                             u32 device_type, u32 data)
 520 {
 521         u32 i, command, error;
 522
 523         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 524                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 525
 526         /* Write IOSF control register */
 527         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 528
 529         /* Write IOSF data register */
 530         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 531         /*
 532          * Check every 10 usec to see if the address cycle completed.
 533          * The SB IOSF BUSY bit will clear when the operation is
 534          * complete
 535          */
 536         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 537                 usec_delay(10);
 538
 539                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 540                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 541                         break;
 542         }
 543
 544         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 545                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 546                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 547                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 548                               "Failed to write, error %x\n", error);
 549                 return IXGBE_ERR_PHY;
 550         }
 551
 552         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 553                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 554                 return IXGBE_ERR_PHY;
 555         }
 556
 557         return IXGBE_SUCCESS;
 558 }
 559
 560 /**
 561  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 562  *  device
 563  *  @hw: pointer to hardware structure
 564  *  @reg_addr: 32 bit PHY register to write
 565  *  @device_type: 3 bit device type
 566  *  @phy_data: Pointer to read data from the register
 567  **/
 568 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 569                            u32 device_type, u32 *data)
 570 {
 571         u32 i, command, error;
 572
 573         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 574                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 575
 576         /* Write IOSF control register */
 577         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 578
 579         /*
 580          * Check every 10 usec to see if the address cycle completed.
 581          * The SB IOSF BUSY bit will clear when the operation is
 582          * complete
 583          */
 584         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 585                 usec_delay(10);
 586
 587                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 588                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 589                         break;
 590         }
 591
 592         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 593                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 594                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 595                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 596                                 "Failed to read, error %x\n", error);
 597                 return IXGBE_ERR_PHY;
 598         }
 599
 600         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 601                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 602                 return IXGBE_ERR_PHY;
 603         }
 604
 605         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 606
 607         return IXGBE_SUCCESS;
 608 }
 609
 610 /**
 611  *  ixgbe_disable_mdd_X550
 612  *  @hw: pointer to hardware structure
 613  *
 614  *  Disable malicious driver detection
 615  **/
 616 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 617 {
 618         u32 reg;
 619
 620         DEBUGFUNC("ixgbe_disable_mdd_X550");
 621
 622         /* Disable MDD for TX DMA and interrupt */
 623         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 624         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 625         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 626
 627         /* Disable MDD for RX and interrupt */
 628         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 629         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 630         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 631 }
 632
 633 /**
 634  *  ixgbe_enable_mdd_X550
 635  *  @hw: pointer to hardware structure
 636  *
 637  *  Enable malicious driver detection
 638  **/
 639 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 640 {
 641         u32 reg;
 642
 643         DEBUGFUNC("ixgbe_enable_mdd_X550");
 644
 645         /* Enable MDD for TX DMA and interrupt */
 646         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 647         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 648         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 649
 650         /* Enable MDD for RX and interrupt */
 651         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 652         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 653         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 654 }
 655
 656 /**
 657  *  ixgbe_restore_mdd_vf_X550
 658  *  @hw: pointer to hardware structure
 659  *  @vf: vf index
 660  *
 661  *  Restore VF that was disabled during malicious driver detection event
 662  **/
 663 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 664 {
 665         u32 idx, reg, num_qs, start_q, bitmask;
 666
 667         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 668
 669         /* Map VF to queues */
 670         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 671         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 672         case IXGBE_MRQC_VMDQRT8TCEN:
 673                 num_qs = 8;  /* 16 VFs / pools */
 674                 bitmask = 0x000000FF;
 675                 break;
 676         case IXGBE_MRQC_VMDQRSS32EN:
 677         case IXGBE_MRQC_VMDQRT4TCEN:
 678                 num_qs = 4;  /* 32 VFs / pools */
 679                 bitmask = 0x0000000F;
 680                 break;
 681         default:            /* 64 VFs / pools */
 682                 num_qs = 2;
 683                 bitmask = 0x00000003;
 684                 break;
 685         }
 686         start_q = vf * num_qs;
 687
 688         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 689         idx = start_q / 32;
 690         reg = 0;
 691         reg |= (bitmask << (start_q % 32));
 692         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 693         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 694 }
 695
 696 /**
 697  *  ixgbe_mdd_event_X550
 698  *  @hw: pointer to hardware structure
 699  *  @vf_bitmap: vf bitmap of malicious vfs
 700  *
 701  *  Handle malicious driver detection event.
 702  **/
 703 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 704 {
 705         u32 wqbr;
 706         u32 i, j, reg, q, shift, vf, idx;
 707
 708         DEBUGFUNC("ixgbe_mdd_event_X550");
 709
 710         /* figure out pool size for mapping to vf's */
 711         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 712         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 713         case IXGBE_MRQC_VMDQRT8TCEN:
 714                 shift = 3;  /* 16 VFs / pools */
 715                 break;
 716         case IXGBE_MRQC_VMDQRSS32EN:
 717         case IXGBE_MRQC_VMDQRT4TCEN:
 718                 shift = 2;  /* 32 VFs / pools */
 719                 break;
 720         default:
 721                 shift = 1;  /* 64 VFs / pools */
 722                 break;
 723         }
 724
 725         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 726         for (i = 0; i < 4; i++) {
 727                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 728                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 729
 730                 if (!wqbr)
 731                         continue;
 732
 733                 /* Get malicious queue */
 734                 for (j = 0; j < 32 && wqbr; j++) {
 735
 736                         if (!(wqbr & (1 << j)))
 737                                 continue;
 738
 739                         /* Get queue from bitmask */
 740                         q = j + (i * 32);
 741
 742                         /* Map queue to vf */
 743                         vf = (q >> shift);
 744
 745                         /* Set vf bit in vf_bitmap */
 746                         idx = vf / 32;
 747                         vf_bitmap[idx] |= (1 << (vf % 32));
 748                         wqbr &= ~(1 << j);
 749                 }
 750         }
 751 }
 752
 753 /**
 754  *  ixgbe_get_media_type_X550em - Get media type
 755  *  @hw: pointer to hardware structure
 756  *
 757  *  Returns the media type (fiber, copper, backplane)
 758  */
 759 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 760 {
 761         enum ixgbe_media_type media_type;
 762
 763         DEBUGFUNC("ixgbe_get_media_type_X550em");
 764
 765         /* Detect if there is a copper PHY attached. */
 766         switch (hw->device_id) {
 767         case IXGBE_DEV_ID_X550EM_X:
 768         case IXGBE_DEV_ID_X550EM_X_KR:
 769         case IXGBE_DEV_ID_X550EM_X_KX4:
 770                 media_type = ixgbe_media_type_backplane;
 771                 break;
 772         case IXGBE_DEV_ID_X550EM_X_SFP:
 773                 media_type = ixgbe_media_type_fiber;
 774                 break;
 775         default:
 776                 media_type = ixgbe_media_type_unknown;
 777                 break;
 778         }
 779         return media_type;
 780 }
 781
 782 /**
 783  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 784  *  @hw: pointer to hardware structure
 785  */
 786 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 787 {
 788         bool setup_linear;
 789         u16 reg_slice, edc_mode;
 790         s32 ret_val;
 791
 792         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
 793
 794         switch (hw->phy.sfp_type) {
 795         case ixgbe_sfp_type_unknown:
 796                 return IXGBE_SUCCESS;
 797         case ixgbe_sfp_type_not_present:
 798                 return IXGBE_ERR_SFP_NOT_PRESENT;
 799         case ixgbe_sfp_type_da_cu_core0:
 800         case ixgbe_sfp_type_da_cu_core1:
 801                 setup_linear = true;
 802                 break;
 803         case ixgbe_sfp_type_srlr_core0:
 804         case ixgbe_sfp_type_srlr_core1:
 805         case ixgbe_sfp_type_da_act_lmt_core0:
 806         case ixgbe_sfp_type_da_act_lmt_core1:
 807         case ixgbe_sfp_type_1g_sx_core0:
 808         case ixgbe_sfp_type_1g_sx_core1:
 809         case ixgbe_sfp_type_1g_lx_core0:
 810         case ixgbe_sfp_type_1g_lx_core1:
 811                 setup_linear = false;
 812                 break;
 813         default:
 814                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 815         }
 816
 817         ixgbe_init_mac_link_ops_X550em(hw);
 818         hw->phy.ops.reset = NULL;
 819
 820         /* The CS4227 slice address is the base address + the port-pair reg
 821          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
 822          */
 823         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
 824
 825         if (setup_linear)
 826                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 827         else
 828                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 829
 830         /* Configure CS4227 for connection type. */
 831         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
 832                                            edc_mode);
 833
 834         if (ret_val != IXGBE_SUCCESS)
 835                 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
 836                                                    edc_mode);
 837
 838         return ret_val;
 839 }
 840
 841 /**
 842  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
 843  *  @hw: pointer to hardware structure
 844  */
 845 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
 846 {
 847         struct ixgbe_mac_info *mac = &hw->mac;
 848
 849         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
 850
 851         /* CS4227 does not support autoneg, so disable the laser control
 852          * functions for SFP+ fiber
 853          */
 854          if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 855                 mac->ops.disable_tx_laser = NULL;
 856                 mac->ops.enable_tx_laser = NULL;
 857                 mac->ops.flap_tx_laser = NULL;
 858          }
 859 }
 860
 861 /**
 862  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
 863  *  @hw: pointer to hardware structure
 864  *  @speed: pointer to link speed
 865  *  @autoneg: true when autoneg or autotry is enabled
 866  */
 867 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
 868                                        ixgbe_link_speed *speed,
 869                                        bool *autoneg)
 870 {
 871         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
 872
 873         /* SFP */
 874         if (hw->phy.media_type == ixgbe_media_type_fiber) {
 875
 876                 /* CS4227 SFP must not enable auto-negotiation */
 877                 *autoneg = false;
 878
 879                 /* Check if 1G SFP module. */
 880                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
 881                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
 882                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
 883                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
 884                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
 885                         return IXGBE_SUCCESS;
 886                 }
 887
 888                 /* Link capabilities are based on SFP */
 889                 if (hw->phy.multispeed_fiber)
 890                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
 891                                  IXGBE_LINK_SPEED_1GB_FULL;
 892                 else
 893                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 894         } else {
 895                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
 896                          IXGBE_LINK_SPEED_1GB_FULL;
 897                 *autoneg = true;
 898         }
 899
 900         return IXGBE_SUCCESS;
 901 }
 902
 903 /**
 904  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
 905  *  @hw: pointer to hardware structure
 906  *
 907  *  Initialize any function pointers that were not able to be
 908  *  set during init_shared_code because the PHY/SFP type was
 909  *  not known.  Perform the SFP init if necessary.
 910  */
 911 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
 912 {
 913         struct ixgbe_phy_info *phy = &hw->phy;
 914         s32 ret_val;
 915         u32 esdp;
 916
 917         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
 918
 919         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 920                 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 921                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 922
 923                 if (hw->bus.lan_id) {
 924                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 925                         esdp |= IXGBE_ESDP_SDP1_DIR;
 926                 }
 927                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 928                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 929         }
 930
 931         /* Identify the PHY or SFP module */
 932         ret_val = phy->ops.identify(hw);
 933         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
 934                 return ret_val;
 935
 936         /* Setup function pointers based on detected SFP module and speeds */
 937         ixgbe_init_mac_link_ops_X550em(hw);
 938         if (phy->sfp_type != ixgbe_sfp_type_unknown)
 939                 phy->ops.reset = NULL;
 940
 941         /* Set functions pointers based on phy type */
 942         switch (hw->phy.type) {
 943         case ixgbe_phy_x550em_kr:
 944                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
 945                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
 946                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
 947                 break;
 948         case ixgbe_phy_x550em_ext_t:
 949                 phy->ops.setup_internal_link = ixgbe_setup_internal_phy_x550em;
 950                 break;
 951         default:
 952                 break;
 953         }
 954         return ret_val;
 955 }
 956
 957 /**
 958  *  ixgbe_reset_hw_X550em - Perform hardware reset
 959  *  @hw: pointer to hardware structure
 960  *
 961  *  Resets the hardware by resetting the transmit and receive units, masks
 962  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
 963  *  reset.
 964  */
 965 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
 966 {
 967         ixgbe_link_speed link_speed;
 968         s32 status;
 969         u32 ctrl = 0;
 970         u32 i;
 971         bool link_up = false;
 972
 973         DEBUGFUNC("ixgbe_reset_hw_X550em");
 974
 975         /* Call adapter stop to disable Tx/Rx and clear interrupts */
 976         status = hw->mac.ops.stop_adapter(hw);
 977         if (status != IXGBE_SUCCESS)
 978                 return status;
 979
 980         /* flush pending Tx transactions */
 981         ixgbe_clear_tx_pending(hw);
 982
 983         /* PHY ops must be identified and initialized prior to reset */
 984
 985         /* Identify PHY and related function pointers */
 986         status = hw->phy.ops.init(hw);
 987
 988         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 989                 return status;
 990
 991         /* start the external PHY */
 992         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
 993                 status = ixgbe_init_ext_t_x550em(hw);
 994                 if (status)
 995                         return status;
 996         }
 997
 998         /* Setup SFP module if there is one present. */
 999         if (hw->phy.sfp_setup_needed) {
1000                 status = hw->mac.ops.setup_sfp(hw);
1001                 hw->phy.sfp_setup_needed = false;
1002         }
1003
1004         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1005                 return status;
1006
1007         /* Reset PHY */
1008         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1009                 hw->phy.ops.reset(hw);
1010
1011 mac_reset_top:
1012         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1013          * If link reset is used when link is up, it might reset the PHY when
1014          * mng is using it.  If link is down or the flag to force full link
1015          * reset is set, then perform link reset.
1016          */
1017         ctrl = IXGBE_CTRL_LNK_RST;
1018         if (!hw->force_full_reset) {
1019                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1020                 if (link_up)
1021                         ctrl = IXGBE_CTRL_RST;
1022         }
1023
1024         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1025         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1026         IXGBE_WRITE_FLUSH(hw);
1027
1028         /* Poll for reset bit to self-clear meaning reset is complete */
1029         for (i = 0; i < 10; i++) {
1030                 usec_delay(1);
1031                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1032                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1033                         break;
1034         }
1035
1036         if (ctrl & IXGBE_CTRL_RST_MASK) {
1037                 status = IXGBE_ERR_RESET_FAILED;
1038                 DEBUGOUT("Reset polling failed to complete.\n");
1039         }
1040
1041         msec_delay(50);
1042
1043         /* Double resets are required for recovery from certain error
1044          * conditions.  Between resets, it is necessary to stall to
1045          * allow time for any pending HW events to complete.
1046          */
1047         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1048                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1049                 goto mac_reset_top;
1050         }
1051
1052         /* Store the permanent mac address */
1053         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1054
1055         /* Store MAC address from RAR0, clear receive address registers, and
1056          * clear the multicast table.  Also reset num_rar_entries to 128,
1057          * since we modify this value when programming the SAN MAC address.
1058          */
1059         hw->mac.num_rar_entries = 128;
1060         hw->mac.ops.init_rx_addrs(hw);
1061
1062
1063         return status;
1064 }
1065
1066 /**
1067  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1068  * @hw: pointer to hardware structure
1069  */
1070 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1071 {
1072         u32 status;
1073         u16 reg;
1074         u32 retries = 1;
1075
1076         /* TODO: The number of attempts and delay between attempts is undefined */
1077         do {
1078                 /* decrement retries counter and exit if we hit 0 */
1079                 if (retries < 1) {
1080                         ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1081                                       "External PHY not yet finished resetting.");
1082                         return IXGBE_ERR_PHY;
1083                 }
1084                 retries--;
1085
1086                 usec_delay(0);
1087
1088                 status = hw->phy.ops.read_reg(hw,
1089                                               IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1090                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1091                                               &reg);
1092
1093                 if (status != IXGBE_SUCCESS)
1094                         return status;
1095
1096                 /* Verify PHY FW reset has completed */
1097         } while ((reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) != 1);
1098
1099         /* Set port to low power mode */
1100         status = hw->phy.ops.read_reg(hw,
1101                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1102                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1103                                       &reg);
1104
1105         if (status != IXGBE_SUCCESS)
1106                 return status;
1107
1108         reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
1109
1110         status = hw->phy.ops.write_reg(hw,
1111                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1112                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1113                                        reg);
1114
1115         if (status != IXGBE_SUCCESS)
1116                 return status;
1117
1118         /* Enable the transmitter */
1119         status = hw->phy.ops.read_reg(hw,
1120                                       IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1121                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1122                                       &reg);
1123
1124         if (status != IXGBE_SUCCESS)
1125                 return status;
1126
1127         reg &= ~IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE;
1128
1129         status = hw->phy.ops.write_reg(hw,
1130                                        IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1131                                        IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1132                                        reg);
1133
1134         if (status != IXGBE_SUCCESS)
1135                 return status;
1136
1137         /* Un-stall the PHY FW */
1138         status = hw->phy.ops.read_reg(hw,
1139                                       IXGBE_MDIO_GLOBAL_RES_PR_10,
1140                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1141                                       &reg);
1142
1143         if (status != IXGBE_SUCCESS)
1144                 return status;
1145
1146         reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1147
1148         status = hw->phy.ops.write_reg(hw,
1149                                        IXGBE_MDIO_GLOBAL_RES_PR_10,
1150                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1151                                        reg);
1152
1153         return status;
1154 }
1155
1156 /**
1157  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1158  *  @hw: pointer to hardware structure
1159  *
1160  *  Configures the integrated KR PHY.
1161  **/
1162 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1163 {
1164         s32 status;
1165         u32 reg_val;
1166
1167         status = ixgbe_read_iosf_sb_reg_x550(hw,
1168                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1169                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1170         if (status)
1171                 return status;
1172
1173         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1174         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ;
1175         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1176         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1177                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1178
1179         /* Advertise 10G support. */
1180         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1181                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1182
1183         /* Advertise 1G support. */
1184         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1185                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1186
1187         /* Restart auto-negotiation. */
1188         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1189         status = ixgbe_write_iosf_sb_reg_x550(hw,
1190                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1191                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1192
1193         return status;
1194 }
1195
1196 /**
1197  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI.
1198  *  @hw: pointer to hardware structure
1199  *  @speed: the link speed to force
1200  *
1201  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1202  *  internal and external PHY at a specific speed, without autonegotiation.
1203  **/
1204 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1205 {
1206         s32 status;
1207         u32 reg_val;
1208
1209         /* Disable AN and force speed to 10G Serial. */
1210         status = ixgbe_read_iosf_sb_reg_x550(hw,
1211                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1212                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1213         if (status != IXGBE_SUCCESS)
1214                 return status;
1215
1216         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1217         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1218
1219         /* Select forced link speed for internal PHY. */
1220         switch (*speed) {
1221         case IXGBE_LINK_SPEED_10GB_FULL:
1222                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1223                 break;
1224         case IXGBE_LINK_SPEED_1GB_FULL:
1225                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1226                 break;
1227         default:
1228                 /* Other link speeds are not supported by internal KR PHY. */
1229                 return IXGBE_ERR_LINK_SETUP;
1230         }
1231
1232         status = ixgbe_write_iosf_sb_reg_x550(hw,
1233                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1234                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1235         if (status != IXGBE_SUCCESS)
1236                 return status;
1237
1238         /* Disable training protocol FSM. */
1239         status = ixgbe_read_iosf_sb_reg_x550(hw,
1240                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1241                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1242         if (status != IXGBE_SUCCESS)
1243                 return status;
1244         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1245         status = ixgbe_write_iosf_sb_reg_x550(hw,
1246                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1247                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1248         if (status != IXGBE_SUCCESS)
1249                 return status;
1250
1251         /* Disable Flex from training TXFFE. */
1252         status = ixgbe_read_iosf_sb_reg_x550(hw,
1253                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1254                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1255         if (status != IXGBE_SUCCESS)
1256                 return status;
1257         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1258         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1259         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1260         status = ixgbe_write_iosf_sb_reg_x550(hw,
1261                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1262                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1263         if (status != IXGBE_SUCCESS)
1264                 return status;
1265         status = ixgbe_read_iosf_sb_reg_x550(hw,
1266                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1267                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1268         if (status != IXGBE_SUCCESS)
1269                 return status;
1270         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1271         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1272         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1273         status = ixgbe_write_iosf_sb_reg_x550(hw,
1274                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1275                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1276         if (status != IXGBE_SUCCESS)
1277                 return status;
1278
1279         /* Enable override for coefficients. */
1280         status = ixgbe_read_iosf_sb_reg_x550(hw,
1281                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1282                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1283         if (status != IXGBE_SUCCESS)
1284                 return status;
1285         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1286         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1287         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1288         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1289         status = ixgbe_write_iosf_sb_reg_x550(hw,
1290                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1291                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1292         if (status != IXGBE_SUCCESS)
1293                 return status;
1294
1295         /* Toggle port SW reset by AN reset. */
1296         status = ixgbe_read_iosf_sb_reg_x550(hw,
1297                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1298                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1299         if (status != IXGBE_SUCCESS)
1300                 return status;
1301         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1302         status = ixgbe_write_iosf_sb_reg_x550(hw,
1303                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1304                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1305
1306         return status;
1307 }
1308
1309 /**
1310  * ixgbe_setup_internal_phy_x550em - Configure integrated KR PHY
1311  * @hw: point to hardware structure
1312  *
1313  * Configures the integrated KR PHY to talk to the external PHY. The base
1314  * driver will call this function when it gets notification via interrupt from
1315  * the external PHY. This function forces the internal PHY into iXFI mode at
1316  * the correct speed.
1317  *
1318  * A return of a non-zero value indicates an error, and the base driver should
1319  * not report link up.
1320  */
1321 s32 ixgbe_setup_internal_phy_x550em(struct ixgbe_hw *hw)
1322 {
1323         u32 status;
1324         u16 lasi, autoneg_status, speed;
1325         ixgbe_link_speed force_speed;
1326
1327         /* Verify that the external link status has changed */
1328         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_XENPAK_LASI_STATUS,
1329                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1330                                       &lasi);
1331         if (status != IXGBE_SUCCESS)
1332                 return status;
1333
1334         /* If there was no change in link status, we can just exit */
1335         if (!(lasi & IXGBE_XENPAK_LASI_LINK_STATUS_ALARM))
1336                 return IXGBE_SUCCESS;
1337
1338         /* we read this twice back to back to indicate current status */
1339         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1340                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1341                                       &autoneg_status);
1342         if (status != IXGBE_SUCCESS)
1343                 return status;
1344
1345         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1346                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1347                                       &autoneg_status);
1348         if (status != IXGBE_SUCCESS)
1349                 return status;
1350
1351         /* If link is not up return an error indicating treat link as down */
1352         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1353                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1354
1355         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1356                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1357                                       &speed);
1358
1359         /* clear everything but the speed and duplex bits */
1360         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1361
1362         switch (speed) {
1363         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1364                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1365                 break;
1366         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1367                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1368                 break;
1369         default:
1370                 /* Internal PHY does not support anything else */
1371                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1372         }
1373
1374         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1375 }
1376
1377 /**
1378  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1379  *  @hw: pointer to hardware structure
1380  *
1381  *  Configures the integrated KR PHY to use internal loopback mode.
1382  **/
1383 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1384 {
1385         s32 status;
1386         u32 reg_val;
1387
1388         /* Disable AN and force speed to 10G Serial. */
1389         status = ixgbe_read_iosf_sb_reg_x550(hw,
1390                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1391                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1392         if (status != IXGBE_SUCCESS)
1393                 return status;
1394         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1395         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1396         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1397         status = ixgbe_write_iosf_sb_reg_x550(hw,
1398                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1399                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1400         if (status != IXGBE_SUCCESS)
1401                 return status;
1402
1403         /* Set near-end loopback clocks. */
1404         status = ixgbe_read_iosf_sb_reg_x550(hw,
1405                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1406                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1407         if (status != IXGBE_SUCCESS)
1408                 return status;
1409         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1410         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1411         status = ixgbe_write_iosf_sb_reg_x550(hw,
1412                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1413                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1414         if (status != IXGBE_SUCCESS)
1415                 return status;
1416
1417         /* Set loopback enable. */
1418         status = ixgbe_read_iosf_sb_reg_x550(hw,
1419                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1420                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1421         if (status != IXGBE_SUCCESS)
1422                 return status;
1423         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1424         status = ixgbe_write_iosf_sb_reg_x550(hw,
1425                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1426                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1427         if (status != IXGBE_SUCCESS)
1428                 return status;
1429
1430         /* Training bypass. */
1431         status = ixgbe_read_iosf_sb_reg_x550(hw,
1432                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1433                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1434         if (status != IXGBE_SUCCESS)
1435                 return status;
1436         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1437         status = ixgbe_write_iosf_sb_reg_x550(hw,
1438                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1439                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1440
1441         return status;
1442 }
1443
1444 /**
1445  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1446  *  assuming that the semaphore is already obtained.
1447  *  @hw: pointer to hardware structure
1448  *  @offset: offset of  word in the EEPROM to read
1449  *  @data: word read from the EEPROM
1450  *
1451  *  Reads a 16 bit word from the EEPROM using the hostif.
1452  **/
1453 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1454                                    u16 *data)
1455 {
1456         s32 status;
1457         struct ixgbe_hic_read_shadow_ram buffer;
1458
1459         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1460         buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1461         buffer.hdr.buf_len1 = 0;
1462         buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1463         buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1464
1465         /* convert offset from words to bytes */
1466         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1467         /* one word */
1468         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1469
1470         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1471                                               sizeof(buffer), false);
1472
1473         if (status)
1474                 return status;
1475
1476         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1477                                           FW_NVM_DATA_OFFSET);
1478
1479         return 0;
1480 }
1481
1482 /**
1483  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1484  *  @hw: pointer to hardware structure
1485  *  @offset: offset of  word in the EEPROM to read
1486  *  @data: word read from the EEPROM
1487  *
1488  *  Reads a 16 bit word from the EEPROM using the hostif.
1489  **/
1490 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1491                               u16 *data)
1492 {
1493         s32 status = IXGBE_SUCCESS;
1494
1495         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1496
1497         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1498             IXGBE_SUCCESS) {
1499                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1500                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1501         } else {
1502                 status = IXGBE_ERR_SWFW_SYNC;
1503         }
1504
1505         return status;
1506 }
1507
1508 /**
1509  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1510  *  @hw: pointer to hardware structure
1511  *  @offset: offset of  word in the EEPROM to read
1512  *  @words: number of words
1513  *  @data: word(s) read from the EEPROM
1514  *
1515  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1516  **/
1517 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1518                                      u16 offset, u16 words, u16 *data)
1519 {
1520         struct ixgbe_hic_read_shadow_ram buffer;
1521         u32 current_word = 0;
1522         u16 words_to_read;
1523         s32 status;
1524         u32 i;
1525
1526         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1527
1528         /* Take semaphore for the entire operation. */
1529         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1530         if (status) {
1531                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1532                 return status;
1533         }
1534         while (words) {
1535                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1536                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1537                 else
1538                         words_to_read = words;
1539
1540                 buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1541                 buffer.hdr.buf_len1 = 0;
1542                 buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1543                 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1544
1545                 /* convert offset from words to bytes */
1546                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1547                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1548
1549                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1550                                                       sizeof(buffer), false);
1551
1552                 if (status) {
1553                         DEBUGOUT("Host interface command failed\n");
1554                         goto out;
1555                 }
1556
1557                 for (i = 0; i < words_to_read; i++) {
1558                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1559                                   2 * i;
1560                         u32 value = IXGBE_READ_REG(hw, reg);
1561
1562                         data[current_word] = (u16)(value & 0xffff);
1563                         current_word++;
1564                         i++;
1565                         if (i < words_to_read) {
1566                                 value >>= 16;
1567                                 data[current_word] = (u16)(value & 0xffff);
1568                                 current_word++;
1569                         }
1570                 }
1571                 words -= words_to_read;
1572         }
1573
1574 out:
1575         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1576         return status;
1577 }
1578
1579 /**
1580  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1581  *  @hw: pointer to hardware structure
1582  *  @offset: offset of  word in the EEPROM to write
1583  *  @data: word write to the EEPROM
1584  *
1585  *  Write a 16 bit word to the EEPROM using the hostif.
1586  **/
1587 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1588                                     u16 data)
1589 {
1590         s32 status;
1591         struct ixgbe_hic_write_shadow_ram buffer;
1592
1593         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1594
1595         buffer.hdr.cmd = FW_WRITE_SHADOW_RAM_CMD;
1596         buffer.hdr.buf_len1 = 0;
1597         buffer.hdr.buf_len2 = FW_WRITE_SHADOW_RAM_LEN;
1598         buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1599
1600          /* one word */
1601         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1602         buffer.data = data;
1603         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1604
1605         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1606                                               sizeof(buffer), false);
1607
1608         return status;
1609 }
1610
1611 /**
1612  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1613  *  @hw: pointer to hardware structure
1614  *  @offset: offset of  word in the EEPROM to write
1615  *  @data: word write to the EEPROM
1616  *
1617  *  Write a 16 bit word to the EEPROM using the hostif.
1618  **/
1619 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1620                                u16 data)
1621 {
1622         s32 status = IXGBE_SUCCESS;
1623
1624         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1625
1626         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1627             IXGBE_SUCCESS) {
1628                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1629                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1630         } else {
1631                 DEBUGOUT("write ee hostif failed to get semaphore");
1632                 status = IXGBE_ERR_SWFW_SYNC;
1633         }
1634
1635         return status;
1636 }
1637
1638 /**
1639  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1640  *  @hw: pointer to hardware structure
1641  *  @offset: offset of  word in the EEPROM to write
1642  *  @words: number of words
1643  *  @data: word(s) write to the EEPROM
1644  *
1645  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1646  **/
1647 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1648                                       u16 offset, u16 words, u16 *data)
1649 {
1650         s32 status = IXGBE_SUCCESS;
1651         u32 i = 0;
1652
1653         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1654
1655         /* Take semaphore for the entire operation. */
1656         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1657         if (status != IXGBE_SUCCESS) {
1658                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1659                 goto out;
1660         }
1661
1662         for (i = 0; i < words; i++) {
1663                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1664                                                          data[i]);
1665
1666                 if (status != IXGBE_SUCCESS) {
1667                         DEBUGOUT("Eeprom buffered write failed\n");
1668                         break;
1669                 }
1670         }
1671
1672         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1673 out:
1674
1675         return status;
1676 }
1677
1678 /**
1679  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1680  * @hw: pointer to hardware structure
1681  * @ptr: pointer offset in eeprom
1682  * @size: size of section pointed by ptr, if 0 first word will be used as size
1683  * @csum: address of checksum to update
1684  *
1685  * Returns error status for any failure
1686  */
1687 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1688                                    u16 size, u16 *csum)
1689 {
1690         u16 buf[256];
1691         s32 status;
1692         u16 length, bufsz, i, start;
1693
1694         bufsz = sizeof(buf) / sizeof(buf[0]);
1695
1696         /* Read a chunk at the pointer location */
1697         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1698         if (status) {
1699                 DEBUGOUT("Failed to read EEPROM image\n");
1700                 return status;
1701         }
1702
1703         if (size) {
1704                 start = 0;
1705                 length = size;
1706         } else {
1707                 start = 1;
1708                 length = buf[0];
1709
1710                 /* Skip pointer section if length is invalid. */
1711                 if (length == 0xFFFF || length == 0 ||
1712                     (ptr + length) >= hw->eeprom.word_size)
1713                         return IXGBE_SUCCESS;
1714         }
1715
1716         for (i = start; length; i++, length--) {
1717                 if (i == bufsz) {
1718                         ptr += bufsz;
1719                         i = 0;
1720                         if (length < bufsz)
1721                                 bufsz = length;
1722
1723                         /* Read a chunk at the pointer location */
1724                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1725                                                                   bufsz, buf);
1726                         if (status) {
1727                                 DEBUGOUT("Failed to read EEPROM image\n");
1728                                 return status;
1729                         }
1730                 }
1731                 *csum += buf[i];
1732         }
1733         return IXGBE_SUCCESS;
1734 }
1735
1736 /**
1737  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1738  *  @hw: pointer to hardware structure
1739  *
1740  *  Returns a negative error code on error, or the 16-bit checksum
1741  **/
1742 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1743 {
1744         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1745         s32 status;
1746         u16 checksum = 0;
1747         u16 pointer, i, size;
1748
1749         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
1750
1751         hw->eeprom.ops.init_params(hw);
1752
1753         /* Read pointer area */
1754         status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1755                                                   IXGBE_EEPROM_LAST_WORD + 1,
1756                                                   eeprom_ptrs);
1757         if (status) {
1758                 DEBUGOUT("Failed to read EEPROM image\n");
1759                 return status;
1760         }
1761
1762         /*
1763          * For X550 hardware include 0x0-0x41 in the checksum, skip the
1764          * checksum word itself
1765          */
1766         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1767                 if (i != IXGBE_EEPROM_CHECKSUM)
1768                         checksum += eeprom_ptrs[i];
1769
1770         /*
1771          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
1772          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1773          */
1774         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1775                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1776                         continue;
1777
1778                 pointer = eeprom_ptrs[i];
1779
1780                 /* Skip pointer section if the pointer is invalid. */
1781                 if (pointer == 0xFFFF || pointer == 0 ||
1782                     pointer >= hw->eeprom.word_size)
1783                         continue;
1784
1785                 switch (i) {
1786                 case IXGBE_PCIE_GENERAL_PTR:
1787                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1788                         break;
1789                 case IXGBE_PCIE_CONFIG0_PTR:
1790                 case IXGBE_PCIE_CONFIG1_PTR:
1791                         size = IXGBE_PCIE_CONFIG_SIZE;
1792                         break;
1793                 default:
1794                         size = 0;
1795                         break;
1796                 }
1797
1798                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum);
1799                 if (status)
1800                         return status;
1801         }
1802
1803         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1804
1805         return (s32)checksum;
1806 }
1807
1808 /**
1809  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1810  *  @hw: pointer to hardware structure
1811  *  @checksum_val: calculated checksum
1812  *
1813  *  Performs checksum calculation and validates the EEPROM checksum.  If the
1814  *  caller does not need checksum_val, the value can be NULL.
1815  **/
1816 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
1817 {
1818         s32 status;
1819         u16 checksum;
1820         u16 read_checksum = 0;
1821
1822         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
1823
1824         /* Read the first word from the EEPROM. If this times out or fails, do
1825          * not continue or we could be in for a very long wait while every
1826          * EEPROM read fails
1827          */
1828         status = hw->eeprom.ops.read(hw, 0, &checksum);
1829         if (status) {
1830                 DEBUGOUT("EEPROM read failed\n");
1831                 return status;
1832         }
1833
1834         status = hw->eeprom.ops.calc_checksum(hw);
1835         if (status < 0)
1836                 return status;
1837
1838         checksum = (u16)(status & 0xffff);
1839
1840         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1841                                            &read_checksum);
1842         if (status)
1843                 return status;
1844
1845         /* Verify read checksum from EEPROM is the same as
1846          * calculated checksum
1847          */
1848         if (read_checksum != checksum) {
1849                 status = IXGBE_ERR_EEPROM_CHECKSUM;
1850                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1851                              "Invalid EEPROM checksum");
1852         }
1853
1854         /* If the user cares, return the calculated checksum */
1855         if (checksum_val)
1856                 *checksum_val = checksum;
1857
1858         return status;
1859 }
1860
1861 /**
1862  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1863  * @hw: pointer to hardware structure
1864  *
1865  * After writing EEPROM to shadow RAM using EEWR register, software calculates
1866  * checksum and updates the EEPROM and instructs the hardware to update
1867  * the flash.
1868  **/
1869 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1870 {
1871         s32 status;
1872         u16 checksum = 0;
1873
1874         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
1875
1876         /* Read the first word from the EEPROM. If this times out or fails, do
1877          * not continue or we could be in for a very long wait while every
1878          * EEPROM read fails
1879          */
1880         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1881         if (status) {
1882                 DEBUGOUT("EEPROM read failed\n");
1883                 return status;
1884         }
1885
1886         status = ixgbe_calc_eeprom_checksum_X550(hw);
1887         if (status < 0)
1888                 return status;
1889
1890         checksum = (u16)(status & 0xffff);
1891
1892         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1893                                             checksum);
1894         if (status)
1895                 return status;
1896
1897         status = ixgbe_update_flash_X550(hw);
1898
1899         return status;
1900 }
1901
1902 /**
1903  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1904  *  @hw: pointer to hardware structure
1905  *
1906  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1907  **/
1908 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1909 {
1910         s32 status = IXGBE_SUCCESS;
1911         struct ixgbe_hic_hdr2 buffer;
1912
1913         DEBUGFUNC("ixgbe_update_flash_X550");
1914
1915         buffer.cmd = FW_SHADOW_RAM_DUMP_CMD;
1916         buffer.buf_len1 = 0;
1917         buffer.buf_len2 = FW_SHADOW_RAM_DUMP_LEN;
1918         buffer.checksum = FW_DEFAULT_CHECKSUM;
1919
1920         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1921                                               sizeof(buffer), false);
1922
1923         return status;
1924 }
1925
1926 /**
1927  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
1928  *  @hw: pointer to hardware structure
1929  *
1930  *  Determines physical layer capabilities of the current configuration.
1931  **/
1932 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
1933 {
1934         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1935         u16 ext_ability = 0;
1936
1937         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
1938
1939         hw->phy.ops.identify(hw);
1940
1941         switch (hw->phy.type) {
1942         case ixgbe_phy_x550em_kr:
1943                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
1944                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1945                 break;
1946         case ixgbe_phy_x550em_kx4:
1947                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1948                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1949                 break;
1950         case ixgbe_phy_x550em_ext_t:
1951                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1952                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1953                                      &ext_ability);
1954                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1955                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1956                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1957                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1958                 break;
1959         default:
1960                 break;
1961         }
1962
1963         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
1964                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
1965
1966         return physical_layer;
1967 }
1968
1969 /**
1970  * ixgbe_get_bus_info_x550em - Set PCI bus info
1971  * @hw: pointer to hardware structure
1972  *
1973  * Sets bus link width and speed to unknown because X550em is
1974  * not a PCI device.
1975  **/
1976 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
1977 {
1978
1979         DEBUGFUNC("ixgbe_get_bus_info_x550em");
1980
1981         hw->bus.width = ixgbe_bus_width_unknown;
1982         hw->bus.speed = ixgbe_bus_speed_unknown;
1983
1984         return IXGBE_SUCCESS;
1985 }
1986
1987 /**
1988  * ixgbe_disable_rx_x550 - Disable RX unit
1989  *
1990  * Enables the Rx DMA unit for x550
1991  **/
1992 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1993 {
1994         u32 rxctrl, pfdtxgswc;
1995         s32 status;
1996         struct ixgbe_hic_disable_rxen fw_cmd;
1997
1998         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
1999
2000         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2001         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2002                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2003                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2004                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2005                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2006                         hw->mac.set_lben = true;
2007                 } else {
2008                         hw->mac.set_lben = false;
2009                 }
2010
2011                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2012                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2013                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2014                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2015
2016                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2017                                         sizeof(struct ixgbe_hic_disable_rxen),
2018                                         true);
2019
2020                 /* If we fail - disable RX using register write */
2021                 if (status) {
2022                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2023                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2024                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2025                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2026                         }
2027                 }
2028         }
2029 }