lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 /**
  42  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  43  *  @hw: pointer to hardware structure
  44  *
  45  *  Initialize the function pointers and assign the MAC type for X550.
  46  *  Does not touch the hardware.
  47  **/
  48 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  49 {
  50         struct ixgbe_mac_info *mac = &hw->mac;
  51         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  52         s32 ret_val;
  53
  54         DEBUGFUNC("ixgbe_init_ops_X550");
  55
  56         ret_val = ixgbe_init_ops_X540(hw);
  57         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  58         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  59         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  60         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  61         mac->ops.set_source_address_pruning =
  62                         ixgbe_set_source_address_pruning_X550;
  63         mac->ops.set_ethertype_anti_spoofing =
  64                         ixgbe_set_ethertype_anti_spoofing_X550;
  65
  66         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  67         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  68         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  69         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  70         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  71         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  72         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  73         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  74         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  75
  76         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  77         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  78         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  79         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  80         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  81         return ret_val;
  82 }
  83
  84 /**
  85  * ixgbe_identify_phy_x550em - Get PHY type based on device id
  86  * @hw: pointer to hardware structure
  87  *
  88  * Returns error code
  89  */
  90 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
  91 {
  92         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  93
  94         switch (hw->device_id) {
  95         case IXGBE_DEV_ID_X550EM_X_SFP:
  96                 /* set up for CS4227 usage */
  97                 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
  98                                  IXGBE_STATUS_LAN_ID_1;
  99                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 100                 if (hw->phy.lan_id) {
 101
 102                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 103                         esdp |= IXGBE_ESDP_SDP1_DIR;
 104                 }
 105                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 106                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 107
 108                 return ixgbe_identify_module_generic(hw);
 109                 break;
 110         case IXGBE_DEV_ID_X550EM_X_KX4:
 111                 hw->phy.type = ixgbe_phy_x550em_kx4;
 112                 break;
 113         case IXGBE_DEV_ID_X550EM_X_KR:
 114         case IXGBE_DEV_ID_X550EM_X:
 115                 hw->phy.type = ixgbe_phy_x550em_kr;
 116                 break;
 117         default:
 118                 break;
 119         }
 120         return IXGBE_SUCCESS;
 121 }
 122
 123 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 124                                      u32 device_type, u16 *phy_data)
 125 {
 126         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 127         return IXGBE_NOT_IMPLEMENTED;
 128 }
 129
 130 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 131                                       u32 device_type, u16 phy_data)
 132 {
 133         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 134         return IXGBE_NOT_IMPLEMENTED;
 135 }
 136
 137 /**
 138 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 139 *  @hw: pointer to hardware structure
 140 *
 141 *  Initialize the function pointers and for MAC type X550EM.
 142 *  Does not touch the hardware.
 143 **/
 144 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 145 {
 146         struct ixgbe_mac_info *mac = &hw->mac;
 147         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 148         struct ixgbe_phy_info *phy = &hw->phy;
 149         s32 ret_val;
 150
 151         DEBUGFUNC("ixgbe_init_ops_X550EM");
 152
 153         /* Similar to X550 so start there. */
 154         ret_val = ixgbe_init_ops_X550(hw);
 155
 156         /* Since this function eventually calls
 157          * ixgbe_init_ops_540 by design, we are setting
 158          * the pointers to NULL explicitly here to overwrite
 159          * the values being set in the x540 function.
 160          */
 161         /* Thermal sensor not supported in x550EM */
 162         mac->ops.get_thermal_sensor_data = NULL;
 163         mac->ops.init_thermal_sensor_thresh = NULL;
 164         mac->thermal_sensor_enabled = false;
 165
 166         /* FCOE not supported in x550EM */
 167         mac->ops.get_san_mac_addr = NULL;
 168         mac->ops.set_san_mac_addr = NULL;
 169         mac->ops.get_wwn_prefix = NULL;
 170         mac->ops.get_fcoe_boot_status = NULL;
 171
 172         /* IPsec not supported in x550EM */
 173         mac->ops.disable_sec_rx_path = NULL;
 174         mac->ops.enable_sec_rx_path = NULL;
 175
 176         /* PCIe bus info not supported in X550EM */
 177         mac->ops.get_bus_info = NULL;
 178
 179         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 180         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 181         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 182         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 183         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 184         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 185         mac->ops.get_supported_physical_layer =
 186                                     ixgbe_get_supported_physical_layer_X550em;
 187
 188         /* PHY */
 189         phy->ops.init = &ixgbe_init_phy_ops_X550em;
 190         phy->ops.identify = &ixgbe_identify_phy_x550em;
 191         phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
 192         phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
 193         phy->ops.setup_link = ixgbe_setup_kr_x550em;
 194
 195
 196         /* EEPROM */
 197         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 198         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 199         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 200         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 201         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 202         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 203         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 204         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 205
 206         return ret_val;
 207 }
 208
 209 /**
 210  *  ixgbe_dmac_config_X550
 211  *  @hw: pointer to hardware structure
 212  *
 213  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 214  *  When disabling dmac, dmac enable dmac bit is cleared.
 215  **/
 216 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 217 {
 218         u32 reg, high_pri_tc;
 219
 220         DEBUGFUNC("ixgbe_dmac_config_X550");
 221
 222         /* Disable DMA coalescing before configuring */
 223         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 224         reg &= ~IXGBE_DMACR_DMAC_EN;
 225         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 226
 227         /* Disable DMA Coalescing if the watchdog timer is 0 */
 228         if (!hw->mac.dmac_config.watchdog_timer)
 229                 goto out;
 230
 231         ixgbe_dmac_config_tcs_X550(hw);
 232
 233         /* Configure DMA Coalescing Control Register */
 234         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 235
 236         /* Set the watchdog timer in units of 40.96 usec */
 237         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 238         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 239
 240         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 241         /* If fcoe is enabled, set high priority traffic class */
 242         if (hw->mac.dmac_config.fcoe_en) {
 243                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 244                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 245                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 246         }
 247         reg |= IXGBE_DMACR_EN_MNG_IND;
 248
 249         /* Enable DMA coalescing after configuration */
 250         reg |= IXGBE_DMACR_DMAC_EN;
 251         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 252
 253 out:
 254         return IXGBE_SUCCESS;
 255 }
 256
 257 /**
 258  *  ixgbe_dmac_config_tcs_X550
 259  *  @hw: pointer to hardware structure
 260  *
 261  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 262  *  be cleared before configuring.
 263  **/
 264 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 265 {
 266         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 267
 268         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 269
 270         /* Configure DMA coalescing enabled */
 271         switch (hw->mac.dmac_config.link_speed) {
 272         case IXGBE_LINK_SPEED_100_FULL:
 273                 pb_headroom = IXGBE_DMACRXT_100M;
 274                 break;
 275         case IXGBE_LINK_SPEED_1GB_FULL:
 276                 pb_headroom = IXGBE_DMACRXT_1G;
 277                 break;
 278         default:
 279                 pb_headroom = IXGBE_DMACRXT_10G;
 280                 break;
 281         }
 282
 283         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 284                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 285
 286         /* Set the per Rx packet buffer receive threshold */
 287         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 288                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 289                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 290
 291                 if (tc < hw->mac.dmac_config.num_tcs) {
 292                         /* Get Rx PB size */
 293                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 294                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 295                                 IXGBE_RXPBSIZE_SHIFT;
 296
 297                         /* Calculate receive buffer threshold in kilobytes */
 298                         if (rx_pb_size > pb_headroom)
 299                                 rx_pb_size = rx_pb_size - pb_headroom;
 300                         else
 301                                 rx_pb_size = 0;
 302
 303                         /* Minimum of MFS shall be set for DMCTH */
 304                         reg |= (rx_pb_size > maxframe_size_kb) ?
 305                                 rx_pb_size : maxframe_size_kb;
 306                 }
 307                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 308         }
 309         return IXGBE_SUCCESS;
 310 }
 311
 312 /**
 313  *  ixgbe_dmac_update_tcs_X550
 314  *  @hw: pointer to hardware structure
 315  *
 316  *  Disables dmac, updates per TC settings, and then enables dmac.
 317  **/
 318 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 319 {
 320         u32 reg;
 321
 322         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 323
 324         /* Disable DMA coalescing before configuring */
 325         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 326         reg &= ~IXGBE_DMACR_DMAC_EN;
 327         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 328
 329         ixgbe_dmac_config_tcs_X550(hw);
 330
 331         /* Enable DMA coalescing after configuration */
 332         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 333         reg |= IXGBE_DMACR_DMAC_EN;
 334         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 335
 336         return IXGBE_SUCCESS;
 337 }
 338
 339 /**
 340  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 341  *  @hw: pointer to hardware structure
 342  *
 343  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 344  *  ixgbe_hw struct in order to set up EEPROM access.
 345  **/
 346 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 347 {
 348         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 349         u32 eec;
 350         u16 eeprom_size;
 351
 352         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 353
 354         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 355                 eeprom->semaphore_delay = 10;
 356                 eeprom->type = ixgbe_flash;
 357
 358                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 359                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 360                                     IXGBE_EEC_SIZE_SHIFT);
 361                 eeprom->word_size = 1 << (eeprom_size +
 362                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 363
 364                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 365                           eeprom->type, eeprom->word_size);
 366         }
 367
 368         return IXGBE_SUCCESS;
 369 }
 370
 371 /**
 372  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 373  *  @hw: pointer to the HW structure
 374  *  @enable_eee: boolean flag to enable EEE
 375  *
 376  *  Enable/disable EEE based on enable_eee flag.
 377  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 378  *  are modified.
 379  *
 380  **/
 381 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 382 {
 383         u32 eeer;
 384         u16 autoneg_eee_reg;
 385         u32 link_reg;
 386         s32 status;
 387
 388         DEBUGFUNC("ixgbe_setup_eee_X550");
 389
 390         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 391         /* Enable or disable EEE per flag */
 392         if (enable_eee) {
 393                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 394
 395                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 396                         /* Advertise EEE capability */
 397                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 398                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 399
 400                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 401                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 402                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 403
 404                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 405                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 406                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
 407                            hw->device_id == IXGBE_DEV_ID_X550EM_X) {
 408                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 409                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 410                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 411                         if (status != IXGBE_SUCCESS)
 412                                 return status;
 413
 414                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 415                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 416
 417                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 418                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 419                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 420                         if (status != IXGBE_SUCCESS)
 421                                 return status;
 422                 }
 423         } else {
 424                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 425
 426                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 427                         /* Disable advertised EEE capability */
 428                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 429                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 430
 431                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 432                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 433                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 434
 435                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 436                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 437                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
 438                            hw->device_id == IXGBE_DEV_ID_X550EM_X) {
 439                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 440                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 441                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 442                         if (status != IXGBE_SUCCESS)
 443                                 return status;
 444
 445                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 446                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 447
 448                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 449                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 450                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 451                         if (status != IXGBE_SUCCESS)
 452                                 return status;
 453                 }
 454         }
 455         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 456
 457         return IXGBE_SUCCESS;
 458 }
 459
 460 /**
 461  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 462  * @hw: pointer to hardware structure
 463  * @enable: enable or disable source address pruning
 464  * @pool: Rx pool to set source address pruning for
 465  **/
 466 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 467                                            unsigned int pool)
 468 {
 469         u64 pfflp;
 470
 471         /* max rx pool is 63 */
 472         if (pool > 63)
 473                 return;
 474
 475         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 476         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 477
 478         if (enable)
 479                 pfflp |= (1ULL << pool);
 480         else
 481                 pfflp &= ~(1ULL << pool);
 482
 483         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 484         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 485 }
 486
 487 /**
 488  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 489  *  @hw: pointer to hardware structure
 490  *  @enable: enable or disable switch for Ethertype anti-spoofing
 491  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 492  *
 493  **/
 494 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 495                 bool enable, int vf)
 496 {
 497         int vf_target_reg = vf >> 3;
 498         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 499         u32 pfvfspoof;
 500
 501         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 502
 503         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 504         if (enable)
 505                 pfvfspoof |= (1 << vf_target_shift);
 506         else
 507                 pfvfspoof &= ~(1 << vf_target_shift);
 508
 509         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 510 }
 511
 512 /**
 513  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 514  *  device
 515  *  @hw: pointer to hardware structure
 516  *  @reg_addr: 32 bit PHY register to write
 517  *  @device_type: 3 bit device type
 518  *  @data: Data to write to the register
 519  **/
 520 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 521                             u32 device_type, u32 data)
 522 {
 523         u32 i, command, error;
 524
 525         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 526                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 527
 528         /* Write IOSF control register */
 529         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 530
 531         /* Write IOSF data register */
 532         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 533         /*
 534          * Check every 10 usec to see if the address cycle completed.
 535          * The SB IOSF BUSY bit will clear when the operation is
 536          * complete
 537          */
 538         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 539                 usec_delay(10);
 540
 541                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 542                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 543                         break;
 544         }
 545
 546         if ((command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) != 0) {
 547                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 548                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 549                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 550                               "Failed to write, error %x\n", error);
 551                 return IXGBE_ERR_PHY;
 552         }
 553
 554         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 555                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 556                 return IXGBE_ERR_PHY;
 557         }
 558
 559         return IXGBE_SUCCESS;
 560 }
 561
 562 /**
 563  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 564  *  device
 565  *  @hw: pointer to hardware structure
 566  *  @reg_addr: 32 bit PHY register to write
 567  *  @device_type: 3 bit device type
 568  *  @phy_data: Pointer to read data from the register
 569  **/
 570 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 571                            u32 device_type, u32 *data)
 572 {
 573         u32 i, command, error;
 574
 575         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 576                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 577
 578         /* Write IOSF control register */
 579         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 580
 581         /*
 582          * Check every 10 usec to see if the address cycle completed.
 583          * The SB IOSF BUSY bit will clear when the operation is
 584          * complete
 585          */
 586         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 587                 usec_delay(10);
 588
 589                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 590                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 591                         break;
 592         }
 593
 594         if ((command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) != 0) {
 595                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 596                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 597                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 598                                 "Failed to read, error %x\n", error);
 599                 return IXGBE_ERR_PHY;
 600         }
 601
 602         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 603                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 604                 return IXGBE_ERR_PHY;
 605         }
 606
 607         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 608
 609         return IXGBE_SUCCESS;
 610 }
 611
 612 /**
 613  *  ixgbe_disable_mdd_X550
 614  *  @hw: pointer to hardware structure
 615  *
 616  *  Disable malicious driver detection
 617  **/
 618 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 619 {
 620         u32 reg;
 621
 622         DEBUGFUNC("ixgbe_disable_mdd_X550");
 623
 624         /* Disable MDD for TX DMA and interrupt */
 625         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 626         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 627         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 628
 629         /* Disable MDD for RX and interrupt */
 630         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 631         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 632         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 633 }
 634
 635 /**
 636  *  ixgbe_enable_mdd_X550
 637  *  @hw: pointer to hardware structure
 638  *
 639  *  Enable malicious driver detection
 640  **/
 641 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 642 {
 643         u32 reg;
 644
 645         DEBUGFUNC("ixgbe_enable_mdd_X550");
 646
 647         /* Enable MDD for TX DMA and interrupt */
 648         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 649         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 650         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 651
 652         /* Enable MDD for RX and interrupt */
 653         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 654         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 655         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 656 }
 657
 658 /**
 659  *  ixgbe_restore_mdd_vf_X550
 660  *  @hw: pointer to hardware structure
 661  *  @vf: vf index
 662  *
 663  *  Restore VF that was disabled during malicious driver detection event
 664  **/
 665 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 666 {
 667         u32 idx, reg, num_qs, start_q, bitmask;
 668
 669         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 670
 671         /* Map VF to queues */
 672         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 673         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 674         case IXGBE_MRQC_VMDQRT8TCEN:
 675                 num_qs = 8;  /* 16 VFs / pools */
 676                 bitmask = 0x000000FF;
 677                 break;
 678         case IXGBE_MRQC_VMDQRSS32EN:
 679         case IXGBE_MRQC_VMDQRT4TCEN:
 680                 num_qs = 4;  /* 32 VFs / pools */
 681                 bitmask = 0x0000000F;
 682                 break;
 683         default:            /* 64 VFs / pools */
 684                 num_qs = 2;
 685                 bitmask = 0x00000003;
 686                 break;
 687         }
 688         start_q = vf * num_qs;
 689
 690         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 691         idx = start_q / 32;
 692         reg = 0;
 693         reg |= (bitmask << (start_q % 32));
 694         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 695         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 696 }
 697
 698 /**
 699  *  ixgbe_mdd_event_X550
 700  *  @hw: pointer to hardware structure
 701  *  @vf_bitmap: vf bitmap of malicious vfs
 702  *
 703  *  Handle malicious driver detection event.
 704  **/
 705 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 706 {
 707         u32 wqbr;
 708         u32 i, j, reg, q, shift, vf, idx;
 709
 710         DEBUGFUNC("ixgbe_mdd_event_X550");
 711
 712         /* figure out pool size for mapping to vf's */
 713         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 714         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 715         case IXGBE_MRQC_VMDQRT8TCEN:
 716                 shift = 3;  /* 16 VFs / pools */
 717                 break;
 718         case IXGBE_MRQC_VMDQRSS32EN:
 719         case IXGBE_MRQC_VMDQRT4TCEN:
 720                 shift = 2;  /* 32 VFs / pools */
 721                 break;
 722         default:
 723                 shift = 1;  /* 64 VFs / pools */
 724                 break;
 725         }
 726
 727         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 728         for (i = 0; i < 4; i++) {
 729                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 730                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 731
 732                 if (!wqbr)
 733                         continue;
 734
 735                 /* Get malicious queue */
 736                 for (j = 0; j < 32 && wqbr; j++) {
 737
 738                         if (!(wqbr & (1 << j)))
 739                                 continue;
 740
 741                         /* Get queue from bitmask */
 742                         q = j + (i * 32);
 743
 744                         /* Map queue to vf */
 745                         vf = (q >> shift);
 746
 747                         /* Set vf bit in vf_bitmap */
 748                         idx = vf / 32;
 749                         vf_bitmap[idx] |= (1 << (vf % 32));
 750                         wqbr &= ~(1 << j);
 751                 }
 752         }
 753 }
 754
 755 /**
 756  *  ixgbe_get_media_type_X550em - Get media type
 757  *  @hw: pointer to hardware structure
 758  *
 759  *  Returns the media type (fiber, copper, backplane)
 760  */
 761 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 762 {
 763         enum ixgbe_media_type media_type;
 764
 765         DEBUGFUNC("ixgbe_get_media_type_X550em");
 766
 767         /* Detect if there is a copper PHY attached. */
 768         switch (hw->device_id) {
 769         case IXGBE_DEV_ID_X550EM_X:
 770         case IXGBE_DEV_ID_X550EM_X_KR:
 771         case IXGBE_DEV_ID_X550EM_X_KX4:
 772                 media_type = ixgbe_media_type_backplane;
 773                 break;
 774         case IXGBE_DEV_ID_X550EM_X_SFP:
 775                 media_type = ixgbe_media_type_fiber;
 776                 break;
 777         default:
 778                 media_type = ixgbe_media_type_unknown;
 779                 break;
 780         }
 781         return media_type;
 782 }
 783
 784 /**
 785  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 786  *  @hw: pointer to hardware structure
 787  */
 788 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 789 {
 790         bool setup_linear;
 791         u16 reg_slice, edc_mode;
 792         s32 ret_val;
 793
 794         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
 795
 796         switch (hw->phy.sfp_type) {
 797         case ixgbe_sfp_type_unknown:
 798                 return IXGBE_SUCCESS;
 799         case ixgbe_sfp_type_not_present:
 800                 return IXGBE_ERR_SFP_NOT_PRESENT;
 801         case ixgbe_sfp_type_da_cu_core0:
 802         case ixgbe_sfp_type_da_cu_core1:
 803                 setup_linear = true;
 804                 break;
 805         case ixgbe_sfp_type_srlr_core0:
 806         case ixgbe_sfp_type_srlr_core1:
 807         case ixgbe_sfp_type_da_act_lmt_core0:
 808         case ixgbe_sfp_type_da_act_lmt_core1:
 809         case ixgbe_sfp_type_1g_sx_core0:
 810         case ixgbe_sfp_type_1g_sx_core1:
 811         case ixgbe_sfp_type_1g_lx_core0:
 812         case ixgbe_sfp_type_1g_lx_core1:
 813                 setup_linear = false;
 814                 break;
 815         default:
 816                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 817         }
 818
 819         ixgbe_init_mac_link_ops_X550em(hw);
 820         hw->phy.ops.reset = NULL;
 821
 822         /* The CS4227 slice address is the base address + the port-pair reg
 823          * offset. I.e. Slice 0 = 0x0000 and slice 1 = 0x1000.
 824          */
 825         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->phy.lan_id << 12);
 826
 827         if (setup_linear)
 828                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 829         else
 830                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 831
 832         /* Configure CS4227 for connection type. */
 833         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
 834                                            edc_mode);
 835
 836         return ret_val;
 837 }
 838
 839 /**
 840  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
 841  *  @hw: pointer to hardware structure
 842  */
 843 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
 844 {
 845         struct ixgbe_mac_info *mac = &hw->mac;
 846
 847         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
 848
 849         /* CS4227 does not support autoneg, so disable the laser control
 850          * functions for SFP+ fiber
 851          */
 852          if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 853                 mac->ops.disable_tx_laser = NULL;
 854                 mac->ops.enable_tx_laser = NULL;
 855                 mac->ops.flap_tx_laser = NULL;
 856          }
 857 }
 858
 859 /**
 860  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
 861  *  @hw: pointer to hardware structure
 862  *  @speed: pointer to link speed
 863  *  @autoneg: true when autoneg or autotry is enabled
 864  */
 865 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
 866                                        ixgbe_link_speed *speed,
 867                                        bool *autoneg)
 868 {
 869         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
 870
 871         /* SFP */
 872         if (hw->phy.media_type == ixgbe_media_type_fiber) {
 873
 874                 /* CS4227 SFP must not enable auto-negotiation */
 875                 *autoneg = false;
 876
 877                 /* Check if 1G SFP module. */
 878                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
 879                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
 880                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
 881                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
 882                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
 883                         return IXGBE_SUCCESS;
 884                 }
 885
 886                 /* Link capabilities are based on SFP */
 887                 if (hw->phy.multispeed_fiber)
 888                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
 889                                  IXGBE_LINK_SPEED_1GB_FULL;
 890                 else
 891                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 892         } else {
 893                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
 894                          IXGBE_LINK_SPEED_1GB_FULL;
 895                 *autoneg = true;
 896         }
 897
 898         return IXGBE_SUCCESS;
 899 }
 900
 901 /**
 902  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
 903  *  @hw: pointer to hardware structure
 904  *
 905  *  Initialize any function pointers that were not able to be
 906  *  set during init_shared_code because the PHY/SFP type was
 907  *  not known.  Perform the SFP init if necessary.
 908  */
 909 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
 910 {
 911         struct ixgbe_phy_info *phy = &hw->phy;
 912         s32 ret_val;
 913         u32 esdp;
 914
 915         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
 916
 917         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 918                 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 919                 phy->lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
 920                               IXGBE_STATUS_LAN_ID_1;
 921                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 922                 if (phy->lan_id) {
 923                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 924                         esdp |= IXGBE_ESDP_SDP1_DIR;
 925                 }
 926                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 927                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 928         }
 929
 930         /* Identify the PHY or SFP module */
 931         ret_val = phy->ops.identify(hw);
 932         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
 933                 return ret_val;
 934
 935         /* Setup function pointers based on detected SFP module and speeds */
 936         ixgbe_init_mac_link_ops_X550em(hw);
 937         if (phy->sfp_type != ixgbe_sfp_type_unknown)
 938                 phy->ops.reset = NULL;
 939
 940         /* Set functions pointers based on phy type */
 941         switch (hw->phy.type) {
 942         case ixgbe_phy_x550em_kr:
 943                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
 944                 break;
 945         default:
 946                 break;
 947         }
 948         return ret_val;
 949 }
 950
 951 /**
 952  *  ixgbe_reset_hw_X550em - Perform hardware reset
 953  *  @hw: pointer to hardware structure
 954  *
 955  *  Resets the hardware by resetting the transmit and receive units, masks
 956  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
 957  *  reset.
 958  */
 959 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
 960 {
 961         ixgbe_link_speed link_speed;
 962         s32 status;
 963         u32 ctrl = 0;
 964         u32 i;
 965         bool link_up = false;
 966
 967         DEBUGFUNC("ixgbe_reset_hw_X550em");
 968
 969         /* Call adapter stop to disable Tx/Rx and clear interrupts */
 970         status = hw->mac.ops.stop_adapter(hw);
 971         if (status != IXGBE_SUCCESS)
 972                 return status;
 973
 974         /* flush pending Tx transactions */
 975         ixgbe_clear_tx_pending(hw);
 976
 977         /* PHY ops must be identified and initialized prior to reset */
 978
 979         /* Identify PHY and related function pointers */
 980         status = hw->phy.ops.init(hw);
 981
 982         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 983                 return status;
 984
 985         /* Setup SFP module if there is one present. */
 986         if (hw->phy.sfp_setup_needed) {
 987                 status = hw->mac.ops.setup_sfp(hw);
 988                 hw->phy.sfp_setup_needed = false;
 989         }
 990
 991         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 992                 return status;
 993
 994         /* Reset PHY */
 995         if (!hw->phy.reset_disable && hw->phy.ops.reset)
 996                 hw->phy.ops.reset(hw);
 997
 998 mac_reset_top:
 999         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1000          * If link reset is used when link is up, it might reset the PHY when
1001          * mng is using it.  If link is down or the flag to force full link
1002          * reset is set, then perform link reset.
1003          */
1004         ctrl = IXGBE_CTRL_LNK_RST;
1005         if (!hw->force_full_reset) {
1006                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1007                 if (link_up)
1008                         ctrl = IXGBE_CTRL_RST;
1009         }
1010
1011         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1012         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1013         IXGBE_WRITE_FLUSH(hw);
1014
1015         /* Poll for reset bit to self-clear meaning reset is complete */
1016         for (i = 0; i < 10; i++) {
1017                 usec_delay(1);
1018                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1019                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1020                         break;
1021         }
1022
1023         if (ctrl & IXGBE_CTRL_RST_MASK) {
1024                 status = IXGBE_ERR_RESET_FAILED;
1025                 DEBUGOUT("Reset polling failed to complete.\n");
1026         }
1027
1028         msec_delay(50);
1029
1030         /* Double resets are required for recovery from certain error
1031          * conditions.  Between resets, it is necessary to stall to
1032          * allow time for any pending HW events to complete.
1033          */
1034         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1035                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1036                 goto mac_reset_top;
1037         }
1038
1039         /* Store the permanent mac address */
1040         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1041
1042         /* Store MAC address from RAR0, clear receive address registers, and
1043          * clear the multicast table.  Also reset num_rar_entries to 128,
1044          * since we modify this value when programming the SAN MAC address.
1045          */
1046         hw->mac.num_rar_entries = 128;
1047         hw->mac.ops.init_rx_addrs(hw);
1048
1049         return status;
1050 }
1051
1052 /**
1053  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1054  *  @hw: pointer to hardware structure
1055  *
1056  *  Configures the integrated KR PHY.
1057  **/
1058 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1059 {
1060         s32 status;
1061         u32 reg_val;
1062
1063         status = ixgbe_read_iosf_sb_reg_x550(hw,
1064                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1065                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1066
1067         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1068         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ;
1069         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1070         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1071                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1072
1073         /* Advertise 10G support. */
1074         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1075                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1076
1077         /* Advertise 1G support. */
1078         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1079                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1080
1081         /* Restart auto-negotiation. */
1082         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1083         status = ixgbe_write_iosf_sb_reg_x550(hw,
1084                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1085                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1086
1087         return status;
1088 }
1089
1090 /**
1091  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI.
1092  *  @hw: pointer to hardware structure
1093  *
1094  *  Configures the integrated KR PHY to use iXFI mode.
1095  **/
1096 s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw)
1097 {
1098         s32 status;
1099         u32 reg_val;
1100
1101         /* Disable AN and force speed to 10G Serial. */
1102         status = ixgbe_read_iosf_sb_reg_x550(hw,
1103                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1104                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1105         if (status != IXGBE_SUCCESS)
1106                 return status;
1107         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1108         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1109         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1110         status = ixgbe_write_iosf_sb_reg_x550(hw,
1111                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1112                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1113         if (status != IXGBE_SUCCESS)
1114                 return status;
1115
1116         /* Disable training protocol FSM. */
1117         status = ixgbe_read_iosf_sb_reg_x550(hw,
1118                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1119                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1120         if (status != IXGBE_SUCCESS)
1121                 return status;
1122         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1123         status = ixgbe_write_iosf_sb_reg_x550(hw,
1124                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1125                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1126         if (status != IXGBE_SUCCESS)
1127                 return status;
1128
1129         /* Disable Flex from training TXFFE. */
1130         status = ixgbe_read_iosf_sb_reg_x550(hw,
1131                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),
1132                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1133         if (status != IXGBE_SUCCESS)
1134                 return status;
1135         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1136         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1137         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1138         status = ixgbe_write_iosf_sb_reg_x550(hw,
1139                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),
1140                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1141         if (status != IXGBE_SUCCESS)
1142                 return status;
1143         status = ixgbe_read_iosf_sb_reg_x550(hw,
1144                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),
1145                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1146         if (status != IXGBE_SUCCESS)
1147                 return status;
1148         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1149         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1150         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1151         status = ixgbe_write_iosf_sb_reg_x550(hw,
1152                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),
1153                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1154         if (status != IXGBE_SUCCESS)
1155                 return status;
1156
1157         /* Enable override for coefficients. */
1158         status = ixgbe_read_iosf_sb_reg_x550(hw,
1159                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),
1160                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1161         if (status != IXGBE_SUCCESS)
1162                 return status;
1163         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1164         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1165         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1166         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1167         status = ixgbe_write_iosf_sb_reg_x550(hw,
1168                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),
1169                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1170         if (status != IXGBE_SUCCESS)
1171                 return status;
1172
1173         /* Toggle port SW reset by AN reset. */
1174         status = ixgbe_read_iosf_sb_reg_x550(hw,
1175                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1176                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1177         if (status != IXGBE_SUCCESS)
1178                 return status;
1179         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1180         status = ixgbe_write_iosf_sb_reg_x550(hw,
1181                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1182                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1183
1184         return status;
1185 }
1186
1187 /**
1188  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1189  *  @hw: pointer to hardware structure
1190  *
1191  *  Configures the integrated KR PHY to use internal loopback mode.
1192  **/
1193 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1194 {
1195         s32 status;
1196         u32 reg_val;
1197
1198         /* Disable AN and force speed to 10G Serial. */
1199         status = ixgbe_read_iosf_sb_reg_x550(hw,
1200                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1201                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1202         if (status != IXGBE_SUCCESS)
1203                 return status;
1204         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1205         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1206         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1207         status = ixgbe_write_iosf_sb_reg_x550(hw,
1208                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1209                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1210         if (status != IXGBE_SUCCESS)
1211                 return status;
1212
1213         /* Set near-end loopback clocks. */
1214         status = ixgbe_read_iosf_sb_reg_x550(hw,
1215                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),
1216                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1217         if (status != IXGBE_SUCCESS)
1218                 return status;
1219         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1220         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1221         status = ixgbe_write_iosf_sb_reg_x550(hw,
1222                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),
1223                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1224         if (status != IXGBE_SUCCESS)
1225                 return status;
1226
1227         /* Set loopback enable. */
1228         status = ixgbe_read_iosf_sb_reg_x550(hw,
1229                 IXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),
1230                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1231         if (status != IXGBE_SUCCESS)
1232                 return status;
1233         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1234         status = ixgbe_write_iosf_sb_reg_x550(hw,
1235                 IXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),
1236                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1237         if (status != IXGBE_SUCCESS)
1238                 return status;
1239
1240         /* Training bypass. */
1241         status = ixgbe_read_iosf_sb_reg_x550(hw,
1242                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1243                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1244         if (status != IXGBE_SUCCESS)
1245                 return status;
1246         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1247         status = ixgbe_write_iosf_sb_reg_x550(hw,
1248                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1249                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1250
1251         return status;
1252 }
1253
1254 /**
1255  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1256  *  assuming that the semaphore is already obtained.
1257  *  @hw: pointer to hardware structure
1258  *  @offset: offset of  word in the EEPROM to read
1259  *  @data: word read from the EEPROM
1260  *
1261  *  Reads a 16 bit word from the EEPROM using the hostif.
1262  **/
1263 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1264                                    u16 *data)
1265 {
1266         s32 status;
1267         struct ixgbe_hic_read_shadow_ram buffer;
1268
1269         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1270         buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1271         buffer.hdr.buf_len1 = 0;
1272         buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1273         buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1274
1275         /* convert offset from words to bytes */
1276         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1277         /* one word */
1278         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1279
1280         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1281                                               sizeof(buffer), false);
1282
1283         if (status)
1284                 return status;
1285
1286         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1287                                           FW_NVM_DATA_OFFSET);
1288
1289         return 0;
1290 }
1291
1292 /**
1293  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1294  *  @hw: pointer to hardware structure
1295  *  @offset: offset of  word in the EEPROM to read
1296  *  @data: word read from the EEPROM
1297  *
1298  *  Reads a 16 bit word from the EEPROM using the hostif.
1299  **/
1300 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1301                               u16 *data)
1302 {
1303         s32 status = IXGBE_SUCCESS;
1304
1305         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1306
1307         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1308             IXGBE_SUCCESS) {
1309                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1310                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1311         } else {
1312                 status = IXGBE_ERR_SWFW_SYNC;
1313         }
1314
1315         return status;
1316 }
1317
1318 /**
1319  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1320  *  @hw: pointer to hardware structure
1321  *  @offset: offset of  word in the EEPROM to read
1322  *  @words: number of words
1323  *  @data: word(s) read from the EEPROM
1324  *
1325  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1326  **/
1327 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1328                                      u16 offset, u16 words, u16 *data)
1329 {
1330         struct ixgbe_hic_read_shadow_ram buffer;
1331         u32 current_word = 0;
1332         u16 words_to_read;
1333         s32 status;
1334         u32 i;
1335
1336         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1337
1338         /* Take semaphore for the entire operation. */
1339         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1340         if (status) {
1341                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1342                 return status;
1343         }
1344         while (words) {
1345                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1346                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1347                 else
1348                         words_to_read = words;
1349
1350                 buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1351                 buffer.hdr.buf_len1 = 0;
1352                 buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1353                 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1354
1355                 /* convert offset from words to bytes */
1356                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1357                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1358
1359                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1360                                                       sizeof(buffer), false);
1361
1362                 if (status) {
1363                         DEBUGOUT("Host interface command failed\n");
1364                         goto out;
1365                 }
1366
1367                 for (i = 0; i < words_to_read; i++) {
1368                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1369                                   2 * i;
1370                         u32 value = IXGBE_READ_REG(hw, reg);
1371
1372                         data[current_word] = (u16)(value & 0xffff);
1373                         current_word++;
1374                         i++;
1375                         if (i < words_to_read) {
1376                                 value >>= 16;
1377                                 data[current_word] = (u16)(value & 0xffff);
1378                                 current_word++;
1379                         }
1380                 }
1381                 words -= words_to_read;
1382         }
1383
1384 out:
1385         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1386         return status;
1387 }
1388
1389 /**
1390  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1391  *  @hw: pointer to hardware structure
1392  *  @offset: offset of  word in the EEPROM to write
1393  *  @data: word write to the EEPROM
1394  *
1395  *  Write a 16 bit word to the EEPROM using the hostif.
1396  **/
1397 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1398                                     u16 data)
1399 {
1400         s32 status;
1401         struct ixgbe_hic_write_shadow_ram buffer;
1402
1403         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1404
1405         buffer.hdr.cmd = FW_WRITE_SHADOW_RAM_CMD;
1406         buffer.hdr.buf_len1 = 0;
1407         buffer.hdr.buf_len2 = FW_WRITE_SHADOW_RAM_LEN;
1408         buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1409
1410          /* one word */
1411         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1412         buffer.data = data;
1413         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1414
1415         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1416                                               sizeof(buffer), false);
1417
1418         return status;
1419 }
1420
1421 /**
1422  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1423  *  @hw: pointer to hardware structure
1424  *  @offset: offset of  word in the EEPROM to write
1425  *  @data: word write to the EEPROM
1426  *
1427  *  Write a 16 bit word to the EEPROM using the hostif.
1428  **/
1429 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1430                                u16 data)
1431 {
1432         s32 status = IXGBE_SUCCESS;
1433
1434         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1435
1436         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1437             IXGBE_SUCCESS) {
1438                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1439                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1440         } else {
1441                 DEBUGOUT("write ee hostif failed to get semaphore");
1442                 status = IXGBE_ERR_SWFW_SYNC;
1443         }
1444
1445         return status;
1446 }
1447
1448 /**
1449  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1450  *  @hw: pointer to hardware structure
1451  *  @offset: offset of  word in the EEPROM to write
1452  *  @words: number of words
1453  *  @data: word(s) write to the EEPROM
1454  *
1455  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1456  **/
1457 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1458                                       u16 offset, u16 words, u16 *data)
1459 {
1460         s32 status = IXGBE_SUCCESS;
1461         u32 i = 0;
1462
1463         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1464
1465         /* Take semaphore for the entire operation. */
1466         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1467         if (status != IXGBE_SUCCESS) {
1468                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1469                 goto out;
1470         }
1471
1472         for (i = 0; i < words; i++) {
1473                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1474                                                          data[i]);
1475
1476                 if (status != IXGBE_SUCCESS) {
1477                         DEBUGOUT("Eeprom buffered write failed\n");
1478                         break;
1479                 }
1480         }
1481
1482         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1483 out:
1484
1485         return status;
1486 }
1487
1488 /**
1489  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1490  * @hw: pointer to hardware structure
1491  * @ptr: pointer offset in eeprom
1492  * @size: size of section pointed by ptr, if 0 first word will be used as size
1493  * @csum: address of checksum to update
1494  *
1495  * Returns error status for any failure
1496  */
1497 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1498                                    u16 size, u16 *csum)
1499 {
1500         u16 buf[256];
1501         s32 status;
1502         u16 length, bufsz, i, start;
1503
1504         bufsz = sizeof(buf) / sizeof(buf[0]);
1505
1506         /* Read a chunk at the pointer location */
1507         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1508         if (status) {
1509                 DEBUGOUT("Failed to read EEPROM image\n");
1510                 return status;
1511         }
1512
1513         if (size) {
1514                 start = 0;
1515                 length = size;
1516         } else {
1517                 start = 1;
1518                 length = buf[0];
1519
1520                 /* Skip pointer section if length is invalid. */
1521                 if (length == 0xFFFF || length == 0 ||
1522                     (ptr + length) >= hw->eeprom.word_size)
1523                         return IXGBE_SUCCESS;
1524         }
1525
1526         for (i = start; length; i++, length--) {
1527                 if (i == bufsz) {
1528                         ptr += bufsz;
1529                         i = 0;
1530                         if (length < bufsz)
1531                                 bufsz = length;
1532
1533                         /* Read a chunk at the pointer location */
1534                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1535                                                                   bufsz, buf);
1536                         if (status) {
1537                                 DEBUGOUT("Failed to read EEPROM image\n");
1538                                 return status;
1539                         }
1540                 }
1541                 *csum += buf[i];
1542         }
1543         return IXGBE_SUCCESS;
1544 }
1545
1546 /**
1547  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1548  *  @hw: pointer to hardware structure
1549  *
1550  *  Returns a negative error code on error, or the 16-bit checksum
1551  **/
1552 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1553 {
1554         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1555         s32 status;
1556         u16 checksum = 0;
1557         u16 pointer, i, size;
1558
1559         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
1560
1561         hw->eeprom.ops.init_params(hw);
1562
1563         /* Read pointer area */
1564         status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1565                                                   IXGBE_EEPROM_LAST_WORD + 1,
1566                                                   eeprom_ptrs);
1567         if (status) {
1568                 DEBUGOUT("Failed to read EEPROM image\n");
1569                 return status;
1570         }
1571
1572         /*
1573          * For X550 hardware include 0x0-0x41 in the checksum, skip the
1574          * checksum word itself
1575          */
1576         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1577                 if (i != IXGBE_EEPROM_CHECKSUM)
1578                         checksum += eeprom_ptrs[i];
1579
1580         /*
1581          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
1582          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1583          */
1584         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1585                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1586                         continue;
1587
1588                 pointer = eeprom_ptrs[i];
1589
1590                 /* Skip pointer section if the pointer is invalid. */
1591                 if (pointer == 0xFFFF || pointer == 0 ||
1592                     pointer >= hw->eeprom.word_size)
1593                         continue;
1594
1595                 switch (i) {
1596                 case IXGBE_PCIE_GENERAL_PTR:
1597                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1598                         break;
1599                 case IXGBE_PCIE_CONFIG0_PTR:
1600                 case IXGBE_PCIE_CONFIG1_PTR:
1601                         size = IXGBE_PCIE_CONFIG_SIZE;
1602                         break;
1603                 default:
1604                         size = 0;
1605                         break;
1606                 }
1607
1608                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum);
1609                 if (status)
1610                         return status;
1611         }
1612
1613         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1614
1615         return (s32)checksum;
1616 }
1617
1618 /**
1619  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1620  *  @hw: pointer to hardware structure
1621  *  @checksum_val: calculated checksum
1622  *
1623  *  Performs checksum calculation and validates the EEPROM checksum.  If the
1624  *  caller does not need checksum_val, the value can be NULL.
1625  **/
1626 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
1627 {
1628         s32 status;
1629         u16 checksum;
1630         u16 read_checksum = 0;
1631
1632         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
1633
1634         /* Read the first word from the EEPROM. If this times out or fails, do
1635          * not continue or we could be in for a very long wait while every
1636          * EEPROM read fails
1637          */
1638         status = hw->eeprom.ops.read(hw, 0, &checksum);
1639         if (status) {
1640                 DEBUGOUT("EEPROM read failed\n");
1641                 return status;
1642         }
1643
1644         status = hw->eeprom.ops.calc_checksum(hw);
1645         if (status < 0)
1646                 return status;
1647
1648         checksum = (u16)(status & 0xffff);
1649
1650         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1651                                            &read_checksum);
1652         if (status)
1653                 return status;
1654
1655         /* Verify read checksum from EEPROM is the same as
1656          * calculated checksum
1657          */
1658         if (read_checksum != checksum) {
1659                 status = IXGBE_ERR_EEPROM_CHECKSUM;
1660                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1661                              "Invalid EEPROM checksum");
1662         }
1663
1664         /* If the user cares, return the calculated checksum */
1665         if (checksum_val)
1666                 *checksum_val = checksum;
1667
1668         return status;
1669 }
1670
1671 /**
1672  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1673  * @hw: pointer to hardware structure
1674  *
1675  * After writing EEPROM to shadow RAM using EEWR register, software calculates
1676  * checksum and updates the EEPROM and instructs the hardware to update
1677  * the flash.
1678  **/
1679 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1680 {
1681         s32 status;
1682         u16 checksum = 0;
1683
1684         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
1685
1686         /* Read the first word from the EEPROM. If this times out or fails, do
1687          * not continue or we could be in for a very long wait while every
1688          * EEPROM read fails
1689          */
1690         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1691         if (status) {
1692                 DEBUGOUT("EEPROM read failed\n");
1693                 return status;
1694         }
1695
1696         status = ixgbe_calc_eeprom_checksum_X550(hw);
1697         if (status < 0)
1698                 return status;
1699
1700         checksum = (u16)(status & 0xffff);
1701
1702         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1703                                             checksum);
1704         if (status)
1705                 return status;
1706
1707         status = ixgbe_update_flash_X550(hw);
1708
1709         return status;
1710 }
1711
1712 /**
1713  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1714  *  @hw: pointer to hardware structure
1715  *
1716  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1717  **/
1718 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1719 {
1720         s32 status = IXGBE_SUCCESS;
1721         struct ixgbe_hic_hdr2 buffer;
1722
1723         DEBUGFUNC("ixgbe_update_flash_X550");
1724
1725         buffer.cmd = FW_SHADOW_RAM_DUMP_CMD;
1726         buffer.buf_len1 = 0;
1727         buffer.buf_len2 = FW_SHADOW_RAM_DUMP_LEN;
1728         buffer.checksum = FW_DEFAULT_CHECKSUM;
1729
1730         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1731                                               sizeof(buffer), false);
1732
1733         return status;
1734 }
1735
1736 /**
1737  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
1738  *  @hw: pointer to hardware structure
1739  *
1740  *  Determines physical layer capabilities of the current configuration.
1741  **/
1742 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
1743 {
1744         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1745
1746         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
1747
1748         hw->phy.ops.identify(hw);
1749
1750         switch (hw->phy.type) {
1751         case ixgbe_phy_x550em_kr:
1752                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
1753                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1754                 break;
1755         case ixgbe_phy_x550em_kx4:
1756                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1757                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1758                 break;
1759         default:
1760                 break;
1761         }
1762
1763         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
1764                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
1765
1766         return physical_layer;
1767 }
1768
1769 /**
1770  * ixgbe_disable_rx_x550 - Disable RX unit
1771  *
1772  * Enables the Rx DMA unit for x550
1773  **/
1774 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1775 {
1776         u32 rxctrl, pfdtxgswc;
1777         s32 status;
1778         struct ixgbe_hic_disable_rxen fw_cmd;
1779
1780         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
1781
1782         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1783         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1784                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1785                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1786                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1787                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1788                         hw->mac.set_lben = true;
1789                 } else {
1790                         hw->mac.set_lben = false;
1791                 }
1792
1793                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1794                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1795                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1796                 fw_cmd.port_number = hw->phy.lan_id;
1797
1798                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1799                                         sizeof(struct ixgbe_hic_disable_rxen),
1800                                         true);
1801
1802                 /* If we fail - disable RX using register write */
1803                 if (status) {
1804                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1805                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1806                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1807                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1808                         }
1809                 }
1810         }
1811 }