lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 /**
  42  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  43  *  @hw: pointer to hardware structure
  44  *
  45  *  Initialize the function pointers and assign the MAC type for X550.
  46  *  Does not touch the hardware.
  47  **/
  48 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  49 {
  50         struct ixgbe_mac_info *mac = &hw->mac;
  51         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  52         s32 ret_val;
  53
  54         DEBUGFUNC("ixgbe_init_ops_X550");
  55
  56         ret_val = ixgbe_init_ops_X540(hw);
  57         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  58         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  59         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  60         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  61         mac->ops.set_source_address_pruning =
  62                         ixgbe_set_source_address_pruning_X550;
  63         mac->ops.set_ethertype_anti_spoofing =
  64                         ixgbe_set_ethertype_anti_spoofing_X550;
  65
  66         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  67         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  68         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  69         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  70         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  71         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  72         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  73         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  74         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  75
  76         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  77         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  78         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  79         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  80         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  81         return ret_val;
  82 }
  83
  84 /**
  85  * ixgbe_identify_phy_x550em - Get PHY type based on device id
  86  * @hw: pointer to hardware structure
  87  *
  88  * Returns error code
  89  */
  90 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
  91 {
  92         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  93
  94         switch (hw->device_id) {
  95         case IXGBE_DEV_ID_X550EM_X_SFP:
  96                 /* set up for CS4227 usage */
  97                 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
  98                                  IXGBE_STATUS_LAN_ID_1;
  99                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 100                 if (hw->phy.lan_id) {
 101
 102                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 103                         esdp |= IXGBE_ESDP_SDP1_DIR;
 104                 }
 105                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 106                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 107
 108                 return ixgbe_identify_module_generic(hw);
 109                 break;
 110         case IXGBE_DEV_ID_X550EM_X_KX4:
 111                 hw->phy.type = ixgbe_phy_x550em_kx4;
 112                 break;
 113         case IXGBE_DEV_ID_X550EM_X_KR:
 114         case IXGBE_DEV_ID_X550EM_X:
 115                 hw->phy.type = ixgbe_phy_x550em_kr;
 116                 break;
 117         default:
 118                 break;
 119         }
 120         return IXGBE_SUCCESS;
 121 }
 122
 123 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 124                                      u32 device_type, u16 *phy_data)
 125 {
 126         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 127         return IXGBE_NOT_IMPLEMENTED;
 128 }
 129
 130 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 131                                       u32 device_type, u16 phy_data)
 132 {
 133         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 134         return IXGBE_NOT_IMPLEMENTED;
 135 }
 136
 137 /**
 138 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 139 *  @hw: pointer to hardware structure
 140 *
 141 *  Initialize the function pointers and for MAC type X550EM.
 142 *  Does not touch the hardware.
 143 **/
 144 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 145 {
 146         struct ixgbe_mac_info *mac = &hw->mac;
 147         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 148         struct ixgbe_phy_info *phy = &hw->phy;
 149         s32 ret_val;
 150
 151         DEBUGFUNC("ixgbe_init_ops_X550EM");
 152
 153         /* Similar to X550 so start there. */
 154         ret_val = ixgbe_init_ops_X550(hw);
 155
 156         /* Since this function eventually calls
 157          * ixgbe_init_ops_540 by design, we are setting
 158          * the pointers to NULL explicitly here to overwrite
 159          * the values being set in the x540 function.
 160          */
 161         /* Thermal sensor not supported in x550EM */
 162         mac->ops.get_thermal_sensor_data = NULL;
 163         mac->ops.init_thermal_sensor_thresh = NULL;
 164         mac->thermal_sensor_enabled = false;
 165
 166         /* FCOE not supported in x550EM */
 167         mac->ops.get_san_mac_addr = NULL;
 168         mac->ops.set_san_mac_addr = NULL;
 169         mac->ops.get_wwn_prefix = NULL;
 170         mac->ops.get_fcoe_boot_status = NULL;
 171
 172         /* IPsec not supported in x550EM */
 173         mac->ops.disable_sec_rx_path = NULL;
 174         mac->ops.enable_sec_rx_path = NULL;
 175
 176         /* PCIe bus info not supported in X550EM */
 177         mac->ops.get_bus_info = NULL;
 178
 179         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 180         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 181         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 182         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 183         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 184         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 185         mac->ops.get_supported_physical_layer =
 186                                     ixgbe_get_supported_physical_layer_X550em;
 187
 188         /* PHY */
 189         phy->ops.init = &ixgbe_init_phy_ops_X550em;
 190         phy->ops.identify = &ixgbe_identify_phy_x550em;
 191         phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
 192         phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
 193         phy->ops.setup_link = ixgbe_setup_kr_x550em;
 194
 195
 196         /* EEPROM */
 197         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 198         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 199         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 200         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 201         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 202         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 203         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 204         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 205
 206         return ret_val;
 207 }
 208
 209 /**
 210  *  ixgbe_dmac_config_X550
 211  *  @hw: pointer to hardware structure
 212  *
 213  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 214  *  When disabling dmac, dmac enable dmac bit is cleared.
 215  **/
 216 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 217 {
 218         u32 reg, high_pri_tc;
 219
 220         DEBUGFUNC("ixgbe_dmac_config_X550");
 221
 222         /* Disable DMA coalescing before configuring */
 223         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 224         reg &= ~IXGBE_DMACR_DMAC_EN;
 225         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 226
 227         /* Disable DMA Coalescing if the watchdog timer is 0 */
 228         if (!hw->mac.dmac_config.watchdog_timer)
 229                 goto out;
 230
 231         ixgbe_dmac_config_tcs_X550(hw);
 232
 233         /* Configure DMA Coalescing Control Register */
 234         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 235
 236         /* Set the watchdog timer in units of 40.96 usec */
 237         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 238         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 239
 240         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 241         /* If fcoe is enabled, set high priority traffic class */
 242         if (hw->mac.dmac_config.fcoe_en) {
 243                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 244                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 245                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 246         }
 247         reg |= IXGBE_DMACR_EN_MNG_IND;
 248
 249         /* Enable DMA coalescing after configuration */
 250         reg |= IXGBE_DMACR_DMAC_EN;
 251         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 252
 253 out:
 254         return IXGBE_SUCCESS;
 255 }
 256
 257 /**
 258  *  ixgbe_dmac_config_tcs_X550
 259  *  @hw: pointer to hardware structure
 260  *
 261  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 262  *  be cleared before configuring.
 263  **/
 264 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 265 {
 266         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 267
 268         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 269
 270         /* Configure DMA coalescing enabled */
 271         switch (hw->mac.dmac_config.link_speed) {
 272         case IXGBE_LINK_SPEED_100_FULL:
 273                 pb_headroom = IXGBE_DMACRXT_100M;
 274                 break;
 275         case IXGBE_LINK_SPEED_1GB_FULL:
 276                 pb_headroom = IXGBE_DMACRXT_1G;
 277                 break;
 278         default:
 279                 pb_headroom = IXGBE_DMACRXT_10G;
 280                 break;
 281         }
 282
 283         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 284                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 285
 286         /* Set the per Rx packet buffer receive threshold */
 287         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 288                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 289                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 290
 291                 if (tc < hw->mac.dmac_config.num_tcs) {
 292                         /* Get Rx PB size */
 293                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 294                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 295                                 IXGBE_RXPBSIZE_SHIFT;
 296
 297                         /* Calculate receive buffer threshold in kilobytes */
 298                         if (rx_pb_size > pb_headroom)
 299                                 rx_pb_size = rx_pb_size - pb_headroom;
 300                         else
 301                                 rx_pb_size = 0;
 302
 303                         /* Minimum of MFS shall be set for DMCTH */
 304                         reg |= (rx_pb_size > maxframe_size_kb) ?
 305                                 rx_pb_size : maxframe_size_kb;
 306                 }
 307                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 308         }
 309         return IXGBE_SUCCESS;
 310 }
 311
 312 /**
 313  *  ixgbe_dmac_update_tcs_X550
 314  *  @hw: pointer to hardware structure
 315  *
 316  *  Disables dmac, updates per TC settings, and then enables dmac.
 317  **/
 318 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 319 {
 320         u32 reg;
 321
 322         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 323
 324         /* Disable DMA coalescing before configuring */
 325         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 326         reg &= ~IXGBE_DMACR_DMAC_EN;
 327         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 328
 329         ixgbe_dmac_config_tcs_X550(hw);
 330
 331         /* Enable DMA coalescing after configuration */
 332         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 333         reg |= IXGBE_DMACR_DMAC_EN;
 334         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 335
 336         return IXGBE_SUCCESS;
 337 }
 338
 339 /**
 340  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 341  *  @hw: pointer to hardware structure
 342  *
 343  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 344  *  ixgbe_hw struct in order to set up EEPROM access.
 345  **/
 346 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 347 {
 348         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 349         u32 eec;
 350         u16 eeprom_size;
 351
 352         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 353
 354         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 355                 eeprom->semaphore_delay = 10;
 356                 eeprom->type = ixgbe_flash;
 357
 358                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 359                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 360                                     IXGBE_EEC_SIZE_SHIFT);
 361                 eeprom->word_size = 1 << (eeprom_size +
 362                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 363
 364                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 365                           eeprom->type, eeprom->word_size);
 366         }
 367
 368         return IXGBE_SUCCESS;
 369 }
 370
 371 /**
 372  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 373  *  @hw: pointer to the HW structure
 374  *  @enable_eee: boolean flag to enable EEE
 375  *
 376  *  Enable/disable EEE based on enable_eee flag.
 377  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 378  *  are modified.
 379  *
 380  **/
 381 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 382 {
 383         u32 eeer;
 384         u16 autoneg_eee_reg;
 385         u32 link_reg;
 386         s32 status;
 387
 388         DEBUGFUNC("ixgbe_setup_eee_X550");
 389
 390         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 391         /* Enable or disable EEE per flag */
 392         if (enable_eee) {
 393                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 394
 395                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 396                         /* Advertise EEE capability */
 397                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 398                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 399
 400                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 401                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 402                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 403
 404                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 405                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 406                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
 407                            hw->device_id == IXGBE_DEV_ID_X550EM_X) {
 408                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 409                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 410                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 411                         if (status != IXGBE_SUCCESS)
 412                                 return status;
 413
 414                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 415                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 416
 417                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 418                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 419                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 420                         if (status != IXGBE_SUCCESS)
 421                                 return status;
 422                 }
 423         } else {
 424                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 425
 426                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 427                         /* Disable advertised EEE capability */
 428                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 429                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 430
 431                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 432                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 433                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 434
 435                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 436                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 437                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
 438                            hw->device_id == IXGBE_DEV_ID_X550EM_X) {
 439                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 440                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 441                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 442                         if (status != IXGBE_SUCCESS)
 443                                 return status;
 444
 445                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 446                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 447
 448                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 449                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 450                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 451                         if (status != IXGBE_SUCCESS)
 452                                 return status;
 453                 }
 454         }
 455         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 456
 457         return IXGBE_SUCCESS;
 458 }
 459
 460 /**
 461  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 462  * @hw: pointer to hardware structure
 463  * @enable: enable or disable source address pruning
 464  * @pool: Rx pool to set source address pruning for
 465  **/
 466 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 467                                            unsigned int pool)
 468 {
 469         u64 pfflp;
 470
 471         /* max rx pool is 63 */
 472         if (pool > 63)
 473                 return;
 474
 475         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 476         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 477
 478         if (enable)
 479                 pfflp |= (1ULL << pool);
 480         else
 481                 pfflp &= ~(1ULL << pool);
 482
 483         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 484         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 485 }
 486
 487 /**
 488  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 489  *  @hw: pointer to hardware structure
 490  *  @enable: enable or disable switch for Ethertype anti-spoofing
 491  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 492  *
 493  **/
 494 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 495                 bool enable, int vf)
 496 {
 497         int vf_target_reg = vf >> 3;
 498         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 499         u32 pfvfspoof;
 500
 501         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 502
 503         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 504         if (enable)
 505                 pfvfspoof |= (1 << vf_target_shift);
 506         else
 507                 pfvfspoof &= ~(1 << vf_target_shift);
 508
 509         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 510 }
 511
 512 /**
 513  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 514  *  device
 515  *  @hw: pointer to hardware structure
 516  *  @reg_addr: 32 bit PHY register to write
 517  *  @device_type: 3 bit device type
 518  *  @data: Data to write to the register
 519  **/
 520 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 521                             u32 device_type, u32 data)
 522 {
 523         u32 i, command, error;
 524
 525         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 526                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 527
 528         /* Write IOSF control register */
 529         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 530
 531         /* Write IOSF data register */
 532         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 533         /*
 534          * Check every 10 usec to see if the address cycle completed.
 535          * The SB IOSF BUSY bit will clear when the operation is
 536          * complete
 537          */
 538         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 539                 usec_delay(10);
 540
 541                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 542                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 543                         break;
 544         }
 545
 546         if ((command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) != 0) {
 547                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 548                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 549                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 550                               "Failed to write, error %x\n", error);
 551                 return IXGBE_ERR_PHY;
 552         }
 553
 554         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 555                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 556                 return IXGBE_ERR_PHY;
 557         }
 558
 559         return IXGBE_SUCCESS;
 560 }
 561
 562 /**
 563  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 564  *  device
 565  *  @hw: pointer to hardware structure
 566  *  @reg_addr: 32 bit PHY register to write
 567  *  @device_type: 3 bit device type
 568  *  @phy_data: Pointer to read data from the register
 569  **/
 570 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 571                            u32 device_type, u32 *data)
 572 {
 573         u32 i, command, error;
 574
 575         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 576                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 577
 578         /* Write IOSF control register */
 579         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 580
 581         /*
 582          * Check every 10 usec to see if the address cycle completed.
 583          * The SB IOSF BUSY bit will clear when the operation is
 584          * complete
 585          */
 586         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 587                 usec_delay(10);
 588
 589                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 590                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 591                         break;
 592         }
 593
 594         if ((command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) != 0) {
 595                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 596                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 597                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 598                                 "Failed to read, error %x\n", error);
 599                 return IXGBE_ERR_PHY;
 600         }
 601
 602         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 603                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 604                 return IXGBE_ERR_PHY;
 605         }
 606
 607         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 608
 609         return IXGBE_SUCCESS;
 610 }
 611
 612 /**
 613  *  ixgbe_disable_mdd_X550
 614  *  @hw: pointer to hardware structure
 615  *
 616  *  Disable malicious driver detection
 617  **/
 618 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 619 {
 620         u32 reg;
 621
 622         DEBUGFUNC("ixgbe_disable_mdd_X550");
 623
 624         /* Disable MDD for TX DMA and interrupt */
 625         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 626         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 627         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 628
 629         /* Disable MDD for RX and interrupt */
 630         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 631         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 632         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 633 }
 634
 635 /**
 636  *  ixgbe_enable_mdd_X550
 637  *  @hw: pointer to hardware structure
 638  *
 639  *  Enable malicious driver detection
 640  **/
 641 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 642 {
 643         u32 reg;
 644
 645         DEBUGFUNC("ixgbe_enable_mdd_X550");
 646
 647         /* Enable MDD for TX DMA and interrupt */
 648         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 649         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 650         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 651
 652         /* Enable MDD for RX and interrupt */
 653         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 654         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 655         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 656 }
 657
 658 /**
 659  *  ixgbe_restore_mdd_vf_X550
 660  *  @hw: pointer to hardware structure
 661  *  @vf: vf index
 662  *
 663  *  Restore VF that was disabled during malicious driver detection event
 664  **/
 665 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 666 {
 667         u32 idx, reg, num_qs, start_q, bitmask;
 668
 669         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 670
 671         /* Map VF to queues */
 672         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 673         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 674         case IXGBE_MRQC_VMDQRT8TCEN:
 675                 num_qs = 8;  /* 16 VFs / pools */
 676                 bitmask = 0x000000FF;
 677                 break;
 678         case IXGBE_MRQC_VMDQRSS32EN:
 679         case IXGBE_MRQC_VMDQRT4TCEN:
 680                 num_qs = 4;  /* 32 VFs / pools */
 681                 bitmask = 0x0000000F;
 682                 break;
 683         default:            /* 64 VFs / pools */
 684                 num_qs = 2;
 685                 bitmask = 0x00000003;
 686                 break;
 687         }
 688         start_q = vf * num_qs;
 689
 690         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 691         idx = start_q / 32;
 692         reg = 0;
 693         reg |= (bitmask << (start_q % 32));
 694         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 695         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 696 }
 697
 698 /**
 699  *  ixgbe_mdd_event_X550
 700  *  @hw: pointer to hardware structure
 701  *  @vf_bitmap: vf bitmap of malicious vfs
 702  *
 703  *  Handle malicious driver detection event.
 704  **/
 705 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 706 {
 707         u32 wqbr;
 708         u32 i, j, reg, q, shift, vf, idx;
 709
 710         DEBUGFUNC("ixgbe_mdd_event_X550");
 711
 712         /* figure out pool size for mapping to vf's */
 713         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 714         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 715         case IXGBE_MRQC_VMDQRT8TCEN:
 716                 shift = 3;  /* 16 VFs / pools */
 717                 break;
 718         case IXGBE_MRQC_VMDQRSS32EN:
 719         case IXGBE_MRQC_VMDQRT4TCEN:
 720                 shift = 2;  /* 32 VFs / pools */
 721                 break;
 722         default:
 723                 shift = 1;  /* 64 VFs / pools */
 724                 break;
 725         }
 726
 727         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 728         for (i = 0; i < 4; i++) {
 729                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 730                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 731
 732                 if (!wqbr)
 733                         continue;
 734
 735                 /* Get malicious queue */
 736                 for (j = 0; j < 32 && wqbr; j++) {
 737
 738                         if (!(wqbr & (1 << j)))
 739                                 continue;
 740
 741                         /* Get queue from bitmask */
 742                         q = j + (i * 32);
 743
 744                         /* Map queue to vf */
 745                         vf = (q >> shift);
 746
 747                         /* Set vf bit in vf_bitmap */
 748                         idx = vf / 32;
 749                         vf_bitmap[idx] |= (1 << (vf % 32));
 750                         wqbr &= ~(1 << j);
 751                 }
 752         }
 753 }
 754
 755 /**
 756  *  ixgbe_get_media_type_X550em - Get media type
 757  *  @hw: pointer to hardware structure
 758  *
 759  *  Returns the media type (fiber, copper, backplane)
 760  */
 761 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 762 {
 763         enum ixgbe_media_type media_type;
 764
 765         DEBUGFUNC("ixgbe_get_media_type_X550em");
 766
 767         /* Detect if there is a copper PHY attached. */
 768         switch (hw->device_id) {
 769         case IXGBE_DEV_ID_X550EM_X:
 770         case IXGBE_DEV_ID_X550EM_X_KR:
 771         case IXGBE_DEV_ID_X550EM_X_KX4:
 772                 media_type = ixgbe_media_type_backplane;
 773                 break;
 774         case IXGBE_DEV_ID_X550EM_X_SFP:
 775                 media_type = ixgbe_media_type_fiber;
 776                 break;
 777         default:
 778                 media_type = ixgbe_media_type_unknown;
 779                 break;
 780         }
 781         return media_type;
 782 }
 783
 784 /**
 785  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 786  *  @hw: pointer to hardware structure
 787  */
 788 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 789 {
 790         bool setup_linear;
 791         u16 reg_slice, edc_mode;
 792         s32 ret_val;
 793
 794         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
 795
 796         switch (hw->phy.sfp_type) {
 797         case ixgbe_sfp_type_unknown:
 798                 return IXGBE_SUCCESS;
 799         case ixgbe_sfp_type_not_present:
 800                 return IXGBE_ERR_SFP_NOT_PRESENT;
 801         case ixgbe_sfp_type_da_cu_core0:
 802         case ixgbe_sfp_type_da_cu_core1:
 803                 setup_linear = true;
 804                 break;
 805         case ixgbe_sfp_type_srlr_core0:
 806         case ixgbe_sfp_type_srlr_core1:
 807         case ixgbe_sfp_type_da_act_lmt_core0:
 808         case ixgbe_sfp_type_da_act_lmt_core1:
 809         case ixgbe_sfp_type_1g_sx_core0:
 810         case ixgbe_sfp_type_1g_sx_core1:
 811         case ixgbe_sfp_type_1g_lx_core0:
 812         case ixgbe_sfp_type_1g_lx_core1:
 813                 setup_linear = false;
 814                 break;
 815         default:
 816                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 817         }
 818
 819         ixgbe_init_mac_link_ops_X550em(hw);
 820         hw->phy.ops.reset = NULL;
 821
 822         /* The CS4227 slice address is the base address + the port-pair reg
 823          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
 824          */
 825         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->phy.lan_id << 12);
 826
 827         if (setup_linear)
 828                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 829         else
 830                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 831
 832         /* Configure CS4227 for connection type. */
 833         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
 834                                            edc_mode);
 835
 836         if (ret_val != IXGBE_SUCCESS)
 837                 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
 838                                                    edc_mode);
 839
 840         return ret_val;
 841 }
 842
 843 /**
 844  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
 845  *  @hw: pointer to hardware structure
 846  */
 847 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
 848 {
 849         struct ixgbe_mac_info *mac = &hw->mac;
 850
 851         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
 852
 853         /* CS4227 does not support autoneg, so disable the laser control
 854          * functions for SFP+ fiber
 855          */
 856          if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 857                 mac->ops.disable_tx_laser = NULL;
 858                 mac->ops.enable_tx_laser = NULL;
 859                 mac->ops.flap_tx_laser = NULL;
 860          }
 861 }
 862
 863 /**
 864  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
 865  *  @hw: pointer to hardware structure
 866  *  @speed: pointer to link speed
 867  *  @autoneg: true when autoneg or autotry is enabled
 868  */
 869 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
 870                                        ixgbe_link_speed *speed,
 871                                        bool *autoneg)
 872 {
 873         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
 874
 875         /* SFP */
 876         if (hw->phy.media_type == ixgbe_media_type_fiber) {
 877
 878                 /* CS4227 SFP must not enable auto-negotiation */
 879                 *autoneg = false;
 880
 881                 /* Check if 1G SFP module. */
 882                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
 883                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
 884                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
 885                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
 886                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
 887                         return IXGBE_SUCCESS;
 888                 }
 889
 890                 /* Link capabilities are based on SFP */
 891                 if (hw->phy.multispeed_fiber)
 892                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
 893                                  IXGBE_LINK_SPEED_1GB_FULL;
 894                 else
 895                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 896         } else {
 897                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
 898                          IXGBE_LINK_SPEED_1GB_FULL;
 899                 *autoneg = true;
 900         }
 901
 902         return IXGBE_SUCCESS;
 903 }
 904
 905 /**
 906  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
 907  *  @hw: pointer to hardware structure
 908  *
 909  *  Initialize any function pointers that were not able to be
 910  *  set during init_shared_code because the PHY/SFP type was
 911  *  not known.  Perform the SFP init if necessary.
 912  */
 913 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
 914 {
 915         struct ixgbe_phy_info *phy = &hw->phy;
 916         s32 ret_val;
 917         u32 esdp;
 918
 919         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
 920
 921         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 922                 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 923                 phy->lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
 924                               IXGBE_STATUS_LAN_ID_1;
 925                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 926                 if (phy->lan_id) {
 927                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 928                         esdp |= IXGBE_ESDP_SDP1_DIR;
 929                 }
 930                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 931                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 932         }
 933
 934         /* Identify the PHY or SFP module */
 935         ret_val = phy->ops.identify(hw);
 936         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
 937                 return ret_val;
 938
 939         /* Setup function pointers based on detected SFP module and speeds */
 940         ixgbe_init_mac_link_ops_X550em(hw);
 941         if (phy->sfp_type != ixgbe_sfp_type_unknown)
 942                 phy->ops.reset = NULL;
 943
 944         /* Set functions pointers based on phy type */
 945         switch (hw->phy.type) {
 946         case ixgbe_phy_x550em_kr:
 947                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
 948                 break;
 949         default:
 950                 break;
 951         }
 952         return ret_val;
 953 }
 954
 955 /**
 956  *  ixgbe_reset_hw_X550em - Perform hardware reset
 957  *  @hw: pointer to hardware structure
 958  *
 959  *  Resets the hardware by resetting the transmit and receive units, masks
 960  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
 961  *  reset.
 962  */
 963 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
 964 {
 965         ixgbe_link_speed link_speed;
 966         s32 status;
 967         u32 ctrl = 0;
 968         u32 i;
 969         bool link_up = false;
 970
 971         DEBUGFUNC("ixgbe_reset_hw_X550em");
 972
 973         /* Call adapter stop to disable Tx/Rx and clear interrupts */
 974         status = hw->mac.ops.stop_adapter(hw);
 975         if (status != IXGBE_SUCCESS)
 976                 return status;
 977
 978         /* flush pending Tx transactions */
 979         ixgbe_clear_tx_pending(hw);
 980
 981         /* PHY ops must be identified and initialized prior to reset */
 982
 983         /* Identify PHY and related function pointers */
 984         status = hw->phy.ops.init(hw);
 985
 986         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 987                 return status;
 988
 989         /* Setup SFP module if there is one present. */
 990         if (hw->phy.sfp_setup_needed) {
 991                 status = hw->mac.ops.setup_sfp(hw);
 992                 hw->phy.sfp_setup_needed = false;
 993         }
 994
 995         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 996                 return status;
 997
 998         /* Reset PHY */
 999         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1000                 hw->phy.ops.reset(hw);
1001
1002 mac_reset_top:
1003         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1004          * If link reset is used when link is up, it might reset the PHY when
1005          * mng is using it.  If link is down or the flag to force full link
1006          * reset is set, then perform link reset.
1007          */
1008         ctrl = IXGBE_CTRL_LNK_RST;
1009         if (!hw->force_full_reset) {
1010                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1011                 if (link_up)
1012                         ctrl = IXGBE_CTRL_RST;
1013         }
1014
1015         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1016         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1017         IXGBE_WRITE_FLUSH(hw);
1018
1019         /* Poll for reset bit to self-clear meaning reset is complete */
1020         for (i = 0; i < 10; i++) {
1021                 usec_delay(1);
1022                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1023                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1024                         break;
1025         }
1026
1027         if (ctrl & IXGBE_CTRL_RST_MASK) {
1028                 status = IXGBE_ERR_RESET_FAILED;
1029                 DEBUGOUT("Reset polling failed to complete.\n");
1030         }
1031
1032         msec_delay(50);
1033
1034         /* Double resets are required for recovery from certain error
1035          * conditions.  Between resets, it is necessary to stall to
1036          * allow time for any pending HW events to complete.
1037          */
1038         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1039                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1040                 goto mac_reset_top;
1041         }
1042
1043         /* Store the permanent mac address */
1044         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1045
1046         /* Store MAC address from RAR0, clear receive address registers, and
1047          * clear the multicast table.  Also reset num_rar_entries to 128,
1048          * since we modify this value when programming the SAN MAC address.
1049          */
1050         hw->mac.num_rar_entries = 128;
1051         hw->mac.ops.init_rx_addrs(hw);
1052
1053         return status;
1054 }
1055
1056 /**
1057  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1058  *  @hw: pointer to hardware structure
1059  *
1060  *  Configures the integrated KR PHY.
1061  **/
1062 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1063 {
1064         s32 status;
1065         u32 reg_val;
1066
1067         status = ixgbe_read_iosf_sb_reg_x550(hw,
1068                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1069                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1070         if (status)
1071                 return status;
1072
1073         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1074         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ;
1075         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1076         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1077                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1078
1079         /* Advertise 10G support. */
1080         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1081                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1082
1083         /* Advertise 1G support. */
1084         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1085                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1086
1087         /* Restart auto-negotiation. */
1088         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1089         status = ixgbe_write_iosf_sb_reg_x550(hw,
1090                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1091                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1092
1093         return status;
1094 }
1095
1096 /**
1097  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI.
1098  *  @hw: pointer to hardware structure
1099  *
1100  *  Configures the integrated KR PHY to use iXFI mode.
1101  **/
1102 s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw)
1103 {
1104         s32 status;
1105         u32 reg_val;
1106
1107         /* Disable AN and force speed to 10G Serial. */
1108         status = ixgbe_read_iosf_sb_reg_x550(hw,
1109                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1110                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1111         if (status != IXGBE_SUCCESS)
1112                 return status;
1113         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1114         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1115         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1116         status = ixgbe_write_iosf_sb_reg_x550(hw,
1117                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1118                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1119         if (status != IXGBE_SUCCESS)
1120                 return status;
1121
1122         /* Disable training protocol FSM. */
1123         status = ixgbe_read_iosf_sb_reg_x550(hw,
1124                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1125                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1126         if (status != IXGBE_SUCCESS)
1127                 return status;
1128         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1129         status = ixgbe_write_iosf_sb_reg_x550(hw,
1130                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1131                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1132         if (status != IXGBE_SUCCESS)
1133                 return status;
1134
1135         /* Disable Flex from training TXFFE. */
1136         status = ixgbe_read_iosf_sb_reg_x550(hw,
1137                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),
1138                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1139         if (status != IXGBE_SUCCESS)
1140                 return status;
1141         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1142         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1143         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1144         status = ixgbe_write_iosf_sb_reg_x550(hw,
1145                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),
1146                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1147         if (status != IXGBE_SUCCESS)
1148                 return status;
1149         status = ixgbe_read_iosf_sb_reg_x550(hw,
1150                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),
1151                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1152         if (status != IXGBE_SUCCESS)
1153                 return status;
1154         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1155         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1156         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1157         status = ixgbe_write_iosf_sb_reg_x550(hw,
1158                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),
1159                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1160         if (status != IXGBE_SUCCESS)
1161                 return status;
1162
1163         /* Enable override for coefficients. */
1164         status = ixgbe_read_iosf_sb_reg_x550(hw,
1165                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),
1166                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1167         if (status != IXGBE_SUCCESS)
1168                 return status;
1169         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1170         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1171         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1172         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1173         status = ixgbe_write_iosf_sb_reg_x550(hw,
1174                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),
1175                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1176         if (status != IXGBE_SUCCESS)
1177                 return status;
1178
1179         /* Toggle port SW reset by AN reset. */
1180         status = ixgbe_read_iosf_sb_reg_x550(hw,
1181                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1182                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1183         if (status != IXGBE_SUCCESS)
1184                 return status;
1185         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1186         status = ixgbe_write_iosf_sb_reg_x550(hw,
1187                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1188                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1189
1190         return status;
1191 }
1192
1193 /**
1194  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1195  *  @hw: pointer to hardware structure
1196  *
1197  *  Configures the integrated KR PHY to use internal loopback mode.
1198  **/
1199 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1200 {
1201         s32 status;
1202         u32 reg_val;
1203
1204         /* Disable AN and force speed to 10G Serial. */
1205         status = ixgbe_read_iosf_sb_reg_x550(hw,
1206                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1207                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1208         if (status != IXGBE_SUCCESS)
1209                 return status;
1210         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1211         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1212         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1213         status = ixgbe_write_iosf_sb_reg_x550(hw,
1214                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1215                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1216         if (status != IXGBE_SUCCESS)
1217                 return status;
1218
1219         /* Set near-end loopback clocks. */
1220         status = ixgbe_read_iosf_sb_reg_x550(hw,
1221                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),
1222                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1223         if (status != IXGBE_SUCCESS)
1224                 return status;
1225         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1226         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1227         status = ixgbe_write_iosf_sb_reg_x550(hw,
1228                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),
1229                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1230         if (status != IXGBE_SUCCESS)
1231                 return status;
1232
1233         /* Set loopback enable. */
1234         status = ixgbe_read_iosf_sb_reg_x550(hw,
1235                 IXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),
1236                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1237         if (status != IXGBE_SUCCESS)
1238                 return status;
1239         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1240         status = ixgbe_write_iosf_sb_reg_x550(hw,
1241                 IXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),
1242                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1243         if (status != IXGBE_SUCCESS)
1244                 return status;
1245
1246         /* Training bypass. */
1247         status = ixgbe_read_iosf_sb_reg_x550(hw,
1248                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1249                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1250         if (status != IXGBE_SUCCESS)
1251                 return status;
1252         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1253         status = ixgbe_write_iosf_sb_reg_x550(hw,
1254                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1255                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1256
1257         return status;
1258 }
1259
1260 /**
1261  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1262  *  assuming that the semaphore is already obtained.
1263  *  @hw: pointer to hardware structure
1264  *  @offset: offset of  word in the EEPROM to read
1265  *  @data: word read from the EEPROM
1266  *
1267  *  Reads a 16 bit word from the EEPROM using the hostif.
1268  **/
1269 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1270                                    u16 *data)
1271 {
1272         s32 status;
1273         struct ixgbe_hic_read_shadow_ram buffer;
1274
1275         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1276         buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1277         buffer.hdr.buf_len1 = 0;
1278         buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1279         buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1280
1281         /* convert offset from words to bytes */
1282         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1283         /* one word */
1284         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1285
1286         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1287                                               sizeof(buffer), false);
1288
1289         if (status)
1290                 return status;
1291
1292         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1293                                           FW_NVM_DATA_OFFSET);
1294
1295         return 0;
1296 }
1297
1298 /**
1299  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1300  *  @hw: pointer to hardware structure
1301  *  @offset: offset of  word in the EEPROM to read
1302  *  @data: word read from the EEPROM
1303  *
1304  *  Reads a 16 bit word from the EEPROM using the hostif.
1305  **/
1306 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1307                               u16 *data)
1308 {
1309         s32 status = IXGBE_SUCCESS;
1310
1311         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1312
1313         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1314             IXGBE_SUCCESS) {
1315                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1316                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1317         } else {
1318                 status = IXGBE_ERR_SWFW_SYNC;
1319         }
1320
1321         return status;
1322 }
1323
1324 /**
1325  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1326  *  @hw: pointer to hardware structure
1327  *  @offset: offset of  word in the EEPROM to read
1328  *  @words: number of words
1329  *  @data: word(s) read from the EEPROM
1330  *
1331  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1332  **/
1333 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1334                                      u16 offset, u16 words, u16 *data)
1335 {
1336         struct ixgbe_hic_read_shadow_ram buffer;
1337         u32 current_word = 0;
1338         u16 words_to_read;
1339         s32 status;
1340         u32 i;
1341
1342         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1343
1344         /* Take semaphore for the entire operation. */
1345         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1346         if (status) {
1347                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1348                 return status;
1349         }
1350         while (words) {
1351                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1352                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1353                 else
1354                         words_to_read = words;
1355
1356                 buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1357                 buffer.hdr.buf_len1 = 0;
1358                 buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1359                 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1360
1361                 /* convert offset from words to bytes */
1362                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1363                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1364
1365                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1366                                                       sizeof(buffer), false);
1367
1368                 if (status) {
1369                         DEBUGOUT("Host interface command failed\n");
1370                         goto out;
1371                 }
1372
1373                 for (i = 0; i < words_to_read; i++) {
1374                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1375                                   2 * i;
1376                         u32 value = IXGBE_READ_REG(hw, reg);
1377
1378                         data[current_word] = (u16)(value & 0xffff);
1379                         current_word++;
1380                         i++;
1381                         if (i < words_to_read) {
1382                                 value >>= 16;
1383                                 data[current_word] = (u16)(value & 0xffff);
1384                                 current_word++;
1385                         }
1386                 }
1387                 words -= words_to_read;
1388         }
1389
1390 out:
1391         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1392         return status;
1393 }
1394
1395 /**
1396  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1397  *  @hw: pointer to hardware structure
1398  *  @offset: offset of  word in the EEPROM to write
1399  *  @data: word write to the EEPROM
1400  *
1401  *  Write a 16 bit word to the EEPROM using the hostif.
1402  **/
1403 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1404                                     u16 data)
1405 {
1406         s32 status;
1407         struct ixgbe_hic_write_shadow_ram buffer;
1408
1409         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1410
1411         buffer.hdr.cmd = FW_WRITE_SHADOW_RAM_CMD;
1412         buffer.hdr.buf_len1 = 0;
1413         buffer.hdr.buf_len2 = FW_WRITE_SHADOW_RAM_LEN;
1414         buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1415
1416          /* one word */
1417         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1418         buffer.data = data;
1419         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1420
1421         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1422                                               sizeof(buffer), false);
1423
1424         return status;
1425 }
1426
1427 /**
1428  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1429  *  @hw: pointer to hardware structure
1430  *  @offset: offset of  word in the EEPROM to write
1431  *  @data: word write to the EEPROM
1432  *
1433  *  Write a 16 bit word to the EEPROM using the hostif.
1434  **/
1435 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1436                                u16 data)
1437 {
1438         s32 status = IXGBE_SUCCESS;
1439
1440         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1441
1442         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1443             IXGBE_SUCCESS) {
1444                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1445                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1446         } else {
1447                 DEBUGOUT("write ee hostif failed to get semaphore");
1448                 status = IXGBE_ERR_SWFW_SYNC;
1449         }
1450
1451         return status;
1452 }
1453
1454 /**
1455  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1456  *  @hw: pointer to hardware structure
1457  *  @offset: offset of  word in the EEPROM to write
1458  *  @words: number of words
1459  *  @data: word(s) write to the EEPROM
1460  *
1461  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1462  **/
1463 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1464                                       u16 offset, u16 words, u16 *data)
1465 {
1466         s32 status = IXGBE_SUCCESS;
1467         u32 i = 0;
1468
1469         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1470
1471         /* Take semaphore for the entire operation. */
1472         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1473         if (status != IXGBE_SUCCESS) {
1474                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1475                 goto out;
1476         }
1477
1478         for (i = 0; i < words; i++) {
1479                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1480                                                          data[i]);
1481
1482                 if (status != IXGBE_SUCCESS) {
1483                         DEBUGOUT("Eeprom buffered write failed\n");
1484                         break;
1485                 }
1486         }
1487
1488         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1489 out:
1490
1491         return status;
1492 }
1493
1494 /**
1495  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1496  * @hw: pointer to hardware structure
1497  * @ptr: pointer offset in eeprom
1498  * @size: size of section pointed by ptr, if 0 first word will be used as size
1499  * @csum: address of checksum to update
1500  *
1501  * Returns error status for any failure
1502  */
1503 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1504                                    u16 size, u16 *csum)
1505 {
1506         u16 buf[256];
1507         s32 status;
1508         u16 length, bufsz, i, start;
1509
1510         bufsz = sizeof(buf) / sizeof(buf[0]);
1511
1512         /* Read a chunk at the pointer location */
1513         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1514         if (status) {
1515                 DEBUGOUT("Failed to read EEPROM image\n");
1516                 return status;
1517         }
1518
1519         if (size) {
1520                 start = 0;
1521                 length = size;
1522         } else {
1523                 start = 1;
1524                 length = buf[0];
1525
1526                 /* Skip pointer section if length is invalid. */
1527                 if (length == 0xFFFF || length == 0 ||
1528                     (ptr + length) >= hw->eeprom.word_size)
1529                         return IXGBE_SUCCESS;
1530         }
1531
1532         for (i = start; length; i++, length--) {
1533                 if (i == bufsz) {
1534                         ptr += bufsz;
1535                         i = 0;
1536                         if (length < bufsz)
1537                                 bufsz = length;
1538
1539                         /* Read a chunk at the pointer location */
1540                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1541                                                                   bufsz, buf);
1542                         if (status) {
1543                                 DEBUGOUT("Failed to read EEPROM image\n");
1544                                 return status;
1545                         }
1546                 }
1547                 *csum += buf[i];
1548         }
1549         return IXGBE_SUCCESS;
1550 }
1551
1552 /**
1553  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1554  *  @hw: pointer to hardware structure
1555  *
1556  *  Returns a negative error code on error, or the 16-bit checksum
1557  **/
1558 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1559 {
1560         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1561         s32 status;
1562         u16 checksum = 0;
1563         u16 pointer, i, size;
1564
1565         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
1566
1567         hw->eeprom.ops.init_params(hw);
1568
1569         /* Read pointer area */
1570         status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1571                                                   IXGBE_EEPROM_LAST_WORD + 1,
1572                                                   eeprom_ptrs);
1573         if (status) {
1574                 DEBUGOUT("Failed to read EEPROM image\n");
1575                 return status;
1576         }
1577
1578         /*
1579          * For X550 hardware include 0x0-0x41 in the checksum, skip the
1580          * checksum word itself
1581          */
1582         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1583                 if (i != IXGBE_EEPROM_CHECKSUM)
1584                         checksum += eeprom_ptrs[i];
1585
1586         /*
1587          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
1588          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1589          */
1590         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1591                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1592                         continue;
1593
1594                 pointer = eeprom_ptrs[i];
1595
1596                 /* Skip pointer section if the pointer is invalid. */
1597                 if (pointer == 0xFFFF || pointer == 0 ||
1598                     pointer >= hw->eeprom.word_size)
1599                         continue;
1600
1601                 switch (i) {
1602                 case IXGBE_PCIE_GENERAL_PTR:
1603                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1604                         break;
1605                 case IXGBE_PCIE_CONFIG0_PTR:
1606                 case IXGBE_PCIE_CONFIG1_PTR:
1607                         size = IXGBE_PCIE_CONFIG_SIZE;
1608                         break;
1609                 default:
1610                         size = 0;
1611                         break;
1612                 }
1613
1614                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum);
1615                 if (status)
1616                         return status;
1617         }
1618
1619         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1620
1621         return (s32)checksum;
1622 }
1623
1624 /**
1625  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1626  *  @hw: pointer to hardware structure
1627  *  @checksum_val: calculated checksum
1628  *
1629  *  Performs checksum calculation and validates the EEPROM checksum.  If the
1630  *  caller does not need checksum_val, the value can be NULL.
1631  **/
1632 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
1633 {
1634         s32 status;
1635         u16 checksum;
1636         u16 read_checksum = 0;
1637
1638         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
1639
1640         /* Read the first word from the EEPROM. If this times out or fails, do
1641          * not continue or we could be in for a very long wait while every
1642          * EEPROM read fails
1643          */
1644         status = hw->eeprom.ops.read(hw, 0, &checksum);
1645         if (status) {
1646                 DEBUGOUT("EEPROM read failed\n");
1647                 return status;
1648         }
1649
1650         status = hw->eeprom.ops.calc_checksum(hw);
1651         if (status < 0)
1652                 return status;
1653
1654         checksum = (u16)(status & 0xffff);
1655
1656         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1657                                            &read_checksum);
1658         if (status)
1659                 return status;
1660
1661         /* Verify read checksum from EEPROM is the same as
1662          * calculated checksum
1663          */
1664         if (read_checksum != checksum) {
1665                 status = IXGBE_ERR_EEPROM_CHECKSUM;
1666                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1667                              "Invalid EEPROM checksum");
1668         }
1669
1670         /* If the user cares, return the calculated checksum */
1671         if (checksum_val)
1672                 *checksum_val = checksum;
1673
1674         return status;
1675 }
1676
1677 /**
1678  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1679  * @hw: pointer to hardware structure
1680  *
1681  * After writing EEPROM to shadow RAM using EEWR register, software calculates
1682  * checksum and updates the EEPROM and instructs the hardware to update
1683  * the flash.
1684  **/
1685 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1686 {
1687         s32 status;
1688         u16 checksum = 0;
1689
1690         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
1691
1692         /* Read the first word from the EEPROM. If this times out or fails, do
1693          * not continue or we could be in for a very long wait while every
1694          * EEPROM read fails
1695          */
1696         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1697         if (status) {
1698                 DEBUGOUT("EEPROM read failed\n");
1699                 return status;
1700         }
1701
1702         status = ixgbe_calc_eeprom_checksum_X550(hw);
1703         if (status < 0)
1704                 return status;
1705
1706         checksum = (u16)(status & 0xffff);
1707
1708         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1709                                             checksum);
1710         if (status)
1711                 return status;
1712
1713         status = ixgbe_update_flash_X550(hw);
1714
1715         return status;
1716 }
1717
1718 /**
1719  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1720  *  @hw: pointer to hardware structure
1721  *
1722  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1723  **/
1724 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1725 {
1726         s32 status = IXGBE_SUCCESS;
1727         struct ixgbe_hic_hdr2 buffer;
1728
1729         DEBUGFUNC("ixgbe_update_flash_X550");
1730
1731         buffer.cmd = FW_SHADOW_RAM_DUMP_CMD;
1732         buffer.buf_len1 = 0;
1733         buffer.buf_len2 = FW_SHADOW_RAM_DUMP_LEN;
1734         buffer.checksum = FW_DEFAULT_CHECKSUM;
1735
1736         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1737                                               sizeof(buffer), false);
1738
1739         return status;
1740 }
1741
1742 /**
1743  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
1744  *  @hw: pointer to hardware structure
1745  *
1746  *  Determines physical layer capabilities of the current configuration.
1747  **/
1748 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
1749 {
1750         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1751
1752         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
1753
1754         hw->phy.ops.identify(hw);
1755
1756         switch (hw->phy.type) {
1757         case ixgbe_phy_x550em_kr:
1758                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
1759                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1760                 break;
1761         case ixgbe_phy_x550em_kx4:
1762                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1763                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1764                 break;
1765         default:
1766                 break;
1767         }
1768
1769         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
1770                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
1771
1772         return physical_layer;
1773 }
1774
1775 /**
1776  * ixgbe_disable_rx_x550 - Disable RX unit
1777  *
1778  * Enables the Rx DMA unit for x550
1779  **/
1780 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1781 {
1782         u32 rxctrl, pfdtxgswc;
1783         s32 status;
1784         struct ixgbe_hic_disable_rxen fw_cmd;
1785
1786         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
1787
1788         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1789         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1790                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1791                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1792                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1793                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1794                         hw->mac.set_lben = true;
1795                 } else {
1796                         hw->mac.set_lben = false;
1797                 }
1798
1799                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1800                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1801                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1802                 fw_cmd.port_number = hw->phy.lan_id;
1803
1804                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1805                                         sizeof(struct ixgbe_hic_disable_rxen),
1806                                         true);
1807
1808                 /* If we fail - disable RX using register write */
1809                 if (status) {
1810                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1811                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1812                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1813                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1814                         }
1815                 }
1816         }
1817 }