lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 /**
  42  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  43  *  @hw: pointer to hardware structure
  44  *
  45  *  Initialize the function pointers and assign the MAC type for X550.
  46  *  Does not touch the hardware.
  47  **/
  48 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  49 {
  50         struct ixgbe_mac_info *mac = &hw->mac;
  51         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  52         s32 ret_val;
  53
  54         DEBUGFUNC("ixgbe_init_ops_X550");
  55
  56         ret_val = ixgbe_init_ops_X540(hw);
  57         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  58         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  59         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  60         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  61         mac->ops.set_source_address_pruning =
  62                         ixgbe_set_source_address_pruning_X550;
  63         mac->ops.set_ethertype_anti_spoofing =
  64                         ixgbe_set_ethertype_anti_spoofing_X550;
  65
  66         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  67         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  68         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  69         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  70         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  71         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  72         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  73         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  74         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  75
  76         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  77         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  78         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  79         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  80         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  81         return ret_val;
  82 }
  83
  84 /**
  85  * ixgbe_identify_phy_x550em - Get PHY type based on device id
  86  * @hw: pointer to hardware structure
  87  *
  88  * Returns error code
  89  */
  90 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
  91 {
  92         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  93
  94         switch (hw->device_id) {
  95         case IXGBE_DEV_ID_X550EM_X_SFP:
  96                 /* set up for CS4227 usage */
  97                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
  98                 if (hw->bus.lan_id) {
  99
 100                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 101                         esdp |= IXGBE_ESDP_SDP1_DIR;
 102                 }
 103                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 104                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 105
 106                 return ixgbe_identify_module_generic(hw);
 107                 break;
 108         case IXGBE_DEV_ID_X550EM_X_KX4:
 109                 hw->phy.type = ixgbe_phy_x550em_kx4;
 110                 break;
 111         case IXGBE_DEV_ID_X550EM_X_KR:
 112         case IXGBE_DEV_ID_X550EM_X:
 113                 hw->phy.type = ixgbe_phy_x550em_kr;
 114                 break;
 115         default:
 116                 break;
 117         }
 118         return IXGBE_SUCCESS;
 119 }
 120
 121 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 122                                      u32 device_type, u16 *phy_data)
 123 {
 124         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 125         return IXGBE_NOT_IMPLEMENTED;
 126 }
 127
 128 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 129                                       u32 device_type, u16 phy_data)
 130 {
 131         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 132         return IXGBE_NOT_IMPLEMENTED;
 133 }
 134
 135 /**
 136 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 137 *  @hw: pointer to hardware structure
 138 *
 139 *  Initialize the function pointers and for MAC type X550EM.
 140 *  Does not touch the hardware.
 141 **/
 142 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 143 {
 144         struct ixgbe_mac_info *mac = &hw->mac;
 145         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 146         struct ixgbe_phy_info *phy = &hw->phy;
 147         s32 ret_val;
 148
 149         DEBUGFUNC("ixgbe_init_ops_X550EM");
 150
 151         /* Similar to X550 so start there. */
 152         ret_val = ixgbe_init_ops_X550(hw);
 153
 154         /* Since this function eventually calls
 155          * ixgbe_init_ops_540 by design, we are setting
 156          * the pointers to NULL explicitly here to overwrite
 157          * the values being set in the x540 function.
 158          */
 159         /* Thermal sensor not supported in x550EM */
 160         mac->ops.get_thermal_sensor_data = NULL;
 161         mac->ops.init_thermal_sensor_thresh = NULL;
 162         mac->thermal_sensor_enabled = false;
 163
 164         /* FCOE not supported in x550EM */
 165         mac->ops.get_san_mac_addr = NULL;
 166         mac->ops.set_san_mac_addr = NULL;
 167         mac->ops.get_wwn_prefix = NULL;
 168         mac->ops.get_fcoe_boot_status = NULL;
 169
 170         /* IPsec not supported in x550EM */
 171         mac->ops.disable_sec_rx_path = NULL;
 172         mac->ops.enable_sec_rx_path = NULL;
 173
 174         /* X550EM bus type is internal*/
 175         hw->bus.type = ixgbe_bus_type_internal;
 176         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 177
 178         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 179         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 180         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 181         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 182         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 183         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 184         mac->ops.get_supported_physical_layer =
 185                                     ixgbe_get_supported_physical_layer_X550em;
 186
 187         /* PHY */
 188         phy->ops.init = ixgbe_init_phy_ops_X550em;
 189         phy->ops.identify = ixgbe_identify_phy_x550em;
 190         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 191                 phy->ops.set_phy_power = NULL;
 192
 193
 194         /* EEPROM */
 195         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 196         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 197         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 198         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 199         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 200         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 201         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 202         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 203
 204         return ret_val;
 205 }
 206
 207 /**
 208  *  ixgbe_dmac_config_X550
 209  *  @hw: pointer to hardware structure
 210  *
 211  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 212  *  When disabling dmac, dmac enable dmac bit is cleared.
 213  **/
 214 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 215 {
 216         u32 reg, high_pri_tc;
 217
 218         DEBUGFUNC("ixgbe_dmac_config_X550");
 219
 220         /* Disable DMA coalescing before configuring */
 221         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 222         reg &= ~IXGBE_DMACR_DMAC_EN;
 223         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 224
 225         /* Disable DMA Coalescing if the watchdog timer is 0 */
 226         if (!hw->mac.dmac_config.watchdog_timer)
 227                 goto out;
 228
 229         ixgbe_dmac_config_tcs_X550(hw);
 230
 231         /* Configure DMA Coalescing Control Register */
 232         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 233
 234         /* Set the watchdog timer in units of 40.96 usec */
 235         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 236         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 237
 238         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 239         /* If fcoe is enabled, set high priority traffic class */
 240         if (hw->mac.dmac_config.fcoe_en) {
 241                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 242                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 243                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 244         }
 245         reg |= IXGBE_DMACR_EN_MNG_IND;
 246
 247         /* Enable DMA coalescing after configuration */
 248         reg |= IXGBE_DMACR_DMAC_EN;
 249         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 250
 251 out:
 252         return IXGBE_SUCCESS;
 253 }
 254
 255 /**
 256  *  ixgbe_dmac_config_tcs_X550
 257  *  @hw: pointer to hardware structure
 258  *
 259  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 260  *  be cleared before configuring.
 261  **/
 262 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 263 {
 264         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 265
 266         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 267
 268         /* Configure DMA coalescing enabled */
 269         switch (hw->mac.dmac_config.link_speed) {
 270         case IXGBE_LINK_SPEED_100_FULL:
 271                 pb_headroom = IXGBE_DMACRXT_100M;
 272                 break;
 273         case IXGBE_LINK_SPEED_1GB_FULL:
 274                 pb_headroom = IXGBE_DMACRXT_1G;
 275                 break;
 276         default:
 277                 pb_headroom = IXGBE_DMACRXT_10G;
 278                 break;
 279         }
 280
 281         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 282                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 283
 284         /* Set the per Rx packet buffer receive threshold */
 285         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 286                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 287                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 288
 289                 if (tc < hw->mac.dmac_config.num_tcs) {
 290                         /* Get Rx PB size */
 291                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 292                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 293                                 IXGBE_RXPBSIZE_SHIFT;
 294
 295                         /* Calculate receive buffer threshold in kilobytes */
 296                         if (rx_pb_size > pb_headroom)
 297                                 rx_pb_size = rx_pb_size - pb_headroom;
 298                         else
 299                                 rx_pb_size = 0;
 300
 301                         /* Minimum of MFS shall be set for DMCTH */
 302                         reg |= (rx_pb_size > maxframe_size_kb) ?
 303                                 rx_pb_size : maxframe_size_kb;
 304                 }
 305                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 306         }
 307         return IXGBE_SUCCESS;
 308 }
 309
 310 /**
 311  *  ixgbe_dmac_update_tcs_X550
 312  *  @hw: pointer to hardware structure
 313  *
 314  *  Disables dmac, updates per TC settings, and then enables dmac.
 315  **/
 316 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 317 {
 318         u32 reg;
 319
 320         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 321
 322         /* Disable DMA coalescing before configuring */
 323         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 324         reg &= ~IXGBE_DMACR_DMAC_EN;
 325         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 326
 327         ixgbe_dmac_config_tcs_X550(hw);
 328
 329         /* Enable DMA coalescing after configuration */
 330         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 331         reg |= IXGBE_DMACR_DMAC_EN;
 332         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 333
 334         return IXGBE_SUCCESS;
 335 }
 336
 337 /**
 338  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 339  *  @hw: pointer to hardware structure
 340  *
 341  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 342  *  ixgbe_hw struct in order to set up EEPROM access.
 343  **/
 344 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 345 {
 346         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 347         u32 eec;
 348         u16 eeprom_size;
 349
 350         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 351
 352         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 353                 eeprom->semaphore_delay = 10;
 354                 eeprom->type = ixgbe_flash;
 355
 356                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 357                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 358                                     IXGBE_EEC_SIZE_SHIFT);
 359                 eeprom->word_size = 1 << (eeprom_size +
 360                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 361
 362                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 363                           eeprom->type, eeprom->word_size);
 364         }
 365
 366         return IXGBE_SUCCESS;
 367 }
 368
 369 /**
 370  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 371  *  @hw: pointer to the HW structure
 372  *  @enable_eee: boolean flag to enable EEE
 373  *
 374  *  Enable/disable EEE based on enable_eee flag.
 375  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 376  *  are modified.
 377  *
 378  **/
 379 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 380 {
 381         u32 eeer;
 382         u16 autoneg_eee_reg;
 383         u32 link_reg;
 384         s32 status;
 385
 386         DEBUGFUNC("ixgbe_setup_eee_X550");
 387
 388         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 389         /* Enable or disable EEE per flag */
 390         if (enable_eee) {
 391                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 392
 393                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 394                         /* Advertise EEE capability */
 395                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 396                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 397
 398                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 399                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 400                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 401
 402                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 403                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 404                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
 405                            hw->device_id == IXGBE_DEV_ID_X550EM_X) {
 406                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 407                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 408                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 409                         if (status != IXGBE_SUCCESS)
 410                                 return status;
 411
 412                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 413                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 414
 415                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 416                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 417                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 418                         if (status != IXGBE_SUCCESS)
 419                                 return status;
 420                 }
 421         } else {
 422                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 423
 424                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 425                         /* Disable advertised EEE capability */
 426                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 427                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 428
 429                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 430                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 431                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 432
 433                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 434                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 435                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
 436                            hw->device_id == IXGBE_DEV_ID_X550EM_X) {
 437                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 438                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 439                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 440                         if (status != IXGBE_SUCCESS)
 441                                 return status;
 442
 443                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 444                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 445
 446                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 447                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 448                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 449                         if (status != IXGBE_SUCCESS)
 450                                 return status;
 451                 }
 452         }
 453         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 454
 455         return IXGBE_SUCCESS;
 456 }
 457
 458 /**
 459  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 460  * @hw: pointer to hardware structure
 461  * @enable: enable or disable source address pruning
 462  * @pool: Rx pool to set source address pruning for
 463  **/
 464 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 465                                            unsigned int pool)
 466 {
 467         u64 pfflp;
 468
 469         /* max rx pool is 63 */
 470         if (pool > 63)
 471                 return;
 472
 473         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 474         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 475
 476         if (enable)
 477                 pfflp |= (1ULL << pool);
 478         else
 479                 pfflp &= ~(1ULL << pool);
 480
 481         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 482         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 483 }
 484
 485 /**
 486  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 487  *  @hw: pointer to hardware structure
 488  *  @enable: enable or disable switch for Ethertype anti-spoofing
 489  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 490  *
 491  **/
 492 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 493                 bool enable, int vf)
 494 {
 495         int vf_target_reg = vf >> 3;
 496         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 497         u32 pfvfspoof;
 498
 499         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 500
 501         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 502         if (enable)
 503                 pfvfspoof |= (1 << vf_target_shift);
 504         else
 505                 pfvfspoof &= ~(1 << vf_target_shift);
 506
 507         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 508 }
 509
 510 /**
 511  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 512  *  device
 513  *  @hw: pointer to hardware structure
 514  *  @reg_addr: 32 bit PHY register to write
 515  *  @device_type: 3 bit device type
 516  *  @data: Data to write to the register
 517  **/
 518 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 519                             u32 device_type, u32 data)
 520 {
 521         u32 i, command, error;
 522
 523         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 524                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 525
 526         /* Write IOSF control register */
 527         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 528
 529         /* Write IOSF data register */
 530         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 531         /*
 532          * Check every 10 usec to see if the address cycle completed.
 533          * The SB IOSF BUSY bit will clear when the operation is
 534          * complete
 535          */
 536         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 537                 usec_delay(10);
 538
 539                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 540                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 541                         break;
 542         }
 543
 544         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 545                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 546                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 547                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 548                               "Failed to write, error %x\n", error);
 549                 return IXGBE_ERR_PHY;
 550         }
 551
 552         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 553                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 554                 return IXGBE_ERR_PHY;
 555         }
 556
 557         return IXGBE_SUCCESS;
 558 }
 559
 560 /**
 561  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 562  *  device
 563  *  @hw: pointer to hardware structure
 564  *  @reg_addr: 32 bit PHY register to write
 565  *  @device_type: 3 bit device type
 566  *  @phy_data: Pointer to read data from the register
 567  **/
 568 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 569                            u32 device_type, u32 *data)
 570 {
 571         u32 i, command, error;
 572
 573         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 574                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 575
 576         /* Write IOSF control register */
 577         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 578
 579         /*
 580          * Check every 10 usec to see if the address cycle completed.
 581          * The SB IOSF BUSY bit will clear when the operation is
 582          * complete
 583          */
 584         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 585                 usec_delay(10);
 586
 587                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 588                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 589                         break;
 590         }
 591
 592         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 593                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 594                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 595                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 596                                 "Failed to read, error %x\n", error);
 597                 return IXGBE_ERR_PHY;
 598         }
 599
 600         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 601                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 602                 return IXGBE_ERR_PHY;
 603         }
 604
 605         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 606
 607         return IXGBE_SUCCESS;
 608 }
 609
 610 /**
 611  *  ixgbe_disable_mdd_X550
 612  *  @hw: pointer to hardware structure
 613  *
 614  *  Disable malicious driver detection
 615  **/
 616 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 617 {
 618         u32 reg;
 619
 620         DEBUGFUNC("ixgbe_disable_mdd_X550");
 621
 622         /* Disable MDD for TX DMA and interrupt */
 623         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 624         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 625         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 626
 627         /* Disable MDD for RX and interrupt */
 628         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 629         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 630         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 631 }
 632
 633 /**
 634  *  ixgbe_enable_mdd_X550
 635  *  @hw: pointer to hardware structure
 636  *
 637  *  Enable malicious driver detection
 638  **/
 639 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 640 {
 641         u32 reg;
 642
 643         DEBUGFUNC("ixgbe_enable_mdd_X550");
 644
 645         /* Enable MDD for TX DMA and interrupt */
 646         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 647         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 648         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 649
 650         /* Enable MDD for RX and interrupt */
 651         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 652         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 653         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 654 }
 655
 656 /**
 657  *  ixgbe_restore_mdd_vf_X550
 658  *  @hw: pointer to hardware structure
 659  *  @vf: vf index
 660  *
 661  *  Restore VF that was disabled during malicious driver detection event
 662  **/
 663 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 664 {
 665         u32 idx, reg, num_qs, start_q, bitmask;
 666
 667         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 668
 669         /* Map VF to queues */
 670         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 671         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 672         case IXGBE_MRQC_VMDQRT8TCEN:
 673                 num_qs = 8;  /* 16 VFs / pools */
 674                 bitmask = 0x000000FF;
 675                 break;
 676         case IXGBE_MRQC_VMDQRSS32EN:
 677         case IXGBE_MRQC_VMDQRT4TCEN:
 678                 num_qs = 4;  /* 32 VFs / pools */
 679                 bitmask = 0x0000000F;
 680                 break;
 681         default:            /* 64 VFs / pools */
 682                 num_qs = 2;
 683                 bitmask = 0x00000003;
 684                 break;
 685         }
 686         start_q = vf * num_qs;
 687
 688         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 689         idx = start_q / 32;
 690         reg = 0;
 691         reg |= (bitmask << (start_q % 32));
 692         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 693         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 694 }
 695
 696 /**
 697  *  ixgbe_mdd_event_X550
 698  *  @hw: pointer to hardware structure
 699  *  @vf_bitmap: vf bitmap of malicious vfs
 700  *
 701  *  Handle malicious driver detection event.
 702  **/
 703 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 704 {
 705         u32 wqbr;
 706         u32 i, j, reg, q, shift, vf, idx;
 707
 708         DEBUGFUNC("ixgbe_mdd_event_X550");
 709
 710         /* figure out pool size for mapping to vf's */
 711         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 712         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 713         case IXGBE_MRQC_VMDQRT8TCEN:
 714                 shift = 3;  /* 16 VFs / pools */
 715                 break;
 716         case IXGBE_MRQC_VMDQRSS32EN:
 717         case IXGBE_MRQC_VMDQRT4TCEN:
 718                 shift = 2;  /* 32 VFs / pools */
 719                 break;
 720         default:
 721                 shift = 1;  /* 64 VFs / pools */
 722                 break;
 723         }
 724
 725         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 726         for (i = 0; i < 4; i++) {
 727                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 728                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 729
 730                 if (!wqbr)
 731                         continue;
 732
 733                 /* Get malicious queue */
 734                 for (j = 0; j < 32 && wqbr; j++) {
 735
 736                         if (!(wqbr & (1 << j)))
 737                                 continue;
 738
 739                         /* Get queue from bitmask */
 740                         q = j + (i * 32);
 741
 742                         /* Map queue to vf */
 743                         vf = (q >> shift);
 744
 745                         /* Set vf bit in vf_bitmap */
 746                         idx = vf / 32;
 747                         vf_bitmap[idx] |= (1 << (vf % 32));
 748                         wqbr &= ~(1 << j);
 749                 }
 750         }
 751 }
 752
 753 /**
 754  *  ixgbe_get_media_type_X550em - Get media type
 755  *  @hw: pointer to hardware structure
 756  *
 757  *  Returns the media type (fiber, copper, backplane)
 758  */
 759 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 760 {
 761         enum ixgbe_media_type media_type;
 762
 763         DEBUGFUNC("ixgbe_get_media_type_X550em");
 764
 765         /* Detect if there is a copper PHY attached. */
 766         switch (hw->device_id) {
 767         case IXGBE_DEV_ID_X550EM_X:
 768         case IXGBE_DEV_ID_X550EM_X_KR:
 769         case IXGBE_DEV_ID_X550EM_X_KX4:
 770                 media_type = ixgbe_media_type_backplane;
 771                 break;
 772         case IXGBE_DEV_ID_X550EM_X_SFP:
 773                 media_type = ixgbe_media_type_fiber;
 774                 break;
 775         default:
 776                 media_type = ixgbe_media_type_unknown;
 777                 break;
 778         }
 779         return media_type;
 780 }
 781
 782 /**
 783  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 784  *  @hw: pointer to hardware structure
 785  */
 786 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 787 {
 788         bool setup_linear;
 789         u16 reg_slice, edc_mode;
 790         s32 ret_val;
 791
 792         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
 793
 794         switch (hw->phy.sfp_type) {
 795         case ixgbe_sfp_type_unknown:
 796                 return IXGBE_SUCCESS;
 797         case ixgbe_sfp_type_not_present:
 798                 return IXGBE_ERR_SFP_NOT_PRESENT;
 799         case ixgbe_sfp_type_da_cu_core0:
 800         case ixgbe_sfp_type_da_cu_core1:
 801                 setup_linear = true;
 802                 break;
 803         case ixgbe_sfp_type_srlr_core0:
 804         case ixgbe_sfp_type_srlr_core1:
 805         case ixgbe_sfp_type_da_act_lmt_core0:
 806         case ixgbe_sfp_type_da_act_lmt_core1:
 807         case ixgbe_sfp_type_1g_sx_core0:
 808         case ixgbe_sfp_type_1g_sx_core1:
 809         case ixgbe_sfp_type_1g_lx_core0:
 810         case ixgbe_sfp_type_1g_lx_core1:
 811                 setup_linear = false;
 812                 break;
 813         default:
 814                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 815         }
 816
 817         ixgbe_init_mac_link_ops_X550em(hw);
 818         hw->phy.ops.reset = NULL;
 819
 820         /* The CS4227 slice address is the base address + the port-pair reg
 821          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
 822          */
 823         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
 824
 825         if (setup_linear)
 826                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 827         else
 828                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 829
 830         /* Configure CS4227 for connection type. */
 831         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
 832                                            edc_mode);
 833
 834         if (ret_val != IXGBE_SUCCESS)
 835                 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
 836                                                    edc_mode);
 837
 838         return ret_val;
 839 }
 840
 841 /**
 842  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
 843  *  @hw: pointer to hardware structure
 844  */
 845 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
 846 {
 847         struct ixgbe_mac_info *mac = &hw->mac;
 848
 849         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
 850
 851         /* CS4227 does not support autoneg, so disable the laser control
 852          * functions for SFP+ fiber
 853          */
 854          if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 855                 mac->ops.disable_tx_laser = NULL;
 856                 mac->ops.enable_tx_laser = NULL;
 857                 mac->ops.flap_tx_laser = NULL;
 858          }
 859 }
 860
 861 /**
 862  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
 863  *  @hw: pointer to hardware structure
 864  *  @speed: pointer to link speed
 865  *  @autoneg: true when autoneg or autotry is enabled
 866  */
 867 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
 868                                        ixgbe_link_speed *speed,
 869                                        bool *autoneg)
 870 {
 871         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
 872
 873         /* SFP */
 874         if (hw->phy.media_type == ixgbe_media_type_fiber) {
 875
 876                 /* CS4227 SFP must not enable auto-negotiation */
 877                 *autoneg = false;
 878
 879                 /* Check if 1G SFP module. */
 880                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
 881                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
 882                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
 883                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
 884                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
 885                         return IXGBE_SUCCESS;
 886                 }
 887
 888                 /* Link capabilities are based on SFP */
 889                 if (hw->phy.multispeed_fiber)
 890                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
 891                                  IXGBE_LINK_SPEED_1GB_FULL;
 892                 else
 893                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 894         } else {
 895                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
 896                          IXGBE_LINK_SPEED_1GB_FULL;
 897                 *autoneg = true;
 898         }
 899
 900         return IXGBE_SUCCESS;
 901 }
 902
 903 /**
 904  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
 905  *  @hw: pointer to hardware structure
 906  *
 907  *  Initialize any function pointers that were not able to be
 908  *  set during init_shared_code because the PHY/SFP type was
 909  *  not known.  Perform the SFP init if necessary.
 910  */
 911 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
 912 {
 913         struct ixgbe_phy_info *phy = &hw->phy;
 914         s32 ret_val;
 915         u32 esdp;
 916
 917         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
 918
 919         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 920                 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 921                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 922
 923                 if (hw->bus.lan_id) {
 924                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 925                         esdp |= IXGBE_ESDP_SDP1_DIR;
 926                 }
 927                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 928                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 929         }
 930
 931         /* Identify the PHY or SFP module */
 932         ret_val = phy->ops.identify(hw);
 933         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
 934                 return ret_val;
 935
 936         /* Setup function pointers based on detected SFP module and speeds */
 937         ixgbe_init_mac_link_ops_X550em(hw);
 938         if (phy->sfp_type != ixgbe_sfp_type_unknown)
 939                 phy->ops.reset = NULL;
 940
 941         /* Set functions pointers based on phy type */
 942         switch (hw->phy.type) {
 943         case ixgbe_phy_x550em_kx4:
 944                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
 945                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
 946                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
 947                 break;
 948         case ixgbe_phy_x550em_kr:
 949                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
 950                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
 951                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
 952                 break;
 953         case ixgbe_phy_x550em_ext_t:
 954                 phy->ops.setup_internal_link = ixgbe_setup_internal_phy_x550em;
 955                 break;
 956         default:
 957                 break;
 958         }
 959         return ret_val;
 960 }
 961
 962 /**
 963  *  ixgbe_reset_hw_X550em - Perform hardware reset
 964  *  @hw: pointer to hardware structure
 965  *
 966  *  Resets the hardware by resetting the transmit and receive units, masks
 967  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
 968  *  reset.
 969  */
 970 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
 971 {
 972         ixgbe_link_speed link_speed;
 973         s32 status;
 974         u32 ctrl = 0;
 975         u32 i;
 976         bool link_up = false;
 977
 978         DEBUGFUNC("ixgbe_reset_hw_X550em");
 979
 980         /* Call adapter stop to disable Tx/Rx and clear interrupts */
 981         status = hw->mac.ops.stop_adapter(hw);
 982         if (status != IXGBE_SUCCESS)
 983                 return status;
 984
 985         /* flush pending Tx transactions */
 986         ixgbe_clear_tx_pending(hw);
 987
 988         /* PHY ops must be identified and initialized prior to reset */
 989
 990         /* Identify PHY and related function pointers */
 991         status = hw->phy.ops.init(hw);
 992
 993         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 994                 return status;
 995
 996         /* start the external PHY */
 997         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
 998                 status = ixgbe_init_ext_t_x550em(hw);
 999                 if (status)
1000                         return status;
1001         }
1002
1003         /* Setup SFP module if there is one present. */
1004         if (hw->phy.sfp_setup_needed) {
1005                 status = hw->mac.ops.setup_sfp(hw);
1006                 hw->phy.sfp_setup_needed = false;
1007         }
1008
1009         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1010                 return status;
1011
1012         /* Reset PHY */
1013         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1014                 hw->phy.ops.reset(hw);
1015
1016 mac_reset_top:
1017         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1018          * If link reset is used when link is up, it might reset the PHY when
1019          * mng is using it.  If link is down or the flag to force full link
1020          * reset is set, then perform link reset.
1021          */
1022         ctrl = IXGBE_CTRL_LNK_RST;
1023         if (!hw->force_full_reset) {
1024                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1025                 if (link_up)
1026                         ctrl = IXGBE_CTRL_RST;
1027         }
1028
1029         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1030         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1031         IXGBE_WRITE_FLUSH(hw);
1032
1033         /* Poll for reset bit to self-clear meaning reset is complete */
1034         for (i = 0; i < 10; i++) {
1035                 usec_delay(1);
1036                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1037                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1038                         break;
1039         }
1040
1041         if (ctrl & IXGBE_CTRL_RST_MASK) {
1042                 status = IXGBE_ERR_RESET_FAILED;
1043                 DEBUGOUT("Reset polling failed to complete.\n");
1044         }
1045
1046         msec_delay(50);
1047
1048         /* Double resets are required for recovery from certain error
1049          * conditions.  Between resets, it is necessary to stall to
1050          * allow time for any pending HW events to complete.
1051          */
1052         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1053                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1054                 goto mac_reset_top;
1055         }
1056
1057         /* Store the permanent mac address */
1058         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1059
1060         /* Store MAC address from RAR0, clear receive address registers, and
1061          * clear the multicast table.  Also reset num_rar_entries to 128,
1062          * since we modify this value when programming the SAN MAC address.
1063          */
1064         hw->mac.num_rar_entries = 128;
1065         hw->mac.ops.init_rx_addrs(hw);
1066
1067
1068         return status;
1069 }
1070
1071 /**
1072  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1073  * @hw: pointer to hardware structure
1074  */
1075 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1076 {
1077         u32 status;
1078         u16 reg;
1079         u32 retries = 1;
1080
1081         /* TODO: The number of attempts and delay between attempts is undefined */
1082         do {
1083                 /* decrement retries counter and exit if we hit 0 */
1084                 if (retries < 1) {
1085                         ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1086                                       "External PHY not yet finished resetting.");
1087                         return IXGBE_ERR_PHY;
1088                 }
1089                 retries--;
1090
1091                 usec_delay(0);
1092
1093                 status = hw->phy.ops.read_reg(hw,
1094                                               IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1095                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1096                                               &reg);
1097
1098                 if (status != IXGBE_SUCCESS)
1099                         return status;
1100
1101                 /* Verify PHY FW reset has completed */
1102         } while ((reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) != 1);
1103
1104         /* Set port to low power mode */
1105         status = hw->phy.ops.read_reg(hw,
1106                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1107                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1108                                       &reg);
1109
1110         if (status != IXGBE_SUCCESS)
1111                 return status;
1112
1113         reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
1114
1115         status = hw->phy.ops.write_reg(hw,
1116                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1117                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1118                                        reg);
1119
1120         if (status != IXGBE_SUCCESS)
1121                 return status;
1122
1123         /* Enable the transmitter */
1124         status = hw->phy.ops.read_reg(hw,
1125                                       IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1126                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1127                                       &reg);
1128
1129         if (status != IXGBE_SUCCESS)
1130                 return status;
1131
1132         reg &= ~IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE;
1133
1134         status = hw->phy.ops.write_reg(hw,
1135                                        IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1136                                        IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1137                                        reg);
1138
1139         if (status != IXGBE_SUCCESS)
1140                 return status;
1141
1142         /* Un-stall the PHY FW */
1143         status = hw->phy.ops.read_reg(hw,
1144                                       IXGBE_MDIO_GLOBAL_RES_PR_10,
1145                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1146                                       &reg);
1147
1148         if (status != IXGBE_SUCCESS)
1149                 return status;
1150
1151         reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1152
1153         status = hw->phy.ops.write_reg(hw,
1154                                        IXGBE_MDIO_GLOBAL_RES_PR_10,
1155                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1156                                        reg);
1157
1158         return status;
1159 }
1160
1161 /**
1162  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1163  *  @hw: pointer to hardware structure
1164  *
1165  *  Configures the integrated KR PHY.
1166  **/
1167 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1168 {
1169         s32 status;
1170         u32 reg_val;
1171
1172         status = ixgbe_read_iosf_sb_reg_x550(hw,
1173                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1174                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1175         if (status)
1176                 return status;
1177
1178         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1179         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ;
1180         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1181         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1182                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1183
1184         /* Advertise 10G support. */
1185         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1186                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1187
1188         /* Advertise 1G support. */
1189         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1190                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1191
1192         /* Restart auto-negotiation. */
1193         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1194         status = ixgbe_write_iosf_sb_reg_x550(hw,
1195                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1196                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1197
1198         return status;
1199 }
1200
1201 /**
1202  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1203  *  @hw: pointer to hardware structure
1204  *
1205  *  Configures the integrated KX4 PHY.
1206  **/
1207 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1208 {
1209         s32 status;
1210         u32 reg_val;
1211
1212         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1213                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, &reg_val);
1214         if (status)
1215                 return status;
1216
1217         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1218                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1219
1220         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1221
1222         /* Advertise 10G support. */
1223         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1224                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1225
1226         /* Advertise 1G support. */
1227         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1228                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1229
1230         /* Restart auto-negotiation. */
1231         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1232         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1233                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1234
1235         return status;
1236 }
1237
1238 /**
1239  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1240  *  @hw: pointer to hardware structure
1241  *  @speed: the link speed to force
1242  *
1243  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1244  *  internal and external PHY at a specific speed, without autonegotiation.
1245  **/
1246 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1247 {
1248         s32 status;
1249         u32 reg_val;
1250
1251         /* Disable AN and force speed to 10G Serial. */
1252         status = ixgbe_read_iosf_sb_reg_x550(hw,
1253                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1254                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1255         if (status != IXGBE_SUCCESS)
1256                 return status;
1257
1258         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1259         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1260
1261         /* Select forced link speed for internal PHY. */
1262         switch (*speed) {
1263         case IXGBE_LINK_SPEED_10GB_FULL:
1264                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1265                 break;
1266         case IXGBE_LINK_SPEED_1GB_FULL:
1267                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1268                 break;
1269         default:
1270                 /* Other link speeds are not supported by internal KR PHY. */
1271                 return IXGBE_ERR_LINK_SETUP;
1272         }
1273
1274         status = ixgbe_write_iosf_sb_reg_x550(hw,
1275                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1276                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1277         if (status != IXGBE_SUCCESS)
1278                 return status;
1279
1280         /* Disable training protocol FSM. */
1281         status = ixgbe_read_iosf_sb_reg_x550(hw,
1282                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1283                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1284         if (status != IXGBE_SUCCESS)
1285                 return status;
1286         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1287         status = ixgbe_write_iosf_sb_reg_x550(hw,
1288                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1289                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1290         if (status != IXGBE_SUCCESS)
1291                 return status;
1292
1293         /* Disable Flex from training TXFFE. */
1294         status = ixgbe_read_iosf_sb_reg_x550(hw,
1295                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1296                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1297         if (status != IXGBE_SUCCESS)
1298                 return status;
1299         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1300         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1301         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1302         status = ixgbe_write_iosf_sb_reg_x550(hw,
1303                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1304                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1305         if (status != IXGBE_SUCCESS)
1306                 return status;
1307         status = ixgbe_read_iosf_sb_reg_x550(hw,
1308                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1309                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1310         if (status != IXGBE_SUCCESS)
1311                 return status;
1312         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1313         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1314         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1315         status = ixgbe_write_iosf_sb_reg_x550(hw,
1316                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1317                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1318         if (status != IXGBE_SUCCESS)
1319                 return status;
1320
1321         /* Enable override for coefficients. */
1322         status = ixgbe_read_iosf_sb_reg_x550(hw,
1323                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1324                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1325         if (status != IXGBE_SUCCESS)
1326                 return status;
1327         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1328         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1329         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1330         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1331         status = ixgbe_write_iosf_sb_reg_x550(hw,
1332                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1333                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1334         if (status != IXGBE_SUCCESS)
1335                 return status;
1336
1337         /* Toggle port SW reset by AN reset. */
1338         status = ixgbe_read_iosf_sb_reg_x550(hw,
1339                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1340                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1341         if (status != IXGBE_SUCCESS)
1342                 return status;
1343         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1344         status = ixgbe_write_iosf_sb_reg_x550(hw,
1345                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1346                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1347
1348         return status;
1349 }
1350
1351 /**
1352  * ixgbe_setup_internal_phy_x550em - Configure integrated KR PHY
1353  * @hw: point to hardware structure
1354  *
1355  * Configures the integrated KR PHY to talk to the external PHY. The base
1356  * driver will call this function when it gets notification via interrupt from
1357  * the external PHY. This function forces the internal PHY into iXFI mode at
1358  * the correct speed.
1359  *
1360  * A return of a non-zero value indicates an error, and the base driver should
1361  * not report link up.
1362  */
1363 s32 ixgbe_setup_internal_phy_x550em(struct ixgbe_hw *hw)
1364 {
1365         u32 status;
1366         u16 lasi, autoneg_status, speed;
1367         ixgbe_link_speed force_speed;
1368
1369         /* Verify that the external link status has changed */
1370         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_XENPAK_LASI_STATUS,
1371                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1372                                       &lasi);
1373         if (status != IXGBE_SUCCESS)
1374                 return status;
1375
1376         /* If there was no change in link status, we can just exit */
1377         if (!(lasi & IXGBE_XENPAK_LASI_LINK_STATUS_ALARM))
1378                 return IXGBE_SUCCESS;
1379
1380         /* we read this twice back to back to indicate current status */
1381         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1382                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1383                                       &autoneg_status);
1384         if (status != IXGBE_SUCCESS)
1385                 return status;
1386
1387         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1388                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1389                                       &autoneg_status);
1390         if (status != IXGBE_SUCCESS)
1391                 return status;
1392
1393         /* If link is not up return an error indicating treat link as down */
1394         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1395                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1396
1397         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1398                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1399                                       &speed);
1400
1401         /* clear everything but the speed and duplex bits */
1402         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1403
1404         switch (speed) {
1405         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1406                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1407                 break;
1408         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1409                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1410                 break;
1411         default:
1412                 /* Internal PHY does not support anything else */
1413                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1414         }
1415
1416         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1417 }
1418
1419 /**
1420  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1421  *  @hw: pointer to hardware structure
1422  *
1423  *  Configures the integrated KR PHY to use internal loopback mode.
1424  **/
1425 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1426 {
1427         s32 status;
1428         u32 reg_val;
1429
1430         /* Disable AN and force speed to 10G Serial. */
1431         status = ixgbe_read_iosf_sb_reg_x550(hw,
1432                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1433                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1434         if (status != IXGBE_SUCCESS)
1435                 return status;
1436         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1437         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1438         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1439         status = ixgbe_write_iosf_sb_reg_x550(hw,
1440                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1441                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1442         if (status != IXGBE_SUCCESS)
1443                 return status;
1444
1445         /* Set near-end loopback clocks. */
1446         status = ixgbe_read_iosf_sb_reg_x550(hw,
1447                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1448                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1449         if (status != IXGBE_SUCCESS)
1450                 return status;
1451         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1452         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1453         status = ixgbe_write_iosf_sb_reg_x550(hw,
1454                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1455                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1456         if (status != IXGBE_SUCCESS)
1457                 return status;
1458
1459         /* Set loopback enable. */
1460         status = ixgbe_read_iosf_sb_reg_x550(hw,
1461                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1462                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1463         if (status != IXGBE_SUCCESS)
1464                 return status;
1465         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1466         status = ixgbe_write_iosf_sb_reg_x550(hw,
1467                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1468                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1469         if (status != IXGBE_SUCCESS)
1470                 return status;
1471
1472         /* Training bypass. */
1473         status = ixgbe_read_iosf_sb_reg_x550(hw,
1474                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1475                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1476         if (status != IXGBE_SUCCESS)
1477                 return status;
1478         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1479         status = ixgbe_write_iosf_sb_reg_x550(hw,
1480                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1481                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1482
1483         return status;
1484 }
1485
1486 /**
1487  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1488  *  assuming that the semaphore is already obtained.
1489  *  @hw: pointer to hardware structure
1490  *  @offset: offset of  word in the EEPROM to read
1491  *  @data: word read from the EEPROM
1492  *
1493  *  Reads a 16 bit word from the EEPROM using the hostif.
1494  **/
1495 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1496                                    u16 *data)
1497 {
1498         s32 status;
1499         struct ixgbe_hic_read_shadow_ram buffer;
1500
1501         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1502         buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1503         buffer.hdr.buf_len1 = 0;
1504         buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1505         buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1506
1507         /* convert offset from words to bytes */
1508         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1509         /* one word */
1510         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1511
1512         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1513                                               sizeof(buffer), false);
1514
1515         if (status)
1516                 return status;
1517
1518         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1519                                           FW_NVM_DATA_OFFSET);
1520
1521         return 0;
1522 }
1523
1524 /**
1525  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1526  *  @hw: pointer to hardware structure
1527  *  @offset: offset of  word in the EEPROM to read
1528  *  @data: word read from the EEPROM
1529  *
1530  *  Reads a 16 bit word from the EEPROM using the hostif.
1531  **/
1532 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1533                               u16 *data)
1534 {
1535         s32 status = IXGBE_SUCCESS;
1536
1537         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1538
1539         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1540             IXGBE_SUCCESS) {
1541                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1542                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1543         } else {
1544                 status = IXGBE_ERR_SWFW_SYNC;
1545         }
1546
1547         return status;
1548 }
1549
1550 /**
1551  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1552  *  @hw: pointer to hardware structure
1553  *  @offset: offset of  word in the EEPROM to read
1554  *  @words: number of words
1555  *  @data: word(s) read from the EEPROM
1556  *
1557  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1558  **/
1559 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1560                                      u16 offset, u16 words, u16 *data)
1561 {
1562         struct ixgbe_hic_read_shadow_ram buffer;
1563         u32 current_word = 0;
1564         u16 words_to_read;
1565         s32 status;
1566         u32 i;
1567
1568         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1569
1570         /* Take semaphore for the entire operation. */
1571         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1572         if (status) {
1573                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1574                 return status;
1575         }
1576         while (words) {
1577                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1578                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1579                 else
1580                         words_to_read = words;
1581
1582                 buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1583                 buffer.hdr.buf_len1 = 0;
1584                 buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1585                 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1586
1587                 /* convert offset from words to bytes */
1588                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1589                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1590
1591                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1592                                                       sizeof(buffer), false);
1593
1594                 if (status) {
1595                         DEBUGOUT("Host interface command failed\n");
1596                         goto out;
1597                 }
1598
1599                 for (i = 0; i < words_to_read; i++) {
1600                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1601                                   2 * i;
1602                         u32 value = IXGBE_READ_REG(hw, reg);
1603
1604                         data[current_word] = (u16)(value & 0xffff);
1605                         current_word++;
1606                         i++;
1607                         if (i < words_to_read) {
1608                                 value >>= 16;
1609                                 data[current_word] = (u16)(value & 0xffff);
1610                                 current_word++;
1611                         }
1612                 }
1613                 words -= words_to_read;
1614         }
1615
1616 out:
1617         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1618         return status;
1619 }
1620
1621 /**
1622  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1623  *  @hw: pointer to hardware structure
1624  *  @offset: offset of  word in the EEPROM to write
1625  *  @data: word write to the EEPROM
1626  *
1627  *  Write a 16 bit word to the EEPROM using the hostif.
1628  **/
1629 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1630                                     u16 data)
1631 {
1632         s32 status;
1633         struct ixgbe_hic_write_shadow_ram buffer;
1634
1635         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1636
1637         buffer.hdr.cmd = FW_WRITE_SHADOW_RAM_CMD;
1638         buffer.hdr.buf_len1 = 0;
1639         buffer.hdr.buf_len2 = FW_WRITE_SHADOW_RAM_LEN;
1640         buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1641
1642          /* one word */
1643         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1644         buffer.data = data;
1645         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1646
1647         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1648                                               sizeof(buffer), false);
1649
1650         return status;
1651 }
1652
1653 /**
1654  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1655  *  @hw: pointer to hardware structure
1656  *  @offset: offset of  word in the EEPROM to write
1657  *  @data: word write to the EEPROM
1658  *
1659  *  Write a 16 bit word to the EEPROM using the hostif.
1660  **/
1661 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1662                                u16 data)
1663 {
1664         s32 status = IXGBE_SUCCESS;
1665
1666         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1667
1668         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1669             IXGBE_SUCCESS) {
1670                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1671                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1672         } else {
1673                 DEBUGOUT("write ee hostif failed to get semaphore");
1674                 status = IXGBE_ERR_SWFW_SYNC;
1675         }
1676
1677         return status;
1678 }
1679
1680 /**
1681  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1682  *  @hw: pointer to hardware structure
1683  *  @offset: offset of  word in the EEPROM to write
1684  *  @words: number of words
1685  *  @data: word(s) write to the EEPROM
1686  *
1687  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1688  **/
1689 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1690                                       u16 offset, u16 words, u16 *data)
1691 {
1692         s32 status = IXGBE_SUCCESS;
1693         u32 i = 0;
1694
1695         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1696
1697         /* Take semaphore for the entire operation. */
1698         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1699         if (status != IXGBE_SUCCESS) {
1700                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1701                 goto out;
1702         }
1703
1704         for (i = 0; i < words; i++) {
1705                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1706                                                          data[i]);
1707
1708                 if (status != IXGBE_SUCCESS) {
1709                         DEBUGOUT("Eeprom buffered write failed\n");
1710                         break;
1711                 }
1712         }
1713
1714         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1715 out:
1716
1717         return status;
1718 }
1719
1720 /**
1721  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1722  * @hw: pointer to hardware structure
1723  * @ptr: pointer offset in eeprom
1724  * @size: size of section pointed by ptr, if 0 first word will be used as size
1725  * @csum: address of checksum to update
1726  *
1727  * Returns error status for any failure
1728  */
1729 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1730                                    u16 size, u16 *csum, u16 *buffer,
1731                                    u32 buffer_size)
1732 {
1733         u16 buf[256];
1734         s32 status;
1735         u16 length, bufsz, i, start;
1736         u16 *local_buffer;
1737
1738         bufsz = sizeof(buf) / sizeof(buf[0]);
1739
1740         /* Read a chunk at the pointer location */
1741         if (!buffer) {
1742                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1743                 if (status) {
1744                         DEBUGOUT("Failed to read EEPROM image\n");
1745                         return status;
1746                 }
1747                 local_buffer = buf;
1748         } else {
1749                 if (buffer_size < ptr)
1750                         return  IXGBE_ERR_PARAM;
1751                 local_buffer = &buffer[ptr];
1752         }
1753
1754         if (size) {
1755                 start = 0;
1756                 length = size;
1757         } else {
1758                 start = 1;
1759                 length = local_buffer[0];
1760
1761                 /* Skip pointer section if length is invalid. */
1762                 if (length == 0xFFFF || length == 0 ||
1763                     (ptr + length) >= hw->eeprom.word_size)
1764                         return IXGBE_SUCCESS;
1765         }
1766
1767         if (buffer && ((u32)start + (u32)length > buffer_size))
1768                 return IXGBE_ERR_PARAM;
1769
1770         for (i = start; length; i++, length--) {
1771                 if (i == bufsz && !buffer) {
1772                         ptr += bufsz;
1773                         i = 0;
1774                         if (length < bufsz)
1775                                 bufsz = length;
1776
1777                         /* Read a chunk at the pointer location */
1778                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1779                                                                   bufsz, buf);
1780                         if (status) {
1781                                 DEBUGOUT("Failed to read EEPROM image\n");
1782                                 return status;
1783                         }
1784                 }
1785                 *csum += local_buffer[i];
1786         }
1787         return IXGBE_SUCCESS;
1788 }
1789
1790 /**
1791  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
1792  *  @hw: pointer to hardware structure
1793  *  @buffer: pointer to buffer containing calculated checksum
1794  *  @buffer_size: size of buffer
1795  *
1796  *  Returns a negative error code on error, or the 16-bit checksum
1797  **/
1798 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
1799 {
1800         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1801         u16 *local_buffer;
1802         s32 status;
1803         u16 checksum = 0;
1804         u16 pointer, i, size;
1805
1806         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
1807
1808         hw->eeprom.ops.init_params(hw);
1809
1810         if (!buffer) {
1811                 /* Read pointer area */
1812                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1813                                                      IXGBE_EEPROM_LAST_WORD + 1,
1814                                                      eeprom_ptrs);
1815                 if (status) {
1816                         DEBUGOUT("Failed to read EEPROM image\n");
1817                         return status;
1818                 }
1819                 local_buffer = eeprom_ptrs;
1820         } else {
1821                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
1822                         return IXGBE_ERR_PARAM;
1823                 local_buffer = buffer;
1824         }
1825
1826         /*
1827          * For X550 hardware include 0x0-0x41 in the checksum, skip the
1828          * checksum word itself
1829          */
1830         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1831                 if (i != IXGBE_EEPROM_CHECKSUM)
1832                         checksum += local_buffer[i];
1833
1834         /*
1835          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
1836          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1837          */
1838         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1839                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1840                         continue;
1841
1842                 pointer = local_buffer[i];
1843
1844                 /* Skip pointer section if the pointer is invalid. */
1845                 if (pointer == 0xFFFF || pointer == 0 ||
1846                     pointer >= hw->eeprom.word_size)
1847                         continue;
1848
1849                 switch (i) {
1850                 case IXGBE_PCIE_GENERAL_PTR:
1851                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1852                         break;
1853                 case IXGBE_PCIE_CONFIG0_PTR:
1854                 case IXGBE_PCIE_CONFIG1_PTR:
1855                         size = IXGBE_PCIE_CONFIG_SIZE;
1856                         break;
1857                 default:
1858                         size = 0;
1859                         break;
1860                 }
1861
1862                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
1863                                                 buffer, buffer_size);
1864                 if (status)
1865                         return status;
1866         }
1867
1868         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1869
1870         return (s32)checksum;
1871 }
1872
1873 /**
1874  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1875  *  @hw: pointer to hardware structure
1876  *
1877  *  Returns a negative error code on error, or the 16-bit checksum
1878  **/
1879 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1880 {
1881         return ixgbe_calc_checksum_X550(hw, NULL, 0);
1882 }
1883
1884 /**
1885  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1886  *  @hw: pointer to hardware structure
1887  *  @checksum_val: calculated checksum
1888  *
1889  *  Performs checksum calculation and validates the EEPROM checksum.  If the
1890  *  caller does not need checksum_val, the value can be NULL.
1891  **/
1892 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
1893 {
1894         s32 status;
1895         u16 checksum;
1896         u16 read_checksum = 0;
1897
1898         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
1899
1900         /* Read the first word from the EEPROM. If this times out or fails, do
1901          * not continue or we could be in for a very long wait while every
1902          * EEPROM read fails
1903          */
1904         status = hw->eeprom.ops.read(hw, 0, &checksum);
1905         if (status) {
1906                 DEBUGOUT("EEPROM read failed\n");
1907                 return status;
1908         }
1909
1910         status = hw->eeprom.ops.calc_checksum(hw);
1911         if (status < 0)
1912                 return status;
1913
1914         checksum = (u16)(status & 0xffff);
1915
1916         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1917                                            &read_checksum);
1918         if (status)
1919                 return status;
1920
1921         /* Verify read checksum from EEPROM is the same as
1922          * calculated checksum
1923          */
1924         if (read_checksum != checksum) {
1925                 status = IXGBE_ERR_EEPROM_CHECKSUM;
1926                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1927                              "Invalid EEPROM checksum");
1928         }
1929
1930         /* If the user cares, return the calculated checksum */
1931         if (checksum_val)
1932                 *checksum_val = checksum;
1933
1934         return status;
1935 }
1936
1937 /**
1938  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1939  * @hw: pointer to hardware structure
1940  *
1941  * After writing EEPROM to shadow RAM using EEWR register, software calculates
1942  * checksum and updates the EEPROM and instructs the hardware to update
1943  * the flash.
1944  **/
1945 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1946 {
1947         s32 status;
1948         u16 checksum = 0;
1949
1950         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
1951
1952         /* Read the first word from the EEPROM. If this times out or fails, do
1953          * not continue or we could be in for a very long wait while every
1954          * EEPROM read fails
1955          */
1956         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1957         if (status) {
1958                 DEBUGOUT("EEPROM read failed\n");
1959                 return status;
1960         }
1961
1962         status = ixgbe_calc_eeprom_checksum_X550(hw);
1963         if (status < 0)
1964                 return status;
1965
1966         checksum = (u16)(status & 0xffff);
1967
1968         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1969                                             checksum);
1970         if (status)
1971                 return status;
1972
1973         status = ixgbe_update_flash_X550(hw);
1974
1975         return status;
1976 }
1977
1978 /**
1979  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1980  *  @hw: pointer to hardware structure
1981  *
1982  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1983  **/
1984 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1985 {
1986         s32 status = IXGBE_SUCCESS;
1987         struct ixgbe_hic_hdr2 buffer;
1988
1989         DEBUGFUNC("ixgbe_update_flash_X550");
1990
1991         buffer.cmd = FW_SHADOW_RAM_DUMP_CMD;
1992         buffer.buf_len1 = 0;
1993         buffer.buf_len2 = FW_SHADOW_RAM_DUMP_LEN;
1994         buffer.checksum = FW_DEFAULT_CHECKSUM;
1995
1996         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1997                                               sizeof(buffer), false);
1998
1999         return status;
2000 }
2001
2002 /**
2003  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2004  *  @hw: pointer to hardware structure
2005  *
2006  *  Determines physical layer capabilities of the current configuration.
2007  **/
2008 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2009 {
2010         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2011         u16 ext_ability = 0;
2012
2013         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2014
2015         hw->phy.ops.identify(hw);
2016
2017         switch (hw->phy.type) {
2018         case ixgbe_phy_x550em_kr:
2019                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2020                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2021                 break;
2022         case ixgbe_phy_x550em_kx4:
2023                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2024                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2025                 break;
2026         case ixgbe_phy_x550em_ext_t:
2027                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2028                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2029                                      &ext_ability);
2030                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2031                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2032                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2033                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2034                 break;
2035         default:
2036                 break;
2037         }
2038
2039         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2040                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2041
2042         return physical_layer;
2043 }
2044
2045 /**
2046  * ixgbe_get_bus_info_x550em - Set PCI bus info
2047  * @hw: pointer to hardware structure
2048  *
2049  * Sets bus link width and speed to unknown because X550em is
2050  * not a PCI device.
2051  **/
2052 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2053 {
2054
2055         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2056
2057         hw->bus.width = ixgbe_bus_width_unknown;
2058         hw->bus.speed = ixgbe_bus_speed_unknown;
2059
2060         return IXGBE_SUCCESS;
2061 }
2062
2063 /**
2064  * ixgbe_disable_rx_x550 - Disable RX unit
2065  *
2066  * Enables the Rx DMA unit for x550
2067  **/
2068 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2069 {
2070         u32 rxctrl, pfdtxgswc;
2071         s32 status;
2072         struct ixgbe_hic_disable_rxen fw_cmd;
2073
2074         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2075
2076         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2077         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2078                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2079                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2080                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2081                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2082                         hw->mac.set_lben = true;
2083                 } else {
2084                         hw->mac.set_lben = false;
2085                 }
2086
2087                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2088                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2089                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2090                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2091
2092                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2093                                         sizeof(struct ixgbe_hic_disable_rxen),
2094                                         true);
2095
2096                 /* If we fail - disable RX using register write */
2097                 if (status) {
2098                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2099                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2100                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2101                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2102                         }
2103                 }
2104         }
2105 }