lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "ixgbe/ixgbe_api.h"
  67 #include "ixgbe/ixgbe_vf.h"
  68 #include "ixgbe/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 /*
  96  *  Default values for RX/TX configuration
  97  */
  98 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  99 #define IXGBE_DEFAULT_RX_PTHRESH      8
 100 #define IXGBE_DEFAULT_RX_HTHRESH      8
 101 #define IXGBE_DEFAULT_RX_WTHRESH      0
 102
 103 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 104 #define IXGBE_DEFAULT_TX_PTHRESH      32
 105 #define IXGBE_DEFAULT_TX_HTHRESH      0
 106 #define IXGBE_DEFAULT_TX_WTHRESH      0
 107 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 108
 109 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 110
 111 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 112
 113 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
 114                 struct rte_eth_dev *eth_dev);
 115 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 116 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 117 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 118 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 119 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 120 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 121 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 122 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 123 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 124 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 125 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 126                                 int wait_to_complete);
 127 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 128                                 struct rte_eth_stats *stats);
 129 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 130 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 131                                              uint16_t queue_id,
 132                                              uint8_t stat_idx,
 133                                              uint8_t is_rx);
 134 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 135                                struct rte_eth_dev_info *dev_info);
 136 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 137                                  struct rte_eth_dev_info *dev_info);
 138 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 139
 140 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 141                 uint16_t vlan_id, int on);
 142 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 143 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 144                 uint16_t queue, bool on);
 145 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 146                 int on);
 147 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 148 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 149 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 150 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 151 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 152
 153 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 155 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 156                                struct rte_eth_fc_conf *fc_conf);
 157 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 158                                struct rte_eth_fc_conf *fc_conf);
 159 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 160                 struct rte_eth_pfc_conf *pfc_conf);
 161 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 162                 struct rte_eth_rss_reta *reta_conf);
 163 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 164                 struct rte_eth_rss_reta *reta_conf);
 165 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 166 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 167 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 170                 void *param);
 171 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 172 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 173                 uint32_t index, uint32_t pool);
 174 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 175 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 176
 177 /* For Virtual Function support */
 178 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 179                 struct rte_eth_dev *eth_dev);
 180 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 181 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 182 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 183 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 184 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 185 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 186                 struct rte_eth_stats *stats);
 187 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 188 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 189                 uint16_t vlan_id, int on);
 190 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 191                 uint16_t queue, int on);
 192 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 193 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 194
 195 /* For Eth VMDQ APIs support */
 196 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 197                 ether_addr* mac_addr,uint8_t on);
 198 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 199 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 200                 uint16_t rx_mask, uint8_t on);
 201 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 202 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 203 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 204                 uint64_t pool_mask,uint8_t vlan_on);
 205 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 206                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 207                 uint8_t rule_id, uint8_t on);
 208 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 209                 uint8_t rule_id);
 210
 211 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 212                 uint16_t queue_idx, uint16_t tx_rate);
 213 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 214                 uint16_t tx_rate, uint64_t q_msk);
 215
 216 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 217                                  struct ether_addr *mac_addr,
 218                                  uint32_t index, uint32_t pool);
 219 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 220 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
 221                         struct rte_syn_filter *filter, uint16_t rx_queue);
 222 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
 223 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
 224                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 225 static int ixgbe_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 226                         struct rte_ethertype_filter *filter, uint16_t rx_queue);
 227 static int ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
 228                         uint16_t index);
 229 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 230                         struct rte_ethertype_filter *filter, uint16_t *rx_queue);
 231 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 232                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 233 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 234                         uint16_t index);
 235 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 236                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 237
 238 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 239
 240 /*
 241  * Define VF Stats MACRO for Non "cleared on read" register
 242  */
 243 #define UPDATE_VF_STAT(reg, last, cur)                          \
 244 {                                                               \
 245         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 246         cur += latest - last;                                   \
 247         last = latest;                                          \
 248 }
 249
 250 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 251 {                                                                \
 252         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 253         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 254         u64 latest = ((new_msb << 32) | new_lsb);                \
 255         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 256         last = latest;                                           \
 257 }
 258
 259 #define IXGBE_SET_HWSTRIP(h, q) do{\
 260                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 261                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 262                 (h)->bitmap[idx] |= 1 << bit;\
 263         }while(0)
 264
 265 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 266                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 267                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 268                 (h)->bitmap[idx] &= ~(1 << bit);\
 269         }while(0)
 270
 271 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 272                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 273                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 274                 (r) = (h)->bitmap[idx] >> bit & 1;\
 275         }while(0)
 276
 277 /*
 278  * The set of PCI devices this driver supports
 279  */
 280 static struct rte_pci_id pci_id_ixgbe_map[] = {
 281
 282 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 283 #include "rte_pci_dev_ids.h"
 284
 285 { .vendor_id = 0, /* sentinel */ },
 286 };
 287
 288
 289 /*
 290  * The set of PCI devices this driver supports (for 82599 VF)
 291  */
 292 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 293
 294 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 295 #include "rte_pci_dev_ids.h"
 296 { .vendor_id = 0, /* sentinel */ },
 297
 298 };
 299
 300 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 301         .dev_configure        = ixgbe_dev_configure,
 302         .dev_start            = ixgbe_dev_start,
 303         .dev_stop             = ixgbe_dev_stop,
 304         .dev_set_link_up    = ixgbe_dev_set_link_up,
 305         .dev_set_link_down  = ixgbe_dev_set_link_down,
 306         .dev_close            = ixgbe_dev_close,
 307         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 308         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 309         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 310         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 311         .link_update          = ixgbe_dev_link_update,
 312         .stats_get            = ixgbe_dev_stats_get,
 313         .stats_reset          = ixgbe_dev_stats_reset,
 314         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 315         .dev_infos_get        = ixgbe_dev_info_get,
 316         .mtu_set              = ixgbe_dev_mtu_set,
 317         .vlan_filter_set      = ixgbe_vlan_filter_set,
 318         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 319         .vlan_offload_set     = ixgbe_vlan_offload_set,
 320         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 321         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 322         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 323         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 324         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 325         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 326         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 327         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 328         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 329         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 330         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 331         .dev_led_on           = ixgbe_dev_led_on,
 332         .dev_led_off          = ixgbe_dev_led_off,
 333         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 334         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 335         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 336         .mac_addr_add         = ixgbe_add_rar,
 337         .mac_addr_remove      = ixgbe_remove_rar,
 338         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 339         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 340         .mirror_rule_set      = ixgbe_mirror_rule_set,
 341         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 342         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 343         .set_vf_rx            = ixgbe_set_pool_rx,
 344         .set_vf_tx            = ixgbe_set_pool_tx,
 345         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 346         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 347         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 348         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 349         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 350         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 351         .fdir_infos_get               = ixgbe_fdir_info_get,
 352         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 353         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 354         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 355         .fdir_set_masks               = ixgbe_fdir_set_masks,
 356         .reta_update          = ixgbe_dev_rss_reta_update,
 357         .reta_query           = ixgbe_dev_rss_reta_query,
 358 #ifdef RTE_NIC_BYPASS
 359         .bypass_init          = ixgbe_bypass_init,
 360         .bypass_state_set     = ixgbe_bypass_state_store,
 361         .bypass_state_show    = ixgbe_bypass_state_show,
 362         .bypass_event_set     = ixgbe_bypass_event_store,
 363         .bypass_event_show    = ixgbe_bypass_event_show,
 364         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 365         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 366         .bypass_ver_show      = ixgbe_bypass_ver_show,
 367         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 368 #endif /* RTE_NIC_BYPASS */
 369         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 370         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 371         .add_syn_filter          = ixgbe_add_syn_filter,
 372         .remove_syn_filter       = ixgbe_remove_syn_filter,
 373         .get_syn_filter          = ixgbe_get_syn_filter,
 374         .add_ethertype_filter    = ixgbe_add_ethertype_filter,
 375         .remove_ethertype_filter = ixgbe_remove_ethertype_filter,
 376         .get_ethertype_filter    = ixgbe_get_ethertype_filter,
 377         .add_5tuple_filter       = ixgbe_add_5tuple_filter,
 378         .remove_5tuple_filter    = ixgbe_remove_5tuple_filter,
 379         .get_5tuple_filter       = ixgbe_get_5tuple_filter,
 380 };
 381
 382 /*
 383  * dev_ops for virtual function, bare necessities for basic vf
 384  * operation have been implemented
 385  */
 386 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 387
 388         .dev_configure        = ixgbevf_dev_configure,
 389         .dev_start            = ixgbevf_dev_start,
 390         .dev_stop             = ixgbevf_dev_stop,
 391         .link_update          = ixgbe_dev_link_update,
 392         .stats_get            = ixgbevf_dev_stats_get,
 393         .stats_reset          = ixgbevf_dev_stats_reset,
 394         .dev_close            = ixgbevf_dev_close,
 395         .dev_infos_get        = ixgbevf_dev_info_get,
 396         .mtu_set              = ixgbevf_dev_set_mtu,
 397         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 398         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 399         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 400         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 401         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 402         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 403         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 404         .mac_addr_add         = ixgbevf_add_mac_addr,
 405         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 406 };
 407
 408 /**
 409  * Atomically reads the link status information from global
 410  * structure rte_eth_dev.
 411  *
 412  * @param dev
 413  *   - Pointer to the structure rte_eth_dev to read from.
 414  *   - Pointer to the buffer to be saved with the link status.
 415  *
 416  * @return
 417  *   - On success, zero.
 418  *   - On failure, negative value.
 419  */
 420 static inline int
 421 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 422                                 struct rte_eth_link *link)
 423 {
 424         struct rte_eth_link *dst = link;
 425         struct rte_eth_link *src = &(dev->data->dev_link);
 426
 427         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 428                                         *(uint64_t *)src) == 0)
 429                 return -1;
 430
 431         return 0;
 432 }
 433
 434 /**
 435  * Atomically writes the link status information into global
 436  * structure rte_eth_dev.
 437  *
 438  * @param dev
 439  *   - Pointer to the structure rte_eth_dev to read from.
 440  *   - Pointer to the buffer to be saved with the link status.
 441  *
 442  * @return
 443  *   - On success, zero.
 444  *   - On failure, negative value.
 445  */
 446 static inline int
 447 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 448                                 struct rte_eth_link *link)
 449 {
 450         struct rte_eth_link *dst = &(dev->data->dev_link);
 451         struct rte_eth_link *src = link;
 452
 453         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 454                                         *(uint64_t *)src) == 0)
 455                 return -1;
 456
 457         return 0;
 458 }
 459
 460 /*
 461  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 462  */
 463 static inline int
 464 ixgbe_is_sfp(struct ixgbe_hw *hw)
 465 {
 466         switch (hw->phy.type) {
 467         case ixgbe_phy_sfp_avago:
 468         case ixgbe_phy_sfp_ftl:
 469         case ixgbe_phy_sfp_intel:
 470         case ixgbe_phy_sfp_unknown:
 471         case ixgbe_phy_sfp_passive_tyco:
 472         case ixgbe_phy_sfp_passive_unknown:
 473                 return 1;
 474         default:
 475                 return 0;
 476         }
 477 }
 478
 479 static inline int32_t
 480 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 481 {
 482         uint32_t ctrl_ext;
 483         int32_t status;
 484
 485         status = ixgbe_reset_hw(hw);
 486
 487         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 488         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 489         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 490         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 491         IXGBE_WRITE_FLUSH(hw);
 492
 493         return status;
 494 }
 495
 496 static inline void
 497 ixgbe_enable_intr(struct rte_eth_dev *dev)
 498 {
 499         struct ixgbe_interrupt *intr =
 500                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 501         struct ixgbe_hw *hw =
 502                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 503
 504         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 505         IXGBE_WRITE_FLUSH(hw);
 506 }
 507
 508 /*
 509  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 510  */
 511 static void
 512 ixgbe_disable_intr(struct ixgbe_hw *hw)
 513 {
 514         PMD_INIT_FUNC_TRACE();
 515
 516         if (hw->mac.type == ixgbe_mac_82598EB) {
 517                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 518         } else {
 519                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 520                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 521                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 522         }
 523         IXGBE_WRITE_FLUSH(hw);
 524 }
 525
 526 /*
 527  * This function resets queue statistics mapping registers.
 528  * From Niantic datasheet, Initialization of Statistics section:
 529  * "...if software requires the queue counters, the RQSMR and TQSM registers
 530  * must be re-programmed following a device reset.
 531  */
 532 static void
 533 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 534 {
 535         uint32_t i;
 536
 537         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 538                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 539                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 540         }
 541 }
 542
 543
 544 static int
 545 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 546                                   uint16_t queue_id,
 547                                   uint8_t stat_idx,
 548                                   uint8_t is_rx)
 549 {
 550 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 551 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 552 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 553
 554         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 555         struct ixgbe_stat_mapping_registers *stat_mappings =
 556                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 557         uint32_t qsmr_mask = 0;
 558         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 559         uint32_t q_map;
 560         uint8_t n, offset;
 561
 562         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 563                 (hw->mac.type != ixgbe_mac_X540) &&
 564                 (hw->mac.type != ixgbe_mac_X550) &&
 565                 (hw->mac.type != ixgbe_mac_X550EM_x))
 566                 return -ENOSYS;
 567
 568         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 569                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 570                      queue_id, stat_idx);
 571
 572         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 573         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 574                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 575                 return -EIO;
 576         }
 577         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 578
 579         /* Now clear any previous stat_idx set */
 580         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 581         if (!is_rx)
 582                 stat_mappings->tqsm[n] &= ~clearing_mask;
 583         else
 584                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 585
 586         q_map = (uint32_t)stat_idx;
 587         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 588         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 589         if (!is_rx)
 590                 stat_mappings->tqsm[n] |= qsmr_mask;
 591         else
 592                 stat_mappings->rqsmr[n] |= qsmr_mask;
 593
 594         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 595                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 596                      queue_id, stat_idx);
 597         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 598                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 599
 600         /* Now write the mapping in the appropriate register */
 601         if (is_rx) {
 602                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 603                              stat_mappings->rqsmr[n], n);
 604                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 605         }
 606         else {
 607                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 608                              stat_mappings->tqsm[n], n);
 609                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 610         }
 611         return 0;
 612 }
 613
 614 static void
 615 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 616 {
 617         struct ixgbe_stat_mapping_registers *stat_mappings =
 618                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 619         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 620         int i;
 621
 622         /* write whatever was in stat mapping table to the NIC */
 623         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 624                 /* rx */
 625                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 626
 627                 /* tx */
 628                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 629         }
 630 }
 631
 632 static void
 633 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 634 {
 635         uint8_t i;
 636         struct ixgbe_dcb_tc_config *tc;
 637         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 638
 639         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 640         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 641         for (i = 0; i < dcb_max_tc; i++) {
 642                 tc = &dcb_config->tc_config[i];
 643                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 644                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 645                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 646                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 647                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 648                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 649                 tc->pfc = ixgbe_dcb_pfc_disabled;
 650         }
 651
 652         /* Initialize default user to priority mapping, UPx->TC0 */
 653         tc = &dcb_config->tc_config[0];
 654         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 655         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 656         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 657                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 658                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 659         }
 660         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 661         dcb_config->pfc_mode_enable = false;
 662         dcb_config->vt_mode = true;
 663         dcb_config->round_robin_enable = false;
 664         /* support all DCB capabilities in 82599 */
 665         dcb_config->support.capabilities = 0xFF;
 666
 667         /*we only support 4 Tcs for X540, X550 */
 668         if (hw->mac.type == ixgbe_mac_X540 ||
 669                 hw->mac.type == ixgbe_mac_X550 ||
 670                 hw->mac.type == ixgbe_mac_X550EM_x) {
 671                 dcb_config->num_tcs.pg_tcs = 4;
 672                 dcb_config->num_tcs.pfc_tcs = 4;
 673         }
 674 }
 675
 676 /*
 677  * Ensure that all locks are released before first NVM or PHY access
 678  */
 679 static void
 680 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 681 {
 682         uint16_t mask;
 683
 684         /*
 685          * Phy lock should not fail in this early stage. If this is the case,
 686          * it is due to an improper exit of the application.
 687          * So force the release of the faulty lock. Release of common lock
 688          * is done automatically by swfw_sync function.
 689          */
 690         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 691         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 692                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 693         }
 694         ixgbe_release_swfw_semaphore(hw, mask);
 695
 696         /*
 697          * These ones are more tricky since they are common to all ports; but
 698          * swfw_sync retries last long enough (1s) to be almost sure that if
 699          * lock can not be taken it is due to an improper lock of the
 700          * semaphore.
 701          */
 702         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 703         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 704                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 705         }
 706         ixgbe_release_swfw_semaphore(hw, mask);
 707 }
 708
 709 /*
 710  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 711  * It returns 0 on success.
 712  */
 713 static int
 714 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 715                      struct rte_eth_dev *eth_dev)
 716 {
 717         struct rte_pci_device *pci_dev;
 718         struct ixgbe_hw *hw =
 719                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 720         struct ixgbe_vfta * shadow_vfta =
 721                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 722         struct ixgbe_hwstrip *hwstrip =
 723                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 724         struct ixgbe_dcb_config *dcb_config =
 725                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 726         uint32_t ctrl_ext;
 727         uint16_t csum;
 728         int diag, i;
 729
 730         PMD_INIT_FUNC_TRACE();
 731
 732         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 733         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 734         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 735
 736         /* for secondary processes, we don't initialise any further as primary
 737          * has already done this work. Only check we don't need a different
 738          * RX function */
 739         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 740                 if (eth_dev->data->scattered_rx)
 741                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 742                 return 0;
 743         }
 744         pci_dev = eth_dev->pci_dev;
 745
 746         /* Vendor and Device ID need to be set before init of shared code */
 747         hw->device_id = pci_dev->id.device_id;
 748         hw->vendor_id = pci_dev->id.vendor_id;
 749         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 750         hw->allow_unsupported_sfp = 1;
 751
 752         /* Initialize the shared code (base driver) */
 753 #ifdef RTE_NIC_BYPASS
 754         diag = ixgbe_bypass_init_shared_code(hw);
 755 #else
 756         diag = ixgbe_init_shared_code(hw);
 757 #endif /* RTE_NIC_BYPASS */
 758
 759         if (diag != IXGBE_SUCCESS) {
 760                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 761                 return -EIO;
 762         }
 763
 764         /* pick up the PCI bus settings for reporting later */
 765         ixgbe_get_bus_info(hw);
 766
 767         /* Unlock any pending hardware semaphore */
 768         ixgbe_swfw_lock_reset(hw);
 769
 770         /* Initialize DCB configuration*/
 771         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 772         ixgbe_dcb_init(hw,dcb_config);
 773         /* Get Hardware Flow Control setting */
 774         hw->fc.requested_mode = ixgbe_fc_full;
 775         hw->fc.current_mode = ixgbe_fc_full;
 776         hw->fc.pause_time = IXGBE_FC_PAUSE;
 777         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 778                 hw->fc.low_water[i] = IXGBE_FC_LO;
 779                 hw->fc.high_water[i] = IXGBE_FC_HI;
 780         }
 781         hw->fc.send_xon = 1;
 782
 783         /* Make sure we have a good EEPROM before we read from it */
 784         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 785         if (diag != IXGBE_SUCCESS) {
 786                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 787                 return -EIO;
 788         }
 789
 790 #ifdef RTE_NIC_BYPASS
 791         diag = ixgbe_bypass_init_hw(hw);
 792 #else
 793         diag = ixgbe_init_hw(hw);
 794 #endif /* RTE_NIC_BYPASS */
 795
 796         /*
 797          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 798          * is called too soon after the kernel driver unbinding/binding occurs.
 799          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 800          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 801          * also called. See ixgbe_identify_phy_82599(). The reason for the
 802          * failure is not known, and only occuts when virtualisation features
 803          * are disabled in the bios. A delay of 100ms  was found to be enough by
 804          * trial-and-error, and is doubled to be safe.
 805          */
 806         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 807                 rte_delay_ms(200);
 808                 diag = ixgbe_init_hw(hw);
 809         }
 810
 811         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 812                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 813                     "LOM.  Please be aware there may be issues associated "
 814                     "with your hardware.");
 815                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 816                     "please contact your Intel or hardware representative "
 817                     "who provided you with this hardware.");
 818         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 819                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 820         if (diag) {
 821                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 822                 return -EIO;
 823         }
 824
 825         /* disable interrupt */
 826         ixgbe_disable_intr(hw);
 827
 828         /* reset mappings for queue statistics hw counters*/
 829         ixgbe_reset_qstat_mappings(hw);
 830
 831         /* Allocate memory for storing MAC addresses */
 832         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 833                         hw->mac.num_rar_entries, 0);
 834         if (eth_dev->data->mac_addrs == NULL) {
 835                 PMD_INIT_LOG(ERR,
 836                         "Failed to allocate %u bytes needed to store "
 837                         "MAC addresses",
 838                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 839                 return -ENOMEM;
 840         }
 841         /* Copy the permanent MAC address */
 842         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 843                         &eth_dev->data->mac_addrs[0]);
 844
 845         /* Allocate memory for storing hash filter MAC addresses */
 846         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 847                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 848         if (eth_dev->data->hash_mac_addrs == NULL) {
 849                 PMD_INIT_LOG(ERR,
 850                         "Failed to allocate %d bytes needed to store MAC addresses",
 851                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 852                 return -ENOMEM;
 853         }
 854
 855         /* initialize the vfta */
 856         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 857
 858         /* initialize the hw strip bitmap*/
 859         memset(hwstrip, 0, sizeof(*hwstrip));
 860
 861         /* initialize PF if max_vfs not zero */
 862         ixgbe_pf_host_init(eth_dev);
 863
 864         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 865         /* let hardware know driver is loaded */
 866         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 867         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 868         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 869         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 870         IXGBE_WRITE_FLUSH(hw);
 871
 872         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 873                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 874                              (int) hw->mac.type, (int) hw->phy.type,
 875                              (int) hw->phy.sfp_type);
 876         else
 877                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 878                              (int) hw->mac.type, (int) hw->phy.type);
 879
 880         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 881                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 882                         pci_dev->id.device_id);
 883
 884         rte_intr_callback_register(&(pci_dev->intr_handle),
 885                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 886
 887         /* enable uio intr after callback register */
 888         rte_intr_enable(&(pci_dev->intr_handle));
 889
 890         /* enable support intr */
 891         ixgbe_enable_intr(eth_dev);
 892
 893         return 0;
 894 }
 895
 896
 897 /*
 898  * Negotiate mailbox API version with the PF.
 899  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 900  * Then we try to negotiate starting with the most recent one.
 901  * If all negotiation attempts fail, then we will proceed with
 902  * the default one (ixgbe_mbox_api_10).
 903  */
 904 static void
 905 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 906 {
 907         int32_t i;
 908
 909         /* start with highest supported, proceed down */
 910         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 911                 ixgbe_mbox_api_11,
 912                 ixgbe_mbox_api_10,
 913         };
 914
 915         for (i = 0;
 916                         i != RTE_DIM(sup_ver) &&
 917                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 918                         i++)
 919                 ;
 920 }
 921
 922 static void
 923 generate_random_mac_addr(struct ether_addr *mac_addr)
 924 {
 925         uint64_t random;
 926
 927         /* Set Organizationally Unique Identifier (OUI) prefix. */
 928         mac_addr->addr_bytes[0] = 0x00;
 929         mac_addr->addr_bytes[1] = 0x09;
 930         mac_addr->addr_bytes[2] = 0xC0;
 931         /* Force indication of locally assigned MAC address. */
 932         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 933         /* Generate the last 3 bytes of the MAC address with a random number. */
 934         random = rte_rand();
 935         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 936 }
 937
 938 /*
 939  * Virtual Function device init
 940  */
 941 static int
 942 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 943                      struct rte_eth_dev *eth_dev)
 944 {
 945         int diag;
 946         uint32_t tc, tcs;
 947         struct rte_pci_device *pci_dev;
 948         struct ixgbe_hw *hw =
 949                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 950         struct ixgbe_vfta * shadow_vfta =
 951                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 952         struct ixgbe_hwstrip *hwstrip =
 953                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 954         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 955
 956         PMD_INIT_FUNC_TRACE();
 957
 958         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 959         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 960         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 961
 962         /* for secondary processes, we don't initialise any further as primary
 963          * has already done this work. Only check we don't need a different
 964          * RX function */
 965         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 966                 if (eth_dev->data->scattered_rx)
 967                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 968                 return 0;
 969         }
 970
 971         pci_dev = eth_dev->pci_dev;
 972
 973         hw->device_id = pci_dev->id.device_id;
 974         hw->vendor_id = pci_dev->id.vendor_id;
 975         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 976
 977         /* initialize the vfta */
 978         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 979
 980         /* initialize the hw strip bitmap*/
 981         memset(hwstrip, 0, sizeof(*hwstrip));
 982
 983         /* Initialize the shared code (base driver) */
 984         diag = ixgbe_init_shared_code(hw);
 985         if (diag != IXGBE_SUCCESS) {
 986                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 987                 return -EIO;
 988         }
 989
 990         /* init_mailbox_params */
 991         hw->mbx.ops.init_params(hw);
 992
 993         /* Disable the interrupts for VF */
 994         ixgbevf_intr_disable(hw);
 995
 996         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
 997         diag = hw->mac.ops.reset_hw(hw);
 998
 999         /*
1000          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1001          * the underlying PF driver has not assigned a MAC address to the VF.
1002          * In this case, assign a random MAC address.
1003          */
1004         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1005                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1006                 return (diag);
1007         }
1008
1009         /* negotiate mailbox API version to use with the PF. */
1010         ixgbevf_negotiate_api(hw);
1011
1012         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1013         ixgbevf_get_queues(hw, &tcs, &tc);
1014
1015         /* Allocate memory for storing MAC addresses */
1016         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1017                         hw->mac.num_rar_entries, 0);
1018         if (eth_dev->data->mac_addrs == NULL) {
1019                 PMD_INIT_LOG(ERR,
1020                         "Failed to allocate %u bytes needed to store "
1021                         "MAC addresses",
1022                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1023                 return -ENOMEM;
1024         }
1025
1026         /* Generate a random MAC address, if none was assigned by PF. */
1027         if (is_zero_ether_addr(perm_addr)) {
1028                 generate_random_mac_addr(perm_addr);
1029                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1030                 if (diag) {
1031                         rte_free(eth_dev->data->mac_addrs);
1032                         eth_dev->data->mac_addrs = NULL;
1033                         return diag;
1034                 }
1035                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1036                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1037                              "%02x:%02x:%02x:%02x:%02x:%02x",
1038                              perm_addr->addr_bytes[0],
1039                              perm_addr->addr_bytes[1],
1040                              perm_addr->addr_bytes[2],
1041                              perm_addr->addr_bytes[3],
1042                              perm_addr->addr_bytes[4],
1043                              perm_addr->addr_bytes[5]);
1044         }
1045
1046         /* Copy the permanent MAC address */
1047         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1048
1049         /* reset the hardware with the new settings */
1050         diag = hw->mac.ops.start_hw(hw);
1051         switch (diag) {
1052                 case  0:
1053                         break;
1054
1055                 default:
1056                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1057                         return (-EIO);
1058         }
1059
1060         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1061                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1062                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1063
1064         return 0;
1065 }
1066
1067 static struct eth_driver rte_ixgbe_pmd = {
1068         {
1069                 .name = "rte_ixgbe_pmd",
1070                 .id_table = pci_id_ixgbe_map,
1071                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1072         },
1073         .eth_dev_init = eth_ixgbe_dev_init,
1074         .dev_private_size = sizeof(struct ixgbe_adapter),
1075 };
1076
1077 /*
1078  * virtual function driver struct
1079  */
1080 static struct eth_driver rte_ixgbevf_pmd = {
1081         {
1082                 .name = "rte_ixgbevf_pmd",
1083                 .id_table = pci_id_ixgbevf_map,
1084                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1085         },
1086         .eth_dev_init = eth_ixgbevf_dev_init,
1087         .dev_private_size = sizeof(struct ixgbe_adapter),
1088 };
1089
1090 /*
1091  * Driver initialization routine.
1092  * Invoked once at EAL init time.
1093  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1094  */
1095 static int
1096 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1097 {
1098         PMD_INIT_FUNC_TRACE();
1099
1100         rte_eth_driver_register(&rte_ixgbe_pmd);
1101         return 0;
1102 }
1103
1104 /*
1105  * VF Driver initialization routine.
1106  * Invoked one at EAL init time.
1107  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1108  */
1109 static int
1110 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1111 {
1112         PMD_INIT_FUNC_TRACE();
1113
1114         rte_eth_driver_register(&rte_ixgbevf_pmd);
1115         return (0);
1116 }
1117
1118 static int
1119 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1120 {
1121         struct ixgbe_hw *hw =
1122                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1123         struct ixgbe_vfta * shadow_vfta =
1124                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1125         uint32_t vfta;
1126         uint32_t vid_idx;
1127         uint32_t vid_bit;
1128
1129         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1130         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1131         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1132         if (on)
1133                 vfta |= vid_bit;
1134         else
1135                 vfta &= ~vid_bit;
1136         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1137
1138         /* update local VFTA copy */
1139         shadow_vfta->vfta[vid_idx] = vfta;
1140
1141         return 0;
1142 }
1143
1144 static void
1145 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1146 {
1147         if (on)
1148                 ixgbe_vlan_hw_strip_enable(dev, queue);
1149         else
1150                 ixgbe_vlan_hw_strip_disable(dev, queue);
1151 }
1152
1153 static void
1154 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1155 {
1156         struct ixgbe_hw *hw =
1157                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1158
1159         /* Only the high 16-bits is valid */
1160         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1161 }
1162
1163 void
1164 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1165 {
1166         struct ixgbe_hw *hw =
1167                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1168         uint32_t vlnctrl;
1169
1170         PMD_INIT_FUNC_TRACE();
1171
1172         /* Filter Table Disable */
1173         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1174         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1175
1176         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1177 }
1178
1179 void
1180 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1181 {
1182         struct ixgbe_hw *hw =
1183                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1184         struct ixgbe_vfta * shadow_vfta =
1185                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1186         uint32_t vlnctrl;
1187         uint16_t i;
1188
1189         PMD_INIT_FUNC_TRACE();
1190
1191         /* Filter Table Enable */
1192         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1193         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1194         vlnctrl |= IXGBE_VLNCTRL_VFE;
1195
1196         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1197
1198         /* write whatever is in local vfta copy */
1199         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1200                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1201 }
1202
1203 static void
1204 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1205 {
1206         struct ixgbe_hwstrip *hwstrip =
1207                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1208
1209         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1210                 return;
1211
1212         if (on)
1213                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1214         else
1215                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1216 }
1217
1218 static void
1219 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1220 {
1221         struct ixgbe_hw *hw =
1222                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1223         uint32_t ctrl;
1224
1225         PMD_INIT_FUNC_TRACE();
1226
1227         if (hw->mac.type == ixgbe_mac_82598EB) {
1228                 /* No queue level support */
1229                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1230                 return;
1231         }
1232         else {
1233                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1234                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1235                 ctrl &= ~IXGBE_RXDCTL_VME;
1236                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1237         }
1238         /* record those setting for HW strip per queue */
1239         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1240 }
1241
1242 static void
1243 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1244 {
1245         struct ixgbe_hw *hw =
1246                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1247         uint32_t ctrl;
1248
1249         PMD_INIT_FUNC_TRACE();
1250
1251         if (hw->mac.type == ixgbe_mac_82598EB) {
1252                 /* No queue level supported */
1253                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1254                 return;
1255         }
1256         else {
1257                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1258                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1259                 ctrl |= IXGBE_RXDCTL_VME;
1260                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1261         }
1262         /* record those setting for HW strip per queue */
1263         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1264 }
1265
1266 void
1267 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1268 {
1269         struct ixgbe_hw *hw =
1270                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1271         uint32_t ctrl;
1272         uint16_t i;
1273
1274         PMD_INIT_FUNC_TRACE();
1275
1276         if (hw->mac.type == ixgbe_mac_82598EB) {
1277                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1278                 ctrl &= ~IXGBE_VLNCTRL_VME;
1279                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1280         }
1281         else {
1282                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1283                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1284                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1285                         ctrl &= ~IXGBE_RXDCTL_VME;
1286                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1287
1288                         /* record those setting for HW strip per queue */
1289                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1290                 }
1291         }
1292 }
1293
1294 void
1295 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1296 {
1297         struct ixgbe_hw *hw =
1298                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1299         uint32_t ctrl;
1300         uint16_t i;
1301
1302         PMD_INIT_FUNC_TRACE();
1303
1304         if (hw->mac.type == ixgbe_mac_82598EB) {
1305                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1306                 ctrl |= IXGBE_VLNCTRL_VME;
1307                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1308         }
1309         else {
1310                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1311                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1312                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1313                         ctrl |= IXGBE_RXDCTL_VME;
1314                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1315
1316                         /* record those setting for HW strip per queue */
1317                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1318                 }
1319         }
1320 }
1321
1322 static void
1323 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1324 {
1325         struct ixgbe_hw *hw =
1326                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1327         uint32_t ctrl;
1328
1329         PMD_INIT_FUNC_TRACE();
1330
1331         /* DMATXCTRL: Geric Double VLAN Disable */
1332         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1333         ctrl &= ~IXGBE_DMATXCTL_GDV;
1334         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1335
1336         /* CTRL_EXT: Global Double VLAN Disable */
1337         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1338         ctrl &= ~IXGBE_EXTENDED_VLAN;
1339         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1340
1341 }
1342
1343 static void
1344 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1345 {
1346         struct ixgbe_hw *hw =
1347                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348         uint32_t ctrl;
1349
1350         PMD_INIT_FUNC_TRACE();
1351
1352         /* DMATXCTRL: Geric Double VLAN Enable */
1353         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1354         ctrl |= IXGBE_DMATXCTL_GDV;
1355         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1356
1357         /* CTRL_EXT: Global Double VLAN Enable */
1358         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1359         ctrl |= IXGBE_EXTENDED_VLAN;
1360         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1361
1362         /*
1363          * VET EXT field in the EXVET register = 0x8100 by default
1364          * So no need to change. Same to VT field of DMATXCTL register
1365          */
1366 }
1367
1368 static void
1369 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1370 {
1371         if(mask & ETH_VLAN_STRIP_MASK){
1372                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1373                         ixgbe_vlan_hw_strip_enable_all(dev);
1374                 else
1375                         ixgbe_vlan_hw_strip_disable_all(dev);
1376         }
1377
1378         if(mask & ETH_VLAN_FILTER_MASK){
1379                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1380                         ixgbe_vlan_hw_filter_enable(dev);
1381                 else
1382                         ixgbe_vlan_hw_filter_disable(dev);
1383         }
1384
1385         if(mask & ETH_VLAN_EXTEND_MASK){
1386                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1387                         ixgbe_vlan_hw_extend_enable(dev);
1388                 else
1389                         ixgbe_vlan_hw_extend_disable(dev);
1390         }
1391 }
1392
1393 static void
1394 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1395 {
1396         struct ixgbe_hw *hw =
1397                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1398         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1399         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1400         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1401         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1402 }
1403
1404 static int
1405 ixgbe_dev_configure(struct rte_eth_dev *dev)
1406 {
1407         struct ixgbe_interrupt *intr =
1408                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1409
1410         PMD_INIT_FUNC_TRACE();
1411
1412         /* set flag to update link status after init */
1413         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1414
1415         return 0;
1416 }
1417
1418 /*
1419  * Configure device link speed and setup link.
1420  * It returns 0 on success.
1421  */
1422 static int
1423 ixgbe_dev_start(struct rte_eth_dev *dev)
1424 {
1425         struct ixgbe_hw *hw =
1426                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1427         struct ixgbe_vf_info *vfinfo =
1428                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1429         int err, link_up = 0, negotiate = 0;
1430         uint32_t speed = 0;
1431         int mask = 0;
1432         int status;
1433         uint16_t vf, idx;
1434
1435         PMD_INIT_FUNC_TRACE();
1436
1437         /* IXGBE devices don't support half duplex */
1438         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1439                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1440                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1441                              dev->data->dev_conf.link_duplex,
1442                              dev->data->port_id);
1443                 return -EINVAL;
1444         }
1445
1446         /* stop adapter */
1447         hw->adapter_stopped = FALSE;
1448         ixgbe_stop_adapter(hw);
1449
1450         /* reinitialize adapter
1451          * this calls reset and start */
1452         status = ixgbe_pf_reset_hw(hw);
1453         if (status != 0)
1454                 return -1;
1455         hw->mac.ops.start_hw(hw);
1456
1457         /* configure PF module if SRIOV enabled */
1458         ixgbe_pf_host_configure(dev);
1459
1460         /* initialize transmission unit */
1461         ixgbe_dev_tx_init(dev);
1462
1463         /* This can fail when allocating mbufs for descriptor rings */
1464         err = ixgbe_dev_rx_init(dev);
1465         if (err) {
1466                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1467                 goto error;
1468         }
1469
1470         ixgbe_dev_rxtx_start(dev);
1471
1472         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1473                 err = hw->mac.ops.setup_sfp(hw);
1474                 if (err)
1475                         goto error;
1476         }
1477
1478         /* Turn on the laser */
1479         ixgbe_enable_tx_laser(hw);
1480
1481         /* Skip link setup if loopback mode is enabled for 82599. */
1482         if (hw->mac.type == ixgbe_mac_82599EB &&
1483                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1484                 goto skip_link_setup;
1485
1486         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1487         if (err)
1488                 goto error;
1489         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1490         if (err)
1491                 goto error;
1492
1493         switch(dev->data->dev_conf.link_speed) {
1494         case ETH_LINK_SPEED_AUTONEG:
1495                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1496                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1497                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1498                 break;
1499         case ETH_LINK_SPEED_100:
1500                 /*
1501                  * Invalid for 82598 but error will be detected by
1502                  * ixgbe_setup_link()
1503                  */
1504                 speed = IXGBE_LINK_SPEED_100_FULL;
1505                 break;
1506         case ETH_LINK_SPEED_1000:
1507                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1508                 break;
1509         case ETH_LINK_SPEED_10000:
1510                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1511                 break;
1512         default:
1513                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1514                              dev->data->dev_conf.link_speed,
1515                              dev->data->port_id);
1516                 goto error;
1517         }
1518
1519         err = ixgbe_setup_link(hw, speed, link_up);
1520         if (err)
1521                 goto error;
1522
1523 skip_link_setup:
1524
1525         /* check if lsc interrupt is enabled */
1526         if (dev->data->dev_conf.intr_conf.lsc != 0)
1527                 ixgbe_dev_lsc_interrupt_setup(dev);
1528
1529         /* resume enabled intr since hw reset */
1530         ixgbe_enable_intr(dev);
1531
1532         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1533                 ETH_VLAN_EXTEND_MASK;
1534         ixgbe_vlan_offload_set(dev, mask);
1535
1536         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1537                 /* Enable vlan filtering for VMDq */
1538                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1539         }
1540
1541         /* Configure DCB hw */
1542         ixgbe_configure_dcb(dev);
1543
1544         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1545                 err = ixgbe_fdir_configure(dev);
1546                 if (err)
1547                         goto error;
1548         }
1549
1550         /* Restore vf rate limit */
1551         if (vfinfo != NULL) {
1552                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1553                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1554                                 if (vfinfo[vf].tx_rate[idx] != 0)
1555                                         ixgbe_set_vf_rate_limit(dev, vf,
1556                                                 vfinfo[vf].tx_rate[idx],
1557                                                 1 << idx);
1558         }
1559
1560         ixgbe_restore_statistics_mapping(dev);
1561
1562         return (0);
1563
1564 error:
1565         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1566         ixgbe_dev_clear_queues(dev);
1567         return -EIO;
1568 }
1569
1570 /*
1571  * Stop device: disable rx and tx functions to allow for reconfiguring.
1572  */
1573 static void
1574 ixgbe_dev_stop(struct rte_eth_dev *dev)
1575 {
1576         struct rte_eth_link link;
1577         struct ixgbe_hw *hw =
1578                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1579         struct ixgbe_vf_info *vfinfo =
1580                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1581         int vf;
1582
1583         PMD_INIT_FUNC_TRACE();
1584
1585         /* disable interrupts */
1586         ixgbe_disable_intr(hw);
1587
1588         /* reset the NIC */
1589         ixgbe_pf_reset_hw(hw);
1590         hw->adapter_stopped = FALSE;
1591
1592         /* stop adapter */
1593         ixgbe_stop_adapter(hw);
1594
1595         for (vf = 0; vfinfo != NULL &&
1596                      vf < dev->pci_dev->max_vfs; vf++)
1597                 vfinfo[vf].clear_to_send = false;
1598
1599         /* Turn off the laser */
1600         ixgbe_disable_tx_laser(hw);
1601
1602         ixgbe_dev_clear_queues(dev);
1603
1604         /* Clear stored conf */
1605         dev->data->scattered_rx = 0;
1606
1607         /* Clear recorded link status */
1608         memset(&link, 0, sizeof(link));
1609         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1610 }
1611
1612 /*
1613  * Set device link up: enable tx laser.
1614  */
1615 static int
1616 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1617 {
1618         struct ixgbe_hw *hw =
1619                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1620         if (hw->mac.type == ixgbe_mac_82599EB) {
1621 #ifdef RTE_NIC_BYPASS
1622                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1623                         /* Not suported in bypass mode */
1624                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1625                                      "by device id 0x%x", hw->device_id);
1626                         return -ENOTSUP;
1627                 }
1628 #endif
1629                 /* Turn on the laser */
1630                 ixgbe_enable_tx_laser(hw);
1631                 return 0;
1632         }
1633
1634         PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1635                      hw->device_id);
1636         return -ENOTSUP;
1637 }
1638
1639 /*
1640  * Set device link down: disable tx laser.
1641  */
1642 static int
1643 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1644 {
1645         struct ixgbe_hw *hw =
1646                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1647         if (hw->mac.type == ixgbe_mac_82599EB) {
1648 #ifdef RTE_NIC_BYPASS
1649                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1650                         /* Not suported in bypass mode */
1651                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1652                                      "by device id 0x%x", hw->device_id);
1653                         return -ENOTSUP;
1654                 }
1655 #endif
1656                 /* Turn off the laser */
1657                 ixgbe_disable_tx_laser(hw);
1658                 return 0;
1659         }
1660
1661         PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1662                      hw->device_id);
1663         return -ENOTSUP;
1664 }
1665
1666 /*
1667  * Reest and stop device.
1668  */
1669 static void
1670 ixgbe_dev_close(struct rte_eth_dev *dev)
1671 {
1672         struct ixgbe_hw *hw =
1673                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1674
1675         PMD_INIT_FUNC_TRACE();
1676
1677         ixgbe_pf_reset_hw(hw);
1678
1679         ixgbe_dev_stop(dev);
1680         hw->adapter_stopped = 1;
1681
1682         ixgbe_disable_pcie_master(hw);
1683
1684         /* reprogram the RAR[0] in case user changed it. */
1685         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1686 }
1687
1688 /*
1689  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1690  */
1691 static void
1692 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1693 {
1694         struct ixgbe_hw *hw =
1695                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1696         struct ixgbe_hw_stats *hw_stats =
1697                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1698         uint32_t bprc, lxon, lxoff, total;
1699         uint64_t total_missed_rx, total_qbrc, total_qprc;
1700         unsigned i;
1701
1702         total_missed_rx = 0;
1703         total_qbrc = 0;
1704         total_qprc = 0;
1705
1706         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1707         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1708         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1709         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1710
1711         for (i = 0; i < 8; i++) {
1712                 uint32_t mp;
1713                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1714                 /* global total per queue */
1715                 hw_stats->mpc[i] += mp;
1716                 /* Running comprehensive total for stats display */
1717                 total_missed_rx += hw_stats->mpc[i];
1718                 if (hw->mac.type == ixgbe_mac_82598EB)
1719                         hw_stats->rnbc[i] +=
1720                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1721                 hw_stats->pxontxc[i] +=
1722                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1723                 hw_stats->pxonrxc[i] +=
1724                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1725                 hw_stats->pxofftxc[i] +=
1726                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1727                 hw_stats->pxoffrxc[i] +=
1728                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1729                 hw_stats->pxon2offc[i] +=
1730                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1731         }
1732         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1733                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1734                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1735                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1736                 hw_stats->qbrc[i] +=
1737                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1738                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1739                 hw_stats->qbtc[i] +=
1740                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1741                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1742
1743                 total_qprc += hw_stats->qprc[i];
1744                 total_qbrc += hw_stats->qbrc[i];
1745         }
1746         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1747         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1748         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1749
1750         /* Note that gprc counts missed packets */
1751         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1752
1753         if (hw->mac.type != ixgbe_mac_82598EB) {
1754                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1755                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1756                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1757                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1758                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1759                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1760                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1761                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1762         } else {
1763                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1764                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1765                 /* 82598 only has a counter in the high register */
1766                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1767                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1768                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1769         }
1770
1771         /*
1772          * Workaround: mprc hardware is incorrectly counting
1773          * broadcasts, so for now we subtract those.
1774          */
1775         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1776         hw_stats->bprc += bprc;
1777         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1778         if (hw->mac.type == ixgbe_mac_82598EB)
1779                 hw_stats->mprc -= bprc;
1780
1781         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1782         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1783         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1784         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1785         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1786         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1787
1788         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1789         hw_stats->lxontxc += lxon;
1790         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1791         hw_stats->lxofftxc += lxoff;
1792         total = lxon + lxoff;
1793
1794         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1795         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1796         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1797         hw_stats->gptc -= total;
1798         hw_stats->mptc -= total;
1799         hw_stats->ptc64 -= total;
1800         hw_stats->gotc -= total * ETHER_MIN_LEN;
1801
1802         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1803         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1804         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1805         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1806         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1807         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1808         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1809         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1810         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1811         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1812         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1813         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1814         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1815         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1816         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1817         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1818         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1819         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1820         /* Only read FCOE on 82599 */
1821         if (hw->mac.type != ixgbe_mac_82598EB) {
1822                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1823                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1824                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1825                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1826                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1827         }
1828
1829         if (stats == NULL)
1830                 return;
1831
1832         /* Fill out the rte_eth_stats statistics structure */
1833         stats->ipackets = total_qprc;
1834         stats->ibytes = total_qbrc;
1835         stats->opackets = hw_stats->gptc;
1836         stats->obytes = hw_stats->gotc;
1837         stats->imcasts = hw_stats->mprc;
1838
1839         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1840                 stats->q_ipackets[i] = hw_stats->qprc[i];
1841                 stats->q_opackets[i] = hw_stats->qptc[i];
1842                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1843                 stats->q_obytes[i] = hw_stats->qbtc[i];
1844                 stats->q_errors[i] = hw_stats->qprdc[i];
1845         }
1846
1847         /* Rx Errors */
1848         stats->ibadcrc  = hw_stats->crcerrs;
1849         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1850         stats->imissed  = total_missed_rx;
1851         stats->ierrors  = stats->ibadcrc +
1852                           stats->ibadlen +
1853                           stats->imissed +
1854                           hw_stats->illerrc + hw_stats->errbc;
1855
1856         /* Tx Errors */
1857         stats->oerrors  = 0;
1858
1859         /* XON/XOFF pause frames */
1860         stats->tx_pause_xon  = hw_stats->lxontxc;
1861         stats->rx_pause_xon  = hw_stats->lxonrxc;
1862         stats->tx_pause_xoff = hw_stats->lxofftxc;
1863         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1864
1865         /* Flow Director Stats registers */
1866         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1867         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1868         stats->fdirmatch = hw_stats->fdirmatch;
1869         stats->fdirmiss = hw_stats->fdirmiss;
1870 }
1871
1872 static void
1873 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1874 {
1875         struct ixgbe_hw_stats *stats =
1876                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1877
1878         /* HW registers are cleared on read */
1879         ixgbe_dev_stats_get(dev, NULL);
1880
1881         /* Reset software totals */
1882         memset(stats, 0, sizeof(*stats));
1883 }
1884
1885 static void
1886 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1887 {
1888         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1889         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1890                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1891
1892         /* Good Rx packet, include VF loopback */
1893         UPDATE_VF_STAT(IXGBE_VFGPRC,
1894             hw_stats->last_vfgprc, hw_stats->vfgprc);
1895
1896         /* Good Rx octets, include VF loopback */
1897         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1898             hw_stats->last_vfgorc, hw_stats->vfgorc);
1899
1900         /* Good Tx packet, include VF loopback */
1901         UPDATE_VF_STAT(IXGBE_VFGPTC,
1902             hw_stats->last_vfgptc, hw_stats->vfgptc);
1903
1904         /* Good Tx octets, include VF loopback */
1905         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1906             hw_stats->last_vfgotc, hw_stats->vfgotc);
1907
1908         /* Rx Multicst Packet */
1909         UPDATE_VF_STAT(IXGBE_VFMPRC,
1910             hw_stats->last_vfmprc, hw_stats->vfmprc);
1911
1912         if (stats == NULL)
1913                 return;
1914
1915         memset(stats, 0, sizeof(*stats));
1916         stats->ipackets = hw_stats->vfgprc;
1917         stats->ibytes = hw_stats->vfgorc;
1918         stats->opackets = hw_stats->vfgptc;
1919         stats->obytes = hw_stats->vfgotc;
1920         stats->imcasts = hw_stats->vfmprc;
1921 }
1922
1923 static void
1924 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1925 {
1926         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1927                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1928
1929         /* Sync HW register to the last stats */
1930         ixgbevf_dev_stats_get(dev, NULL);
1931
1932         /* reset HW current stats*/
1933         hw_stats->vfgprc = 0;
1934         hw_stats->vfgorc = 0;
1935         hw_stats->vfgptc = 0;
1936         hw_stats->vfgotc = 0;
1937         hw_stats->vfmprc = 0;
1938
1939 }
1940
1941 static void
1942 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1943 {
1944         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1945
1946         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1947         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1948         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1949         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1950         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1951         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1952         dev_info->max_vfs = dev->pci_dev->max_vfs;
1953         if (hw->mac.type == ixgbe_mac_82598EB)
1954                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1955         else
1956                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1957         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
1958         dev_info->rx_offload_capa =
1959                 DEV_RX_OFFLOAD_VLAN_STRIP |
1960                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1961                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1962                 DEV_RX_OFFLOAD_TCP_CKSUM;
1963         dev_info->tx_offload_capa =
1964                 DEV_TX_OFFLOAD_VLAN_INSERT |
1965                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1966                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1967                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1968                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1969
1970         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1971                 .rx_thresh = {
1972                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
1973                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
1974                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
1975                 },
1976                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
1977                 .rx_drop_en = 0,
1978         };
1979
1980         dev_info->default_txconf = (struct rte_eth_txconf) {
1981                 .tx_thresh = {
1982                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
1983                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
1984                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
1985                 },
1986                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
1987                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
1988                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1989                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1990         };
1991         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1992 }
1993
1994 static void
1995 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
1996                      struct rte_eth_dev_info *dev_info)
1997 {
1998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1999
2000         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2001         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2002         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2003         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2004         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2005         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2006         dev_info->max_vfs = dev->pci_dev->max_vfs;
2007         if (hw->mac.type == ixgbe_mac_82598EB)
2008                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2009         else
2010                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2011         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2012                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2013                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2014                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2015         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2016                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2017                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2018                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2019                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2020
2021         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2022                 .rx_thresh = {
2023                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2024                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2025                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2026                 },
2027                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2028                 .rx_drop_en = 0,
2029         };
2030
2031         dev_info->default_txconf = (struct rte_eth_txconf) {
2032                 .tx_thresh = {
2033                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2034                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2035                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2036                 },
2037                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2038                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2039                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2040                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2041         };
2042 }
2043
2044 /* return 0 means link status changed, -1 means not changed */
2045 static int
2046 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2047 {
2048         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2049         struct rte_eth_link link, old;
2050         ixgbe_link_speed link_speed;
2051         int link_up;
2052         int diag;
2053
2054         link.link_status = 0;
2055         link.link_speed = 0;
2056         link.link_duplex = 0;
2057         memset(&old, 0, sizeof(old));
2058         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2059
2060         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2061         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2062                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2063         else
2064                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2065         if (diag != 0) {
2066                 link.link_speed = ETH_LINK_SPEED_100;
2067                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2068                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2069                 if (link.link_status == old.link_status)
2070                         return -1;
2071                 return 0;
2072         }
2073
2074         if (link_up == 0) {
2075                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2076                 if (link.link_status == old.link_status)
2077                         return -1;
2078                 return 0;
2079         }
2080         link.link_status = 1;
2081         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2082
2083         switch (link_speed) {
2084         default:
2085         case IXGBE_LINK_SPEED_UNKNOWN:
2086                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2087                 link.link_speed = ETH_LINK_SPEED_100;
2088                 break;
2089
2090         case IXGBE_LINK_SPEED_100_FULL:
2091                 link.link_speed = ETH_LINK_SPEED_100;
2092                 break;
2093
2094         case IXGBE_LINK_SPEED_1GB_FULL:
2095                 link.link_speed = ETH_LINK_SPEED_1000;
2096                 break;
2097
2098         case IXGBE_LINK_SPEED_10GB_FULL:
2099                 link.link_speed = ETH_LINK_SPEED_10000;
2100                 break;
2101         }
2102         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2103
2104         if (link.link_status == old.link_status)
2105                 return -1;
2106
2107         return 0;
2108 }
2109
2110 static void
2111 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2112 {
2113         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2114         uint32_t fctrl;
2115
2116         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2117         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2118         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2119 }
2120
2121 static void
2122 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2123 {
2124         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125         uint32_t fctrl;
2126
2127         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2128         fctrl &= (~IXGBE_FCTRL_UPE);
2129         if (dev->data->all_multicast == 1)
2130                 fctrl |= IXGBE_FCTRL_MPE;
2131         else
2132                 fctrl &= (~IXGBE_FCTRL_MPE);
2133         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2134 }
2135
2136 static void
2137 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2138 {
2139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2140         uint32_t fctrl;
2141
2142         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2143         fctrl |= IXGBE_FCTRL_MPE;
2144         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2145 }
2146
2147 static void
2148 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2149 {
2150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2151         uint32_t fctrl;
2152
2153         if (dev->data->promiscuous == 1)
2154                 return; /* must remain in all_multicast mode */
2155
2156         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2157         fctrl &= (~IXGBE_FCTRL_MPE);
2158         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2159 }
2160
2161 /**
2162  * It clears the interrupt causes and enables the interrupt.
2163  * It will be called once only during nic initialized.
2164  *
2165  * @param dev
2166  *  Pointer to struct rte_eth_dev.
2167  *
2168  * @return
2169  *  - On success, zero.
2170  *  - On failure, a negative value.
2171  */
2172 static int
2173 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2174 {
2175         struct ixgbe_interrupt *intr =
2176                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2177
2178         ixgbe_dev_link_status_print(dev);
2179         intr->mask |= IXGBE_EICR_LSC;
2180
2181         return 0;
2182 }
2183
2184 /*
2185  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2186  *
2187  * @param dev
2188  *  Pointer to struct rte_eth_dev.
2189  *
2190  * @return
2191  *  - On success, zero.
2192  *  - On failure, a negative value.
2193  */
2194 static int
2195 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2196 {
2197         uint32_t eicr;
2198         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2199         struct ixgbe_interrupt *intr =
2200                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2201
2202         /* clear all cause mask */
2203         ixgbe_disable_intr(hw);
2204
2205         /* read-on-clear nic registers here */
2206         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2207         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2208
2209         intr->flags = 0;
2210         if (eicr & IXGBE_EICR_LSC) {
2211                 /* set flag for async link update */
2212                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2213         }
2214
2215         if (eicr & IXGBE_EICR_MAILBOX)
2216                 intr->flags |= IXGBE_FLAG_MAILBOX;
2217
2218         return 0;
2219 }
2220
2221 /**
2222  * It gets and then prints the link status.
2223  *
2224  * @param dev
2225  *  Pointer to struct rte_eth_dev.
2226  *
2227  * @return
2228  *  - On success, zero.
2229  *  - On failure, a negative value.
2230  */
2231 static void
2232 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2233 {
2234         struct rte_eth_link link;
2235
2236         memset(&link, 0, sizeof(link));
2237         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2238         if (link.link_status) {
2239                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2240                                         (int)(dev->data->port_id),
2241                                         (unsigned)link.link_speed,
2242                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2243                                         "full-duplex" : "half-duplex");
2244         } else {
2245                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2246                                 (int)(dev->data->port_id));
2247         }
2248         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2249                                 dev->pci_dev->addr.domain,
2250                                 dev->pci_dev->addr.bus,
2251                                 dev->pci_dev->addr.devid,
2252                                 dev->pci_dev->addr.function);
2253 }
2254
2255 /*
2256  * It executes link_update after knowing an interrupt occurred.
2257  *
2258  * @param dev
2259  *  Pointer to struct rte_eth_dev.
2260  *
2261  * @return
2262  *  - On success, zero.
2263  *  - On failure, a negative value.
2264  */
2265 static int
2266 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2267 {
2268         struct ixgbe_interrupt *intr =
2269                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2270         int64_t timeout;
2271         struct rte_eth_link link;
2272         int intr_enable_delay = false;
2273
2274         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2275
2276         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2277                 ixgbe_pf_mbx_process(dev);
2278                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2279         }
2280
2281         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2282                 /* get the link status before link update, for predicting later */
2283                 memset(&link, 0, sizeof(link));
2284                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2285
2286                 ixgbe_dev_link_update(dev, 0);
2287
2288                 /* likely to up */
2289                 if (!link.link_status)
2290                         /* handle it 1 sec later, wait it being stable */
2291                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2292                 /* likely to down */
2293                 else
2294                         /* handle it 4 sec later, wait it being stable */
2295                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2296
2297                 ixgbe_dev_link_status_print(dev);
2298
2299                 intr_enable_delay = true;
2300         }
2301
2302         if (intr_enable_delay) {
2303                 if (rte_eal_alarm_set(timeout * 1000,
2304                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2305                         PMD_DRV_LOG(ERR, "Error setting alarm");
2306         } else {
2307                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2308                 ixgbe_enable_intr(dev);
2309                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2310         }
2311
2312
2313         return 0;
2314 }
2315
2316 /**
2317  * Interrupt handler which shall be registered for alarm callback for delayed
2318  * handling specific interrupt to wait for the stable nic state. As the
2319  * NIC interrupt state is not stable for ixgbe after link is just down,
2320  * it needs to wait 4 seconds to get the stable status.
2321  *
2322  * @param handle
2323  *  Pointer to interrupt handle.
2324  * @param param
2325  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2326  *
2327  * @return
2328  *  void
2329  */
2330 static void
2331 ixgbe_dev_interrupt_delayed_handler(void *param)
2332 {
2333         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2334         struct ixgbe_interrupt *intr =
2335                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2336         struct ixgbe_hw *hw =
2337                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2338         uint32_t eicr;
2339
2340         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2341         if (eicr & IXGBE_EICR_MAILBOX)
2342                 ixgbe_pf_mbx_process(dev);
2343
2344         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2345                 ixgbe_dev_link_update(dev, 0);
2346                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2347                 ixgbe_dev_link_status_print(dev);
2348                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2349         }
2350
2351         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2352         ixgbe_enable_intr(dev);
2353         rte_intr_enable(&(dev->pci_dev->intr_handle));
2354 }
2355
2356 /**
2357  * Interrupt handler triggered by NIC  for handling
2358  * specific interrupt.
2359  *
2360  * @param handle
2361  *  Pointer to interrupt handle.
2362  * @param param
2363  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2364  *
2365  * @return
2366  *  void
2367  */
2368 static void
2369 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2370                                                         void *param)
2371 {
2372         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2373         ixgbe_dev_interrupt_get_status(dev);
2374         ixgbe_dev_interrupt_action(dev);
2375 }
2376
2377 static int
2378 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2379 {
2380         struct ixgbe_hw *hw;
2381
2382         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2383         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2384 }
2385
2386 static int
2387 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2388 {
2389         struct ixgbe_hw *hw;
2390
2391         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2392         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2393 }
2394
2395 static int
2396 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2397 {
2398         struct ixgbe_hw *hw;
2399         uint32_t mflcn_reg;
2400         uint32_t fccfg_reg;
2401         int rx_pause;
2402         int tx_pause;
2403
2404         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2405
2406         fc_conf->pause_time = hw->fc.pause_time;
2407         fc_conf->high_water = hw->fc.high_water[0];
2408         fc_conf->low_water = hw->fc.low_water[0];
2409         fc_conf->send_xon = hw->fc.send_xon;
2410         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2411
2412         /*
2413          * Return rx_pause status according to actual setting of
2414          * MFLCN register.
2415          */
2416         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2417         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2418                 rx_pause = 1;
2419         else
2420                 rx_pause = 0;
2421
2422         /*
2423          * Return tx_pause status according to actual setting of
2424          * FCCFG register.
2425          */
2426         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2427         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2428                 tx_pause = 1;
2429         else
2430                 tx_pause = 0;
2431
2432         if (rx_pause && tx_pause)
2433                 fc_conf->mode = RTE_FC_FULL;
2434         else if (rx_pause)
2435                 fc_conf->mode = RTE_FC_RX_PAUSE;
2436         else if (tx_pause)
2437                 fc_conf->mode = RTE_FC_TX_PAUSE;
2438         else
2439                 fc_conf->mode = RTE_FC_NONE;
2440
2441         return 0;
2442 }
2443
2444 static int
2445 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2446 {
2447         struct ixgbe_hw *hw;
2448         int err;
2449         uint32_t rx_buf_size;
2450         uint32_t max_high_water;
2451         uint32_t mflcn;
2452         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2453                 ixgbe_fc_none,
2454                 ixgbe_fc_rx_pause,
2455                 ixgbe_fc_tx_pause,
2456                 ixgbe_fc_full
2457         };
2458
2459         PMD_INIT_FUNC_TRACE();
2460
2461         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2462         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2463                 return -ENOTSUP;
2464         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2465         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2466
2467         /*
2468          * At least reserve one Ethernet frame for watermark
2469          * high_water/low_water in kilo bytes for ixgbe
2470          */
2471         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2472         if ((fc_conf->high_water > max_high_water) ||
2473                 (fc_conf->high_water < fc_conf->low_water)) {
2474                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2475                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2476                 return (-EINVAL);
2477         }
2478
2479         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2480         hw->fc.pause_time     = fc_conf->pause_time;
2481         hw->fc.high_water[0]  = fc_conf->high_water;
2482         hw->fc.low_water[0]   = fc_conf->low_water;
2483         hw->fc.send_xon       = fc_conf->send_xon;
2484
2485         err = ixgbe_fc_enable(hw);
2486
2487         /* Not negotiated is not an error case */
2488         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2489
2490                 /* check if we want to forward MAC frames - driver doesn't have native
2491                  * capability to do that, so we'll write the registers ourselves */
2492
2493                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2494
2495                 /* set or clear MFLCN.PMCF bit depending on configuration */
2496                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2497                         mflcn |= IXGBE_MFLCN_PMCF;
2498                 else
2499                         mflcn &= ~IXGBE_MFLCN_PMCF;
2500
2501                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2502                 IXGBE_WRITE_FLUSH(hw);
2503
2504                 return 0;
2505         }
2506
2507         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2508         return -EIO;
2509 }
2510
2511 /**
2512  *  ixgbe_pfc_enable_generic - Enable flow control
2513  *  @hw: pointer to hardware structure
2514  *  @tc_num: traffic class number
2515  *  Enable flow control according to the current settings.
2516  */
2517 static int
2518 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2519 {
2520         int ret_val = 0;
2521         uint32_t mflcn_reg, fccfg_reg;
2522         uint32_t reg;
2523         uint32_t fcrtl, fcrth;
2524         uint8_t i;
2525         uint8_t nb_rx_en;
2526
2527         /* Validate the water mark configuration */
2528         if (!hw->fc.pause_time) {
2529                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2530                 goto out;
2531         }
2532
2533         /* Low water mark of zero causes XOFF floods */
2534         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2535                  /* High/Low water can not be 0 */
2536                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2537                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2538                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2539                         goto out;
2540                 }
2541
2542                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2543                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2544                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2545                         goto out;
2546                 }
2547         }
2548         /* Negotiate the fc mode to use */
2549         ixgbe_fc_autoneg(hw);
2550
2551         /* Disable any previous flow control settings */
2552         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2553         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2554
2555         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2556         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2557
2558         switch (hw->fc.current_mode) {
2559         case ixgbe_fc_none:
2560                 /*
2561                  * If the count of enabled RX Priority Flow control >1,
2562                  * and the TX pause can not be disabled
2563                  */
2564                 nb_rx_en = 0;
2565                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2566                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2567                         if (reg & IXGBE_FCRTH_FCEN)
2568                                 nb_rx_en++;
2569                 }
2570                 if (nb_rx_en > 1)
2571                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2572                 break;
2573         case ixgbe_fc_rx_pause:
2574                 /*
2575                  * Rx Flow control is enabled and Tx Flow control is
2576                  * disabled by software override. Since there really
2577                  * isn't a way to advertise that we are capable of RX
2578                  * Pause ONLY, we will advertise that we support both
2579                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2580                  * disable the adapter's ability to send PAUSE frames.
2581                  */
2582                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2583                 /*
2584                  * If the count of enabled RX Priority Flow control >1,
2585                  * and the TX pause can not be disabled
2586                  */
2587                 nb_rx_en = 0;
2588                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2589                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2590                         if (reg & IXGBE_FCRTH_FCEN)
2591                                 nb_rx_en++;
2592                 }
2593                 if (nb_rx_en > 1)
2594                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2595                 break;
2596         case ixgbe_fc_tx_pause:
2597                 /*
2598                  * Tx Flow control is enabled, and Rx Flow control is
2599                  * disabled by software override.
2600                  */
2601                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2602                 break;
2603         case ixgbe_fc_full:
2604                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2605                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2606                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2607                 break;
2608         default:
2609                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2610                 ret_val = IXGBE_ERR_CONFIG;
2611                 goto out;
2612                 break;
2613         }
2614
2615         /* Set 802.3x based flow control settings. */
2616         mflcn_reg |= IXGBE_MFLCN_DPF;
2617         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2618         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2619
2620         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2621         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2622                 hw->fc.high_water[tc_num]) {
2623                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2624                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2625                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2626         } else {
2627                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2628                 /*
2629                  * In order to prevent Tx hangs when the internal Tx
2630                  * switch is enabled we must set the high water mark
2631                  * to the maximum FCRTH value.  This allows the Tx
2632                  * switch to function even under heavy Rx workloads.
2633                  */
2634                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2635         }
2636         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2637
2638         /* Configure pause time (2 TCs per register) */
2639         reg = hw->fc.pause_time * 0x00010001;
2640         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2641                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2642
2643         /* Configure flow control refresh threshold value */
2644         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2645
2646 out:
2647         return ret_val;
2648 }
2649
2650 static int
2651 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2652 {
2653         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2654         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2655
2656         if(hw->mac.type != ixgbe_mac_82598EB) {
2657                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2658         }
2659         return ret_val;
2660 }
2661
2662 static int
2663 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2664 {
2665         int err;
2666         uint32_t rx_buf_size;
2667         uint32_t max_high_water;
2668         uint8_t tc_num;
2669         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2670         struct ixgbe_hw *hw =
2671                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2672         struct ixgbe_dcb_config *dcb_config =
2673                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2674
2675         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2676                 ixgbe_fc_none,
2677                 ixgbe_fc_rx_pause,
2678                 ixgbe_fc_tx_pause,
2679                 ixgbe_fc_full
2680         };
2681
2682         PMD_INIT_FUNC_TRACE();
2683
2684         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2685         tc_num = map[pfc_conf->priority];
2686         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2687         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2688         /*
2689          * At least reserve one Ethernet frame for watermark
2690          * high_water/low_water in kilo bytes for ixgbe
2691          */
2692         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2693         if ((pfc_conf->fc.high_water > max_high_water) ||
2694             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2695                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2696                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2697                 return (-EINVAL);
2698         }
2699
2700         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2701         hw->fc.pause_time = pfc_conf->fc.pause_time;
2702         hw->fc.send_xon = pfc_conf->fc.send_xon;
2703         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2704         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2705
2706         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2707
2708         /* Not negotiated is not an error case */
2709         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2710                 return 0;
2711
2712         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2713         return -EIO;
2714 }
2715
2716 static int
2717 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2718                                 struct rte_eth_rss_reta *reta_conf)
2719 {
2720         uint8_t i,j,mask;
2721         uint32_t reta;
2722         struct ixgbe_hw *hw =
2723                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2724
2725         PMD_INIT_FUNC_TRACE();
2726         /*
2727         * Update Redirection Table RETA[n],n=0...31,The redirection table has
2728         * 128-entries in 32 registers
2729          */
2730         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2731                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2732                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2733                 else
2734                         mask = (uint8_t)((reta_conf->mask_hi >>
2735                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2736                 if (mask != 0) {
2737                         reta = 0;
2738                         if (mask != 0xF)
2739                                 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2740
2741                         for (j = 0; j < 4; j++) {
2742                                 if (mask & (0x1 << j)) {
2743                                         if (mask != 0xF)
2744                                                 reta &= ~(0xFF << 8 * j);
2745                                         reta |= reta_conf->reta[i + j] << 8*j;
2746                                 }
2747                         }
2748                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2749                 }
2750         }
2751
2752         return 0;
2753 }
2754
2755 static int
2756 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2757                                 struct rte_eth_rss_reta *reta_conf)
2758 {
2759         uint8_t i,j,mask;
2760         uint32_t reta;
2761         struct ixgbe_hw *hw =
2762                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2763
2764         PMD_INIT_FUNC_TRACE();
2765         /*
2766          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2767          * 128-entries in 32 registers
2768          */
2769         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2770                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2771                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2772                 else
2773                         mask = (uint8_t)((reta_conf->mask_hi >>
2774                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2775
2776                 if (mask != 0) {
2777                         reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2778                         for (j = 0; j < 4; j++) {
2779                                 if (mask & (0x1 << j))
2780                                         reta_conf->reta[i + j] =
2781                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2782                         }
2783                 }
2784         }
2785
2786         return 0;
2787 }
2788
2789 static void
2790 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2791                                 uint32_t index, uint32_t pool)
2792 {
2793         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2794         uint32_t enable_addr = 1;
2795
2796         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2797 }
2798
2799 static void
2800 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2801 {
2802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2803
2804         ixgbe_clear_rar(hw, index);
2805 }
2806
2807 static int
2808 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2809 {
2810         uint32_t hlreg0;
2811         uint32_t maxfrs;
2812         struct ixgbe_hw *hw;
2813         struct rte_eth_dev_info dev_info;
2814         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2815
2816         ixgbe_dev_info_get(dev, &dev_info);
2817
2818         /* check that mtu is within the allowed range */
2819         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2820                 return -EINVAL;
2821
2822         /* refuse mtu that requires the support of scattered packets when this
2823          * feature has not been enabled before. */
2824         if (!dev->data->scattered_rx &&
2825             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2826              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2827                 return -EINVAL;
2828
2829         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2830         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2831
2832         /* switch to jumbo mode if needed */
2833         if (frame_size > ETHER_MAX_LEN) {
2834                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2835                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2836         } else {
2837                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2838                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2839         }
2840         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2841
2842         /* update max frame size */
2843         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2844
2845         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2846         maxfrs &= 0x0000FFFF;
2847         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2848         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2849
2850         return 0;
2851 }
2852
2853 /*
2854  * Virtual Function operations
2855  */
2856 static void
2857 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2858 {
2859         PMD_INIT_FUNC_TRACE();
2860
2861         /* Clear interrupt mask to stop from interrupts being generated */
2862         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2863
2864         IXGBE_WRITE_FLUSH(hw);
2865 }
2866
2867 static int
2868 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2869 {
2870         struct rte_eth_conf* conf = &dev->data->dev_conf;
2871
2872         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2873                      dev->data->port_id);
2874
2875         /*
2876          * VF has no ability to enable/disable HW CRC
2877          * Keep the persistent behavior the same as Host PF
2878          */
2879 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2880         if (!conf->rxmode.hw_strip_crc) {
2881                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2882                 conf->rxmode.hw_strip_crc = 1;
2883         }
2884 #else
2885         if (conf->rxmode.hw_strip_crc) {
2886                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2887                 conf->rxmode.hw_strip_crc = 0;
2888         }
2889 #endif
2890
2891         return 0;
2892 }
2893
2894 static int
2895 ixgbevf_dev_start(struct rte_eth_dev *dev)
2896 {
2897         struct ixgbe_hw *hw =
2898                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2899         int err, mask = 0;
2900
2901         PMD_INIT_FUNC_TRACE();
2902
2903         hw->mac.ops.reset_hw(hw);
2904
2905         /* negotiate mailbox API version to use with the PF. */
2906         ixgbevf_negotiate_api(hw);
2907
2908         ixgbevf_dev_tx_init(dev);
2909
2910         /* This can fail when allocating mbufs for descriptor rings */
2911         err = ixgbevf_dev_rx_init(dev);
2912         if (err) {
2913                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2914                 ixgbe_dev_clear_queues(dev);
2915                 return err;
2916         }
2917
2918         /* Set vfta */
2919         ixgbevf_set_vfta_all(dev,1);
2920
2921         /* Set HW strip */
2922         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2923                 ETH_VLAN_EXTEND_MASK;
2924         ixgbevf_vlan_offload_set(dev, mask);
2925
2926         ixgbevf_dev_rxtx_start(dev);
2927
2928         return 0;
2929 }
2930
2931 static void
2932 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2933 {
2934         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2935
2936         PMD_INIT_FUNC_TRACE();
2937
2938         hw->adapter_stopped = TRUE;
2939         ixgbe_stop_adapter(hw);
2940
2941         /*
2942           * Clear what we set, but we still keep shadow_vfta to
2943           * restore after device starts
2944           */
2945         ixgbevf_set_vfta_all(dev,0);
2946
2947         /* Clear stored conf */
2948         dev->data->scattered_rx = 0;
2949
2950         ixgbe_dev_clear_queues(dev);
2951 }
2952
2953 static void
2954 ixgbevf_dev_close(struct rte_eth_dev *dev)
2955 {
2956         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2957
2958         PMD_INIT_FUNC_TRACE();
2959
2960         ixgbe_reset_hw(hw);
2961
2962         ixgbevf_dev_stop(dev);
2963
2964         /* reprogram the RAR[0] in case user changed it. */
2965         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2966 }
2967
2968 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2969 {
2970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971         struct ixgbe_vfta * shadow_vfta =
2972                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2973         int i = 0, j = 0, vfta = 0, mask = 1;
2974
2975         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2976                 vfta = shadow_vfta->vfta[i];
2977                 if(vfta){
2978                         mask = 1;
2979                         for (j = 0; j < 32; j++){
2980                                 if(vfta & mask)
2981                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2982                                 mask<<=1;
2983                         }
2984                 }
2985         }
2986
2987 }
2988
2989 static int
2990 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2991 {
2992         struct ixgbe_hw *hw =
2993                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2994         struct ixgbe_vfta * shadow_vfta =
2995                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2996         uint32_t vid_idx = 0;
2997         uint32_t vid_bit = 0;
2998         int ret = 0;
2999
3000         PMD_INIT_FUNC_TRACE();
3001
3002         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3003         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3004         if(ret){
3005                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3006                 return ret;
3007         }
3008         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3009         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3010
3011         /* Save what we set and retore it after device reset */
3012         if (on)
3013                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3014         else
3015                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3016
3017         return 0;
3018 }
3019
3020 static void
3021 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3022 {
3023         struct ixgbe_hw *hw =
3024                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3025         uint32_t ctrl;
3026
3027         PMD_INIT_FUNC_TRACE();
3028
3029         if(queue >= hw->mac.max_rx_queues)
3030                 return;
3031
3032         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3033         if(on)
3034                 ctrl |= IXGBE_RXDCTL_VME;
3035         else
3036                 ctrl &= ~IXGBE_RXDCTL_VME;
3037         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3038
3039         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3040 }
3041
3042 static void
3043 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3044 {
3045         struct ixgbe_hw *hw =
3046                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3047         uint16_t i;
3048         int on = 0;
3049
3050         /* VF function only support hw strip feature, others are not support */
3051         if(mask & ETH_VLAN_STRIP_MASK){
3052                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3053
3054                 for(i=0; i < hw->mac.max_rx_queues; i++)
3055                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3056         }
3057 }
3058
3059 static int
3060 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3061 {
3062         uint32_t reg_val;
3063
3064         /* we only need to do this if VMDq is enabled */
3065         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3066         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3067                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3068                 return (-1);
3069         }
3070
3071         return 0;
3072 }
3073
3074 static uint32_t
3075 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3076 {
3077         uint32_t vector = 0;
3078         switch (hw->mac.mc_filter_type) {
3079         case 0:   /* use bits [47:36] of the address */
3080                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3081                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3082                 break;
3083         case 1:   /* use bits [46:35] of the address */
3084                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3085                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3086                 break;
3087         case 2:   /* use bits [45:34] of the address */
3088                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3089                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3090                 break;
3091         case 3:   /* use bits [43:32] of the address */
3092                 vector = ((uc_addr->addr_bytes[4]) |
3093                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3094                 break;
3095         default:  /* Invalid mc_filter_type */
3096                 break;
3097         }
3098
3099         /* vector can only be 12-bits or boundary will be exceeded */
3100         vector &= 0xFFF;
3101         return vector;
3102 }
3103
3104 static int
3105 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3106                                uint8_t on)
3107 {
3108         uint32_t vector;
3109         uint32_t uta_idx;
3110         uint32_t reg_val;
3111         uint32_t uta_shift;
3112         uint32_t rc;
3113         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3114         const uint32_t ixgbe_uta_bit_shift = 5;
3115         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3116         const uint32_t bit1 = 0x1;
3117
3118         struct ixgbe_hw *hw =
3119                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3120         struct ixgbe_uta_info *uta_info =
3121                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3122
3123         /* The UTA table only exists on 82599 hardware and newer */
3124         if (hw->mac.type < ixgbe_mac_82599EB)
3125                 return (-ENOTSUP);
3126
3127         vector = ixgbe_uta_vector(hw,mac_addr);
3128         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3129         uta_shift = vector & ixgbe_uta_bit_mask;
3130
3131         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3132         if(rc == on)
3133                 return 0;
3134
3135         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3136         if (on) {
3137                 uta_info->uta_in_use++;
3138                 reg_val |= (bit1 << uta_shift);
3139                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3140         } else {
3141                 uta_info->uta_in_use--;
3142                 reg_val &= ~(bit1 << uta_shift);
3143                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3144         }
3145
3146         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3147
3148         if (uta_info->uta_in_use > 0)
3149                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3150                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3151         else
3152                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3153
3154         return 0;
3155 }
3156
3157 static int
3158 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3159 {
3160         int i;
3161         struct ixgbe_hw *hw =
3162                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3163         struct ixgbe_uta_info *uta_info =
3164                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3165
3166         /* The UTA table only exists on 82599 hardware and newer */
3167         if (hw->mac.type < ixgbe_mac_82599EB)
3168                 return (-ENOTSUP);
3169
3170         if(on) {
3171                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3172                         uta_info->uta_shadow[i] = ~0;
3173                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3174                 }
3175         } else {
3176                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3177                         uta_info->uta_shadow[i] = 0;
3178                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3179                 }
3180         }
3181         return 0;
3182
3183 }
3184
3185 uint32_t
3186 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3187 {
3188         uint32_t new_val = orig_val;
3189
3190         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3191                 new_val |= IXGBE_VMOLR_AUPE;
3192         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3193                 new_val |= IXGBE_VMOLR_ROMPE;
3194         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3195                 new_val |= IXGBE_VMOLR_ROPE;
3196         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3197                 new_val |= IXGBE_VMOLR_BAM;
3198         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3199                 new_val |= IXGBE_VMOLR_MPE;
3200
3201         return new_val;
3202 }
3203
3204 static int
3205 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3206                                uint16_t rx_mask, uint8_t on)
3207 {
3208         int val = 0;
3209
3210         struct ixgbe_hw *hw =
3211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3212         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3213
3214         if (hw->mac.type == ixgbe_mac_82598EB) {
3215                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3216                              " on 82599 hardware and newer");
3217                 return (-ENOTSUP);
3218         }
3219         if (ixgbe_vmdq_mode_check(hw) < 0)
3220                 return (-ENOTSUP);
3221
3222         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3223
3224         if (on)
3225                 vmolr |= val;
3226         else
3227                 vmolr &= ~val;
3228
3229         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3230
3231         return 0;
3232 }
3233
3234 static int
3235 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3236 {
3237         uint32_t reg,addr;
3238         uint32_t val;
3239         const uint8_t bit1 = 0x1;
3240
3241         struct ixgbe_hw *hw =
3242                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3243
3244         if (ixgbe_vmdq_mode_check(hw) < 0)
3245                 return (-ENOTSUP);
3246
3247         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3248         reg = IXGBE_READ_REG(hw, addr);
3249         val = bit1 << pool;
3250
3251         if (on)
3252                 reg |= val;
3253         else
3254                 reg &= ~val;
3255
3256         IXGBE_WRITE_REG(hw, addr,reg);
3257
3258         return 0;
3259 }
3260
3261 static int
3262 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3263 {
3264         uint32_t reg,addr;
3265         uint32_t val;
3266         const uint8_t bit1 = 0x1;
3267
3268         struct ixgbe_hw *hw =
3269                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3270
3271         if (ixgbe_vmdq_mode_check(hw) < 0)
3272                 return (-ENOTSUP);
3273
3274         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3275         reg = IXGBE_READ_REG(hw, addr);
3276         val = bit1 << pool;
3277
3278         if (on)
3279                 reg |= val;
3280         else
3281                 reg &= ~val;
3282
3283         IXGBE_WRITE_REG(hw, addr,reg);
3284
3285         return 0;
3286 }
3287
3288 static int
3289 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3290                         uint64_t pool_mask, uint8_t vlan_on)
3291 {
3292         int ret = 0;
3293         uint16_t pool_idx;
3294         struct ixgbe_hw *hw =
3295                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3296
3297         if (ixgbe_vmdq_mode_check(hw) < 0)
3298                 return (-ENOTSUP);
3299         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3300                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3301                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3302                         if (ret < 0)
3303                                 return ret;
3304         }
3305
3306         return ret;
3307 }
3308
3309 static int
3310 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3311                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3312                         uint8_t rule_id, uint8_t on)
3313 {
3314         uint32_t mr_ctl,vlvf;
3315         uint32_t mp_lsb = 0;
3316         uint32_t mv_msb = 0;
3317         uint32_t mv_lsb = 0;
3318         uint32_t mp_msb = 0;
3319         uint8_t i = 0;
3320         int reg_index = 0;
3321         uint64_t vlan_mask = 0;
3322
3323         const uint8_t pool_mask_offset = 32;
3324         const uint8_t vlan_mask_offset = 32;
3325         const uint8_t dst_pool_offset = 8;
3326         const uint8_t rule_mr_offset  = 4;
3327         const uint8_t mirror_rule_mask= 0x0F;
3328
3329         struct ixgbe_mirror_info *mr_info =
3330                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3331         struct ixgbe_hw *hw =
3332                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3333
3334         if (ixgbe_vmdq_mode_check(hw) < 0)
3335                 return (-ENOTSUP);
3336
3337         /* Check if vlan mask is valid */
3338         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3339                 if (mirror_conf->vlan.vlan_mask == 0)
3340                         return (-EINVAL);
3341         }
3342
3343         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3344         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3345                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3346                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3347                                 /* search vlan id related pool vlan filter index */
3348                                 reg_index = ixgbe_find_vlvf_slot(hw,
3349                                                 mirror_conf->vlan.vlan_id[i]);
3350                                 if(reg_index < 0)
3351                                         return (-EINVAL);
3352                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3353                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3354                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3355                                                 == mirror_conf->vlan.vlan_id[i]))
3356                                         vlan_mask |= (1ULL << reg_index);
3357                                 else
3358                                         return (-EINVAL);
3359                         }
3360                 }
3361
3362                 if (on) {
3363                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3364                         mv_msb = vlan_mask >> vlan_mask_offset;
3365
3366                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3367                                                 mirror_conf->vlan.vlan_mask;
3368                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3369                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3370                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3371                                                 mirror_conf->vlan.vlan_id[i];
3372                         }
3373                 } else {
3374                         mv_lsb = 0;
3375                         mv_msb = 0;
3376                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3377                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3378                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3379                 }
3380         }
3381
3382         /*
3383          * if enable pool mirror, write related pool mask register,if disable
3384          * pool mirror, clear PFMRVM register
3385          */
3386         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3387                 if (on) {
3388                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3389                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3390                         mr_info->mr_conf[rule_id].pool_mask =
3391                                         mirror_conf->pool_mask;
3392
3393                 } else {
3394                         mp_lsb = 0;
3395                         mp_msb = 0;
3396                         mr_info->mr_conf[rule_id].pool_mask = 0;
3397                 }
3398         }
3399
3400         /* read  mirror control register and recalculate it */
3401         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3402
3403         if (on) {
3404                 mr_ctl |= mirror_conf->rule_type_mask;
3405                 mr_ctl &= mirror_rule_mask;
3406                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3407         } else
3408                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3409
3410         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3411         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3412
3413         /* write mirrror control  register */
3414         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3415
3416         /* write pool mirrror control  register */
3417         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3418                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3419                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3420                                 mp_msb);
3421         }
3422         /* write VLAN mirrror control  register */
3423         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3424                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3425                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3426                                 mv_msb);
3427         }
3428
3429         return 0;
3430 }
3431
3432 static int
3433 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3434 {
3435         int mr_ctl = 0;
3436         uint32_t lsb_val = 0;
3437         uint32_t msb_val = 0;
3438         const uint8_t rule_mr_offset = 4;
3439
3440         struct ixgbe_hw *hw =
3441                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3442         struct ixgbe_mirror_info *mr_info =
3443                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3444
3445         if (ixgbe_vmdq_mode_check(hw) < 0)
3446                 return (-ENOTSUP);
3447
3448         memset(&mr_info->mr_conf[rule_id], 0,
3449                 sizeof(struct rte_eth_vmdq_mirror_conf));
3450
3451         /* clear PFVMCTL register */
3452         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3453
3454         /* clear pool mask register */
3455         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3456         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3457
3458         /* clear vlan mask register */
3459         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3460         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3461
3462         return 0;
3463 }
3464
3465 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3466         uint16_t queue_idx, uint16_t tx_rate)
3467 {
3468         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3469         uint32_t rf_dec, rf_int;
3470         uint32_t bcnrc_val;
3471         uint16_t link_speed = dev->data->dev_link.link_speed;
3472
3473         if (queue_idx >= hw->mac.max_tx_queues)
3474                 return -EINVAL;
3475
3476         if (tx_rate != 0) {
3477                 /* Calculate the rate factor values to set */
3478                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3479                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3480                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3481
3482                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3483                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3484                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3485                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3486         } else {
3487                 bcnrc_val = 0;
3488         }
3489
3490         /*
3491          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3492          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3493          * set as 0x4.
3494          */
3495         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3496                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3497                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3498                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3499                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3500         else
3501                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3502                         IXGBE_MMW_SIZE_DEFAULT);
3503
3504         /* Set RTTBCNRC of queue X */
3505         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3506         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3507         IXGBE_WRITE_FLUSH(hw);
3508
3509         return 0;
3510 }
3511
3512 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3513         uint16_t tx_rate, uint64_t q_msk)
3514 {
3515         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3516         struct ixgbe_vf_info *vfinfo =
3517                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3518         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3519         uint32_t queue_stride =
3520                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3521         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3522         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3523         uint16_t total_rate = 0;
3524
3525         if (queue_end >= hw->mac.max_tx_queues)
3526                 return -EINVAL;
3527
3528         if (vfinfo != NULL) {
3529                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3530                         if (vf_idx == vf)
3531                                 continue;
3532                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3533                                 idx++)
3534                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3535                 }
3536         } else
3537                 return -EINVAL;
3538
3539         /* Store tx_rate for this vf. */
3540         for (idx = 0; idx < nb_q_per_pool; idx++) {
3541                 if (((uint64_t)0x1 << idx) & q_msk) {
3542                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3543                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3544                         total_rate += tx_rate;
3545                 }
3546         }
3547
3548         if (total_rate > dev->data->dev_link.link_speed) {
3549                 /*
3550                  * Reset stored TX rate of the VF if it causes exceed
3551                  * link speed.
3552                  */
3553                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3554                 return -EINVAL;
3555         }
3556
3557         /* Set RTTBCNRC of each queue/pool for vf X  */
3558         for (; queue_idx <= queue_end; queue_idx++) {
3559                 if (0x1 & q_msk)
3560                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3561                 q_msk = q_msk >> 1;
3562         }
3563
3564         return 0;
3565 }
3566
3567 static void
3568 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3569                      __attribute__((unused)) uint32_t index,
3570                      __attribute__((unused)) uint32_t pool)
3571 {
3572         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3573         int diag;
3574
3575         /*
3576          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3577          * operation. Trap this case to avoid exhausting the [very limited]
3578          * set of PF resources used to store VF MAC addresses.
3579          */
3580         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3581                 return;
3582         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3583         if (diag == 0)
3584                 return;
3585         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3586 }
3587
3588 static void
3589 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3590 {
3591         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3592         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3593         struct ether_addr *mac_addr;
3594         uint32_t i;
3595         int diag;
3596
3597         /*
3598          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3599          * not support the deletion of a given MAC address.
3600          * Instead, it imposes to delete all MAC addresses, then to add again
3601          * all MAC addresses with the exception of the one to be deleted.
3602          */
3603         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3604
3605         /*
3606          * Add again all MAC addresses, with the exception of the deleted one
3607          * and of the permanent MAC address.
3608          */
3609         for (i = 0, mac_addr = dev->data->mac_addrs;
3610              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3611                 /* Skip the deleted MAC address */
3612                 if (i == index)
3613                         continue;
3614                 /* Skip NULL MAC addresses */
3615                 if (is_zero_ether_addr(mac_addr))
3616                         continue;
3617                 /* Skip the permanent MAC address */
3618                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3619                         continue;
3620                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3621                 if (diag != 0)
3622                         PMD_DRV_LOG(ERR,
3623                                     "Adding again MAC address "
3624                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3625                                     "diag=%d",
3626                                     mac_addr->addr_bytes[0],
3627                                     mac_addr->addr_bytes[1],
3628                                     mac_addr->addr_bytes[2],
3629                                     mac_addr->addr_bytes[3],
3630                                     mac_addr->addr_bytes[4],
3631                                     mac_addr->addr_bytes[5],
3632                                     diag);
3633         }
3634 }
3635
3636 /*
3637  * add syn filter
3638  *
3639  * @param
3640  * dev: Pointer to struct rte_eth_dev.
3641  * filter: ponter to the filter that will be added.
3642  * rx_queue: the queue id the filter assigned to.
3643  *
3644  * @return
3645  *    - On success, zero.
3646  *    - On failure, a negative value.
3647  */
3648 static int
3649 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3650                         struct rte_syn_filter *filter, uint16_t rx_queue)
3651 {
3652         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3653         uint32_t synqf;
3654
3655         if (hw->mac.type != ixgbe_mac_82599EB)
3656                 return -ENOSYS;
3657
3658         if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3659                 return -EINVAL;
3660
3661         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3662
3663         if (synqf & IXGBE_SYN_FILTER_ENABLE)
3664                 return -EINVAL;
3665
3666         synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3667                 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3668
3669         if (filter->hig_pri)
3670                 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3671         else
3672                 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3673
3674         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3675         return 0;
3676 }
3677
3678 /*
3679  * remove syn filter
3680  *
3681  * @param
3682  * dev: Pointer to struct rte_eth_dev.
3683  *
3684  * @return
3685  *    - On success, zero.
3686  *    - On failure, a negative value.
3687  */
3688 static int
3689 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3690 {
3691         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3692         uint32_t synqf;
3693
3694         if (hw->mac.type != ixgbe_mac_82599EB)
3695                 return -ENOSYS;
3696
3697         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3698
3699         synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3700
3701         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3702         return 0;
3703 }
3704
3705 /*
3706  * get the syn filter's info
3707  *
3708  * @param
3709  * dev: Pointer to struct rte_eth_dev.
3710  * filter: ponter to the filter that returns.
3711  * *rx_queue: pointer to the queue id the filter assigned to.
3712  *
3713  * @return
3714  *    - On success, zero.
3715  *    - On failure, a negative value.
3716  */
3717 static int
3718 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3719                         struct rte_syn_filter *filter, uint16_t *rx_queue)
3720
3721 {
3722         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3723         uint32_t synqf;
3724
3725         if (hw->mac.type != ixgbe_mac_82599EB)
3726                 return -ENOSYS;
3727
3728         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3729         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3730                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3731                 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3732                 return 0;
3733         }
3734         return -ENOENT;
3735 }
3736
3737 /*
3738  * add an ethertype filter
3739  *
3740  * @param
3741  * dev: Pointer to struct rte_eth_dev.
3742  * index: the index the filter allocates.
3743  * filter: ponter to the filter that will be added.
3744  * rx_queue: the queue id the filter assigned to.
3745  *
3746  * @return
3747  *    - On success, zero.
3748  *    - On failure, a negative value.
3749  */
3750 static int
3751 ixgbe_add_ethertype_filter(struct rte_eth_dev *dev,
3752                         uint16_t index, struct rte_ethertype_filter *filter,
3753                         uint16_t rx_queue)
3754 {
3755         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3756         uint32_t etqf, etqs = 0;
3757
3758         if (hw->mac.type != ixgbe_mac_82599EB)
3759                 return -ENOSYS;
3760
3761         if (index >= IXGBE_MAX_ETQF_FILTERS ||
3762                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3763                 return -EINVAL;
3764
3765         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3766         if (etqf & IXGBE_ETQF_FILTER_EN)
3767                 return -EINVAL;  /* filter index is in use. */
3768
3769         etqf = 0;
3770         etqf |= IXGBE_ETQF_FILTER_EN;
3771         etqf |= (uint32_t)filter->ethertype;
3772
3773         if (filter->priority_en) {
3774                 if (filter->priority > IXGBE_ETQF_MAX_PRI)
3775                         return -EINVAL;
3776                 etqf |= (uint32_t)((filter->priority << IXGBE_ETQF_SHIFT) & IXGBE_ETQF_UP);
3777                 etqf |= IXGBE_ETQF_UP_EN;
3778         }
3779         etqs |= (uint32_t)((rx_queue << IXGBE_ETQS_RX_QUEUE_SHIFT) & IXGBE_ETQS_RX_QUEUE);
3780         etqs |= IXGBE_ETQS_QUEUE_EN;
3781
3782         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), etqf);
3783         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), etqs);
3784         return 0;
3785 }
3786
3787 /*
3788  * remove an ethertype filter
3789  *
3790  * @param
3791  * dev: Pointer to struct rte_eth_dev.
3792  * index: the index the filter allocates.
3793  *
3794  * @return
3795  *    - On success, zero.
3796  *    - On failure, a negative value.
3797  */
3798 static int
3799 ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
3800                         uint16_t index)
3801 {
3802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3803
3804         if (hw->mac.type != ixgbe_mac_82599EB)
3805                 return -ENOSYS;
3806
3807         if (index >= IXGBE_MAX_ETQF_FILTERS)
3808                 return -EINVAL;
3809
3810         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), 0);
3811         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), 0);
3812
3813         return 0;
3814 }
3815
3816 /*
3817  * get an ethertype filter
3818  *
3819  * @param
3820  * dev: Pointer to struct rte_eth_dev.
3821  * index: the index the filter allocates.
3822  * filter: ponter to the filter that will be gotten.
3823  * *rx_queue: the ponited of the queue id the filter assigned to.
3824  *
3825  * @return
3826  *    - On success, zero.
3827  *    - On failure, a negative value.
3828  */
3829 static int
3830 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
3831                         uint16_t index, struct rte_ethertype_filter *filter,
3832                         uint16_t *rx_queue)
3833 {
3834         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3835         uint32_t etqf, etqs;
3836
3837         if (hw->mac.type != ixgbe_mac_82599EB)
3838                 return -ENOSYS;
3839
3840         if (index >= IXGBE_MAX_ETQF_FILTERS)
3841                 return -EINVAL;
3842
3843         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3844         etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(index));
3845         if (etqf & IXGBE_ETQF_FILTER_EN) {
3846                 filter->ethertype = etqf & IXGBE_ETQF_ETHERTYPE;
3847                 filter->priority_en = (etqf & IXGBE_ETQF_UP_EN) ? 1 : 0;
3848                 if (filter->priority_en)
3849                         filter->priority = (etqf & IXGBE_ETQF_UP) >> 16;
3850                 *rx_queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> IXGBE_ETQS_RX_QUEUE_SHIFT;
3851                 return 0;
3852         }
3853         return -ENOENT;
3854 }
3855
3856 static inline enum ixgbe_5tuple_protocol
3857 convert_protocol_type(uint8_t protocol_value)
3858 {
3859         if (protocol_value == IPPROTO_TCP)
3860                 return IXGBE_FILTER_PROTOCOL_TCP;
3861         else if (protocol_value == IPPROTO_UDP)
3862                 return IXGBE_FILTER_PROTOCOL_UDP;
3863         else if (protocol_value == IPPROTO_SCTP)
3864                 return IXGBE_FILTER_PROTOCOL_SCTP;
3865         else
3866                 return IXGBE_FILTER_PROTOCOL_NONE;
3867 }
3868
3869 static inline uint8_t
3870 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3871 {
3872         if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3873                 return IPPROTO_TCP;
3874         else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3875                 return IPPROTO_UDP;
3876         else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3877                 return IPPROTO_SCTP;
3878         else
3879                 return 0;
3880 }
3881
3882 /*
3883  * add a 5tuple filter
3884  *
3885  * @param
3886  * dev: Pointer to struct rte_eth_dev.
3887  * index: the index the filter allocates.
3888  * filter: ponter to the filter that will be added.
3889  * rx_queue: the queue id the filter assigned to.
3890  *
3891  * @return
3892  *    - On success, zero.
3893  *    - On failure, a negative value.
3894  */
3895 static int
3896 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3897                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
3898 {
3899         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3900         uint32_t ftqf, sdpqf = 0;
3901         uint32_t l34timir = 0;
3902         uint8_t mask = 0xff;
3903
3904         if (hw->mac.type != ixgbe_mac_82599EB)
3905                 return -ENOSYS;
3906
3907         if (index >= IXGBE_MAX_FTQF_FILTERS ||
3908                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3909                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3910                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3911                 return -EINVAL;  /* filter index is out of range. */
3912
3913         if (filter->tcp_flags) {
3914                 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3915                 return -EINVAL;
3916         }
3917
3918         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3919         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3920                 return -EINVAL;  /* filter index is in use. */
3921
3922         ftqf = 0;
3923         sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3924         sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3925
3926         ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3927                 IXGBE_FTQF_PROTOCOL_MASK);
3928         ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3929                 IXGBE_FTQF_PRIORITY_SHIFT);
3930         if (filter->src_ip_mask == 0) /* 0 means compare. */
3931                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3932         if (filter->dst_ip_mask == 0)
3933                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3934         if (filter->src_port_mask == 0)
3935                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3936         if (filter->dst_port_mask == 0)
3937                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3938         if (filter->protocol_mask == 0)
3939                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3940         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3941         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3942         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3943
3944         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3945         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3946         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3947         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3948
3949         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3950         l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3951         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3952         return 0;
3953 }
3954
3955 /*
3956  * remove a 5tuple filter
3957  *
3958  * @param
3959  * dev: Pointer to struct rte_eth_dev.
3960  * index: the index the filter allocates.
3961  *
3962  * @return
3963  *    - On success, zero.
3964  *    - On failure, a negative value.
3965  */
3966 static int
3967 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3968                         uint16_t index)
3969 {
3970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3971
3972         if (hw->mac.type != ixgbe_mac_82599EB)
3973                 return -ENOSYS;
3974
3975         if (index >= IXGBE_MAX_FTQF_FILTERS)
3976                 return -EINVAL;  /* filter index is out of range. */
3977
3978         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3979         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3980         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3981         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3982         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3983         return 0;
3984 }
3985
3986 /*
3987  * get a 5tuple filter
3988  *
3989  * @param
3990  * dev: Pointer to struct rte_eth_dev.
3991  * index: the index the filter allocates
3992  * filter: ponter to the filter that returns.
3993  * *rx_queue: pointer of the queue id the filter assigned to.
3994  *
3995  * @return
3996  *    - On success, zero.
3997  *    - On failure, a negative value.
3998  */
3999 static int
4000 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
4001                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
4002 {
4003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4004         uint32_t sdpqf, ftqf, l34timir;
4005         uint8_t mask;
4006         enum ixgbe_5tuple_protocol proto;
4007
4008         if (hw->mac.type != ixgbe_mac_82599EB)
4009                 return -ENOSYS;
4010
4011         if (index >= IXGBE_MAX_FTQF_FILTERS)
4012                 return -EINVAL;  /* filter index is out of range. */
4013
4014         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
4015         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
4016                 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
4017                 filter->protocol = revert_protocol_type(proto);
4018                 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
4019                                         IXGBE_FTQF_PRIORITY_MASK;
4020                 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
4021                                         IXGBE_FTQF_5TUPLE_MASK_MASK);
4022                 filter->src_ip_mask =
4023                         (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
4024                 filter->dst_ip_mask =
4025                         (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
4026                 filter->src_port_mask =
4027                         (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
4028                 filter->dst_port_mask =
4029                         (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
4030                 filter->protocol_mask =
4031                         (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
4032
4033                 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
4034                 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
4035                                         IXGBE_SDPQF_DSTPORT_SHIFT;
4036                 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
4037                 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
4038                 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
4039
4040                 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
4041                 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
4042                                         IXGBE_L34T_IMIR_QUEUE_SHIFT;
4043                 return 0;
4044         }
4045         return -ENOENT;
4046 }
4047
4048 static int
4049 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4050 {
4051         struct ixgbe_hw *hw;
4052         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4053
4054         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4055
4056         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4057                 return -EINVAL;
4058
4059         /* refuse mtu that requires the support of scattered packets when this
4060          * feature has not been enabled before. */
4061         if (!dev->data->scattered_rx &&
4062             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4063              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4064                 return -EINVAL;
4065
4066         /*
4067          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4068          * request of the version 2.0 of the mailbox API.
4069          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4070          * of the mailbox API.
4071          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4072          * prior to 3.11.33 which contains the following change:
4073          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4074          */
4075         ixgbevf_rlpml_set_vf(hw, max_frame);
4076
4077         /* update max frame size */
4078         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4079         return 0;
4080 }
4081
4082 static struct rte_driver rte_ixgbe_driver = {
4083         .type = PMD_PDEV,
4084         .init = rte_ixgbe_pmd_init,
4085 };
4086
4087 static struct rte_driver rte_ixgbevf_driver = {
4088         .type = PMD_PDEV,
4089         .init = rte_ixgbevf_pmd_init,
4090 };
4091
4092 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4093 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);