lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "ixgbe/ixgbe_api.h"
  66 #include "ixgbe/ixgbe_vf.h"
  67 #include "ixgbe/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 /*
  96  *  Default values for RX/TX configuration
  97  */
  98 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  99 #define IXGBE_DEFAULT_RX_PTHRESH      8
 100 #define IXGBE_DEFAULT_RX_HTHRESH      8
 101 #define IXGBE_DEFAULT_RX_WTHRESH      0
 102
 103 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 104 #define IXGBE_DEFAULT_TX_PTHRESH      32
 105 #define IXGBE_DEFAULT_TX_HTHRESH      0
 106 #define IXGBE_DEFAULT_TX_WTHRESH      0
 107 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 108
 109 /* Bit shift and mask */
 110 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 111 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 112 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 113 #define IXGBE_8_BIT_MASK   UINT8_MAX
 114
 115 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 116
 117 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 118
 119 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 120 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 121 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 122 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 123 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 124 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 125 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 126 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 127 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 128 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 129 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 130 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 131                                 int wait_to_complete);
 132 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 133                                 struct rte_eth_stats *stats);
 134 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 135 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 136                                              uint16_t queue_id,
 137                                              uint8_t stat_idx,
 138                                              uint8_t is_rx);
 139 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 140                                struct rte_eth_dev_info *dev_info);
 141 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 142                                  struct rte_eth_dev_info *dev_info);
 143 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 144
 145 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 146                 uint16_t vlan_id, int on);
 147 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 148 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 149                 uint16_t queue, bool on);
 150 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 151                 int on);
 152 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 153 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 154 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 155 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 156 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 157
 158 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 159 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 160 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 161                                struct rte_eth_fc_conf *fc_conf);
 162 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 163                                struct rte_eth_fc_conf *fc_conf);
 164 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 165                 struct rte_eth_pfc_conf *pfc_conf);
 166 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 167                         struct rte_eth_rss_reta_entry64 *reta_conf,
 168                         uint16_t reta_size);
 169 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 170                         struct rte_eth_rss_reta_entry64 *reta_conf,
 171                         uint16_t reta_size);
 172 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 173 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 174 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 177                 void *param);
 178 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 179 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 180                 uint32_t index, uint32_t pool);
 181 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 182 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 183
 184 /* For Virtual Function support */
 185 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 186 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 187 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 188 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 189 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 190 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 191 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 192                 struct rte_eth_stats *stats);
 193 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 194 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 195                 uint16_t vlan_id, int on);
 196 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 197                 uint16_t queue, int on);
 198 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 199 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 200
 201 /* For Eth VMDQ APIs support */
 202 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 203                 ether_addr* mac_addr,uint8_t on);
 204 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 205 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 206                 uint16_t rx_mask, uint8_t on);
 207 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 208 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 209 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 210                 uint64_t pool_mask,uint8_t vlan_on);
 211 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 212                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 213                 uint8_t rule_id, uint8_t on);
 214 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 215                 uint8_t rule_id);
 216
 217 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 218                 uint16_t queue_idx, uint16_t tx_rate);
 219 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 220                 uint16_t tx_rate, uint64_t q_msk);
 221
 222 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 223                                  struct ether_addr *mac_addr,
 224                                  uint32_t index, uint32_t pool);
 225 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 226 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 227                         struct rte_eth_syn_filter *filter,
 228                         bool add);
 229 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 230                         struct rte_eth_syn_filter *filter);
 231 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 232                         enum rte_filter_op filter_op,
 233                         void *arg);
 234 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 235                         struct ixgbe_5tuple_filter *filter);
 236 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 237                         struct ixgbe_5tuple_filter *filter);
 238 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 239                         struct rte_eth_ntuple_filter *filter,
 240                         bool add);
 241 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 242                                 enum rte_filter_op filter_op,
 243                                 void *arg);
 244 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 245                         struct rte_eth_ntuple_filter *filter);
 246 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 247                         struct rte_eth_ethertype_filter *filter,
 248                         bool add);
 249 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 250                                 enum rte_filter_op filter_op,
 251                                 void *arg);
 252 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 253                         struct rte_eth_ethertype_filter *filter);
 254 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 255                      enum rte_filter_type filter_type,
 256                      enum rte_filter_op filter_op,
 257                      void *arg);
 258 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 259
 260 /*
 261  * Define VF Stats MACRO for Non "cleared on read" register
 262  */
 263 #define UPDATE_VF_STAT(reg, last, cur)                          \
 264 {                                                               \
 265         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 266         cur += latest - last;                                   \
 267         last = latest;                                          \
 268 }
 269
 270 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 271 {                                                                \
 272         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 273         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 274         u64 latest = ((new_msb << 32) | new_lsb);                \
 275         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 276         last = latest;                                           \
 277 }
 278
 279 #define IXGBE_SET_HWSTRIP(h, q) do{\
 280                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 281                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 282                 (h)->bitmap[idx] |= 1 << bit;\
 283         }while(0)
 284
 285 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 286                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 287                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 288                 (h)->bitmap[idx] &= ~(1 << bit);\
 289         }while(0)
 290
 291 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 292                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 293                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 294                 (r) = (h)->bitmap[idx] >> bit & 1;\
 295         }while(0)
 296
 297 /*
 298  * The set of PCI devices this driver supports
 299  */
 300 static struct rte_pci_id pci_id_ixgbe_map[] = {
 301
 302 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 303 #include "rte_pci_dev_ids.h"
 304
 305 { .vendor_id = 0, /* sentinel */ },
 306 };
 307
 308
 309 /*
 310  * The set of PCI devices this driver supports (for 82599 VF)
 311  */
 312 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 313
 314 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 315 #include "rte_pci_dev_ids.h"
 316 { .vendor_id = 0, /* sentinel */ },
 317
 318 };
 319
 320 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 321         .dev_configure        = ixgbe_dev_configure,
 322         .dev_start            = ixgbe_dev_start,
 323         .dev_stop             = ixgbe_dev_stop,
 324         .dev_set_link_up    = ixgbe_dev_set_link_up,
 325         .dev_set_link_down  = ixgbe_dev_set_link_down,
 326         .dev_close            = ixgbe_dev_close,
 327         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 328         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 329         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 330         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 331         .link_update          = ixgbe_dev_link_update,
 332         .stats_get            = ixgbe_dev_stats_get,
 333         .stats_reset          = ixgbe_dev_stats_reset,
 334         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 335         .dev_infos_get        = ixgbe_dev_info_get,
 336         .mtu_set              = ixgbe_dev_mtu_set,
 337         .vlan_filter_set      = ixgbe_vlan_filter_set,
 338         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 339         .vlan_offload_set     = ixgbe_vlan_offload_set,
 340         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 341         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 342         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 343         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 344         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 345         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 346         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 347         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 348         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 349         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 350         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 351         .dev_led_on           = ixgbe_dev_led_on,
 352         .dev_led_off          = ixgbe_dev_led_off,
 353         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 354         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 355         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 356         .mac_addr_add         = ixgbe_add_rar,
 357         .mac_addr_remove      = ixgbe_remove_rar,
 358         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 359         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 360         .mirror_rule_set      = ixgbe_mirror_rule_set,
 361         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 362         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 363         .set_vf_rx            = ixgbe_set_pool_rx,
 364         .set_vf_tx            = ixgbe_set_pool_tx,
 365         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 366         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 367         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 368         .reta_update          = ixgbe_dev_rss_reta_update,
 369         .reta_query           = ixgbe_dev_rss_reta_query,
 370 #ifdef RTE_NIC_BYPASS
 371         .bypass_init          = ixgbe_bypass_init,
 372         .bypass_state_set     = ixgbe_bypass_state_store,
 373         .bypass_state_show    = ixgbe_bypass_state_show,
 374         .bypass_event_set     = ixgbe_bypass_event_store,
 375         .bypass_event_show    = ixgbe_bypass_event_show,
 376         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 377         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 378         .bypass_ver_show      = ixgbe_bypass_ver_show,
 379         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 380 #endif /* RTE_NIC_BYPASS */
 381         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 382         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 383         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 384 };
 385
 386 /*
 387  * dev_ops for virtual function, bare necessities for basic vf
 388  * operation have been implemented
 389  */
 390 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 391
 392         .dev_configure        = ixgbevf_dev_configure,
 393         .dev_start            = ixgbevf_dev_start,
 394         .dev_stop             = ixgbevf_dev_stop,
 395         .link_update          = ixgbe_dev_link_update,
 396         .stats_get            = ixgbevf_dev_stats_get,
 397         .stats_reset          = ixgbevf_dev_stats_reset,
 398         .dev_close            = ixgbevf_dev_close,
 399         .dev_infos_get        = ixgbevf_dev_info_get,
 400         .mtu_set              = ixgbevf_dev_set_mtu,
 401         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 402         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 403         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 404         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 405         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 406         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 407         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 408         .mac_addr_add         = ixgbevf_add_mac_addr,
 409         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 410 };
 411
 412 /**
 413  * Atomically reads the link status information from global
 414  * structure rte_eth_dev.
 415  *
 416  * @param dev
 417  *   - Pointer to the structure rte_eth_dev to read from.
 418  *   - Pointer to the buffer to be saved with the link status.
 419  *
 420  * @return
 421  *   - On success, zero.
 422  *   - On failure, negative value.
 423  */
 424 static inline int
 425 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 426                                 struct rte_eth_link *link)
 427 {
 428         struct rte_eth_link *dst = link;
 429         struct rte_eth_link *src = &(dev->data->dev_link);
 430
 431         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 432                                         *(uint64_t *)src) == 0)
 433                 return -1;
 434
 435         return 0;
 436 }
 437
 438 /**
 439  * Atomically writes the link status information into global
 440  * structure rte_eth_dev.
 441  *
 442  * @param dev
 443  *   - Pointer to the structure rte_eth_dev to read from.
 444  *   - Pointer to the buffer to be saved with the link status.
 445  *
 446  * @return
 447  *   - On success, zero.
 448  *   - On failure, negative value.
 449  */
 450 static inline int
 451 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 452                                 struct rte_eth_link *link)
 453 {
 454         struct rte_eth_link *dst = &(dev->data->dev_link);
 455         struct rte_eth_link *src = link;
 456
 457         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 458                                         *(uint64_t *)src) == 0)
 459                 return -1;
 460
 461         return 0;
 462 }
 463
 464 /*
 465  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 466  */
 467 static inline int
 468 ixgbe_is_sfp(struct ixgbe_hw *hw)
 469 {
 470         switch (hw->phy.type) {
 471         case ixgbe_phy_sfp_avago:
 472         case ixgbe_phy_sfp_ftl:
 473         case ixgbe_phy_sfp_intel:
 474         case ixgbe_phy_sfp_unknown:
 475         case ixgbe_phy_sfp_passive_tyco:
 476         case ixgbe_phy_sfp_passive_unknown:
 477                 return 1;
 478         default:
 479                 return 0;
 480         }
 481 }
 482
 483 static inline int32_t
 484 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 485 {
 486         uint32_t ctrl_ext;
 487         int32_t status;
 488
 489         status = ixgbe_reset_hw(hw);
 490
 491         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 492         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 493         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 494         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 495         IXGBE_WRITE_FLUSH(hw);
 496
 497         return status;
 498 }
 499
 500 static inline void
 501 ixgbe_enable_intr(struct rte_eth_dev *dev)
 502 {
 503         struct ixgbe_interrupt *intr =
 504                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 505         struct ixgbe_hw *hw =
 506                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 507
 508         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 509         IXGBE_WRITE_FLUSH(hw);
 510 }
 511
 512 /*
 513  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 514  */
 515 static void
 516 ixgbe_disable_intr(struct ixgbe_hw *hw)
 517 {
 518         PMD_INIT_FUNC_TRACE();
 519
 520         if (hw->mac.type == ixgbe_mac_82598EB) {
 521                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 522         } else {
 523                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 524                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 525                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 526         }
 527         IXGBE_WRITE_FLUSH(hw);
 528 }
 529
 530 /*
 531  * This function resets queue statistics mapping registers.
 532  * From Niantic datasheet, Initialization of Statistics section:
 533  * "...if software requires the queue counters, the RQSMR and TQSM registers
 534  * must be re-programmed following a device reset.
 535  */
 536 static void
 537 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 538 {
 539         uint32_t i;
 540
 541         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 542                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 543                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 544         }
 545 }
 546
 547
 548 static int
 549 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 550                                   uint16_t queue_id,
 551                                   uint8_t stat_idx,
 552                                   uint8_t is_rx)
 553 {
 554 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 555 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 556 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 557
 558         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 559         struct ixgbe_stat_mapping_registers *stat_mappings =
 560                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 561         uint32_t qsmr_mask = 0;
 562         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 563         uint32_t q_map;
 564         uint8_t n, offset;
 565
 566         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 567                 (hw->mac.type != ixgbe_mac_X540) &&
 568                 (hw->mac.type != ixgbe_mac_X550) &&
 569                 (hw->mac.type != ixgbe_mac_X550EM_x))
 570                 return -ENOSYS;
 571
 572         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 573                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 574                      queue_id, stat_idx);
 575
 576         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 577         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 578                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 579                 return -EIO;
 580         }
 581         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 582
 583         /* Now clear any previous stat_idx set */
 584         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 585         if (!is_rx)
 586                 stat_mappings->tqsm[n] &= ~clearing_mask;
 587         else
 588                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 589
 590         q_map = (uint32_t)stat_idx;
 591         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 592         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 593         if (!is_rx)
 594                 stat_mappings->tqsm[n] |= qsmr_mask;
 595         else
 596                 stat_mappings->rqsmr[n] |= qsmr_mask;
 597
 598         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 599                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 600                      queue_id, stat_idx);
 601         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 602                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 603
 604         /* Now write the mapping in the appropriate register */
 605         if (is_rx) {
 606                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 607                              stat_mappings->rqsmr[n], n);
 608                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 609         }
 610         else {
 611                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 612                              stat_mappings->tqsm[n], n);
 613                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 614         }
 615         return 0;
 616 }
 617
 618 static void
 619 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 620 {
 621         struct ixgbe_stat_mapping_registers *stat_mappings =
 622                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 623         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 624         int i;
 625
 626         /* write whatever was in stat mapping table to the NIC */
 627         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 628                 /* rx */
 629                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 630
 631                 /* tx */
 632                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 633         }
 634 }
 635
 636 static void
 637 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 638 {
 639         uint8_t i;
 640         struct ixgbe_dcb_tc_config *tc;
 641         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 642
 643         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 644         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 645         for (i = 0; i < dcb_max_tc; i++) {
 646                 tc = &dcb_config->tc_config[i];
 647                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 648                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 649                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 650                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 651                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 652                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 653                 tc->pfc = ixgbe_dcb_pfc_disabled;
 654         }
 655
 656         /* Initialize default user to priority mapping, UPx->TC0 */
 657         tc = &dcb_config->tc_config[0];
 658         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 659         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 660         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 661                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 662                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 663         }
 664         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 665         dcb_config->pfc_mode_enable = false;
 666         dcb_config->vt_mode = true;
 667         dcb_config->round_robin_enable = false;
 668         /* support all DCB capabilities in 82599 */
 669         dcb_config->support.capabilities = 0xFF;
 670
 671         /*we only support 4 Tcs for X540, X550 */
 672         if (hw->mac.type == ixgbe_mac_X540 ||
 673                 hw->mac.type == ixgbe_mac_X550 ||
 674                 hw->mac.type == ixgbe_mac_X550EM_x) {
 675                 dcb_config->num_tcs.pg_tcs = 4;
 676                 dcb_config->num_tcs.pfc_tcs = 4;
 677         }
 678 }
 679
 680 /*
 681  * Ensure that all locks are released before first NVM or PHY access
 682  */
 683 static void
 684 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 685 {
 686         uint16_t mask;
 687
 688         /*
 689          * Phy lock should not fail in this early stage. If this is the case,
 690          * it is due to an improper exit of the application.
 691          * So force the release of the faulty lock. Release of common lock
 692          * is done automatically by swfw_sync function.
 693          */
 694         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 695         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 696                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 697         }
 698         ixgbe_release_swfw_semaphore(hw, mask);
 699
 700         /*
 701          * These ones are more tricky since they are common to all ports; but
 702          * swfw_sync retries last long enough (1s) to be almost sure that if
 703          * lock can not be taken it is due to an improper lock of the
 704          * semaphore.
 705          */
 706         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 707         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 708                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 709         }
 710         ixgbe_release_swfw_semaphore(hw, mask);
 711 }
 712
 713 /*
 714  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 715  * It returns 0 on success.
 716  */
 717 static int
 718 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 719 {
 720         struct rte_pci_device *pci_dev;
 721         struct ixgbe_hw *hw =
 722                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 723         struct ixgbe_vfta * shadow_vfta =
 724                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 725         struct ixgbe_hwstrip *hwstrip =
 726                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 727         struct ixgbe_dcb_config *dcb_config =
 728                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 729         struct ixgbe_filter_info *filter_info =
 730                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 731         uint32_t ctrl_ext;
 732         uint16_t csum;
 733         int diag, i;
 734
 735         PMD_INIT_FUNC_TRACE();
 736
 737         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 738         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 739         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 740
 741         /*
 742          * For secondary processes, we don't initialise any further as primary
 743          * has already done this work. Only check we don't need a different
 744          * RX and TX function.
 745          */
 746         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 747                 struct ixgbe_tx_queue *txq;
 748                 /* TX queue function in primary, set by last queue initialized
 749                  * Tx queue may not initialized by primary process */
 750                 if (eth_dev->data->tx_queues) {
 751                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 752                         ixgbe_set_tx_function(eth_dev, txq);
 753                 } else {
 754                         /* Use default TX function if we get here */
 755                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 756                                            "Using default TX function.");
 757                 }
 758
 759                 ixgbe_set_rx_function(eth_dev);
 760
 761                 return 0;
 762         }
 763         pci_dev = eth_dev->pci_dev;
 764
 765         /* Vendor and Device ID need to be set before init of shared code */
 766         hw->device_id = pci_dev->id.device_id;
 767         hw->vendor_id = pci_dev->id.vendor_id;
 768         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 769         hw->allow_unsupported_sfp = 1;
 770
 771         /* Initialize the shared code (base driver) */
 772 #ifdef RTE_NIC_BYPASS
 773         diag = ixgbe_bypass_init_shared_code(hw);
 774 #else
 775         diag = ixgbe_init_shared_code(hw);
 776 #endif /* RTE_NIC_BYPASS */
 777
 778         if (diag != IXGBE_SUCCESS) {
 779                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 780                 return -EIO;
 781         }
 782
 783         /* pick up the PCI bus settings for reporting later */
 784         ixgbe_get_bus_info(hw);
 785
 786         /* Unlock any pending hardware semaphore */
 787         ixgbe_swfw_lock_reset(hw);
 788
 789         /* Initialize DCB configuration*/
 790         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 791         ixgbe_dcb_init(hw,dcb_config);
 792         /* Get Hardware Flow Control setting */
 793         hw->fc.requested_mode = ixgbe_fc_full;
 794         hw->fc.current_mode = ixgbe_fc_full;
 795         hw->fc.pause_time = IXGBE_FC_PAUSE;
 796         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 797                 hw->fc.low_water[i] = IXGBE_FC_LO;
 798                 hw->fc.high_water[i] = IXGBE_FC_HI;
 799         }
 800         hw->fc.send_xon = 1;
 801
 802         /* Make sure we have a good EEPROM before we read from it */
 803         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 804         if (diag != IXGBE_SUCCESS) {
 805                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 806                 return -EIO;
 807         }
 808
 809 #ifdef RTE_NIC_BYPASS
 810         diag = ixgbe_bypass_init_hw(hw);
 811 #else
 812         diag = ixgbe_init_hw(hw);
 813 #endif /* RTE_NIC_BYPASS */
 814
 815         /*
 816          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 817          * is called too soon after the kernel driver unbinding/binding occurs.
 818          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 819          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 820          * also called. See ixgbe_identify_phy_82599(). The reason for the
 821          * failure is not known, and only occuts when virtualisation features
 822          * are disabled in the bios. A delay of 100ms  was found to be enough by
 823          * trial-and-error, and is doubled to be safe.
 824          */
 825         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 826                 rte_delay_ms(200);
 827                 diag = ixgbe_init_hw(hw);
 828         }
 829
 830         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 831                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 832                     "LOM.  Please be aware there may be issues associated "
 833                     "with your hardware.");
 834                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 835                     "please contact your Intel or hardware representative "
 836                     "who provided you with this hardware.");
 837         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 838                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 839         if (diag) {
 840                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 841                 return -EIO;
 842         }
 843
 844         /* disable interrupt */
 845         ixgbe_disable_intr(hw);
 846
 847         /* reset mappings for queue statistics hw counters*/
 848         ixgbe_reset_qstat_mappings(hw);
 849
 850         /* Allocate memory for storing MAC addresses */
 851         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 852                         hw->mac.num_rar_entries, 0);
 853         if (eth_dev->data->mac_addrs == NULL) {
 854                 PMD_INIT_LOG(ERR,
 855                         "Failed to allocate %u bytes needed to store "
 856                         "MAC addresses",
 857                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 858                 return -ENOMEM;
 859         }
 860         /* Copy the permanent MAC address */
 861         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 862                         &eth_dev->data->mac_addrs[0]);
 863
 864         /* Allocate memory for storing hash filter MAC addresses */
 865         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 866                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 867         if (eth_dev->data->hash_mac_addrs == NULL) {
 868                 PMD_INIT_LOG(ERR,
 869                         "Failed to allocate %d bytes needed to store MAC addresses",
 870                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 871                 return -ENOMEM;
 872         }
 873
 874         /* initialize the vfta */
 875         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 876
 877         /* initialize the hw strip bitmap*/
 878         memset(hwstrip, 0, sizeof(*hwstrip));
 879
 880         /* initialize PF if max_vfs not zero */
 881         ixgbe_pf_host_init(eth_dev);
 882
 883         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 884         /* let hardware know driver is loaded */
 885         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 886         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 887         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 888         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 889         IXGBE_WRITE_FLUSH(hw);
 890
 891         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 892                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 893                              (int) hw->mac.type, (int) hw->phy.type,
 894                              (int) hw->phy.sfp_type);
 895         else
 896                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 897                              (int) hw->mac.type, (int) hw->phy.type);
 898
 899         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 900                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 901                         pci_dev->id.device_id);
 902
 903         rte_intr_callback_register(&(pci_dev->intr_handle),
 904                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 905
 906         /* enable uio intr after callback register */
 907         rte_intr_enable(&(pci_dev->intr_handle));
 908
 909         /* enable support intr */
 910         ixgbe_enable_intr(eth_dev);
 911
 912         /* initialize 5tuple filter list */
 913         TAILQ_INIT(&filter_info->fivetuple_list);
 914         memset(filter_info->fivetuple_mask, 0,
 915                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
 916
 917         return 0;
 918 }
 919
 920
 921 /*
 922  * Negotiate mailbox API version with the PF.
 923  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 924  * Then we try to negotiate starting with the most recent one.
 925  * If all negotiation attempts fail, then we will proceed with
 926  * the default one (ixgbe_mbox_api_10).
 927  */
 928 static void
 929 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 930 {
 931         int32_t i;
 932
 933         /* start with highest supported, proceed down */
 934         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 935                 ixgbe_mbox_api_11,
 936                 ixgbe_mbox_api_10,
 937         };
 938
 939         for (i = 0;
 940                         i != RTE_DIM(sup_ver) &&
 941                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 942                         i++)
 943                 ;
 944 }
 945
 946 static void
 947 generate_random_mac_addr(struct ether_addr *mac_addr)
 948 {
 949         uint64_t random;
 950
 951         /* Set Organizationally Unique Identifier (OUI) prefix. */
 952         mac_addr->addr_bytes[0] = 0x00;
 953         mac_addr->addr_bytes[1] = 0x09;
 954         mac_addr->addr_bytes[2] = 0xC0;
 955         /* Force indication of locally assigned MAC address. */
 956         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 957         /* Generate the last 3 bytes of the MAC address with a random number. */
 958         random = rte_rand();
 959         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 960 }
 961
 962 /*
 963  * Virtual Function device init
 964  */
 965 static int
 966 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
 967 {
 968         int diag;
 969         uint32_t tc, tcs;
 970         struct rte_pci_device *pci_dev;
 971         struct ixgbe_hw *hw =
 972                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 973         struct ixgbe_vfta * shadow_vfta =
 974                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 975         struct ixgbe_hwstrip *hwstrip =
 976                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 977         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 978
 979         PMD_INIT_FUNC_TRACE();
 980
 981         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 982         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 983         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 984
 985         /* for secondary processes, we don't initialise any further as primary
 986          * has already done this work. Only check we don't need a different
 987          * RX function */
 988         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 989                 if (eth_dev->data->scattered_rx)
 990                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 991                 return 0;
 992         }
 993
 994         pci_dev = eth_dev->pci_dev;
 995
 996         hw->device_id = pci_dev->id.device_id;
 997         hw->vendor_id = pci_dev->id.vendor_id;
 998         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 999
1000         /* initialize the vfta */
1001         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1002
1003         /* initialize the hw strip bitmap*/
1004         memset(hwstrip, 0, sizeof(*hwstrip));
1005
1006         /* Initialize the shared code (base driver) */
1007         diag = ixgbe_init_shared_code(hw);
1008         if (diag != IXGBE_SUCCESS) {
1009                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1010                 return -EIO;
1011         }
1012
1013         /* init_mailbox_params */
1014         hw->mbx.ops.init_params(hw);
1015
1016         /* Disable the interrupts for VF */
1017         ixgbevf_intr_disable(hw);
1018
1019         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1020         diag = hw->mac.ops.reset_hw(hw);
1021
1022         /*
1023          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1024          * the underlying PF driver has not assigned a MAC address to the VF.
1025          * In this case, assign a random MAC address.
1026          */
1027         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1028                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1029                 return (diag);
1030         }
1031
1032         /* negotiate mailbox API version to use with the PF. */
1033         ixgbevf_negotiate_api(hw);
1034
1035         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1036         ixgbevf_get_queues(hw, &tcs, &tc);
1037
1038         /* Allocate memory for storing MAC addresses */
1039         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1040                         hw->mac.num_rar_entries, 0);
1041         if (eth_dev->data->mac_addrs == NULL) {
1042                 PMD_INIT_LOG(ERR,
1043                         "Failed to allocate %u bytes needed to store "
1044                         "MAC addresses",
1045                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1046                 return -ENOMEM;
1047         }
1048
1049         /* Generate a random MAC address, if none was assigned by PF. */
1050         if (is_zero_ether_addr(perm_addr)) {
1051                 generate_random_mac_addr(perm_addr);
1052                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1053                 if (diag) {
1054                         rte_free(eth_dev->data->mac_addrs);
1055                         eth_dev->data->mac_addrs = NULL;
1056                         return diag;
1057                 }
1058                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1059                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1060                              "%02x:%02x:%02x:%02x:%02x:%02x",
1061                              perm_addr->addr_bytes[0],
1062                              perm_addr->addr_bytes[1],
1063                              perm_addr->addr_bytes[2],
1064                              perm_addr->addr_bytes[3],
1065                              perm_addr->addr_bytes[4],
1066                              perm_addr->addr_bytes[5]);
1067         }
1068
1069         /* Copy the permanent MAC address */
1070         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1071
1072         /* reset the hardware with the new settings */
1073         diag = hw->mac.ops.start_hw(hw);
1074         switch (diag) {
1075                 case  0:
1076                         break;
1077
1078                 default:
1079                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1080                         return (-EIO);
1081         }
1082
1083         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1084                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1085                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1086
1087         return 0;
1088 }
1089
1090 static struct eth_driver rte_ixgbe_pmd = {
1091         {
1092                 .name = "rte_ixgbe_pmd",
1093                 .id_table = pci_id_ixgbe_map,
1094                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1095         },
1096         .eth_dev_init = eth_ixgbe_dev_init,
1097         .dev_private_size = sizeof(struct ixgbe_adapter),
1098 };
1099
1100 /*
1101  * virtual function driver struct
1102  */
1103 static struct eth_driver rte_ixgbevf_pmd = {
1104         {
1105                 .name = "rte_ixgbevf_pmd",
1106                 .id_table = pci_id_ixgbevf_map,
1107                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1108         },
1109         .eth_dev_init = eth_ixgbevf_dev_init,
1110         .dev_private_size = sizeof(struct ixgbe_adapter),
1111 };
1112
1113 /*
1114  * Driver initialization routine.
1115  * Invoked once at EAL init time.
1116  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1117  */
1118 static int
1119 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1120 {
1121         PMD_INIT_FUNC_TRACE();
1122
1123         rte_eth_driver_register(&rte_ixgbe_pmd);
1124         return 0;
1125 }
1126
1127 /*
1128  * VF Driver initialization routine.
1129  * Invoked one at EAL init time.
1130  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1131  */
1132 static int
1133 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1134 {
1135         PMD_INIT_FUNC_TRACE();
1136
1137         rte_eth_driver_register(&rte_ixgbevf_pmd);
1138         return (0);
1139 }
1140
1141 static int
1142 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1143 {
1144         struct ixgbe_hw *hw =
1145                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1146         struct ixgbe_vfta * shadow_vfta =
1147                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1148         uint32_t vfta;
1149         uint32_t vid_idx;
1150         uint32_t vid_bit;
1151
1152         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1153         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1154         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1155         if (on)
1156                 vfta |= vid_bit;
1157         else
1158                 vfta &= ~vid_bit;
1159         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1160
1161         /* update local VFTA copy */
1162         shadow_vfta->vfta[vid_idx] = vfta;
1163
1164         return 0;
1165 }
1166
1167 static void
1168 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1169 {
1170         if (on)
1171                 ixgbe_vlan_hw_strip_enable(dev, queue);
1172         else
1173                 ixgbe_vlan_hw_strip_disable(dev, queue);
1174 }
1175
1176 static void
1177 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1178 {
1179         struct ixgbe_hw *hw =
1180                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1181
1182         /* Only the high 16-bits is valid */
1183         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1184 }
1185
1186 void
1187 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1188 {
1189         struct ixgbe_hw *hw =
1190                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1191         uint32_t vlnctrl;
1192
1193         PMD_INIT_FUNC_TRACE();
1194
1195         /* Filter Table Disable */
1196         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1197         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1198
1199         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1200 }
1201
1202 void
1203 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1204 {
1205         struct ixgbe_hw *hw =
1206                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1207         struct ixgbe_vfta * shadow_vfta =
1208                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1209         uint32_t vlnctrl;
1210         uint16_t i;
1211
1212         PMD_INIT_FUNC_TRACE();
1213
1214         /* Filter Table Enable */
1215         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1216         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1217         vlnctrl |= IXGBE_VLNCTRL_VFE;
1218
1219         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1220
1221         /* write whatever is in local vfta copy */
1222         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1223                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1224 }
1225
1226 static void
1227 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1228 {
1229         struct ixgbe_hwstrip *hwstrip =
1230                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1231
1232         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1233                 return;
1234
1235         if (on)
1236                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1237         else
1238                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1239 }
1240
1241 static void
1242 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1243 {
1244         struct ixgbe_hw *hw =
1245                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1246         uint32_t ctrl;
1247
1248         PMD_INIT_FUNC_TRACE();
1249
1250         if (hw->mac.type == ixgbe_mac_82598EB) {
1251                 /* No queue level support */
1252                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1253                 return;
1254         }
1255         else {
1256                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1257                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1258                 ctrl &= ~IXGBE_RXDCTL_VME;
1259                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1260         }
1261         /* record those setting for HW strip per queue */
1262         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1263 }
1264
1265 static void
1266 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1267 {
1268         struct ixgbe_hw *hw =
1269                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1270         uint32_t ctrl;
1271
1272         PMD_INIT_FUNC_TRACE();
1273
1274         if (hw->mac.type == ixgbe_mac_82598EB) {
1275                 /* No queue level supported */
1276                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1277                 return;
1278         }
1279         else {
1280                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1281                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1282                 ctrl |= IXGBE_RXDCTL_VME;
1283                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1284         }
1285         /* record those setting for HW strip per queue */
1286         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1287 }
1288
1289 void
1290 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1291 {
1292         struct ixgbe_hw *hw =
1293                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1294         uint32_t ctrl;
1295         uint16_t i;
1296
1297         PMD_INIT_FUNC_TRACE();
1298
1299         if (hw->mac.type == ixgbe_mac_82598EB) {
1300                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1301                 ctrl &= ~IXGBE_VLNCTRL_VME;
1302                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1303         }
1304         else {
1305                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1306                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1307                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1308                         ctrl &= ~IXGBE_RXDCTL_VME;
1309                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1310
1311                         /* record those setting for HW strip per queue */
1312                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1313                 }
1314         }
1315 }
1316
1317 void
1318 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1319 {
1320         struct ixgbe_hw *hw =
1321                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1322         uint32_t ctrl;
1323         uint16_t i;
1324
1325         PMD_INIT_FUNC_TRACE();
1326
1327         if (hw->mac.type == ixgbe_mac_82598EB) {
1328                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1329                 ctrl |= IXGBE_VLNCTRL_VME;
1330                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1331         }
1332         else {
1333                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1334                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1335                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1336                         ctrl |= IXGBE_RXDCTL_VME;
1337                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1338
1339                         /* record those setting for HW strip per queue */
1340                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1341                 }
1342         }
1343 }
1344
1345 static void
1346 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1347 {
1348         struct ixgbe_hw *hw =
1349                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1350         uint32_t ctrl;
1351
1352         PMD_INIT_FUNC_TRACE();
1353
1354         /* DMATXCTRL: Geric Double VLAN Disable */
1355         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1356         ctrl &= ~IXGBE_DMATXCTL_GDV;
1357         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1358
1359         /* CTRL_EXT: Global Double VLAN Disable */
1360         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1361         ctrl &= ~IXGBE_EXTENDED_VLAN;
1362         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1363
1364 }
1365
1366 static void
1367 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1368 {
1369         struct ixgbe_hw *hw =
1370                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1371         uint32_t ctrl;
1372
1373         PMD_INIT_FUNC_TRACE();
1374
1375         /* DMATXCTRL: Geric Double VLAN Enable */
1376         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1377         ctrl |= IXGBE_DMATXCTL_GDV;
1378         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1379
1380         /* CTRL_EXT: Global Double VLAN Enable */
1381         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1382         ctrl |= IXGBE_EXTENDED_VLAN;
1383         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1384
1385         /*
1386          * VET EXT field in the EXVET register = 0x8100 by default
1387          * So no need to change. Same to VT field of DMATXCTL register
1388          */
1389 }
1390
1391 static void
1392 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1393 {
1394         if(mask & ETH_VLAN_STRIP_MASK){
1395                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1396                         ixgbe_vlan_hw_strip_enable_all(dev);
1397                 else
1398                         ixgbe_vlan_hw_strip_disable_all(dev);
1399         }
1400
1401         if(mask & ETH_VLAN_FILTER_MASK){
1402                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1403                         ixgbe_vlan_hw_filter_enable(dev);
1404                 else
1405                         ixgbe_vlan_hw_filter_disable(dev);
1406         }
1407
1408         if(mask & ETH_VLAN_EXTEND_MASK){
1409                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1410                         ixgbe_vlan_hw_extend_enable(dev);
1411                 else
1412                         ixgbe_vlan_hw_extend_disable(dev);
1413         }
1414 }
1415
1416 static void
1417 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1418 {
1419         struct ixgbe_hw *hw =
1420                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1421         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1422         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1423         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1424         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1425 }
1426
1427 static int
1428 ixgbe_dev_configure(struct rte_eth_dev *dev)
1429 {
1430         struct ixgbe_interrupt *intr =
1431                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1432         struct ixgbe_hw *hw =
1433                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1434
1435         PMD_INIT_FUNC_TRACE();
1436
1437         /* set flag to update link status after init */
1438         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1439
1440         /*
1441          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1442          * allocation or vector Rx preconditions we will reset it.
1443          */
1444         hw->rx_bulk_alloc_allowed = true;
1445         hw->rx_vec_allowed = true;
1446
1447         return 0;
1448 }
1449
1450 /*
1451  * Configure device link speed and setup link.
1452  * It returns 0 on success.
1453  */
1454 static int
1455 ixgbe_dev_start(struct rte_eth_dev *dev)
1456 {
1457         struct ixgbe_hw *hw =
1458                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1459         struct ixgbe_vf_info *vfinfo =
1460                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1461         int err, link_up = 0, negotiate = 0;
1462         uint32_t speed = 0;
1463         int mask = 0;
1464         int status;
1465         uint16_t vf, idx;
1466
1467         PMD_INIT_FUNC_TRACE();
1468
1469         /* IXGBE devices don't support half duplex */
1470         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1471                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1472                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1473                              dev->data->dev_conf.link_duplex,
1474                              dev->data->port_id);
1475                 return -EINVAL;
1476         }
1477
1478         /* stop adapter */
1479         hw->adapter_stopped = FALSE;
1480         ixgbe_stop_adapter(hw);
1481
1482         /* reinitialize adapter
1483          * this calls reset and start */
1484         status = ixgbe_pf_reset_hw(hw);
1485         if (status != 0)
1486                 return -1;
1487         hw->mac.ops.start_hw(hw);
1488         hw->mac.get_link_status = true;
1489
1490         /* configure PF module if SRIOV enabled */
1491         ixgbe_pf_host_configure(dev);
1492
1493         /* initialize transmission unit */
1494         ixgbe_dev_tx_init(dev);
1495
1496         /* This can fail when allocating mbufs for descriptor rings */
1497         err = ixgbe_dev_rx_init(dev);
1498         if (err) {
1499                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1500                 goto error;
1501         }
1502
1503         err = ixgbe_dev_rxtx_start(dev);
1504         if (err < 0) {
1505                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1506                 goto error;
1507         }
1508
1509         /* Skip link setup if loopback mode is enabled for 82599. */
1510         if (hw->mac.type == ixgbe_mac_82599EB &&
1511                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1512                 goto skip_link_setup;
1513
1514         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1515                 err = hw->mac.ops.setup_sfp(hw);
1516                 if (err)
1517                         goto error;
1518         }
1519
1520         /* Turn on the laser */
1521         ixgbe_enable_tx_laser(hw);
1522
1523         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1524         if (err)
1525                 goto error;
1526         dev->data->dev_link.link_status = link_up;
1527
1528         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1529         if (err)
1530                 goto error;
1531
1532         switch(dev->data->dev_conf.link_speed) {
1533         case ETH_LINK_SPEED_AUTONEG:
1534                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1535                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1536                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1537                 break;
1538         case ETH_LINK_SPEED_100:
1539                 /*
1540                  * Invalid for 82598 but error will be detected by
1541                  * ixgbe_setup_link()
1542                  */
1543                 speed = IXGBE_LINK_SPEED_100_FULL;
1544                 break;
1545         case ETH_LINK_SPEED_1000:
1546                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1547                 break;
1548         case ETH_LINK_SPEED_10000:
1549                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1550                 break;
1551         default:
1552                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1553                              dev->data->dev_conf.link_speed,
1554                              dev->data->port_id);
1555                 goto error;
1556         }
1557
1558         err = ixgbe_setup_link(hw, speed, link_up);
1559         if (err)
1560                 goto error;
1561
1562 skip_link_setup:
1563
1564         /* check if lsc interrupt is enabled */
1565         if (dev->data->dev_conf.intr_conf.lsc != 0)
1566                 ixgbe_dev_lsc_interrupt_setup(dev);
1567
1568         /* resume enabled intr since hw reset */
1569         ixgbe_enable_intr(dev);
1570
1571         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1572                 ETH_VLAN_EXTEND_MASK;
1573         ixgbe_vlan_offload_set(dev, mask);
1574
1575         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1576                 /* Enable vlan filtering for VMDq */
1577                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1578         }
1579
1580         /* Configure DCB hw */
1581         ixgbe_configure_dcb(dev);
1582
1583         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1584                 err = ixgbe_fdir_configure(dev);
1585                 if (err)
1586                         goto error;
1587         }
1588
1589         /* Restore vf rate limit */
1590         if (vfinfo != NULL) {
1591                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1592                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1593                                 if (vfinfo[vf].tx_rate[idx] != 0)
1594                                         ixgbe_set_vf_rate_limit(dev, vf,
1595                                                 vfinfo[vf].tx_rate[idx],
1596                                                 1 << idx);
1597         }
1598
1599         ixgbe_restore_statistics_mapping(dev);
1600
1601         return (0);
1602
1603 error:
1604         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1605         ixgbe_dev_clear_queues(dev);
1606         return -EIO;
1607 }
1608
1609 /*
1610  * Stop device: disable rx and tx functions to allow for reconfiguring.
1611  */
1612 static void
1613 ixgbe_dev_stop(struct rte_eth_dev *dev)
1614 {
1615         struct rte_eth_link link;
1616         struct ixgbe_hw *hw =
1617                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1618         struct ixgbe_vf_info *vfinfo =
1619                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1620         struct ixgbe_filter_info *filter_info =
1621                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1622         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1623         int vf;
1624
1625         PMD_INIT_FUNC_TRACE();
1626
1627         /* disable interrupts */
1628         ixgbe_disable_intr(hw);
1629
1630         /* reset the NIC */
1631         ixgbe_pf_reset_hw(hw);
1632         hw->adapter_stopped = FALSE;
1633
1634         /* stop adapter */
1635         ixgbe_stop_adapter(hw);
1636
1637         for (vf = 0; vfinfo != NULL &&
1638                      vf < dev->pci_dev->max_vfs; vf++)
1639                 vfinfo[vf].clear_to_send = false;
1640
1641         /* Turn off the laser */
1642         ixgbe_disable_tx_laser(hw);
1643
1644         ixgbe_dev_clear_queues(dev);
1645
1646         /* Clear stored conf */
1647         dev->data->scattered_rx = 0;
1648
1649         /* Clear recorded link status */
1650         memset(&link, 0, sizeof(link));
1651         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1652
1653         /* Remove all ntuple filters of the device */
1654         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1655              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1656                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1657                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1658                              p_5tuple, entries);
1659                 rte_free(p_5tuple);
1660         }
1661         memset(filter_info->fivetuple_mask, 0,
1662                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1663
1664 }
1665
1666 /*
1667  * Set device link up: enable tx laser.
1668  */
1669 static int
1670 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1671 {
1672         struct ixgbe_hw *hw =
1673                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1674         if (hw->mac.type == ixgbe_mac_82599EB) {
1675 #ifdef RTE_NIC_BYPASS
1676                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1677                         /* Not suported in bypass mode */
1678                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1679                                      "by device id 0x%x", hw->device_id);
1680                         return -ENOTSUP;
1681                 }
1682 #endif
1683                 /* Turn on the laser */
1684                 ixgbe_enable_tx_laser(hw);
1685                 return 0;
1686         }
1687
1688         PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1689                      hw->device_id);
1690         return -ENOTSUP;
1691 }
1692
1693 /*
1694  * Set device link down: disable tx laser.
1695  */
1696 static int
1697 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1698 {
1699         struct ixgbe_hw *hw =
1700                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1701         if (hw->mac.type == ixgbe_mac_82599EB) {
1702 #ifdef RTE_NIC_BYPASS
1703                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1704                         /* Not suported in bypass mode */
1705                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1706                                      "by device id 0x%x", hw->device_id);
1707                         return -ENOTSUP;
1708                 }
1709 #endif
1710                 /* Turn off the laser */
1711                 ixgbe_disable_tx_laser(hw);
1712                 return 0;
1713         }
1714
1715         PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1716                      hw->device_id);
1717         return -ENOTSUP;
1718 }
1719
1720 /*
1721  * Reest and stop device.
1722  */
1723 static void
1724 ixgbe_dev_close(struct rte_eth_dev *dev)
1725 {
1726         struct ixgbe_hw *hw =
1727                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1728
1729         PMD_INIT_FUNC_TRACE();
1730
1731         ixgbe_pf_reset_hw(hw);
1732
1733         ixgbe_dev_stop(dev);
1734         hw->adapter_stopped = 1;
1735
1736         ixgbe_disable_pcie_master(hw);
1737
1738         /* reprogram the RAR[0] in case user changed it. */
1739         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1740 }
1741
1742 /*
1743  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1744  */
1745 static void
1746 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1747 {
1748         struct ixgbe_hw *hw =
1749                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1750         struct ixgbe_hw_stats *hw_stats =
1751                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1752         uint32_t bprc, lxon, lxoff, total;
1753         uint64_t total_missed_rx, total_qbrc, total_qprc;
1754         unsigned i;
1755
1756         total_missed_rx = 0;
1757         total_qbrc = 0;
1758         total_qprc = 0;
1759
1760         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1761         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1762         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1763         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1764
1765         for (i = 0; i < 8; i++) {
1766                 uint32_t mp;
1767                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1768                 /* global total per queue */
1769                 hw_stats->mpc[i] += mp;
1770                 /* Running comprehensive total for stats display */
1771                 total_missed_rx += hw_stats->mpc[i];
1772                 if (hw->mac.type == ixgbe_mac_82598EB)
1773                         hw_stats->rnbc[i] +=
1774                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1775                 hw_stats->pxontxc[i] +=
1776                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1777                 hw_stats->pxonrxc[i] +=
1778                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1779                 hw_stats->pxofftxc[i] +=
1780                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1781                 hw_stats->pxoffrxc[i] +=
1782                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1783                 hw_stats->pxon2offc[i] +=
1784                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1785         }
1786         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1787                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1788                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1789                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1790                 hw_stats->qbrc[i] +=
1791                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1792                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1793                 hw_stats->qbtc[i] +=
1794                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1795                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1796
1797                 total_qprc += hw_stats->qprc[i];
1798                 total_qbrc += hw_stats->qbrc[i];
1799         }
1800         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1801         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1802         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1803
1804         /* Note that gprc counts missed packets */
1805         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1806
1807         if (hw->mac.type != ixgbe_mac_82598EB) {
1808                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1809                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1810                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1811                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1812                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1813                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1814                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1815                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1816         } else {
1817                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1818                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1819                 /* 82598 only has a counter in the high register */
1820                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1821                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1822                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1823         }
1824
1825         /*
1826          * Workaround: mprc hardware is incorrectly counting
1827          * broadcasts, so for now we subtract those.
1828          */
1829         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1830         hw_stats->bprc += bprc;
1831         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1832         if (hw->mac.type == ixgbe_mac_82598EB)
1833                 hw_stats->mprc -= bprc;
1834
1835         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1836         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1837         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1838         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1839         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1840         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1841
1842         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1843         hw_stats->lxontxc += lxon;
1844         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1845         hw_stats->lxofftxc += lxoff;
1846         total = lxon + lxoff;
1847
1848         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1849         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1850         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1851         hw_stats->gptc -= total;
1852         hw_stats->mptc -= total;
1853         hw_stats->ptc64 -= total;
1854         hw_stats->gotc -= total * ETHER_MIN_LEN;
1855
1856         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1857         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1858         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1859         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1860         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1861         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1862         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1863         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1864         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1865         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1866         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1867         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1868         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1869         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1870         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1871         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1872         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1873         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1874         /* Only read FCOE on 82599 */
1875         if (hw->mac.type != ixgbe_mac_82598EB) {
1876                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1877                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1878                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1879                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1880                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1881         }
1882
1883         if (stats == NULL)
1884                 return;
1885
1886         /* Fill out the rte_eth_stats statistics structure */
1887         stats->ipackets = total_qprc;
1888         stats->ibytes = total_qbrc;
1889         stats->opackets = hw_stats->gptc;
1890         stats->obytes = hw_stats->gotc;
1891         stats->imcasts = hw_stats->mprc;
1892
1893         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1894                 stats->q_ipackets[i] = hw_stats->qprc[i];
1895                 stats->q_opackets[i] = hw_stats->qptc[i];
1896                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1897                 stats->q_obytes[i] = hw_stats->qbtc[i];
1898                 stats->q_errors[i] = hw_stats->qprdc[i];
1899         }
1900
1901         /* Rx Errors */
1902         stats->ibadcrc  = hw_stats->crcerrs;
1903         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1904         stats->imissed  = total_missed_rx;
1905         stats->ierrors  = stats->ibadcrc +
1906                           stats->ibadlen +
1907                           stats->imissed +
1908                           hw_stats->illerrc + hw_stats->errbc;
1909
1910         /* Tx Errors */
1911         stats->oerrors  = 0;
1912
1913         /* XON/XOFF pause frames */
1914         stats->tx_pause_xon  = hw_stats->lxontxc;
1915         stats->rx_pause_xon  = hw_stats->lxonrxc;
1916         stats->tx_pause_xoff = hw_stats->lxofftxc;
1917         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1918
1919         /* Flow Director Stats registers */
1920         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1921         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1922         stats->fdirmatch = hw_stats->fdirmatch;
1923         stats->fdirmiss = hw_stats->fdirmiss;
1924 }
1925
1926 static void
1927 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1928 {
1929         struct ixgbe_hw_stats *stats =
1930                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1931
1932         /* HW registers are cleared on read */
1933         ixgbe_dev_stats_get(dev, NULL);
1934
1935         /* Reset software totals */
1936         memset(stats, 0, sizeof(*stats));
1937 }
1938
1939 static void
1940 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1941 {
1942         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1944                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1945
1946         /* Good Rx packet, include VF loopback */
1947         UPDATE_VF_STAT(IXGBE_VFGPRC,
1948             hw_stats->last_vfgprc, hw_stats->vfgprc);
1949
1950         /* Good Rx octets, include VF loopback */
1951         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1952             hw_stats->last_vfgorc, hw_stats->vfgorc);
1953
1954         /* Good Tx packet, include VF loopback */
1955         UPDATE_VF_STAT(IXGBE_VFGPTC,
1956             hw_stats->last_vfgptc, hw_stats->vfgptc);
1957
1958         /* Good Tx octets, include VF loopback */
1959         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1960             hw_stats->last_vfgotc, hw_stats->vfgotc);
1961
1962         /* Rx Multicst Packet */
1963         UPDATE_VF_STAT(IXGBE_VFMPRC,
1964             hw_stats->last_vfmprc, hw_stats->vfmprc);
1965
1966         if (stats == NULL)
1967                 return;
1968
1969         stats->ipackets = hw_stats->vfgprc;
1970         stats->ibytes = hw_stats->vfgorc;
1971         stats->opackets = hw_stats->vfgptc;
1972         stats->obytes = hw_stats->vfgotc;
1973         stats->imcasts = hw_stats->vfmprc;
1974 }
1975
1976 static void
1977 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1978 {
1979         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1980                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1981
1982         /* Sync HW register to the last stats */
1983         ixgbevf_dev_stats_get(dev, NULL);
1984
1985         /* reset HW current stats*/
1986         hw_stats->vfgprc = 0;
1987         hw_stats->vfgorc = 0;
1988         hw_stats->vfgptc = 0;
1989         hw_stats->vfgotc = 0;
1990         hw_stats->vfmprc = 0;
1991
1992 }
1993
1994 static void
1995 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1996 {
1997         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1998
1999         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2000         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2001         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2002         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2003         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2004         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2005         dev_info->max_vfs = dev->pci_dev->max_vfs;
2006         if (hw->mac.type == ixgbe_mac_82598EB)
2007                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2008         else
2009                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2010         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2011         dev_info->rx_offload_capa =
2012                 DEV_RX_OFFLOAD_VLAN_STRIP |
2013                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2014                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2015                 DEV_RX_OFFLOAD_TCP_CKSUM;
2016         dev_info->tx_offload_capa =
2017                 DEV_TX_OFFLOAD_VLAN_INSERT |
2018                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2019                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2020                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2021                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2022                 DEV_TX_OFFLOAD_TCP_TSO;
2023
2024         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2025                 .rx_thresh = {
2026                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2027                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2028                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2029                 },
2030                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2031                 .rx_drop_en = 0,
2032         };
2033
2034         dev_info->default_txconf = (struct rte_eth_txconf) {
2035                 .tx_thresh = {
2036                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2037                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2038                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2039                 },
2040                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2041                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2042                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2043                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2044         };
2045         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2046         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2047 }
2048
2049 static void
2050 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2051                      struct rte_eth_dev_info *dev_info)
2052 {
2053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2054
2055         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2056         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2057         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2058         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2059         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2060         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2061         dev_info->max_vfs = dev->pci_dev->max_vfs;
2062         if (hw->mac.type == ixgbe_mac_82598EB)
2063                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2064         else
2065                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2066         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2067                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2068                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2069                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2070         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2071                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2072                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2073                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2074                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2075
2076         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2077                 .rx_thresh = {
2078                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2079                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2080                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2081                 },
2082                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2083                 .rx_drop_en = 0,
2084         };
2085
2086         dev_info->default_txconf = (struct rte_eth_txconf) {
2087                 .tx_thresh = {
2088                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2089                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2090                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2091                 },
2092                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2093                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2094                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2095                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2096         };
2097 }
2098
2099 /* return 0 means link status changed, -1 means not changed */
2100 static int
2101 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2102 {
2103         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2104         struct rte_eth_link link, old;
2105         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2106         int link_up;
2107         int diag;
2108
2109         link.link_status = 0;
2110         link.link_speed = 0;
2111         link.link_duplex = 0;
2112         memset(&old, 0, sizeof(old));
2113         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2114
2115         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2116         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2117                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2118         else
2119                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2120         if (diag != 0) {
2121                 link.link_speed = ETH_LINK_SPEED_100;
2122                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2123                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2124                 if (link.link_status == old.link_status)
2125                         return -1;
2126                 return 0;
2127         }
2128
2129         if (link_speed == IXGBE_LINK_SPEED_UNKNOWN &&
2130             !hw->mac.get_link_status) {
2131                 memcpy(&link, &old, sizeof(link));
2132                 return -1;
2133         }
2134
2135         if (link_up == 0) {
2136                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2137                 if (link.link_status == old.link_status)
2138                         return -1;
2139                 return 0;
2140         }
2141         link.link_status = 1;
2142         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2143
2144         switch (link_speed) {
2145         default:
2146         case IXGBE_LINK_SPEED_UNKNOWN:
2147                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2148                 link.link_speed = ETH_LINK_SPEED_100;
2149                 break;
2150
2151         case IXGBE_LINK_SPEED_100_FULL:
2152                 link.link_speed = ETH_LINK_SPEED_100;
2153                 break;
2154
2155         case IXGBE_LINK_SPEED_1GB_FULL:
2156                 link.link_speed = ETH_LINK_SPEED_1000;
2157                 break;
2158
2159         case IXGBE_LINK_SPEED_10GB_FULL:
2160                 link.link_speed = ETH_LINK_SPEED_10000;
2161                 break;
2162         }
2163         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2164
2165         if (link.link_status == old.link_status)
2166                 return -1;
2167
2168         return 0;
2169 }
2170
2171 static void
2172 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2173 {
2174         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2175         uint32_t fctrl;
2176
2177         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2178         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2179         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2180 }
2181
2182 static void
2183 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2184 {
2185         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2186         uint32_t fctrl;
2187
2188         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2189         fctrl &= (~IXGBE_FCTRL_UPE);
2190         if (dev->data->all_multicast == 1)
2191                 fctrl |= IXGBE_FCTRL_MPE;
2192         else
2193                 fctrl &= (~IXGBE_FCTRL_MPE);
2194         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2195 }
2196
2197 static void
2198 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2199 {
2200         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2201         uint32_t fctrl;
2202
2203         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2204         fctrl |= IXGBE_FCTRL_MPE;
2205         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2206 }
2207
2208 static void
2209 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2210 {
2211         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212         uint32_t fctrl;
2213
2214         if (dev->data->promiscuous == 1)
2215                 return; /* must remain in all_multicast mode */
2216
2217         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2218         fctrl &= (~IXGBE_FCTRL_MPE);
2219         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2220 }
2221
2222 /**
2223  * It clears the interrupt causes and enables the interrupt.
2224  * It will be called once only during nic initialized.
2225  *
2226  * @param dev
2227  *  Pointer to struct rte_eth_dev.
2228  *
2229  * @return
2230  *  - On success, zero.
2231  *  - On failure, a negative value.
2232  */
2233 static int
2234 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2235 {
2236         struct ixgbe_interrupt *intr =
2237                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2238
2239         ixgbe_dev_link_status_print(dev);
2240         intr->mask |= IXGBE_EICR_LSC;
2241
2242         return 0;
2243 }
2244
2245 /*
2246  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2247  *
2248  * @param dev
2249  *  Pointer to struct rte_eth_dev.
2250  *
2251  * @return
2252  *  - On success, zero.
2253  *  - On failure, a negative value.
2254  */
2255 static int
2256 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2257 {
2258         uint32_t eicr;
2259         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2260         struct ixgbe_interrupt *intr =
2261                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2262
2263         /* clear all cause mask */
2264         ixgbe_disable_intr(hw);
2265
2266         /* read-on-clear nic registers here */
2267         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2268         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2269
2270         intr->flags = 0;
2271         if (eicr & IXGBE_EICR_LSC) {
2272                 /* set flag for async link update */
2273                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2274         }
2275
2276         if (eicr & IXGBE_EICR_MAILBOX)
2277                 intr->flags |= IXGBE_FLAG_MAILBOX;
2278
2279         return 0;
2280 }
2281
2282 /**
2283  * It gets and then prints the link status.
2284  *
2285  * @param dev
2286  *  Pointer to struct rte_eth_dev.
2287  *
2288  * @return
2289  *  - On success, zero.
2290  *  - On failure, a negative value.
2291  */
2292 static void
2293 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2294 {
2295         struct rte_eth_link link;
2296
2297         memset(&link, 0, sizeof(link));
2298         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2299         if (link.link_status) {
2300                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2301                                         (int)(dev->data->port_id),
2302                                         (unsigned)link.link_speed,
2303                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2304                                         "full-duplex" : "half-duplex");
2305         } else {
2306                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2307                                 (int)(dev->data->port_id));
2308         }
2309         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2310                                 dev->pci_dev->addr.domain,
2311                                 dev->pci_dev->addr.bus,
2312                                 dev->pci_dev->addr.devid,
2313                                 dev->pci_dev->addr.function);
2314 }
2315
2316 /*
2317  * It executes link_update after knowing an interrupt occurred.
2318  *
2319  * @param dev
2320  *  Pointer to struct rte_eth_dev.
2321  *
2322  * @return
2323  *  - On success, zero.
2324  *  - On failure, a negative value.
2325  */
2326 static int
2327 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2328 {
2329         struct ixgbe_interrupt *intr =
2330                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2331         int64_t timeout;
2332         struct rte_eth_link link;
2333         int intr_enable_delay = false;
2334
2335         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2336
2337         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2338                 ixgbe_pf_mbx_process(dev);
2339                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2340         }
2341
2342         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2343                 /* get the link status before link update, for predicting later */
2344                 memset(&link, 0, sizeof(link));
2345                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2346
2347                 ixgbe_dev_link_update(dev, 0);
2348
2349                 /* likely to up */
2350                 if (!link.link_status)
2351                         /* handle it 1 sec later, wait it being stable */
2352                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2353                 /* likely to down */
2354                 else
2355                         /* handle it 4 sec later, wait it being stable */
2356                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2357
2358                 ixgbe_dev_link_status_print(dev);
2359
2360                 intr_enable_delay = true;
2361         }
2362
2363         if (intr_enable_delay) {
2364                 if (rte_eal_alarm_set(timeout * 1000,
2365                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2366                         PMD_DRV_LOG(ERR, "Error setting alarm");
2367         } else {
2368                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2369                 ixgbe_enable_intr(dev);
2370                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2371         }
2372
2373
2374         return 0;
2375 }
2376
2377 /**
2378  * Interrupt handler which shall be registered for alarm callback for delayed
2379  * handling specific interrupt to wait for the stable nic state. As the
2380  * NIC interrupt state is not stable for ixgbe after link is just down,
2381  * it needs to wait 4 seconds to get the stable status.
2382  *
2383  * @param handle
2384  *  Pointer to interrupt handle.
2385  * @param param
2386  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2387  *
2388  * @return
2389  *  void
2390  */
2391 static void
2392 ixgbe_dev_interrupt_delayed_handler(void *param)
2393 {
2394         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2395         struct ixgbe_interrupt *intr =
2396                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2397         struct ixgbe_hw *hw =
2398                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2399         uint32_t eicr;
2400
2401         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2402         if (eicr & IXGBE_EICR_MAILBOX)
2403                 ixgbe_pf_mbx_process(dev);
2404
2405         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2406                 ixgbe_dev_link_update(dev, 0);
2407                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2408                 ixgbe_dev_link_status_print(dev);
2409                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2410         }
2411
2412         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2413         ixgbe_enable_intr(dev);
2414         rte_intr_enable(&(dev->pci_dev->intr_handle));
2415 }
2416
2417 /**
2418  * Interrupt handler triggered by NIC  for handling
2419  * specific interrupt.
2420  *
2421  * @param handle
2422  *  Pointer to interrupt handle.
2423  * @param param
2424  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2425  *
2426  * @return
2427  *  void
2428  */
2429 static void
2430 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2431                                                         void *param)
2432 {
2433         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2434         ixgbe_dev_interrupt_get_status(dev);
2435         ixgbe_dev_interrupt_action(dev);
2436 }
2437
2438 static int
2439 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2440 {
2441         struct ixgbe_hw *hw;
2442
2443         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2444         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2445 }
2446
2447 static int
2448 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2449 {
2450         struct ixgbe_hw *hw;
2451
2452         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2453         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2454 }
2455
2456 static int
2457 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2458 {
2459         struct ixgbe_hw *hw;
2460         uint32_t mflcn_reg;
2461         uint32_t fccfg_reg;
2462         int rx_pause;
2463         int tx_pause;
2464
2465         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2466
2467         fc_conf->pause_time = hw->fc.pause_time;
2468         fc_conf->high_water = hw->fc.high_water[0];
2469         fc_conf->low_water = hw->fc.low_water[0];
2470         fc_conf->send_xon = hw->fc.send_xon;
2471         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2472
2473         /*
2474          * Return rx_pause status according to actual setting of
2475          * MFLCN register.
2476          */
2477         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2478         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2479                 rx_pause = 1;
2480         else
2481                 rx_pause = 0;
2482
2483         /*
2484          * Return tx_pause status according to actual setting of
2485          * FCCFG register.
2486          */
2487         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2488         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2489                 tx_pause = 1;
2490         else
2491                 tx_pause = 0;
2492
2493         if (rx_pause && tx_pause)
2494                 fc_conf->mode = RTE_FC_FULL;
2495         else if (rx_pause)
2496                 fc_conf->mode = RTE_FC_RX_PAUSE;
2497         else if (tx_pause)
2498                 fc_conf->mode = RTE_FC_TX_PAUSE;
2499         else
2500                 fc_conf->mode = RTE_FC_NONE;
2501
2502         return 0;
2503 }
2504
2505 static int
2506 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2507 {
2508         struct ixgbe_hw *hw;
2509         int err;
2510         uint32_t rx_buf_size;
2511         uint32_t max_high_water;
2512         uint32_t mflcn;
2513         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2514                 ixgbe_fc_none,
2515                 ixgbe_fc_rx_pause,
2516                 ixgbe_fc_tx_pause,
2517                 ixgbe_fc_full
2518         };
2519
2520         PMD_INIT_FUNC_TRACE();
2521
2522         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2524                 return -ENOTSUP;
2525         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2526         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2527
2528         /*
2529          * At least reserve one Ethernet frame for watermark
2530          * high_water/low_water in kilo bytes for ixgbe
2531          */
2532         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2533         if ((fc_conf->high_water > max_high_water) ||
2534                 (fc_conf->high_water < fc_conf->low_water)) {
2535                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2536                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2537                 return (-EINVAL);
2538         }
2539
2540         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2541         hw->fc.pause_time     = fc_conf->pause_time;
2542         hw->fc.high_water[0]  = fc_conf->high_water;
2543         hw->fc.low_water[0]   = fc_conf->low_water;
2544         hw->fc.send_xon       = fc_conf->send_xon;
2545
2546         err = ixgbe_fc_enable(hw);
2547
2548         /* Not negotiated is not an error case */
2549         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2550
2551                 /* check if we want to forward MAC frames - driver doesn't have native
2552                  * capability to do that, so we'll write the registers ourselves */
2553
2554                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2555
2556                 /* set or clear MFLCN.PMCF bit depending on configuration */
2557                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2558                         mflcn |= IXGBE_MFLCN_PMCF;
2559                 else
2560                         mflcn &= ~IXGBE_MFLCN_PMCF;
2561
2562                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2563                 IXGBE_WRITE_FLUSH(hw);
2564
2565                 return 0;
2566         }
2567
2568         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2569         return -EIO;
2570 }
2571
2572 /**
2573  *  ixgbe_pfc_enable_generic - Enable flow control
2574  *  @hw: pointer to hardware structure
2575  *  @tc_num: traffic class number
2576  *  Enable flow control according to the current settings.
2577  */
2578 static int
2579 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2580 {
2581         int ret_val = 0;
2582         uint32_t mflcn_reg, fccfg_reg;
2583         uint32_t reg;
2584         uint32_t fcrtl, fcrth;
2585         uint8_t i;
2586         uint8_t nb_rx_en;
2587
2588         /* Validate the water mark configuration */
2589         if (!hw->fc.pause_time) {
2590                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2591                 goto out;
2592         }
2593
2594         /* Low water mark of zero causes XOFF floods */
2595         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2596                  /* High/Low water can not be 0 */
2597                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2598                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2599                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2600                         goto out;
2601                 }
2602
2603                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2604                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2605                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2606                         goto out;
2607                 }
2608         }
2609         /* Negotiate the fc mode to use */
2610         ixgbe_fc_autoneg(hw);
2611
2612         /* Disable any previous flow control settings */
2613         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2614         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2615
2616         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2617         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2618
2619         switch (hw->fc.current_mode) {
2620         case ixgbe_fc_none:
2621                 /*
2622                  * If the count of enabled RX Priority Flow control >1,
2623                  * and the TX pause can not be disabled
2624                  */
2625                 nb_rx_en = 0;
2626                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2627                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2628                         if (reg & IXGBE_FCRTH_FCEN)
2629                                 nb_rx_en++;
2630                 }
2631                 if (nb_rx_en > 1)
2632                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2633                 break;
2634         case ixgbe_fc_rx_pause:
2635                 /*
2636                  * Rx Flow control is enabled and Tx Flow control is
2637                  * disabled by software override. Since there really
2638                  * isn't a way to advertise that we are capable of RX
2639                  * Pause ONLY, we will advertise that we support both
2640                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2641                  * disable the adapter's ability to send PAUSE frames.
2642                  */
2643                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2644                 /*
2645                  * If the count of enabled RX Priority Flow control >1,
2646                  * and the TX pause can not be disabled
2647                  */
2648                 nb_rx_en = 0;
2649                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2650                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2651                         if (reg & IXGBE_FCRTH_FCEN)
2652                                 nb_rx_en++;
2653                 }
2654                 if (nb_rx_en > 1)
2655                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2656                 break;
2657         case ixgbe_fc_tx_pause:
2658                 /*
2659                  * Tx Flow control is enabled, and Rx Flow control is
2660                  * disabled by software override.
2661                  */
2662                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2663                 break;
2664         case ixgbe_fc_full:
2665                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2666                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2667                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2668                 break;
2669         default:
2670                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2671                 ret_val = IXGBE_ERR_CONFIG;
2672                 goto out;
2673                 break;
2674         }
2675
2676         /* Set 802.3x based flow control settings. */
2677         mflcn_reg |= IXGBE_MFLCN_DPF;
2678         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2679         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2680
2681         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2682         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2683                 hw->fc.high_water[tc_num]) {
2684                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2685                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2686                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2687         } else {
2688                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2689                 /*
2690                  * In order to prevent Tx hangs when the internal Tx
2691                  * switch is enabled we must set the high water mark
2692                  * to the maximum FCRTH value.  This allows the Tx
2693                  * switch to function even under heavy Rx workloads.
2694                  */
2695                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2696         }
2697         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2698
2699         /* Configure pause time (2 TCs per register) */
2700         reg = hw->fc.pause_time * 0x00010001;
2701         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2702                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2703
2704         /* Configure flow control refresh threshold value */
2705         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2706
2707 out:
2708         return ret_val;
2709 }
2710
2711 static int
2712 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2713 {
2714         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2715         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2716
2717         if(hw->mac.type != ixgbe_mac_82598EB) {
2718                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2719         }
2720         return ret_val;
2721 }
2722
2723 static int
2724 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2725 {
2726         int err;
2727         uint32_t rx_buf_size;
2728         uint32_t max_high_water;
2729         uint8_t tc_num;
2730         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2731         struct ixgbe_hw *hw =
2732                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2733         struct ixgbe_dcb_config *dcb_config =
2734                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2735
2736         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2737                 ixgbe_fc_none,
2738                 ixgbe_fc_rx_pause,
2739                 ixgbe_fc_tx_pause,
2740                 ixgbe_fc_full
2741         };
2742
2743         PMD_INIT_FUNC_TRACE();
2744
2745         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2746         tc_num = map[pfc_conf->priority];
2747         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2748         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2749         /*
2750          * At least reserve one Ethernet frame for watermark
2751          * high_water/low_water in kilo bytes for ixgbe
2752          */
2753         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2754         if ((pfc_conf->fc.high_water > max_high_water) ||
2755             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2756                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2757                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2758                 return (-EINVAL);
2759         }
2760
2761         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2762         hw->fc.pause_time = pfc_conf->fc.pause_time;
2763         hw->fc.send_xon = pfc_conf->fc.send_xon;
2764         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2765         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2766
2767         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2768
2769         /* Not negotiated is not an error case */
2770         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2771                 return 0;
2772
2773         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2774         return -EIO;
2775 }
2776
2777 static int
2778 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2779                           struct rte_eth_rss_reta_entry64 *reta_conf,
2780                           uint16_t reta_size)
2781 {
2782         uint8_t i, j, mask;
2783         uint32_t reta, r;
2784         uint16_t idx, shift;
2785         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2786
2787         PMD_INIT_FUNC_TRACE();
2788         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2789                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2790                         "(%d) doesn't match the number hardware can supported "
2791                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2792                 return -EINVAL;
2793         }
2794
2795         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2796                 idx = i / RTE_RETA_GROUP_SIZE;
2797                 shift = i % RTE_RETA_GROUP_SIZE;
2798                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2799                                                 IXGBE_4_BIT_MASK);
2800                 if (!mask)
2801                         continue;
2802                 if (mask == IXGBE_4_BIT_MASK)
2803                         r = 0;
2804                 else
2805                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2806                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2807                         if (mask & (0x1 << j))
2808                                 reta |= reta_conf[idx].reta[shift + j] <<
2809                                                         (CHAR_BIT * j);
2810                         else
2811                                 reta |= r & (IXGBE_8_BIT_MASK <<
2812                                                 (CHAR_BIT * j));
2813                 }
2814                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2815         }
2816
2817         return 0;
2818 }
2819
2820 static int
2821 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2822                          struct rte_eth_rss_reta_entry64 *reta_conf,
2823                          uint16_t reta_size)
2824 {
2825         uint8_t i, j, mask;
2826         uint32_t reta;
2827         uint16_t idx, shift;
2828         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2829
2830         PMD_INIT_FUNC_TRACE();
2831         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2832                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2833                         "(%d) doesn't match the number hardware can supported "
2834                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2835                 return -EINVAL;
2836         }
2837
2838         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2839                 idx = i / RTE_RETA_GROUP_SIZE;
2840                 shift = i % RTE_RETA_GROUP_SIZE;
2841                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2842                                                 IXGBE_4_BIT_MASK);
2843                 if (!mask)
2844                         continue;
2845
2846                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2847                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2848                         if (mask & (0x1 << j))
2849                                 reta_conf[idx].reta[shift + j] =
2850                                         ((reta >> (CHAR_BIT * j)) &
2851                                                 IXGBE_8_BIT_MASK);
2852                 }
2853         }
2854
2855         return 0;
2856 }
2857
2858 static void
2859 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2860                                 uint32_t index, uint32_t pool)
2861 {
2862         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2863         uint32_t enable_addr = 1;
2864
2865         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2866 }
2867
2868 static void
2869 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2870 {
2871         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2872
2873         ixgbe_clear_rar(hw, index);
2874 }
2875
2876 static int
2877 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2878 {
2879         uint32_t hlreg0;
2880         uint32_t maxfrs;
2881         struct ixgbe_hw *hw;
2882         struct rte_eth_dev_info dev_info;
2883         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2884
2885         ixgbe_dev_info_get(dev, &dev_info);
2886
2887         /* check that mtu is within the allowed range */
2888         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2889                 return -EINVAL;
2890
2891         /* refuse mtu that requires the support of scattered packets when this
2892          * feature has not been enabled before. */
2893         if (!dev->data->scattered_rx &&
2894             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2895              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2896                 return -EINVAL;
2897
2898         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2899         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2900
2901         /* switch to jumbo mode if needed */
2902         if (frame_size > ETHER_MAX_LEN) {
2903                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2904                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2905         } else {
2906                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2907                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2908         }
2909         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2910
2911         /* update max frame size */
2912         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2913
2914         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2915         maxfrs &= 0x0000FFFF;
2916         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2917         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2918
2919         return 0;
2920 }
2921
2922 /*
2923  * Virtual Function operations
2924  */
2925 static void
2926 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2927 {
2928         PMD_INIT_FUNC_TRACE();
2929
2930         /* Clear interrupt mask to stop from interrupts being generated */
2931         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2932
2933         IXGBE_WRITE_FLUSH(hw);
2934 }
2935
2936 static int
2937 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2938 {
2939         struct rte_eth_conf* conf = &dev->data->dev_conf;
2940
2941         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2942                      dev->data->port_id);
2943
2944         /*
2945          * VF has no ability to enable/disable HW CRC
2946          * Keep the persistent behavior the same as Host PF
2947          */
2948 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2949         if (!conf->rxmode.hw_strip_crc) {
2950                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2951                 conf->rxmode.hw_strip_crc = 1;
2952         }
2953 #else
2954         if (conf->rxmode.hw_strip_crc) {
2955                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2956                 conf->rxmode.hw_strip_crc = 0;
2957         }
2958 #endif
2959
2960         return 0;
2961 }
2962
2963 static int
2964 ixgbevf_dev_start(struct rte_eth_dev *dev)
2965 {
2966         struct ixgbe_hw *hw =
2967                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2968         int err, mask = 0;
2969
2970         PMD_INIT_FUNC_TRACE();
2971
2972         hw->mac.ops.reset_hw(hw);
2973         hw->mac.get_link_status = true;
2974
2975         /* negotiate mailbox API version to use with the PF. */
2976         ixgbevf_negotiate_api(hw);
2977
2978         ixgbevf_dev_tx_init(dev);
2979
2980         /* This can fail when allocating mbufs for descriptor rings */
2981         err = ixgbevf_dev_rx_init(dev);
2982         if (err) {
2983                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2984                 ixgbe_dev_clear_queues(dev);
2985                 return err;
2986         }
2987
2988         /* Set vfta */
2989         ixgbevf_set_vfta_all(dev,1);
2990
2991         /* Set HW strip */
2992         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2993                 ETH_VLAN_EXTEND_MASK;
2994         ixgbevf_vlan_offload_set(dev, mask);
2995
2996         ixgbevf_dev_rxtx_start(dev);
2997
2998         return 0;
2999 }
3000
3001 static void
3002 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3003 {
3004         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3005
3006         PMD_INIT_FUNC_TRACE();
3007
3008         hw->adapter_stopped = TRUE;
3009         ixgbe_stop_adapter(hw);
3010
3011         /*
3012           * Clear what we set, but we still keep shadow_vfta to
3013           * restore after device starts
3014           */
3015         ixgbevf_set_vfta_all(dev,0);
3016
3017         /* Clear stored conf */
3018         dev->data->scattered_rx = 0;
3019
3020         ixgbe_dev_clear_queues(dev);
3021 }
3022
3023 static void
3024 ixgbevf_dev_close(struct rte_eth_dev *dev)
3025 {
3026         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3027
3028         PMD_INIT_FUNC_TRACE();
3029
3030         ixgbe_reset_hw(hw);
3031
3032         ixgbevf_dev_stop(dev);
3033
3034         /* reprogram the RAR[0] in case user changed it. */
3035         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3036 }
3037
3038 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3039 {
3040         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3041         struct ixgbe_vfta * shadow_vfta =
3042                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3043         int i = 0, j = 0, vfta = 0, mask = 1;
3044
3045         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3046                 vfta = shadow_vfta->vfta[i];
3047                 if(vfta){
3048                         mask = 1;
3049                         for (j = 0; j < 32; j++){
3050                                 if(vfta & mask)
3051                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3052                                 mask<<=1;
3053                         }
3054                 }
3055         }
3056
3057 }
3058
3059 static int
3060 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3061 {
3062         struct ixgbe_hw *hw =
3063                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3064         struct ixgbe_vfta * shadow_vfta =
3065                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3066         uint32_t vid_idx = 0;
3067         uint32_t vid_bit = 0;
3068         int ret = 0;
3069
3070         PMD_INIT_FUNC_TRACE();
3071
3072         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3073         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3074         if(ret){
3075                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3076                 return ret;
3077         }
3078         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3079         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3080
3081         /* Save what we set and retore it after device reset */
3082         if (on)
3083                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3084         else
3085                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3086
3087         return 0;
3088 }
3089
3090 static void
3091 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3092 {
3093         struct ixgbe_hw *hw =
3094                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3095         uint32_t ctrl;
3096
3097         PMD_INIT_FUNC_TRACE();
3098
3099         if(queue >= hw->mac.max_rx_queues)
3100                 return;
3101
3102         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3103         if(on)
3104                 ctrl |= IXGBE_RXDCTL_VME;
3105         else
3106                 ctrl &= ~IXGBE_RXDCTL_VME;
3107         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3108
3109         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3110 }
3111
3112 static void
3113 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3114 {
3115         struct ixgbe_hw *hw =
3116                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3117         uint16_t i;
3118         int on = 0;
3119
3120         /* VF function only support hw strip feature, others are not support */
3121         if(mask & ETH_VLAN_STRIP_MASK){
3122                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3123
3124                 for(i=0; i < hw->mac.max_rx_queues; i++)
3125                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3126         }
3127 }
3128
3129 static int
3130 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3131 {
3132         uint32_t reg_val;
3133
3134         /* we only need to do this if VMDq is enabled */
3135         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3136         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3137                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3138                 return (-1);
3139         }
3140
3141         return 0;
3142 }
3143
3144 static uint32_t
3145 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3146 {
3147         uint32_t vector = 0;
3148         switch (hw->mac.mc_filter_type) {
3149         case 0:   /* use bits [47:36] of the address */
3150                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3151                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3152                 break;
3153         case 1:   /* use bits [46:35] of the address */
3154                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3155                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3156                 break;
3157         case 2:   /* use bits [45:34] of the address */
3158                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3159                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3160                 break;
3161         case 3:   /* use bits [43:32] of the address */
3162                 vector = ((uc_addr->addr_bytes[4]) |
3163                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3164                 break;
3165         default:  /* Invalid mc_filter_type */
3166                 break;
3167         }
3168
3169         /* vector can only be 12-bits or boundary will be exceeded */
3170         vector &= 0xFFF;
3171         return vector;
3172 }
3173
3174 static int
3175 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3176                                uint8_t on)
3177 {
3178         uint32_t vector;
3179         uint32_t uta_idx;
3180         uint32_t reg_val;
3181         uint32_t uta_shift;
3182         uint32_t rc;
3183         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3184         const uint32_t ixgbe_uta_bit_shift = 5;
3185         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3186         const uint32_t bit1 = 0x1;
3187
3188         struct ixgbe_hw *hw =
3189                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3190         struct ixgbe_uta_info *uta_info =
3191                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3192
3193         /* The UTA table only exists on 82599 hardware and newer */
3194         if (hw->mac.type < ixgbe_mac_82599EB)
3195                 return (-ENOTSUP);
3196
3197         vector = ixgbe_uta_vector(hw,mac_addr);
3198         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3199         uta_shift = vector & ixgbe_uta_bit_mask;
3200
3201         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3202         if(rc == on)
3203                 return 0;
3204
3205         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3206         if (on) {
3207                 uta_info->uta_in_use++;
3208                 reg_val |= (bit1 << uta_shift);
3209                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3210         } else {
3211                 uta_info->uta_in_use--;
3212                 reg_val &= ~(bit1 << uta_shift);
3213                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3214         }
3215
3216         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3217
3218         if (uta_info->uta_in_use > 0)
3219                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3220                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3221         else
3222                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3223
3224         return 0;
3225 }
3226
3227 static int
3228 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3229 {
3230         int i;
3231         struct ixgbe_hw *hw =
3232                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3233         struct ixgbe_uta_info *uta_info =
3234                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3235
3236         /* The UTA table only exists on 82599 hardware and newer */
3237         if (hw->mac.type < ixgbe_mac_82599EB)
3238                 return (-ENOTSUP);
3239
3240         if(on) {
3241                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3242                         uta_info->uta_shadow[i] = ~0;
3243                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3244                 }
3245         } else {
3246                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3247                         uta_info->uta_shadow[i] = 0;
3248                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3249                 }
3250         }
3251         return 0;
3252
3253 }
3254
3255 uint32_t
3256 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3257 {
3258         uint32_t new_val = orig_val;
3259
3260         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3261                 new_val |= IXGBE_VMOLR_AUPE;
3262         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3263                 new_val |= IXGBE_VMOLR_ROMPE;
3264         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3265                 new_val |= IXGBE_VMOLR_ROPE;
3266         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3267                 new_val |= IXGBE_VMOLR_BAM;
3268         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3269                 new_val |= IXGBE_VMOLR_MPE;
3270
3271         return new_val;
3272 }
3273
3274 static int
3275 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3276                                uint16_t rx_mask, uint8_t on)
3277 {
3278         int val = 0;
3279
3280         struct ixgbe_hw *hw =
3281                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3282         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3283
3284         if (hw->mac.type == ixgbe_mac_82598EB) {
3285                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3286                              " on 82599 hardware and newer");
3287                 return (-ENOTSUP);
3288         }
3289         if (ixgbe_vmdq_mode_check(hw) < 0)
3290                 return (-ENOTSUP);
3291
3292         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3293
3294         if (on)
3295                 vmolr |= val;
3296         else
3297                 vmolr &= ~val;
3298
3299         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3300
3301         return 0;
3302 }
3303
3304 static int
3305 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3306 {
3307         uint32_t reg,addr;
3308         uint32_t val;
3309         const uint8_t bit1 = 0x1;
3310
3311         struct ixgbe_hw *hw =
3312                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3313
3314         if (ixgbe_vmdq_mode_check(hw) < 0)
3315                 return (-ENOTSUP);
3316
3317         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3318         reg = IXGBE_READ_REG(hw, addr);
3319         val = bit1 << pool;
3320
3321         if (on)
3322                 reg |= val;
3323         else
3324                 reg &= ~val;
3325
3326         IXGBE_WRITE_REG(hw, addr,reg);
3327
3328         return 0;
3329 }
3330
3331 static int
3332 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3333 {
3334         uint32_t reg,addr;
3335         uint32_t val;
3336         const uint8_t bit1 = 0x1;
3337
3338         struct ixgbe_hw *hw =
3339                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3340
3341         if (ixgbe_vmdq_mode_check(hw) < 0)
3342                 return (-ENOTSUP);
3343
3344         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3345         reg = IXGBE_READ_REG(hw, addr);
3346         val = bit1 << pool;
3347
3348         if (on)
3349                 reg |= val;
3350         else
3351                 reg &= ~val;
3352
3353         IXGBE_WRITE_REG(hw, addr,reg);
3354
3355         return 0;
3356 }
3357
3358 static int
3359 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3360                         uint64_t pool_mask, uint8_t vlan_on)
3361 {
3362         int ret = 0;
3363         uint16_t pool_idx;
3364         struct ixgbe_hw *hw =
3365                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3366
3367         if (ixgbe_vmdq_mode_check(hw) < 0)
3368                 return (-ENOTSUP);
3369         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3370                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3371                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3372                         if (ret < 0)
3373                                 return ret;
3374         }
3375
3376         return ret;
3377 }
3378
3379 static int
3380 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3381                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3382                         uint8_t rule_id, uint8_t on)
3383 {
3384         uint32_t mr_ctl,vlvf;
3385         uint32_t mp_lsb = 0;
3386         uint32_t mv_msb = 0;
3387         uint32_t mv_lsb = 0;
3388         uint32_t mp_msb = 0;
3389         uint8_t i = 0;
3390         int reg_index = 0;
3391         uint64_t vlan_mask = 0;
3392
3393         const uint8_t pool_mask_offset = 32;
3394         const uint8_t vlan_mask_offset = 32;
3395         const uint8_t dst_pool_offset = 8;
3396         const uint8_t rule_mr_offset  = 4;
3397         const uint8_t mirror_rule_mask= 0x0F;
3398
3399         struct ixgbe_mirror_info *mr_info =
3400                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3401         struct ixgbe_hw *hw =
3402                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3403
3404         if (ixgbe_vmdq_mode_check(hw) < 0)
3405                 return (-ENOTSUP);
3406
3407         /* Check if vlan mask is valid */
3408         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3409                 if (mirror_conf->vlan.vlan_mask == 0)
3410                         return (-EINVAL);
3411         }
3412
3413         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3414         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3415                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3416                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3417                                 /* search vlan id related pool vlan filter index */
3418                                 reg_index = ixgbe_find_vlvf_slot(hw,
3419                                                 mirror_conf->vlan.vlan_id[i]);
3420                                 if(reg_index < 0)
3421                                         return (-EINVAL);
3422                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3423                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3424                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3425                                                 == mirror_conf->vlan.vlan_id[i]))
3426                                         vlan_mask |= (1ULL << reg_index);
3427                                 else
3428                                         return (-EINVAL);
3429                         }
3430                 }
3431
3432                 if (on) {
3433                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3434                         mv_msb = vlan_mask >> vlan_mask_offset;
3435
3436                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3437                                                 mirror_conf->vlan.vlan_mask;
3438                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3439                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3440                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3441                                                 mirror_conf->vlan.vlan_id[i];
3442                         }
3443                 } else {
3444                         mv_lsb = 0;
3445                         mv_msb = 0;
3446                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3447                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3448                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3449                 }
3450         }
3451
3452         /*
3453          * if enable pool mirror, write related pool mask register,if disable
3454          * pool mirror, clear PFMRVM register
3455          */
3456         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3457                 if (on) {
3458                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3459                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3460                         mr_info->mr_conf[rule_id].pool_mask =
3461                                         mirror_conf->pool_mask;
3462
3463                 } else {
3464                         mp_lsb = 0;
3465                         mp_msb = 0;
3466                         mr_info->mr_conf[rule_id].pool_mask = 0;
3467                 }
3468         }
3469
3470         /* read  mirror control register and recalculate it */
3471         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3472
3473         if (on) {
3474                 mr_ctl |= mirror_conf->rule_type_mask;
3475                 mr_ctl &= mirror_rule_mask;
3476                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3477         } else
3478                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3479
3480         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3481         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3482
3483         /* write mirrror control  register */
3484         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3485
3486         /* write pool mirrror control  register */
3487         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3488                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3489                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3490                                 mp_msb);
3491         }
3492         /* write VLAN mirrror control  register */
3493         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3494                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3495                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3496                                 mv_msb);
3497         }
3498
3499         return 0;
3500 }
3501
3502 static int
3503 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3504 {
3505         int mr_ctl = 0;
3506         uint32_t lsb_val = 0;
3507         uint32_t msb_val = 0;
3508         const uint8_t rule_mr_offset = 4;
3509
3510         struct ixgbe_hw *hw =
3511                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3512         struct ixgbe_mirror_info *mr_info =
3513                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3514
3515         if (ixgbe_vmdq_mode_check(hw) < 0)
3516                 return (-ENOTSUP);
3517
3518         memset(&mr_info->mr_conf[rule_id], 0,
3519                 sizeof(struct rte_eth_vmdq_mirror_conf));
3520
3521         /* clear PFVMCTL register */
3522         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3523
3524         /* clear pool mask register */
3525         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3526         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3527
3528         /* clear vlan mask register */
3529         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3530         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3531
3532         return 0;
3533 }
3534
3535 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3536         uint16_t queue_idx, uint16_t tx_rate)
3537 {
3538         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3539         uint32_t rf_dec, rf_int;
3540         uint32_t bcnrc_val;
3541         uint16_t link_speed = dev->data->dev_link.link_speed;
3542
3543         if (queue_idx >= hw->mac.max_tx_queues)
3544                 return -EINVAL;
3545
3546         if (tx_rate != 0) {
3547                 /* Calculate the rate factor values to set */
3548                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3549                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3550                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3551
3552                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3553                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3554                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3555                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3556         } else {
3557                 bcnrc_val = 0;
3558         }
3559
3560         /*
3561          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3562          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3563          * set as 0x4.
3564          */
3565         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3566                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3567                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3568                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3569                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3570         else
3571                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3572                         IXGBE_MMW_SIZE_DEFAULT);
3573
3574         /* Set RTTBCNRC of queue X */
3575         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3576         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3577         IXGBE_WRITE_FLUSH(hw);
3578
3579         return 0;
3580 }
3581
3582 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3583         uint16_t tx_rate, uint64_t q_msk)
3584 {
3585         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3586         struct ixgbe_vf_info *vfinfo =
3587                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3588         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3589         uint32_t queue_stride =
3590                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3591         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3592         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3593         uint16_t total_rate = 0;
3594
3595         if (queue_end >= hw->mac.max_tx_queues)
3596                 return -EINVAL;
3597
3598         if (vfinfo != NULL) {
3599                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3600                         if (vf_idx == vf)
3601                                 continue;
3602                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3603                                 idx++)
3604                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3605                 }
3606         } else
3607                 return -EINVAL;
3608
3609         /* Store tx_rate for this vf. */
3610         for (idx = 0; idx < nb_q_per_pool; idx++) {
3611                 if (((uint64_t)0x1 << idx) & q_msk) {
3612                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3613                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3614                         total_rate += tx_rate;
3615                 }
3616         }
3617
3618         if (total_rate > dev->data->dev_link.link_speed) {
3619                 /*
3620                  * Reset stored TX rate of the VF if it causes exceed
3621                  * link speed.
3622                  */
3623                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3624                 return -EINVAL;
3625         }
3626
3627         /* Set RTTBCNRC of each queue/pool for vf X  */
3628         for (; queue_idx <= queue_end; queue_idx++) {
3629                 if (0x1 & q_msk)
3630                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3631                 q_msk = q_msk >> 1;
3632         }
3633
3634         return 0;
3635 }
3636
3637 static void
3638 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3639                      __attribute__((unused)) uint32_t index,
3640                      __attribute__((unused)) uint32_t pool)
3641 {
3642         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3643         int diag;
3644
3645         /*
3646          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3647          * operation. Trap this case to avoid exhausting the [very limited]
3648          * set of PF resources used to store VF MAC addresses.
3649          */
3650         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3651                 return;
3652         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3653         if (diag == 0)
3654                 return;
3655         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3656 }
3657
3658 static void
3659 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3660 {
3661         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3662         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3663         struct ether_addr *mac_addr;
3664         uint32_t i;
3665         int diag;
3666
3667         /*
3668          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3669          * not support the deletion of a given MAC address.
3670          * Instead, it imposes to delete all MAC addresses, then to add again
3671          * all MAC addresses with the exception of the one to be deleted.
3672          */
3673         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3674
3675         /*
3676          * Add again all MAC addresses, with the exception of the deleted one
3677          * and of the permanent MAC address.
3678          */
3679         for (i = 0, mac_addr = dev->data->mac_addrs;
3680              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3681                 /* Skip the deleted MAC address */
3682                 if (i == index)
3683                         continue;
3684                 /* Skip NULL MAC addresses */
3685                 if (is_zero_ether_addr(mac_addr))
3686                         continue;
3687                 /* Skip the permanent MAC address */
3688                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3689                         continue;
3690                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3691                 if (diag != 0)
3692                         PMD_DRV_LOG(ERR,
3693                                     "Adding again MAC address "
3694                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3695                                     "diag=%d",
3696                                     mac_addr->addr_bytes[0],
3697                                     mac_addr->addr_bytes[1],
3698                                     mac_addr->addr_bytes[2],
3699                                     mac_addr->addr_bytes[3],
3700                                     mac_addr->addr_bytes[4],
3701                                     mac_addr->addr_bytes[5],
3702                                     diag);
3703         }
3704 }
3705
3706 #define MAC_TYPE_FILTER_SUP(type)    do {\
3707         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
3708                 (type) != ixgbe_mac_X550)\
3709                 return -ENOTSUP;\
3710 } while (0)
3711
3712 static int
3713 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
3714                         struct rte_eth_syn_filter *filter,
3715                         bool add)
3716 {
3717         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3718         uint32_t synqf;
3719
3720         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
3721                 return -EINVAL;
3722
3723         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3724
3725         if (add) {
3726                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3727                         return -EINVAL;
3728                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3729                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3730
3731                 if (filter->hig_pri)
3732                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
3733                 else
3734                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3735         } else {
3736                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
3737                         return -ENOENT;
3738                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3739         }
3740         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3741         IXGBE_WRITE_FLUSH(hw);
3742         return 0;
3743 }
3744
3745 static int
3746 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
3747                         struct rte_eth_syn_filter *filter)
3748 {
3749         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3750         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3751
3752         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3753                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3754                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3755                 return 0;
3756         }
3757         return -ENOENT;
3758 }
3759
3760 static int
3761 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
3762                         enum rte_filter_op filter_op,
3763                         void *arg)
3764 {
3765         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3766         int ret;
3767
3768         MAC_TYPE_FILTER_SUP(hw->mac.type);
3769
3770         if (filter_op == RTE_ETH_FILTER_NOP)
3771                 return 0;
3772
3773         if (arg == NULL) {
3774                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3775                             filter_op);
3776                 return -EINVAL;
3777         }
3778
3779         switch (filter_op) {
3780         case RTE_ETH_FILTER_ADD:
3781                 ret = ixgbe_syn_filter_set(dev,
3782                                 (struct rte_eth_syn_filter *)arg,
3783                                 TRUE);
3784                 break;
3785         case RTE_ETH_FILTER_DELETE:
3786                 ret = ixgbe_syn_filter_set(dev,
3787                                 (struct rte_eth_syn_filter *)arg,
3788                                 FALSE);
3789                 break;
3790         case RTE_ETH_FILTER_GET:
3791                 ret = ixgbe_syn_filter_get(dev,
3792                                 (struct rte_eth_syn_filter *)arg);
3793                 break;
3794         default:
3795                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3796                 ret = -EINVAL;
3797                 break;
3798         }
3799
3800         return ret;
3801 }
3802
3803
3804 static inline enum ixgbe_5tuple_protocol
3805 convert_protocol_type(uint8_t protocol_value)
3806 {
3807         if (protocol_value == IPPROTO_TCP)
3808                 return IXGBE_FILTER_PROTOCOL_TCP;
3809         else if (protocol_value == IPPROTO_UDP)
3810                 return IXGBE_FILTER_PROTOCOL_UDP;
3811         else if (protocol_value == IPPROTO_SCTP)
3812                 return IXGBE_FILTER_PROTOCOL_SCTP;
3813         else
3814                 return IXGBE_FILTER_PROTOCOL_NONE;
3815 }
3816
3817 /*
3818  * add a 5tuple filter
3819  *
3820  * @param
3821  * dev: Pointer to struct rte_eth_dev.
3822  * index: the index the filter allocates.
3823  * filter: ponter to the filter that will be added.
3824  * rx_queue: the queue id the filter assigned to.
3825  *
3826  * @return
3827  *    - On success, zero.
3828  *    - On failure, a negative value.
3829  */
3830 static int
3831 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3832                         struct ixgbe_5tuple_filter *filter)
3833 {
3834         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3835         struct ixgbe_filter_info *filter_info =
3836                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3837         int i, idx, shift;
3838         uint32_t ftqf, sdpqf;
3839         uint32_t l34timir = 0;
3840         uint8_t mask = 0xff;
3841
3842         /*
3843          * look for an unused 5tuple filter index,
3844          * and insert the filter to list.
3845          */
3846         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
3847                 idx = i / (sizeof(uint32_t) * NBBY);
3848                 shift = i % (sizeof(uint32_t) * NBBY);
3849                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3850                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3851                         filter->index = i;
3852                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3853                                           filter,
3854                                           entries);
3855                         break;
3856                 }
3857         }
3858         if (i >= IXGBE_MAX_FTQF_FILTERS) {
3859                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3860                 return -ENOSYS;
3861         }
3862
3863         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
3864                                 IXGBE_SDPQF_DSTPORT_SHIFT);
3865         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
3866
3867         ftqf = (uint32_t)(filter->filter_info.proto &
3868                 IXGBE_FTQF_PROTOCOL_MASK);
3869         ftqf |= (uint32_t)((filter->filter_info.priority &
3870                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
3871         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3872                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3873         if (filter->filter_info.dst_ip_mask == 0)
3874                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3875         if (filter->filter_info.src_port_mask == 0)
3876                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3877         if (filter->filter_info.dst_port_mask == 0)
3878                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3879         if (filter->filter_info.proto_mask == 0)
3880                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3881         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3882         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3883         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3884
3885         IXGBE_WRITE_REG(hw, IXGBE_DAQF(idx), filter->filter_info.dst_ip);
3886         IXGBE_WRITE_REG(hw, IXGBE_SAQF(idx), filter->filter_info.src_ip);
3887         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(idx), sdpqf);
3888         IXGBE_WRITE_REG(hw, IXGBE_FTQF(idx), ftqf);
3889
3890         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3891         l34timir |= (uint32_t)(filter->queue <<
3892                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
3893         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
3894         return 0;
3895 }
3896
3897 /*
3898  * remove a 5tuple filter
3899  *
3900  * @param
3901  * dev: Pointer to struct rte_eth_dev.
3902  * filter: the pointer of the filter will be removed.
3903  */
3904 static void
3905 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3906                         struct ixgbe_5tuple_filter *filter)
3907 {
3908         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3909         struct ixgbe_filter_info *filter_info =
3910                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3911         uint16_t index = filter->index;
3912
3913         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3914                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3915         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3916         rte_free(filter);
3917
3918         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3919         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3920         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3921         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3922         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3923 }
3924
3925 static int
3926 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3927 {
3928         struct ixgbe_hw *hw;
3929         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3930
3931         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3932
3933         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3934                 return -EINVAL;
3935
3936         /* refuse mtu that requires the support of scattered packets when this
3937          * feature has not been enabled before. */
3938         if (!dev->data->scattered_rx &&
3939             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3940              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3941                 return -EINVAL;
3942
3943         /*
3944          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3945          * request of the version 2.0 of the mailbox API.
3946          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3947          * of the mailbox API.
3948          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3949          * prior to 3.11.33 which contains the following change:
3950          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3951          */
3952         ixgbevf_rlpml_set_vf(hw, max_frame);
3953
3954         /* update max frame size */
3955         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
3956         return 0;
3957 }
3958
3959 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3960         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
3961                 return -ENOTSUP;\
3962 } while (0)
3963
3964 static inline struct ixgbe_5tuple_filter *
3965 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
3966                         struct ixgbe_5tuple_filter_info *key)
3967 {
3968         struct ixgbe_5tuple_filter *it;
3969
3970         TAILQ_FOREACH(it, filter_list, entries) {
3971                 if (memcmp(key, &it->filter_info,
3972                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
3973                         return it;
3974                 }
3975         }
3976         return NULL;
3977 }
3978
3979 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
3980 static inline int
3981 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3982                         struct ixgbe_5tuple_filter_info *filter_info)
3983 {
3984         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3985                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3986                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3987                 return -EINVAL;
3988
3989         switch (filter->dst_ip_mask) {
3990         case UINT32_MAX:
3991                 filter_info->dst_ip_mask = 0;
3992                 filter_info->dst_ip = filter->dst_ip;
3993                 break;
3994         case 0:
3995                 filter_info->dst_ip_mask = 1;
3996                 break;
3997         default:
3998                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3999                 return -EINVAL;
4000         }
4001
4002         switch (filter->src_ip_mask) {
4003         case UINT32_MAX:
4004                 filter_info->src_ip_mask = 0;
4005                 filter_info->src_ip = filter->src_ip;
4006                 break;
4007         case 0:
4008                 filter_info->src_ip_mask = 1;
4009                 break;
4010         default:
4011                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4012                 return -EINVAL;
4013         }
4014
4015         switch (filter->dst_port_mask) {
4016         case UINT16_MAX:
4017                 filter_info->dst_port_mask = 0;
4018                 filter_info->dst_port = filter->dst_port;
4019                 break;
4020         case 0:
4021                 filter_info->dst_port_mask = 1;
4022                 break;
4023         default:
4024                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4025                 return -EINVAL;
4026         }
4027
4028         switch (filter->src_port_mask) {
4029         case UINT16_MAX:
4030                 filter_info->src_port_mask = 0;
4031                 filter_info->src_port = filter->src_port;
4032                 break;
4033         case 0:
4034                 filter_info->src_port_mask = 1;
4035                 break;
4036         default:
4037                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4038                 return -EINVAL;
4039         }
4040
4041         switch (filter->proto_mask) {
4042         case UINT8_MAX:
4043                 filter_info->proto_mask = 0;
4044                 filter_info->proto =
4045                         convert_protocol_type(filter->proto);
4046                 break;
4047         case 0:
4048                 filter_info->proto_mask = 1;
4049                 break;
4050         default:
4051                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4052                 return -EINVAL;
4053         }
4054
4055         filter_info->priority = (uint8_t)filter->priority;
4056         return 0;
4057 }
4058
4059 /*
4060  * add or delete a ntuple filter
4061  *
4062  * @param
4063  * dev: Pointer to struct rte_eth_dev.
4064  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4065  * add: if true, add filter, if false, remove filter
4066  *
4067  * @return
4068  *    - On success, zero.
4069  *    - On failure, a negative value.
4070  */
4071 static int
4072 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4073                         struct rte_eth_ntuple_filter *ntuple_filter,
4074                         bool add)
4075 {
4076         struct ixgbe_filter_info *filter_info =
4077                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4078         struct ixgbe_5tuple_filter_info filter_5tuple;
4079         struct ixgbe_5tuple_filter *filter;
4080         int ret;
4081
4082         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4083                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4084                 return -EINVAL;
4085         }
4086
4087         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4088         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4089         if (ret < 0)
4090                 return ret;
4091
4092         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4093                                          &filter_5tuple);
4094         if (filter != NULL && add) {
4095                 PMD_DRV_LOG(ERR, "filter exists.");
4096                 return -EEXIST;
4097         }
4098         if (filter == NULL && !add) {
4099                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4100                 return -ENOENT;
4101         }
4102
4103         if (add) {
4104                 filter = rte_zmalloc("ixgbe_5tuple_filter",
4105                                 sizeof(struct ixgbe_5tuple_filter), 0);
4106                 if (filter == NULL)
4107                         return -ENOMEM;
4108                 (void)rte_memcpy(&filter->filter_info,
4109                                  &filter_5tuple,
4110                                  sizeof(struct ixgbe_5tuple_filter_info));
4111                 filter->queue = ntuple_filter->queue;
4112                 ret = ixgbe_add_5tuple_filter(dev, filter);
4113                 if (ret < 0) {
4114                         rte_free(filter);
4115                         return ret;
4116                 }
4117         } else
4118                 ixgbe_remove_5tuple_filter(dev, filter);
4119
4120         return 0;
4121 }
4122
4123 /*
4124  * get a ntuple filter
4125  *
4126  * @param
4127  * dev: Pointer to struct rte_eth_dev.
4128  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4129  *
4130  * @return
4131  *    - On success, zero.
4132  *    - On failure, a negative value.
4133  */
4134 static int
4135 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4136                         struct rte_eth_ntuple_filter *ntuple_filter)
4137 {
4138         struct ixgbe_filter_info *filter_info =
4139                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4140         struct ixgbe_5tuple_filter_info filter_5tuple;
4141         struct ixgbe_5tuple_filter *filter;
4142         int ret;
4143
4144         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4145                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4146                 return -EINVAL;
4147         }
4148
4149         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4150         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4151         if (ret < 0)
4152                 return ret;
4153
4154         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4155                                          &filter_5tuple);
4156         if (filter == NULL) {
4157                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4158                 return -ENOENT;
4159         }
4160         ntuple_filter->queue = filter->queue;
4161         return 0;
4162 }
4163
4164 /*
4165  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4166  * @dev: pointer to rte_eth_dev structure
4167  * @filter_op:operation will be taken.
4168  * @arg: a pointer to specific structure corresponding to the filter_op
4169  *
4170  * @return
4171  *    - On success, zero.
4172  *    - On failure, a negative value.
4173  */
4174 static int
4175 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4176                                 enum rte_filter_op filter_op,
4177                                 void *arg)
4178 {
4179         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4180         int ret;
4181
4182         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4183
4184         if (filter_op == RTE_ETH_FILTER_NOP)
4185                 return 0;
4186
4187         if (arg == NULL) {
4188                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4189                             filter_op);
4190                 return -EINVAL;
4191         }
4192
4193         switch (filter_op) {
4194         case RTE_ETH_FILTER_ADD:
4195                 ret = ixgbe_add_del_ntuple_filter(dev,
4196                         (struct rte_eth_ntuple_filter *)arg,
4197                         TRUE);
4198                 break;
4199         case RTE_ETH_FILTER_DELETE:
4200                 ret = ixgbe_add_del_ntuple_filter(dev,
4201                         (struct rte_eth_ntuple_filter *)arg,
4202                         FALSE);
4203                 break;
4204         case RTE_ETH_FILTER_GET:
4205                 ret = ixgbe_get_ntuple_filter(dev,
4206                         (struct rte_eth_ntuple_filter *)arg);
4207                 break;
4208         default:
4209                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4210                 ret = -EINVAL;
4211                 break;
4212         }
4213         return ret;
4214 }
4215
4216 static inline int
4217 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4218                         uint16_t ethertype)
4219 {
4220         int i;
4221
4222         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4223                 if (filter_info->ethertype_filters[i] == ethertype &&
4224                     (filter_info->ethertype_mask & (1 << i)))
4225                         return i;
4226         }
4227         return -1;
4228 }
4229
4230 static inline int
4231 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4232                         uint16_t ethertype)
4233 {
4234         int i;
4235
4236         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4237                 if (!(filter_info->ethertype_mask & (1 << i))) {
4238                         filter_info->ethertype_mask |= 1 << i;
4239                         filter_info->ethertype_filters[i] = ethertype;
4240                         return i;
4241                 }
4242         }
4243         return -1;
4244 }
4245
4246 static inline int
4247 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4248                         uint8_t idx)
4249 {
4250         if (idx >= IXGBE_MAX_ETQF_FILTERS)
4251                 return -1;
4252         filter_info->ethertype_mask &= ~(1 << idx);
4253         filter_info->ethertype_filters[idx] = 0;
4254         return idx;
4255 }
4256
4257 static int
4258 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4259                         struct rte_eth_ethertype_filter *filter,
4260                         bool add)
4261 {
4262         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4263         struct ixgbe_filter_info *filter_info =
4264                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4265         uint32_t etqf = 0;
4266         uint32_t etqs = 0;
4267         int ret;
4268
4269         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4270                 return -EINVAL;
4271
4272         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4273                 filter->ether_type == ETHER_TYPE_IPv6) {
4274                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4275                         " ethertype filter.", filter->ether_type);
4276                 return -EINVAL;
4277         }
4278
4279         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4280                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4281                 return -EINVAL;
4282         }
4283         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4284                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4285                 return -EINVAL;
4286         }
4287
4288         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4289         if (ret >= 0 && add) {
4290                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4291                             filter->ether_type);
4292                 return -EEXIST;
4293         }
4294         if (ret < 0 && !add) {
4295                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4296                             filter->ether_type);
4297                 return -ENOENT;
4298         }
4299
4300         if (add) {
4301                 ret = ixgbe_ethertype_filter_insert(filter_info,
4302                         filter->ether_type);
4303                 if (ret < 0) {
4304                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4305                         return -ENOSYS;
4306                 }
4307                 etqf = IXGBE_ETQF_FILTER_EN;
4308                 etqf |= (uint32_t)filter->ether_type;
4309                 etqs |= (uint32_t)((filter->queue <<
4310                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
4311                                     IXGBE_ETQS_RX_QUEUE);
4312                 etqs |= IXGBE_ETQS_QUEUE_EN;
4313         } else {
4314                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4315                 if (ret < 0)
4316                         return -ENOSYS;
4317         }
4318         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4319         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4320         IXGBE_WRITE_FLUSH(hw);
4321
4322         return 0;
4323 }
4324
4325 static int
4326 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4327                         struct rte_eth_ethertype_filter *filter)
4328 {
4329         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4330         struct ixgbe_filter_info *filter_info =
4331                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4332         uint32_t etqf, etqs;
4333         int ret;
4334
4335         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4336         if (ret < 0) {
4337                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4338                             filter->ether_type);
4339                 return -ENOENT;
4340         }
4341
4342         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4343         if (etqf & IXGBE_ETQF_FILTER_EN) {
4344                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4345                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4346                 filter->flags = 0;
4347                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4348                                IXGBE_ETQS_RX_QUEUE_SHIFT;
4349                 return 0;
4350         }
4351         return -ENOENT;
4352 }
4353
4354 /*
4355  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4356  * @dev: pointer to rte_eth_dev structure
4357  * @filter_op:operation will be taken.
4358  * @arg: a pointer to specific structure corresponding to the filter_op
4359  */
4360 static int
4361 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4362                                 enum rte_filter_op filter_op,
4363                                 void *arg)
4364 {
4365         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4366         int ret;
4367
4368         MAC_TYPE_FILTER_SUP(hw->mac.type);
4369
4370         if (filter_op == RTE_ETH_FILTER_NOP)
4371                 return 0;
4372
4373         if (arg == NULL) {
4374                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4375                             filter_op);
4376                 return -EINVAL;
4377         }
4378
4379         switch (filter_op) {
4380         case RTE_ETH_FILTER_ADD:
4381                 ret = ixgbe_add_del_ethertype_filter(dev,
4382                         (struct rte_eth_ethertype_filter *)arg,
4383                         TRUE);
4384                 break;
4385         case RTE_ETH_FILTER_DELETE:
4386                 ret = ixgbe_add_del_ethertype_filter(dev,
4387                         (struct rte_eth_ethertype_filter *)arg,
4388                         FALSE);
4389                 break;
4390         case RTE_ETH_FILTER_GET:
4391                 ret = ixgbe_get_ethertype_filter(dev,
4392                         (struct rte_eth_ethertype_filter *)arg);
4393                 break;
4394         default:
4395                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4396                 ret = -EINVAL;
4397                 break;
4398         }
4399         return ret;
4400 }
4401
4402 static int
4403 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4404                      enum rte_filter_type filter_type,
4405                      enum rte_filter_op filter_op,
4406                      void *arg)
4407 {
4408         int ret = -EINVAL;
4409
4410         switch (filter_type) {
4411         case RTE_ETH_FILTER_NTUPLE:
4412                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
4413                 break;
4414         case RTE_ETH_FILTER_ETHERTYPE:
4415                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4416                 break;
4417         case RTE_ETH_FILTER_SYN:
4418                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
4419                 break;
4420         case RTE_ETH_FILTER_FDIR:
4421                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4422                 break;
4423         default:
4424                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4425                                                         filter_type);
4426                 break;
4427         }
4428
4429         return ret;
4430 }
4431
4432 static struct rte_driver rte_ixgbe_driver = {
4433         .type = PMD_PDEV,
4434         .init = rte_ixgbe_pmd_init,
4435 };
4436
4437 static struct rte_driver rte_ixgbevf_driver = {
4438         .type = PMD_PDEV,
4439         .init = rte_ixgbevf_pmd_init,
4440 };
4441
4442 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4443 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);