lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "ixgbe/ixgbe_api.h"
  66 #include "ixgbe/ixgbe_vf.h"
  67 #include "ixgbe/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 /*
  96  *  Default values for RX/TX configuration
  97  */
  98 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  99 #define IXGBE_DEFAULT_RX_PTHRESH      8
 100 #define IXGBE_DEFAULT_RX_HTHRESH      8
 101 #define IXGBE_DEFAULT_RX_WTHRESH      0
 102
 103 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 104 #define IXGBE_DEFAULT_TX_PTHRESH      32
 105 #define IXGBE_DEFAULT_TX_HTHRESH      0
 106 #define IXGBE_DEFAULT_TX_WTHRESH      0
 107 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 108
 109 /* Bit shift and mask */
 110 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 111 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 112 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 113 #define IXGBE_8_BIT_MASK   UINT8_MAX
 114
 115 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 116
 117 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 118
 119 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 120 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 121 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 122 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 123 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 124 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 125 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 126 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 127 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 128 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 129 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 130 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 131                                 int wait_to_complete);
 132 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 133                                 struct rte_eth_stats *stats);
 134 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 135 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 136                                              uint16_t queue_id,
 137                                              uint8_t stat_idx,
 138                                              uint8_t is_rx);
 139 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 140                                struct rte_eth_dev_info *dev_info);
 141 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 142                                  struct rte_eth_dev_info *dev_info);
 143 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 144
 145 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 146                 uint16_t vlan_id, int on);
 147 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 148 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 149                 uint16_t queue, bool on);
 150 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 151                 int on);
 152 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 153 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 154 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 155 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 156 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 157
 158 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 159 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 160 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 161                                struct rte_eth_fc_conf *fc_conf);
 162 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 163                                struct rte_eth_fc_conf *fc_conf);
 164 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 165                 struct rte_eth_pfc_conf *pfc_conf);
 166 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 167                         struct rte_eth_rss_reta_entry64 *reta_conf,
 168                         uint16_t reta_size);
 169 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 170                         struct rte_eth_rss_reta_entry64 *reta_conf,
 171                         uint16_t reta_size);
 172 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 173 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 174 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 177                 void *param);
 178 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 179 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 180                 uint32_t index, uint32_t pool);
 181 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 182 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 183
 184 /* For Virtual Function support */
 185 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 186 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 187 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 188 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 189 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 190 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 191 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 192                 struct rte_eth_stats *stats);
 193 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 194 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 195                 uint16_t vlan_id, int on);
 196 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 197                 uint16_t queue, int on);
 198 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 199 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 200
 201 /* For Eth VMDQ APIs support */
 202 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 203                 ether_addr* mac_addr,uint8_t on);
 204 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 205 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 206                 uint16_t rx_mask, uint8_t on);
 207 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 208 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 209 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 210                 uint64_t pool_mask,uint8_t vlan_on);
 211 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 212                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 213                 uint8_t rule_id, uint8_t on);
 214 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 215                 uint8_t rule_id);
 216
 217 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 218                 uint16_t queue_idx, uint16_t tx_rate);
 219 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 220                 uint16_t tx_rate, uint64_t q_msk);
 221
 222 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 223                                  struct ether_addr *mac_addr,
 224                                  uint32_t index, uint32_t pool);
 225 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 226 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 227                         struct rte_eth_syn_filter *filter,
 228                         bool add);
 229 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 230                         struct rte_eth_syn_filter *filter);
 231 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 232                         enum rte_filter_op filter_op,
 233                         void *arg);
 234 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 235                         struct ixgbe_5tuple_filter *filter);
 236 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 237                         struct ixgbe_5tuple_filter *filter);
 238 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 239                         struct rte_eth_ntuple_filter *filter,
 240                         bool add);
 241 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 242                                 enum rte_filter_op filter_op,
 243                                 void *arg);
 244 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 245                         struct rte_eth_ntuple_filter *filter);
 246 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 247                         struct rte_eth_ethertype_filter *filter,
 248                         bool add);
 249 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 250                                 enum rte_filter_op filter_op,
 251                                 void *arg);
 252 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 253                         struct rte_eth_ethertype_filter *filter);
 254 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 255                      enum rte_filter_type filter_type,
 256                      enum rte_filter_op filter_op,
 257                      void *arg);
 258 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 259
 260 /*
 261  * Define VF Stats MACRO for Non "cleared on read" register
 262  */
 263 #define UPDATE_VF_STAT(reg, last, cur)                          \
 264 {                                                               \
 265         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 266         cur += latest - last;                                   \
 267         last = latest;                                          \
 268 }
 269
 270 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 271 {                                                                \
 272         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 273         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 274         u64 latest = ((new_msb << 32) | new_lsb);                \
 275         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 276         last = latest;                                           \
 277 }
 278
 279 #define IXGBE_SET_HWSTRIP(h, q) do{\
 280                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 281                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 282                 (h)->bitmap[idx] |= 1 << bit;\
 283         }while(0)
 284
 285 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 286                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 287                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 288                 (h)->bitmap[idx] &= ~(1 << bit);\
 289         }while(0)
 290
 291 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 292                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 293                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 294                 (r) = (h)->bitmap[idx] >> bit & 1;\
 295         }while(0)
 296
 297 /*
 298  * The set of PCI devices this driver supports
 299  */
 300 static struct rte_pci_id pci_id_ixgbe_map[] = {
 301
 302 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 303 #include "rte_pci_dev_ids.h"
 304
 305 { .vendor_id = 0, /* sentinel */ },
 306 };
 307
 308
 309 /*
 310  * The set of PCI devices this driver supports (for 82599 VF)
 311  */
 312 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 313
 314 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 315 #include "rte_pci_dev_ids.h"
 316 { .vendor_id = 0, /* sentinel */ },
 317
 318 };
 319
 320 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 321         .dev_configure        = ixgbe_dev_configure,
 322         .dev_start            = ixgbe_dev_start,
 323         .dev_stop             = ixgbe_dev_stop,
 324         .dev_set_link_up    = ixgbe_dev_set_link_up,
 325         .dev_set_link_down  = ixgbe_dev_set_link_down,
 326         .dev_close            = ixgbe_dev_close,
 327         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 328         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 329         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 330         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 331         .link_update          = ixgbe_dev_link_update,
 332         .stats_get            = ixgbe_dev_stats_get,
 333         .stats_reset          = ixgbe_dev_stats_reset,
 334         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 335         .dev_infos_get        = ixgbe_dev_info_get,
 336         .mtu_set              = ixgbe_dev_mtu_set,
 337         .vlan_filter_set      = ixgbe_vlan_filter_set,
 338         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 339         .vlan_offload_set     = ixgbe_vlan_offload_set,
 340         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 341         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 342         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 343         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 344         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 345         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 346         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 347         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 348         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 349         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 350         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 351         .dev_led_on           = ixgbe_dev_led_on,
 352         .dev_led_off          = ixgbe_dev_led_off,
 353         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 354         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 355         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 356         .mac_addr_add         = ixgbe_add_rar,
 357         .mac_addr_remove      = ixgbe_remove_rar,
 358         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 359         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 360         .mirror_rule_set      = ixgbe_mirror_rule_set,
 361         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 362         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 363         .set_vf_rx            = ixgbe_set_pool_rx,
 364         .set_vf_tx            = ixgbe_set_pool_tx,
 365         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 366         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 367         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 368         .reta_update          = ixgbe_dev_rss_reta_update,
 369         .reta_query           = ixgbe_dev_rss_reta_query,
 370 #ifdef RTE_NIC_BYPASS
 371         .bypass_init          = ixgbe_bypass_init,
 372         .bypass_state_set     = ixgbe_bypass_state_store,
 373         .bypass_state_show    = ixgbe_bypass_state_show,
 374         .bypass_event_set     = ixgbe_bypass_event_store,
 375         .bypass_event_show    = ixgbe_bypass_event_show,
 376         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 377         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 378         .bypass_ver_show      = ixgbe_bypass_ver_show,
 379         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 380 #endif /* RTE_NIC_BYPASS */
 381         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 382         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 383         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 384 };
 385
 386 /*
 387  * dev_ops for virtual function, bare necessities for basic vf
 388  * operation have been implemented
 389  */
 390 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 391         .dev_configure        = ixgbevf_dev_configure,
 392         .dev_start            = ixgbevf_dev_start,
 393         .dev_stop             = ixgbevf_dev_stop,
 394         .link_update          = ixgbe_dev_link_update,
 395         .stats_get            = ixgbevf_dev_stats_get,
 396         .stats_reset          = ixgbevf_dev_stats_reset,
 397         .dev_close            = ixgbevf_dev_close,
 398         .dev_infos_get        = ixgbevf_dev_info_get,
 399         .mtu_set              = ixgbevf_dev_set_mtu,
 400         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 401         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 402         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 403         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 404         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 405         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 406         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 407         .mac_addr_add         = ixgbevf_add_mac_addr,
 408         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 409 };
 410
 411 /**
 412  * Atomically reads the link status information from global
 413  * structure rte_eth_dev.
 414  *
 415  * @param dev
 416  *   - Pointer to the structure rte_eth_dev to read from.
 417  *   - Pointer to the buffer to be saved with the link status.
 418  *
 419  * @return
 420  *   - On success, zero.
 421  *   - On failure, negative value.
 422  */
 423 static inline int
 424 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 425                                 struct rte_eth_link *link)
 426 {
 427         struct rte_eth_link *dst = link;
 428         struct rte_eth_link *src = &(dev->data->dev_link);
 429
 430         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 431                                         *(uint64_t *)src) == 0)
 432                 return -1;
 433
 434         return 0;
 435 }
 436
 437 /**
 438  * Atomically writes the link status information into global
 439  * structure rte_eth_dev.
 440  *
 441  * @param dev
 442  *   - Pointer to the structure rte_eth_dev to read from.
 443  *   - Pointer to the buffer to be saved with the link status.
 444  *
 445  * @return
 446  *   - On success, zero.
 447  *   - On failure, negative value.
 448  */
 449 static inline int
 450 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 451                                 struct rte_eth_link *link)
 452 {
 453         struct rte_eth_link *dst = &(dev->data->dev_link);
 454         struct rte_eth_link *src = link;
 455
 456         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 457                                         *(uint64_t *)src) == 0)
 458                 return -1;
 459
 460         return 0;
 461 }
 462
 463 /*
 464  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 465  */
 466 static inline int
 467 ixgbe_is_sfp(struct ixgbe_hw *hw)
 468 {
 469         switch (hw->phy.type) {
 470         case ixgbe_phy_sfp_avago:
 471         case ixgbe_phy_sfp_ftl:
 472         case ixgbe_phy_sfp_intel:
 473         case ixgbe_phy_sfp_unknown:
 474         case ixgbe_phy_sfp_passive_tyco:
 475         case ixgbe_phy_sfp_passive_unknown:
 476                 return 1;
 477         default:
 478                 return 0;
 479         }
 480 }
 481
 482 static inline int32_t
 483 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 484 {
 485         uint32_t ctrl_ext;
 486         int32_t status;
 487
 488         status = ixgbe_reset_hw(hw);
 489
 490         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 491         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 492         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 493         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 494         IXGBE_WRITE_FLUSH(hw);
 495
 496         return status;
 497 }
 498
 499 static inline void
 500 ixgbe_enable_intr(struct rte_eth_dev *dev)
 501 {
 502         struct ixgbe_interrupt *intr =
 503                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 504         struct ixgbe_hw *hw =
 505                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 506
 507         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 508         IXGBE_WRITE_FLUSH(hw);
 509 }
 510
 511 /*
 512  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 513  */
 514 static void
 515 ixgbe_disable_intr(struct ixgbe_hw *hw)
 516 {
 517         PMD_INIT_FUNC_TRACE();
 518
 519         if (hw->mac.type == ixgbe_mac_82598EB) {
 520                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 521         } else {
 522                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 523                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 524                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 525         }
 526         IXGBE_WRITE_FLUSH(hw);
 527 }
 528
 529 /*
 530  * This function resets queue statistics mapping registers.
 531  * From Niantic datasheet, Initialization of Statistics section:
 532  * "...if software requires the queue counters, the RQSMR and TQSM registers
 533  * must be re-programmed following a device reset.
 534  */
 535 static void
 536 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 537 {
 538         uint32_t i;
 539
 540         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 541                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 542                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 543         }
 544 }
 545
 546
 547 static int
 548 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 549                                   uint16_t queue_id,
 550                                   uint8_t stat_idx,
 551                                   uint8_t is_rx)
 552 {
 553 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 554 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 555 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 556
 557         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 558         struct ixgbe_stat_mapping_registers *stat_mappings =
 559                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 560         uint32_t qsmr_mask = 0;
 561         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 562         uint32_t q_map;
 563         uint8_t n, offset;
 564
 565         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 566                 (hw->mac.type != ixgbe_mac_X540) &&
 567                 (hw->mac.type != ixgbe_mac_X550) &&
 568                 (hw->mac.type != ixgbe_mac_X550EM_x))
 569                 return -ENOSYS;
 570
 571         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 572                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 573                      queue_id, stat_idx);
 574
 575         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 576         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 577                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 578                 return -EIO;
 579         }
 580         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 581
 582         /* Now clear any previous stat_idx set */
 583         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 584         if (!is_rx)
 585                 stat_mappings->tqsm[n] &= ~clearing_mask;
 586         else
 587                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 588
 589         q_map = (uint32_t)stat_idx;
 590         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 591         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 592         if (!is_rx)
 593                 stat_mappings->tqsm[n] |= qsmr_mask;
 594         else
 595                 stat_mappings->rqsmr[n] |= qsmr_mask;
 596
 597         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 598                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 599                      queue_id, stat_idx);
 600         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 601                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 602
 603         /* Now write the mapping in the appropriate register */
 604         if (is_rx) {
 605                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 606                              stat_mappings->rqsmr[n], n);
 607                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 608         }
 609         else {
 610                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 611                              stat_mappings->tqsm[n], n);
 612                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 613         }
 614         return 0;
 615 }
 616
 617 static void
 618 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 619 {
 620         struct ixgbe_stat_mapping_registers *stat_mappings =
 621                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 622         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 623         int i;
 624
 625         /* write whatever was in stat mapping table to the NIC */
 626         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 627                 /* rx */
 628                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 629
 630                 /* tx */
 631                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 632         }
 633 }
 634
 635 static void
 636 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 637 {
 638         uint8_t i;
 639         struct ixgbe_dcb_tc_config *tc;
 640         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 641
 642         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 643         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 644         for (i = 0; i < dcb_max_tc; i++) {
 645                 tc = &dcb_config->tc_config[i];
 646                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 647                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 648                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 649                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 650                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 651                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 652                 tc->pfc = ixgbe_dcb_pfc_disabled;
 653         }
 654
 655         /* Initialize default user to priority mapping, UPx->TC0 */
 656         tc = &dcb_config->tc_config[0];
 657         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 658         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 659         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 660                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 661                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 662         }
 663         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 664         dcb_config->pfc_mode_enable = false;
 665         dcb_config->vt_mode = true;
 666         dcb_config->round_robin_enable = false;
 667         /* support all DCB capabilities in 82599 */
 668         dcb_config->support.capabilities = 0xFF;
 669
 670         /*we only support 4 Tcs for X540, X550 */
 671         if (hw->mac.type == ixgbe_mac_X540 ||
 672                 hw->mac.type == ixgbe_mac_X550 ||
 673                 hw->mac.type == ixgbe_mac_X550EM_x) {
 674                 dcb_config->num_tcs.pg_tcs = 4;
 675                 dcb_config->num_tcs.pfc_tcs = 4;
 676         }
 677 }
 678
 679 /*
 680  * Ensure that all locks are released before first NVM or PHY access
 681  */
 682 static void
 683 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 684 {
 685         uint16_t mask;
 686
 687         /*
 688          * Phy lock should not fail in this early stage. If this is the case,
 689          * it is due to an improper exit of the application.
 690          * So force the release of the faulty lock. Release of common lock
 691          * is done automatically by swfw_sync function.
 692          */
 693         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 694         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 695                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 696         }
 697         ixgbe_release_swfw_semaphore(hw, mask);
 698
 699         /*
 700          * These ones are more tricky since they are common to all ports; but
 701          * swfw_sync retries last long enough (1s) to be almost sure that if
 702          * lock can not be taken it is due to an improper lock of the
 703          * semaphore.
 704          */
 705         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 706         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 707                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 708         }
 709         ixgbe_release_swfw_semaphore(hw, mask);
 710 }
 711
 712 /*
 713  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 714  * It returns 0 on success.
 715  */
 716 static int
 717 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 718 {
 719         struct rte_pci_device *pci_dev;
 720         struct ixgbe_hw *hw =
 721                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 722         struct ixgbe_vfta * shadow_vfta =
 723                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 724         struct ixgbe_hwstrip *hwstrip =
 725                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 726         struct ixgbe_dcb_config *dcb_config =
 727                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 728         struct ixgbe_filter_info *filter_info =
 729                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 730         uint32_t ctrl_ext;
 731         uint16_t csum;
 732         int diag, i;
 733
 734         PMD_INIT_FUNC_TRACE();
 735
 736         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 737         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 738         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 739
 740         /*
 741          * For secondary processes, we don't initialise any further as primary
 742          * has already done this work. Only check we don't need a different
 743          * RX and TX function.
 744          */
 745         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 746                 struct ixgbe_tx_queue *txq;
 747                 /* TX queue function in primary, set by last queue initialized
 748                  * Tx queue may not initialized by primary process */
 749                 if (eth_dev->data->tx_queues) {
 750                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 751                         ixgbe_set_tx_function(eth_dev, txq);
 752                 } else {
 753                         /* Use default TX function if we get here */
 754                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 755                                            "Using default TX function.");
 756                 }
 757
 758                 ixgbe_set_rx_function(eth_dev);
 759
 760                 return 0;
 761         }
 762         pci_dev = eth_dev->pci_dev;
 763
 764         /* Vendor and Device ID need to be set before init of shared code */
 765         hw->device_id = pci_dev->id.device_id;
 766         hw->vendor_id = pci_dev->id.vendor_id;
 767         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 768         hw->allow_unsupported_sfp = 1;
 769
 770         /* Initialize the shared code (base driver) */
 771 #ifdef RTE_NIC_BYPASS
 772         diag = ixgbe_bypass_init_shared_code(hw);
 773 #else
 774         diag = ixgbe_init_shared_code(hw);
 775 #endif /* RTE_NIC_BYPASS */
 776
 777         if (diag != IXGBE_SUCCESS) {
 778                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 779                 return -EIO;
 780         }
 781
 782         /* pick up the PCI bus settings for reporting later */
 783         ixgbe_get_bus_info(hw);
 784
 785         /* Unlock any pending hardware semaphore */
 786         ixgbe_swfw_lock_reset(hw);
 787
 788         /* Initialize DCB configuration*/
 789         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 790         ixgbe_dcb_init(hw,dcb_config);
 791         /* Get Hardware Flow Control setting */
 792         hw->fc.requested_mode = ixgbe_fc_full;
 793         hw->fc.current_mode = ixgbe_fc_full;
 794         hw->fc.pause_time = IXGBE_FC_PAUSE;
 795         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 796                 hw->fc.low_water[i] = IXGBE_FC_LO;
 797                 hw->fc.high_water[i] = IXGBE_FC_HI;
 798         }
 799         hw->fc.send_xon = 1;
 800
 801         /* Make sure we have a good EEPROM before we read from it */
 802         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 803         if (diag != IXGBE_SUCCESS) {
 804                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 805                 return -EIO;
 806         }
 807
 808 #ifdef RTE_NIC_BYPASS
 809         diag = ixgbe_bypass_init_hw(hw);
 810 #else
 811         diag = ixgbe_init_hw(hw);
 812 #endif /* RTE_NIC_BYPASS */
 813
 814         /*
 815          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 816          * is called too soon after the kernel driver unbinding/binding occurs.
 817          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 818          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 819          * also called. See ixgbe_identify_phy_82599(). The reason for the
 820          * failure is not known, and only occuts when virtualisation features
 821          * are disabled in the bios. A delay of 100ms  was found to be enough by
 822          * trial-and-error, and is doubled to be safe.
 823          */
 824         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 825                 rte_delay_ms(200);
 826                 diag = ixgbe_init_hw(hw);
 827         }
 828
 829         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 830                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 831                     "LOM.  Please be aware there may be issues associated "
 832                     "with your hardware.");
 833                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 834                     "please contact your Intel or hardware representative "
 835                     "who provided you with this hardware.");
 836         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 837                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 838         if (diag) {
 839                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 840                 return -EIO;
 841         }
 842
 843         /* disable interrupt */
 844         ixgbe_disable_intr(hw);
 845
 846         /* reset mappings for queue statistics hw counters*/
 847         ixgbe_reset_qstat_mappings(hw);
 848
 849         /* Allocate memory for storing MAC addresses */
 850         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 851                         hw->mac.num_rar_entries, 0);
 852         if (eth_dev->data->mac_addrs == NULL) {
 853                 PMD_INIT_LOG(ERR,
 854                         "Failed to allocate %u bytes needed to store "
 855                         "MAC addresses",
 856                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 857                 return -ENOMEM;
 858         }
 859         /* Copy the permanent MAC address */
 860         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 861                         &eth_dev->data->mac_addrs[0]);
 862
 863         /* Allocate memory for storing hash filter MAC addresses */
 864         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 865                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 866         if (eth_dev->data->hash_mac_addrs == NULL) {
 867                 PMD_INIT_LOG(ERR,
 868                         "Failed to allocate %d bytes needed to store MAC addresses",
 869                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 870                 return -ENOMEM;
 871         }
 872
 873         /* initialize the vfta */
 874         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 875
 876         /* initialize the hw strip bitmap*/
 877         memset(hwstrip, 0, sizeof(*hwstrip));
 878
 879         /* initialize PF if max_vfs not zero */
 880         ixgbe_pf_host_init(eth_dev);
 881
 882         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 883         /* let hardware know driver is loaded */
 884         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 885         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 886         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 887         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 888         IXGBE_WRITE_FLUSH(hw);
 889
 890         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 891                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 892                              (int) hw->mac.type, (int) hw->phy.type,
 893                              (int) hw->phy.sfp_type);
 894         else
 895                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 896                              (int) hw->mac.type, (int) hw->phy.type);
 897
 898         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 899                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 900                         pci_dev->id.device_id);
 901
 902         rte_intr_callback_register(&(pci_dev->intr_handle),
 903                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 904
 905         /* enable uio intr after callback register */
 906         rte_intr_enable(&(pci_dev->intr_handle));
 907
 908         /* enable support intr */
 909         ixgbe_enable_intr(eth_dev);
 910
 911         /* initialize 5tuple filter list */
 912         TAILQ_INIT(&filter_info->fivetuple_list);
 913         memset(filter_info->fivetuple_mask, 0,
 914                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
 915
 916         return 0;
 917 }
 918
 919
 920 /*
 921  * Negotiate mailbox API version with the PF.
 922  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 923  * Then we try to negotiate starting with the most recent one.
 924  * If all negotiation attempts fail, then we will proceed with
 925  * the default one (ixgbe_mbox_api_10).
 926  */
 927 static void
 928 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 929 {
 930         int32_t i;
 931
 932         /* start with highest supported, proceed down */
 933         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 934                 ixgbe_mbox_api_11,
 935                 ixgbe_mbox_api_10,
 936         };
 937
 938         for (i = 0;
 939                         i != RTE_DIM(sup_ver) &&
 940                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 941                         i++)
 942                 ;
 943 }
 944
 945 static void
 946 generate_random_mac_addr(struct ether_addr *mac_addr)
 947 {
 948         uint64_t random;
 949
 950         /* Set Organizationally Unique Identifier (OUI) prefix. */
 951         mac_addr->addr_bytes[0] = 0x00;
 952         mac_addr->addr_bytes[1] = 0x09;
 953         mac_addr->addr_bytes[2] = 0xC0;
 954         /* Force indication of locally assigned MAC address. */
 955         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 956         /* Generate the last 3 bytes of the MAC address with a random number. */
 957         random = rte_rand();
 958         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 959 }
 960
 961 /*
 962  * Virtual Function device init
 963  */
 964 static int
 965 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
 966 {
 967         int diag;
 968         uint32_t tc, tcs;
 969         struct rte_pci_device *pci_dev;
 970         struct ixgbe_hw *hw =
 971                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 972         struct ixgbe_vfta * shadow_vfta =
 973                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 974         struct ixgbe_hwstrip *hwstrip =
 975                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 976         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 977
 978         PMD_INIT_FUNC_TRACE();
 979
 980         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 981         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 982         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 983
 984         /* for secondary processes, we don't initialise any further as primary
 985          * has already done this work. Only check we don't need a different
 986          * RX function */
 987         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 988                 if (eth_dev->data->scattered_rx)
 989                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 990                 return 0;
 991         }
 992
 993         pci_dev = eth_dev->pci_dev;
 994
 995         hw->device_id = pci_dev->id.device_id;
 996         hw->vendor_id = pci_dev->id.vendor_id;
 997         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 998
 999         /* initialize the vfta */
1000         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1001
1002         /* initialize the hw strip bitmap*/
1003         memset(hwstrip, 0, sizeof(*hwstrip));
1004
1005         /* Initialize the shared code (base driver) */
1006         diag = ixgbe_init_shared_code(hw);
1007         if (diag != IXGBE_SUCCESS) {
1008                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1009                 return -EIO;
1010         }
1011
1012         /* init_mailbox_params */
1013         hw->mbx.ops.init_params(hw);
1014
1015         /* Disable the interrupts for VF */
1016         ixgbevf_intr_disable(hw);
1017
1018         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1019         diag = hw->mac.ops.reset_hw(hw);
1020
1021         /*
1022          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1023          * the underlying PF driver has not assigned a MAC address to the VF.
1024          * In this case, assign a random MAC address.
1025          */
1026         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1027                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1028                 return (diag);
1029         }
1030
1031         /* negotiate mailbox API version to use with the PF. */
1032         ixgbevf_negotiate_api(hw);
1033
1034         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1035         ixgbevf_get_queues(hw, &tcs, &tc);
1036
1037         /* Allocate memory for storing MAC addresses */
1038         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1039                         hw->mac.num_rar_entries, 0);
1040         if (eth_dev->data->mac_addrs == NULL) {
1041                 PMD_INIT_LOG(ERR,
1042                         "Failed to allocate %u bytes needed to store "
1043                         "MAC addresses",
1044                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1045                 return -ENOMEM;
1046         }
1047
1048         /* Generate a random MAC address, if none was assigned by PF. */
1049         if (is_zero_ether_addr(perm_addr)) {
1050                 generate_random_mac_addr(perm_addr);
1051                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1052                 if (diag) {
1053                         rte_free(eth_dev->data->mac_addrs);
1054                         eth_dev->data->mac_addrs = NULL;
1055                         return diag;
1056                 }
1057                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1058                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1059                              "%02x:%02x:%02x:%02x:%02x:%02x",
1060                              perm_addr->addr_bytes[0],
1061                              perm_addr->addr_bytes[1],
1062                              perm_addr->addr_bytes[2],
1063                              perm_addr->addr_bytes[3],
1064                              perm_addr->addr_bytes[4],
1065                              perm_addr->addr_bytes[5]);
1066         }
1067
1068         /* Copy the permanent MAC address */
1069         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1070
1071         /* reset the hardware with the new settings */
1072         diag = hw->mac.ops.start_hw(hw);
1073         switch (diag) {
1074                 case  0:
1075                         break;
1076
1077                 default:
1078                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1079                         return (-EIO);
1080         }
1081
1082         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1083                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1084                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1085
1086         return 0;
1087 }
1088
1089 static struct eth_driver rte_ixgbe_pmd = {
1090         {
1091                 .name = "rte_ixgbe_pmd",
1092                 .id_table = pci_id_ixgbe_map,
1093                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1094         },
1095         .eth_dev_init = eth_ixgbe_dev_init,
1096         .dev_private_size = sizeof(struct ixgbe_adapter),
1097 };
1098
1099 /*
1100  * virtual function driver struct
1101  */
1102 static struct eth_driver rte_ixgbevf_pmd = {
1103         {
1104                 .name = "rte_ixgbevf_pmd",
1105                 .id_table = pci_id_ixgbevf_map,
1106                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1107         },
1108         .eth_dev_init = eth_ixgbevf_dev_init,
1109         .dev_private_size = sizeof(struct ixgbe_adapter),
1110 };
1111
1112 /*
1113  * Driver initialization routine.
1114  * Invoked once at EAL init time.
1115  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1116  */
1117 static int
1118 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1119 {
1120         PMD_INIT_FUNC_TRACE();
1121
1122         rte_eth_driver_register(&rte_ixgbe_pmd);
1123         return 0;
1124 }
1125
1126 /*
1127  * VF Driver initialization routine.
1128  * Invoked one at EAL init time.
1129  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1130  */
1131 static int
1132 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1133 {
1134         PMD_INIT_FUNC_TRACE();
1135
1136         rte_eth_driver_register(&rte_ixgbevf_pmd);
1137         return (0);
1138 }
1139
1140 static int
1141 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1142 {
1143         struct ixgbe_hw *hw =
1144                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1145         struct ixgbe_vfta * shadow_vfta =
1146                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1147         uint32_t vfta;
1148         uint32_t vid_idx;
1149         uint32_t vid_bit;
1150
1151         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1152         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1153         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1154         if (on)
1155                 vfta |= vid_bit;
1156         else
1157                 vfta &= ~vid_bit;
1158         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1159
1160         /* update local VFTA copy */
1161         shadow_vfta->vfta[vid_idx] = vfta;
1162
1163         return 0;
1164 }
1165
1166 static void
1167 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1168 {
1169         if (on)
1170                 ixgbe_vlan_hw_strip_enable(dev, queue);
1171         else
1172                 ixgbe_vlan_hw_strip_disable(dev, queue);
1173 }
1174
1175 static void
1176 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1177 {
1178         struct ixgbe_hw *hw =
1179                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1180
1181         /* Only the high 16-bits is valid */
1182         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1183 }
1184
1185 void
1186 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1187 {
1188         struct ixgbe_hw *hw =
1189                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1190         uint32_t vlnctrl;
1191
1192         PMD_INIT_FUNC_TRACE();
1193
1194         /* Filter Table Disable */
1195         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1196         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1197
1198         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1199 }
1200
1201 void
1202 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1203 {
1204         struct ixgbe_hw *hw =
1205                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1206         struct ixgbe_vfta * shadow_vfta =
1207                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1208         uint32_t vlnctrl;
1209         uint16_t i;
1210
1211         PMD_INIT_FUNC_TRACE();
1212
1213         /* Filter Table Enable */
1214         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1215         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1216         vlnctrl |= IXGBE_VLNCTRL_VFE;
1217
1218         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1219
1220         /* write whatever is in local vfta copy */
1221         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1222                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1223 }
1224
1225 static void
1226 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1227 {
1228         struct ixgbe_hwstrip *hwstrip =
1229                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1230
1231         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1232                 return;
1233
1234         if (on)
1235                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1236         else
1237                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1238 }
1239
1240 static void
1241 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1242 {
1243         struct ixgbe_hw *hw =
1244                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1245         uint32_t ctrl;
1246
1247         PMD_INIT_FUNC_TRACE();
1248
1249         if (hw->mac.type == ixgbe_mac_82598EB) {
1250                 /* No queue level support */
1251                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1252                 return;
1253         }
1254         else {
1255                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1256                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1257                 ctrl &= ~IXGBE_RXDCTL_VME;
1258                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1259         }
1260         /* record those setting for HW strip per queue */
1261         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1262 }
1263
1264 static void
1265 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1266 {
1267         struct ixgbe_hw *hw =
1268                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1269         uint32_t ctrl;
1270
1271         PMD_INIT_FUNC_TRACE();
1272
1273         if (hw->mac.type == ixgbe_mac_82598EB) {
1274                 /* No queue level supported */
1275                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1276                 return;
1277         }
1278         else {
1279                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1280                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1281                 ctrl |= IXGBE_RXDCTL_VME;
1282                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1283         }
1284         /* record those setting for HW strip per queue */
1285         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1286 }
1287
1288 void
1289 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1290 {
1291         struct ixgbe_hw *hw =
1292                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1293         uint32_t ctrl;
1294         uint16_t i;
1295
1296         PMD_INIT_FUNC_TRACE();
1297
1298         if (hw->mac.type == ixgbe_mac_82598EB) {
1299                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1300                 ctrl &= ~IXGBE_VLNCTRL_VME;
1301                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1302         }
1303         else {
1304                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1305                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1306                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1307                         ctrl &= ~IXGBE_RXDCTL_VME;
1308                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1309
1310                         /* record those setting for HW strip per queue */
1311                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1312                 }
1313         }
1314 }
1315
1316 void
1317 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1318 {
1319         struct ixgbe_hw *hw =
1320                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1321         uint32_t ctrl;
1322         uint16_t i;
1323
1324         PMD_INIT_FUNC_TRACE();
1325
1326         if (hw->mac.type == ixgbe_mac_82598EB) {
1327                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1328                 ctrl |= IXGBE_VLNCTRL_VME;
1329                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1330         }
1331         else {
1332                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1333                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1334                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1335                         ctrl |= IXGBE_RXDCTL_VME;
1336                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1337
1338                         /* record those setting for HW strip per queue */
1339                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1340                 }
1341         }
1342 }
1343
1344 static void
1345 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1346 {
1347         struct ixgbe_hw *hw =
1348                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349         uint32_t ctrl;
1350
1351         PMD_INIT_FUNC_TRACE();
1352
1353         /* DMATXCTRL: Geric Double VLAN Disable */
1354         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1355         ctrl &= ~IXGBE_DMATXCTL_GDV;
1356         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1357
1358         /* CTRL_EXT: Global Double VLAN Disable */
1359         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1360         ctrl &= ~IXGBE_EXTENDED_VLAN;
1361         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1362
1363 }
1364
1365 static void
1366 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1367 {
1368         struct ixgbe_hw *hw =
1369                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1370         uint32_t ctrl;
1371
1372         PMD_INIT_FUNC_TRACE();
1373
1374         /* DMATXCTRL: Geric Double VLAN Enable */
1375         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1376         ctrl |= IXGBE_DMATXCTL_GDV;
1377         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1378
1379         /* CTRL_EXT: Global Double VLAN Enable */
1380         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1381         ctrl |= IXGBE_EXTENDED_VLAN;
1382         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1383
1384         /*
1385          * VET EXT field in the EXVET register = 0x8100 by default
1386          * So no need to change. Same to VT field of DMATXCTL register
1387          */
1388 }
1389
1390 static void
1391 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1392 {
1393         if(mask & ETH_VLAN_STRIP_MASK){
1394                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1395                         ixgbe_vlan_hw_strip_enable_all(dev);
1396                 else
1397                         ixgbe_vlan_hw_strip_disable_all(dev);
1398         }
1399
1400         if(mask & ETH_VLAN_FILTER_MASK){
1401                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1402                         ixgbe_vlan_hw_filter_enable(dev);
1403                 else
1404                         ixgbe_vlan_hw_filter_disable(dev);
1405         }
1406
1407         if(mask & ETH_VLAN_EXTEND_MASK){
1408                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1409                         ixgbe_vlan_hw_extend_enable(dev);
1410                 else
1411                         ixgbe_vlan_hw_extend_disable(dev);
1412         }
1413 }
1414
1415 static void
1416 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1417 {
1418         struct ixgbe_hw *hw =
1419                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1420         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1421         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1422         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1423         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1424 }
1425
1426 static int
1427 ixgbe_dev_configure(struct rte_eth_dev *dev)
1428 {
1429         struct ixgbe_interrupt *intr =
1430                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1431         struct ixgbe_hw *hw =
1432                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1433
1434         PMD_INIT_FUNC_TRACE();
1435
1436         /* set flag to update link status after init */
1437         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1438
1439         /*
1440          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1441          * allocation or vector Rx preconditions we will reset it.
1442          */
1443         hw->rx_bulk_alloc_allowed = true;
1444         hw->rx_vec_allowed = true;
1445
1446         return 0;
1447 }
1448
1449 /*
1450  * Configure device link speed and setup link.
1451  * It returns 0 on success.
1452  */
1453 static int
1454 ixgbe_dev_start(struct rte_eth_dev *dev)
1455 {
1456         struct ixgbe_hw *hw =
1457                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1458         struct ixgbe_vf_info *vfinfo =
1459                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1460         int err, link_up = 0, negotiate = 0;
1461         uint32_t speed = 0;
1462         int mask = 0;
1463         int status;
1464         uint16_t vf, idx;
1465
1466         PMD_INIT_FUNC_TRACE();
1467
1468         /* IXGBE devices don't support half duplex */
1469         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1470                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1471                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1472                              dev->data->dev_conf.link_duplex,
1473                              dev->data->port_id);
1474                 return -EINVAL;
1475         }
1476
1477         /* stop adapter */
1478         hw->adapter_stopped = FALSE;
1479         ixgbe_stop_adapter(hw);
1480
1481         /* reinitialize adapter
1482          * this calls reset and start */
1483         status = ixgbe_pf_reset_hw(hw);
1484         if (status != 0)
1485                 return -1;
1486         hw->mac.ops.start_hw(hw);
1487         hw->mac.get_link_status = true;
1488
1489         /* configure PF module if SRIOV enabled */
1490         ixgbe_pf_host_configure(dev);
1491
1492         /* initialize transmission unit */
1493         ixgbe_dev_tx_init(dev);
1494
1495         /* This can fail when allocating mbufs for descriptor rings */
1496         err = ixgbe_dev_rx_init(dev);
1497         if (err) {
1498                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1499                 goto error;
1500         }
1501
1502         err = ixgbe_dev_rxtx_start(dev);
1503         if (err < 0) {
1504                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1505                 goto error;
1506         }
1507
1508         /* Skip link setup if loopback mode is enabled for 82599. */
1509         if (hw->mac.type == ixgbe_mac_82599EB &&
1510                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1511                 goto skip_link_setup;
1512
1513         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1514                 err = hw->mac.ops.setup_sfp(hw);
1515                 if (err)
1516                         goto error;
1517         }
1518
1519         /* Turn on the laser */
1520         ixgbe_enable_tx_laser(hw);
1521
1522         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1523         if (err)
1524                 goto error;
1525         dev->data->dev_link.link_status = link_up;
1526
1527         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1528         if (err)
1529                 goto error;
1530
1531         switch(dev->data->dev_conf.link_speed) {
1532         case ETH_LINK_SPEED_AUTONEG:
1533                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1534                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1535                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1536                 break;
1537         case ETH_LINK_SPEED_100:
1538                 /*
1539                  * Invalid for 82598 but error will be detected by
1540                  * ixgbe_setup_link()
1541                  */
1542                 speed = IXGBE_LINK_SPEED_100_FULL;
1543                 break;
1544         case ETH_LINK_SPEED_1000:
1545                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1546                 break;
1547         case ETH_LINK_SPEED_10000:
1548                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1549                 break;
1550         default:
1551                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1552                              dev->data->dev_conf.link_speed,
1553                              dev->data->port_id);
1554                 goto error;
1555         }
1556
1557         err = ixgbe_setup_link(hw, speed, link_up);
1558         if (err)
1559                 goto error;
1560
1561 skip_link_setup:
1562
1563         /* check if lsc interrupt is enabled */
1564         if (dev->data->dev_conf.intr_conf.lsc != 0)
1565                 ixgbe_dev_lsc_interrupt_setup(dev);
1566
1567         /* resume enabled intr since hw reset */
1568         ixgbe_enable_intr(dev);
1569
1570         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1571                 ETH_VLAN_EXTEND_MASK;
1572         ixgbe_vlan_offload_set(dev, mask);
1573
1574         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1575                 /* Enable vlan filtering for VMDq */
1576                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1577         }
1578
1579         /* Configure DCB hw */
1580         ixgbe_configure_dcb(dev);
1581
1582         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1583                 err = ixgbe_fdir_configure(dev);
1584                 if (err)
1585                         goto error;
1586         }
1587
1588         /* Restore vf rate limit */
1589         if (vfinfo != NULL) {
1590                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1591                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1592                                 if (vfinfo[vf].tx_rate[idx] != 0)
1593                                         ixgbe_set_vf_rate_limit(dev, vf,
1594                                                 vfinfo[vf].tx_rate[idx],
1595                                                 1 << idx);
1596         }
1597
1598         ixgbe_restore_statistics_mapping(dev);
1599
1600         return (0);
1601
1602 error:
1603         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1604         ixgbe_dev_clear_queues(dev);
1605         return -EIO;
1606 }
1607
1608 /*
1609  * Stop device: disable rx and tx functions to allow for reconfiguring.
1610  */
1611 static void
1612 ixgbe_dev_stop(struct rte_eth_dev *dev)
1613 {
1614         struct rte_eth_link link;
1615         struct ixgbe_hw *hw =
1616                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1617         struct ixgbe_vf_info *vfinfo =
1618                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1619         struct ixgbe_filter_info *filter_info =
1620                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1621         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1622         int vf;
1623
1624         PMD_INIT_FUNC_TRACE();
1625
1626         /* disable interrupts */
1627         ixgbe_disable_intr(hw);
1628
1629         /* reset the NIC */
1630         ixgbe_pf_reset_hw(hw);
1631         hw->adapter_stopped = FALSE;
1632
1633         /* stop adapter */
1634         ixgbe_stop_adapter(hw);
1635
1636         for (vf = 0; vfinfo != NULL &&
1637                      vf < dev->pci_dev->max_vfs; vf++)
1638                 vfinfo[vf].clear_to_send = false;
1639
1640         /* Turn off the laser */
1641         ixgbe_disable_tx_laser(hw);
1642
1643         ixgbe_dev_clear_queues(dev);
1644
1645         /* Clear stored conf */
1646         dev->data->scattered_rx = 0;
1647
1648         /* Clear recorded link status */
1649         memset(&link, 0, sizeof(link));
1650         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1651
1652         /* Remove all ntuple filters of the device */
1653         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1654              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1655                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1656                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1657                              p_5tuple, entries);
1658                 rte_free(p_5tuple);
1659         }
1660         memset(filter_info->fivetuple_mask, 0,
1661                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1662
1663 }
1664
1665 /*
1666  * Set device link up: enable tx laser.
1667  */
1668 static int
1669 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1670 {
1671         struct ixgbe_hw *hw =
1672                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1673         if (hw->mac.type == ixgbe_mac_82599EB) {
1674 #ifdef RTE_NIC_BYPASS
1675                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1676                         /* Not suported in bypass mode */
1677                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1678                                      "by device id 0x%x", hw->device_id);
1679                         return -ENOTSUP;
1680                 }
1681 #endif
1682                 /* Turn on the laser */
1683                 ixgbe_enable_tx_laser(hw);
1684                 return 0;
1685         }
1686
1687         PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1688                      hw->device_id);
1689         return -ENOTSUP;
1690 }
1691
1692 /*
1693  * Set device link down: disable tx laser.
1694  */
1695 static int
1696 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1697 {
1698         struct ixgbe_hw *hw =
1699                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1700         if (hw->mac.type == ixgbe_mac_82599EB) {
1701 #ifdef RTE_NIC_BYPASS
1702                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1703                         /* Not suported in bypass mode */
1704                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1705                                      "by device id 0x%x", hw->device_id);
1706                         return -ENOTSUP;
1707                 }
1708 #endif
1709                 /* Turn off the laser */
1710                 ixgbe_disable_tx_laser(hw);
1711                 return 0;
1712         }
1713
1714         PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1715                      hw->device_id);
1716         return -ENOTSUP;
1717 }
1718
1719 /*
1720  * Reest and stop device.
1721  */
1722 static void
1723 ixgbe_dev_close(struct rte_eth_dev *dev)
1724 {
1725         struct ixgbe_hw *hw =
1726                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1727
1728         PMD_INIT_FUNC_TRACE();
1729
1730         ixgbe_pf_reset_hw(hw);
1731
1732         ixgbe_dev_stop(dev);
1733         hw->adapter_stopped = 1;
1734
1735         ixgbe_disable_pcie_master(hw);
1736
1737         /* reprogram the RAR[0] in case user changed it. */
1738         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1739 }
1740
1741 /*
1742  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1743  */
1744 static void
1745 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1746 {
1747         struct ixgbe_hw *hw =
1748                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1749         struct ixgbe_hw_stats *hw_stats =
1750                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1751         uint32_t bprc, lxon, lxoff, total;
1752         uint64_t total_missed_rx, total_qbrc, total_qprc;
1753         unsigned i;
1754
1755         total_missed_rx = 0;
1756         total_qbrc = 0;
1757         total_qprc = 0;
1758
1759         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1760         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1761         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1762         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1763
1764         for (i = 0; i < 8; i++) {
1765                 uint32_t mp;
1766                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1767                 /* global total per queue */
1768                 hw_stats->mpc[i] += mp;
1769                 /* Running comprehensive total for stats display */
1770                 total_missed_rx += hw_stats->mpc[i];
1771                 if (hw->mac.type == ixgbe_mac_82598EB)
1772                         hw_stats->rnbc[i] +=
1773                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1774                 hw_stats->pxontxc[i] +=
1775                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1776                 hw_stats->pxonrxc[i] +=
1777                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1778                 hw_stats->pxofftxc[i] +=
1779                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1780                 hw_stats->pxoffrxc[i] +=
1781                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1782                 hw_stats->pxon2offc[i] +=
1783                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1784         }
1785         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1786                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1787                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1788                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1789                 hw_stats->qbrc[i] +=
1790                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1791                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1792                 hw_stats->qbtc[i] +=
1793                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1794                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1795
1796                 total_qprc += hw_stats->qprc[i];
1797                 total_qbrc += hw_stats->qbrc[i];
1798         }
1799         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1800         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1801         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1802
1803         /* Note that gprc counts missed packets */
1804         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1805
1806         if (hw->mac.type != ixgbe_mac_82598EB) {
1807                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1808                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1809                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1810                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1811                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1812                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1813                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1814                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1815         } else {
1816                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1817                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1818                 /* 82598 only has a counter in the high register */
1819                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1820                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1821                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1822         }
1823
1824         /*
1825          * Workaround: mprc hardware is incorrectly counting
1826          * broadcasts, so for now we subtract those.
1827          */
1828         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1829         hw_stats->bprc += bprc;
1830         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1831         if (hw->mac.type == ixgbe_mac_82598EB)
1832                 hw_stats->mprc -= bprc;
1833
1834         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1835         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1836         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1837         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1838         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1839         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1840
1841         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1842         hw_stats->lxontxc += lxon;
1843         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1844         hw_stats->lxofftxc += lxoff;
1845         total = lxon + lxoff;
1846
1847         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1848         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1849         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1850         hw_stats->gptc -= total;
1851         hw_stats->mptc -= total;
1852         hw_stats->ptc64 -= total;
1853         hw_stats->gotc -= total * ETHER_MIN_LEN;
1854
1855         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1856         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1857         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1858         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1859         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1860         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1861         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1862         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1863         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1864         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1865         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1866         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1867         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1868         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1869         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1870         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1871         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1872         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1873         /* Only read FCOE on 82599 */
1874         if (hw->mac.type != ixgbe_mac_82598EB) {
1875                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1876                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1877                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1878                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1879                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1880         }
1881
1882         if (stats == NULL)
1883                 return;
1884
1885         /* Fill out the rte_eth_stats statistics structure */
1886         stats->ipackets = total_qprc;
1887         stats->ibytes = total_qbrc;
1888         stats->opackets = hw_stats->gptc;
1889         stats->obytes = hw_stats->gotc;
1890         stats->imcasts = hw_stats->mprc;
1891
1892         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1893                 stats->q_ipackets[i] = hw_stats->qprc[i];
1894                 stats->q_opackets[i] = hw_stats->qptc[i];
1895                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1896                 stats->q_obytes[i] = hw_stats->qbtc[i];
1897                 stats->q_errors[i] = hw_stats->qprdc[i];
1898         }
1899
1900         /* Rx Errors */
1901         stats->ibadcrc  = hw_stats->crcerrs;
1902         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1903         stats->imissed  = total_missed_rx;
1904         stats->ierrors  = stats->ibadcrc +
1905                           stats->ibadlen +
1906                           stats->imissed +
1907                           hw_stats->illerrc + hw_stats->errbc;
1908
1909         /* Tx Errors */
1910         stats->oerrors  = 0;
1911
1912         /* XON/XOFF pause frames */
1913         stats->tx_pause_xon  = hw_stats->lxontxc;
1914         stats->rx_pause_xon  = hw_stats->lxonrxc;
1915         stats->tx_pause_xoff = hw_stats->lxofftxc;
1916         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1917
1918         /* Flow Director Stats registers */
1919         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1920         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1921         stats->fdirmatch = hw_stats->fdirmatch;
1922         stats->fdirmiss = hw_stats->fdirmiss;
1923 }
1924
1925 static void
1926 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1927 {
1928         struct ixgbe_hw_stats *stats =
1929                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1930
1931         /* HW registers are cleared on read */
1932         ixgbe_dev_stats_get(dev, NULL);
1933
1934         /* Reset software totals */
1935         memset(stats, 0, sizeof(*stats));
1936 }
1937
1938 static void
1939 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1940 {
1941         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1943                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1944
1945         /* Good Rx packet, include VF loopback */
1946         UPDATE_VF_STAT(IXGBE_VFGPRC,
1947             hw_stats->last_vfgprc, hw_stats->vfgprc);
1948
1949         /* Good Rx octets, include VF loopback */
1950         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1951             hw_stats->last_vfgorc, hw_stats->vfgorc);
1952
1953         /* Good Tx packet, include VF loopback */
1954         UPDATE_VF_STAT(IXGBE_VFGPTC,
1955             hw_stats->last_vfgptc, hw_stats->vfgptc);
1956
1957         /* Good Tx octets, include VF loopback */
1958         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1959             hw_stats->last_vfgotc, hw_stats->vfgotc);
1960
1961         /* Rx Multicst Packet */
1962         UPDATE_VF_STAT(IXGBE_VFMPRC,
1963             hw_stats->last_vfmprc, hw_stats->vfmprc);
1964
1965         if (stats == NULL)
1966                 return;
1967
1968         stats->ipackets = hw_stats->vfgprc;
1969         stats->ibytes = hw_stats->vfgorc;
1970         stats->opackets = hw_stats->vfgptc;
1971         stats->obytes = hw_stats->vfgotc;
1972         stats->imcasts = hw_stats->vfmprc;
1973 }
1974
1975 static void
1976 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1977 {
1978         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1979                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1980
1981         /* Sync HW register to the last stats */
1982         ixgbevf_dev_stats_get(dev, NULL);
1983
1984         /* reset HW current stats*/
1985         hw_stats->vfgprc = 0;
1986         hw_stats->vfgorc = 0;
1987         hw_stats->vfgptc = 0;
1988         hw_stats->vfgotc = 0;
1989         hw_stats->vfmprc = 0;
1990
1991 }
1992
1993 static void
1994 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1995 {
1996         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1997
1998         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1999         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2000         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2001         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2002         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2003         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2004         dev_info->max_vfs = dev->pci_dev->max_vfs;
2005         if (hw->mac.type == ixgbe_mac_82598EB)
2006                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2007         else
2008                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2009         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2010         dev_info->rx_offload_capa =
2011                 DEV_RX_OFFLOAD_VLAN_STRIP |
2012                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2013                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2014                 DEV_RX_OFFLOAD_TCP_CKSUM;
2015         dev_info->tx_offload_capa =
2016                 DEV_TX_OFFLOAD_VLAN_INSERT |
2017                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2018                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2019                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2020                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2021                 DEV_TX_OFFLOAD_TCP_TSO;
2022
2023         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2024                 .rx_thresh = {
2025                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2026                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2027                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2028                 },
2029                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2030                 .rx_drop_en = 0,
2031         };
2032
2033         dev_info->default_txconf = (struct rte_eth_txconf) {
2034                 .tx_thresh = {
2035                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2036                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2037                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2038                 },
2039                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2040                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2041                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2042                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2043         };
2044         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2045         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2046 }
2047
2048 static void
2049 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2050                      struct rte_eth_dev_info *dev_info)
2051 {
2052         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2053
2054         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2055         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2056         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2057         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2058         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2059         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2060         dev_info->max_vfs = dev->pci_dev->max_vfs;
2061         if (hw->mac.type == ixgbe_mac_82598EB)
2062                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2063         else
2064                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2065         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2066                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2067                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2068                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2069         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2070                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2071                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2072                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2073                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2074
2075         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2076                 .rx_thresh = {
2077                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2078                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2079                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2080                 },
2081                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2082                 .rx_drop_en = 0,
2083         };
2084
2085         dev_info->default_txconf = (struct rte_eth_txconf) {
2086                 .tx_thresh = {
2087                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2088                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2089                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2090                 },
2091                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2092                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2093                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2094                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2095         };
2096 }
2097
2098 /* return 0 means link status changed, -1 means not changed */
2099 static int
2100 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2101 {
2102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103         struct rte_eth_link link, old;
2104         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2105         int link_up;
2106         int diag;
2107
2108         link.link_status = 0;
2109         link.link_speed = 0;
2110         link.link_duplex = 0;
2111         memset(&old, 0, sizeof(old));
2112         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2113
2114         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2115         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2116                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2117         else
2118                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2119         if (diag != 0) {
2120                 link.link_speed = ETH_LINK_SPEED_100;
2121                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2122                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2123                 if (link.link_status == old.link_status)
2124                         return -1;
2125                 return 0;
2126         }
2127
2128         if (link_speed == IXGBE_LINK_SPEED_UNKNOWN &&
2129             !hw->mac.get_link_status) {
2130                 memcpy(&link, &old, sizeof(link));
2131                 return -1;
2132         }
2133
2134         if (link_up == 0) {
2135                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2136                 if (link.link_status == old.link_status)
2137                         return -1;
2138                 return 0;
2139         }
2140         link.link_status = 1;
2141         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2142
2143         switch (link_speed) {
2144         default:
2145         case IXGBE_LINK_SPEED_UNKNOWN:
2146                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2147                 link.link_speed = ETH_LINK_SPEED_100;
2148                 break;
2149
2150         case IXGBE_LINK_SPEED_100_FULL:
2151                 link.link_speed = ETH_LINK_SPEED_100;
2152                 break;
2153
2154         case IXGBE_LINK_SPEED_1GB_FULL:
2155                 link.link_speed = ETH_LINK_SPEED_1000;
2156                 break;
2157
2158         case IXGBE_LINK_SPEED_10GB_FULL:
2159                 link.link_speed = ETH_LINK_SPEED_10000;
2160                 break;
2161         }
2162         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2163
2164         if (link.link_status == old.link_status)
2165                 return -1;
2166
2167         return 0;
2168 }
2169
2170 static void
2171 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2172 {
2173         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2174         uint32_t fctrl;
2175
2176         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2177         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2178         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2179 }
2180
2181 static void
2182 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2183 {
2184         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2185         uint32_t fctrl;
2186
2187         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2188         fctrl &= (~IXGBE_FCTRL_UPE);
2189         if (dev->data->all_multicast == 1)
2190                 fctrl |= IXGBE_FCTRL_MPE;
2191         else
2192                 fctrl &= (~IXGBE_FCTRL_MPE);
2193         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2194 }
2195
2196 static void
2197 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2198 {
2199         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200         uint32_t fctrl;
2201
2202         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2203         fctrl |= IXGBE_FCTRL_MPE;
2204         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2205 }
2206
2207 static void
2208 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2209 {
2210         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2211         uint32_t fctrl;
2212
2213         if (dev->data->promiscuous == 1)
2214                 return; /* must remain in all_multicast mode */
2215
2216         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2217         fctrl &= (~IXGBE_FCTRL_MPE);
2218         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2219 }
2220
2221 /**
2222  * It clears the interrupt causes and enables the interrupt.
2223  * It will be called once only during nic initialized.
2224  *
2225  * @param dev
2226  *  Pointer to struct rte_eth_dev.
2227  *
2228  * @return
2229  *  - On success, zero.
2230  *  - On failure, a negative value.
2231  */
2232 static int
2233 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2234 {
2235         struct ixgbe_interrupt *intr =
2236                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2237
2238         ixgbe_dev_link_status_print(dev);
2239         intr->mask |= IXGBE_EICR_LSC;
2240
2241         return 0;
2242 }
2243
2244 /*
2245  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2246  *
2247  * @param dev
2248  *  Pointer to struct rte_eth_dev.
2249  *
2250  * @return
2251  *  - On success, zero.
2252  *  - On failure, a negative value.
2253  */
2254 static int
2255 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2256 {
2257         uint32_t eicr;
2258         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2259         struct ixgbe_interrupt *intr =
2260                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2261
2262         /* clear all cause mask */
2263         ixgbe_disable_intr(hw);
2264
2265         /* read-on-clear nic registers here */
2266         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2267         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2268
2269         intr->flags = 0;
2270         if (eicr & IXGBE_EICR_LSC) {
2271                 /* set flag for async link update */
2272                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2273         }
2274
2275         if (eicr & IXGBE_EICR_MAILBOX)
2276                 intr->flags |= IXGBE_FLAG_MAILBOX;
2277
2278         return 0;
2279 }
2280
2281 /**
2282  * It gets and then prints the link status.
2283  *
2284  * @param dev
2285  *  Pointer to struct rte_eth_dev.
2286  *
2287  * @return
2288  *  - On success, zero.
2289  *  - On failure, a negative value.
2290  */
2291 static void
2292 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2293 {
2294         struct rte_eth_link link;
2295
2296         memset(&link, 0, sizeof(link));
2297         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2298         if (link.link_status) {
2299                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2300                                         (int)(dev->data->port_id),
2301                                         (unsigned)link.link_speed,
2302                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2303                                         "full-duplex" : "half-duplex");
2304         } else {
2305                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2306                                 (int)(dev->data->port_id));
2307         }
2308         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2309                                 dev->pci_dev->addr.domain,
2310                                 dev->pci_dev->addr.bus,
2311                                 dev->pci_dev->addr.devid,
2312                                 dev->pci_dev->addr.function);
2313 }
2314
2315 /*
2316  * It executes link_update after knowing an interrupt occurred.
2317  *
2318  * @param dev
2319  *  Pointer to struct rte_eth_dev.
2320  *
2321  * @return
2322  *  - On success, zero.
2323  *  - On failure, a negative value.
2324  */
2325 static int
2326 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2327 {
2328         struct ixgbe_interrupt *intr =
2329                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2330         int64_t timeout;
2331         struct rte_eth_link link;
2332         int intr_enable_delay = false;
2333
2334         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2335
2336         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2337                 ixgbe_pf_mbx_process(dev);
2338                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2339         }
2340
2341         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2342                 /* get the link status before link update, for predicting later */
2343                 memset(&link, 0, sizeof(link));
2344                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2345
2346                 ixgbe_dev_link_update(dev, 0);
2347
2348                 /* likely to up */
2349                 if (!link.link_status)
2350                         /* handle it 1 sec later, wait it being stable */
2351                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2352                 /* likely to down */
2353                 else
2354                         /* handle it 4 sec later, wait it being stable */
2355                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2356
2357                 ixgbe_dev_link_status_print(dev);
2358
2359                 intr_enable_delay = true;
2360         }
2361
2362         if (intr_enable_delay) {
2363                 if (rte_eal_alarm_set(timeout * 1000,
2364                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2365                         PMD_DRV_LOG(ERR, "Error setting alarm");
2366         } else {
2367                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2368                 ixgbe_enable_intr(dev);
2369                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2370         }
2371
2372
2373         return 0;
2374 }
2375
2376 /**
2377  * Interrupt handler which shall be registered for alarm callback for delayed
2378  * handling specific interrupt to wait for the stable nic state. As the
2379  * NIC interrupt state is not stable for ixgbe after link is just down,
2380  * it needs to wait 4 seconds to get the stable status.
2381  *
2382  * @param handle
2383  *  Pointer to interrupt handle.
2384  * @param param
2385  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2386  *
2387  * @return
2388  *  void
2389  */
2390 static void
2391 ixgbe_dev_interrupt_delayed_handler(void *param)
2392 {
2393         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2394         struct ixgbe_interrupt *intr =
2395                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2396         struct ixgbe_hw *hw =
2397                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2398         uint32_t eicr;
2399
2400         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2401         if (eicr & IXGBE_EICR_MAILBOX)
2402                 ixgbe_pf_mbx_process(dev);
2403
2404         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2405                 ixgbe_dev_link_update(dev, 0);
2406                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2407                 ixgbe_dev_link_status_print(dev);
2408                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2409         }
2410
2411         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2412         ixgbe_enable_intr(dev);
2413         rte_intr_enable(&(dev->pci_dev->intr_handle));
2414 }
2415
2416 /**
2417  * Interrupt handler triggered by NIC  for handling
2418  * specific interrupt.
2419  *
2420  * @param handle
2421  *  Pointer to interrupt handle.
2422  * @param param
2423  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2424  *
2425  * @return
2426  *  void
2427  */
2428 static void
2429 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2430                                                         void *param)
2431 {
2432         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2433         ixgbe_dev_interrupt_get_status(dev);
2434         ixgbe_dev_interrupt_action(dev);
2435 }
2436
2437 static int
2438 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2439 {
2440         struct ixgbe_hw *hw;
2441
2442         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2443         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2444 }
2445
2446 static int
2447 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2448 {
2449         struct ixgbe_hw *hw;
2450
2451         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2452         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2453 }
2454
2455 static int
2456 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2457 {
2458         struct ixgbe_hw *hw;
2459         uint32_t mflcn_reg;
2460         uint32_t fccfg_reg;
2461         int rx_pause;
2462         int tx_pause;
2463
2464         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465
2466         fc_conf->pause_time = hw->fc.pause_time;
2467         fc_conf->high_water = hw->fc.high_water[0];
2468         fc_conf->low_water = hw->fc.low_water[0];
2469         fc_conf->send_xon = hw->fc.send_xon;
2470         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2471
2472         /*
2473          * Return rx_pause status according to actual setting of
2474          * MFLCN register.
2475          */
2476         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2477         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2478                 rx_pause = 1;
2479         else
2480                 rx_pause = 0;
2481
2482         /*
2483          * Return tx_pause status according to actual setting of
2484          * FCCFG register.
2485          */
2486         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2487         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2488                 tx_pause = 1;
2489         else
2490                 tx_pause = 0;
2491
2492         if (rx_pause && tx_pause)
2493                 fc_conf->mode = RTE_FC_FULL;
2494         else if (rx_pause)
2495                 fc_conf->mode = RTE_FC_RX_PAUSE;
2496         else if (tx_pause)
2497                 fc_conf->mode = RTE_FC_TX_PAUSE;
2498         else
2499                 fc_conf->mode = RTE_FC_NONE;
2500
2501         return 0;
2502 }
2503
2504 static int
2505 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2506 {
2507         struct ixgbe_hw *hw;
2508         int err;
2509         uint32_t rx_buf_size;
2510         uint32_t max_high_water;
2511         uint32_t mflcn;
2512         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2513                 ixgbe_fc_none,
2514                 ixgbe_fc_rx_pause,
2515                 ixgbe_fc_tx_pause,
2516                 ixgbe_fc_full
2517         };
2518
2519         PMD_INIT_FUNC_TRACE();
2520
2521         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2522         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2523                 return -ENOTSUP;
2524         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2525         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2526
2527         /*
2528          * At least reserve one Ethernet frame for watermark
2529          * high_water/low_water in kilo bytes for ixgbe
2530          */
2531         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2532         if ((fc_conf->high_water > max_high_water) ||
2533                 (fc_conf->high_water < fc_conf->low_water)) {
2534                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2535                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2536                 return (-EINVAL);
2537         }
2538
2539         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2540         hw->fc.pause_time     = fc_conf->pause_time;
2541         hw->fc.high_water[0]  = fc_conf->high_water;
2542         hw->fc.low_water[0]   = fc_conf->low_water;
2543         hw->fc.send_xon       = fc_conf->send_xon;
2544
2545         err = ixgbe_fc_enable(hw);
2546
2547         /* Not negotiated is not an error case */
2548         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2549
2550                 /* check if we want to forward MAC frames - driver doesn't have native
2551                  * capability to do that, so we'll write the registers ourselves */
2552
2553                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2554
2555                 /* set or clear MFLCN.PMCF bit depending on configuration */
2556                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2557                         mflcn |= IXGBE_MFLCN_PMCF;
2558                 else
2559                         mflcn &= ~IXGBE_MFLCN_PMCF;
2560
2561                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2562                 IXGBE_WRITE_FLUSH(hw);
2563
2564                 return 0;
2565         }
2566
2567         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2568         return -EIO;
2569 }
2570
2571 /**
2572  *  ixgbe_pfc_enable_generic - Enable flow control
2573  *  @hw: pointer to hardware structure
2574  *  @tc_num: traffic class number
2575  *  Enable flow control according to the current settings.
2576  */
2577 static int
2578 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2579 {
2580         int ret_val = 0;
2581         uint32_t mflcn_reg, fccfg_reg;
2582         uint32_t reg;
2583         uint32_t fcrtl, fcrth;
2584         uint8_t i;
2585         uint8_t nb_rx_en;
2586
2587         /* Validate the water mark configuration */
2588         if (!hw->fc.pause_time) {
2589                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2590                 goto out;
2591         }
2592
2593         /* Low water mark of zero causes XOFF floods */
2594         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2595                  /* High/Low water can not be 0 */
2596                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2597                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2598                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2599                         goto out;
2600                 }
2601
2602                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2603                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2604                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2605                         goto out;
2606                 }
2607         }
2608         /* Negotiate the fc mode to use */
2609         ixgbe_fc_autoneg(hw);
2610
2611         /* Disable any previous flow control settings */
2612         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2613         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2614
2615         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2616         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2617
2618         switch (hw->fc.current_mode) {
2619         case ixgbe_fc_none:
2620                 /*
2621                  * If the count of enabled RX Priority Flow control >1,
2622                  * and the TX pause can not be disabled
2623                  */
2624                 nb_rx_en = 0;
2625                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2626                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2627                         if (reg & IXGBE_FCRTH_FCEN)
2628                                 nb_rx_en++;
2629                 }
2630                 if (nb_rx_en > 1)
2631                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2632                 break;
2633         case ixgbe_fc_rx_pause:
2634                 /*
2635                  * Rx Flow control is enabled and Tx Flow control is
2636                  * disabled by software override. Since there really
2637                  * isn't a way to advertise that we are capable of RX
2638                  * Pause ONLY, we will advertise that we support both
2639                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2640                  * disable the adapter's ability to send PAUSE frames.
2641                  */
2642                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2643                 /*
2644                  * If the count of enabled RX Priority Flow control >1,
2645                  * and the TX pause can not be disabled
2646                  */
2647                 nb_rx_en = 0;
2648                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2649                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2650                         if (reg & IXGBE_FCRTH_FCEN)
2651                                 nb_rx_en++;
2652                 }
2653                 if (nb_rx_en > 1)
2654                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2655                 break;
2656         case ixgbe_fc_tx_pause:
2657                 /*
2658                  * Tx Flow control is enabled, and Rx Flow control is
2659                  * disabled by software override.
2660                  */
2661                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2662                 break;
2663         case ixgbe_fc_full:
2664                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2665                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2666                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2667                 break;
2668         default:
2669                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2670                 ret_val = IXGBE_ERR_CONFIG;
2671                 goto out;
2672                 break;
2673         }
2674
2675         /* Set 802.3x based flow control settings. */
2676         mflcn_reg |= IXGBE_MFLCN_DPF;
2677         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2678         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2679
2680         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2681         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2682                 hw->fc.high_water[tc_num]) {
2683                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2684                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2685                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2686         } else {
2687                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2688                 /*
2689                  * In order to prevent Tx hangs when the internal Tx
2690                  * switch is enabled we must set the high water mark
2691                  * to the maximum FCRTH value.  This allows the Tx
2692                  * switch to function even under heavy Rx workloads.
2693                  */
2694                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2695         }
2696         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2697
2698         /* Configure pause time (2 TCs per register) */
2699         reg = hw->fc.pause_time * 0x00010001;
2700         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2701                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2702
2703         /* Configure flow control refresh threshold value */
2704         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2705
2706 out:
2707         return ret_val;
2708 }
2709
2710 static int
2711 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2712 {
2713         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2714         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2715
2716         if(hw->mac.type != ixgbe_mac_82598EB) {
2717                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2718         }
2719         return ret_val;
2720 }
2721
2722 static int
2723 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2724 {
2725         int err;
2726         uint32_t rx_buf_size;
2727         uint32_t max_high_water;
2728         uint8_t tc_num;
2729         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2730         struct ixgbe_hw *hw =
2731                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2732         struct ixgbe_dcb_config *dcb_config =
2733                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2734
2735         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2736                 ixgbe_fc_none,
2737                 ixgbe_fc_rx_pause,
2738                 ixgbe_fc_tx_pause,
2739                 ixgbe_fc_full
2740         };
2741
2742         PMD_INIT_FUNC_TRACE();
2743
2744         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2745         tc_num = map[pfc_conf->priority];
2746         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2747         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2748         /*
2749          * At least reserve one Ethernet frame for watermark
2750          * high_water/low_water in kilo bytes for ixgbe
2751          */
2752         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2753         if ((pfc_conf->fc.high_water > max_high_water) ||
2754             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2755                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2756                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2757                 return (-EINVAL);
2758         }
2759
2760         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2761         hw->fc.pause_time = pfc_conf->fc.pause_time;
2762         hw->fc.send_xon = pfc_conf->fc.send_xon;
2763         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2764         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2765
2766         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2767
2768         /* Not negotiated is not an error case */
2769         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2770                 return 0;
2771
2772         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2773         return -EIO;
2774 }
2775
2776 static int
2777 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2778                           struct rte_eth_rss_reta_entry64 *reta_conf,
2779                           uint16_t reta_size)
2780 {
2781         uint8_t i, j, mask;
2782         uint32_t reta, r;
2783         uint16_t idx, shift;
2784         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2785
2786         PMD_INIT_FUNC_TRACE();
2787         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2788                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2789                         "(%d) doesn't match the number hardware can supported "
2790                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2791                 return -EINVAL;
2792         }
2793
2794         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2795                 idx = i / RTE_RETA_GROUP_SIZE;
2796                 shift = i % RTE_RETA_GROUP_SIZE;
2797                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2798                                                 IXGBE_4_BIT_MASK);
2799                 if (!mask)
2800                         continue;
2801                 if (mask == IXGBE_4_BIT_MASK)
2802                         r = 0;
2803                 else
2804                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2805                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2806                         if (mask & (0x1 << j))
2807                                 reta |= reta_conf[idx].reta[shift + j] <<
2808                                                         (CHAR_BIT * j);
2809                         else
2810                                 reta |= r & (IXGBE_8_BIT_MASK <<
2811                                                 (CHAR_BIT * j));
2812                 }
2813                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2814         }
2815
2816         return 0;
2817 }
2818
2819 static int
2820 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2821                          struct rte_eth_rss_reta_entry64 *reta_conf,
2822                          uint16_t reta_size)
2823 {
2824         uint8_t i, j, mask;
2825         uint32_t reta;
2826         uint16_t idx, shift;
2827         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2828
2829         PMD_INIT_FUNC_TRACE();
2830         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2831                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2832                         "(%d) doesn't match the number hardware can supported "
2833                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2834                 return -EINVAL;
2835         }
2836
2837         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2838                 idx = i / RTE_RETA_GROUP_SIZE;
2839                 shift = i % RTE_RETA_GROUP_SIZE;
2840                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2841                                                 IXGBE_4_BIT_MASK);
2842                 if (!mask)
2843                         continue;
2844
2845                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2846                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2847                         if (mask & (0x1 << j))
2848                                 reta_conf[idx].reta[shift + j] =
2849                                         ((reta >> (CHAR_BIT * j)) &
2850                                                 IXGBE_8_BIT_MASK);
2851                 }
2852         }
2853
2854         return 0;
2855 }
2856
2857 static void
2858 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2859                                 uint32_t index, uint32_t pool)
2860 {
2861         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2862         uint32_t enable_addr = 1;
2863
2864         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2865 }
2866
2867 static void
2868 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2869 {
2870         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2871
2872         ixgbe_clear_rar(hw, index);
2873 }
2874
2875 static int
2876 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2877 {
2878         uint32_t hlreg0;
2879         uint32_t maxfrs;
2880         struct ixgbe_hw *hw;
2881         struct rte_eth_dev_info dev_info;
2882         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2883
2884         ixgbe_dev_info_get(dev, &dev_info);
2885
2886         /* check that mtu is within the allowed range */
2887         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2888                 return -EINVAL;
2889
2890         /* refuse mtu that requires the support of scattered packets when this
2891          * feature has not been enabled before. */
2892         if (!dev->data->scattered_rx &&
2893             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2894              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2895                 return -EINVAL;
2896
2897         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2898         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2899
2900         /* switch to jumbo mode if needed */
2901         if (frame_size > ETHER_MAX_LEN) {
2902                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2903                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2904         } else {
2905                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2906                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2907         }
2908         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2909
2910         /* update max frame size */
2911         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2912
2913         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2914         maxfrs &= 0x0000FFFF;
2915         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2916         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2917
2918         return 0;
2919 }
2920
2921 /*
2922  * Virtual Function operations
2923  */
2924 static void
2925 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2926 {
2927         PMD_INIT_FUNC_TRACE();
2928
2929         /* Clear interrupt mask to stop from interrupts being generated */
2930         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2931
2932         IXGBE_WRITE_FLUSH(hw);
2933 }
2934
2935 static int
2936 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2937 {
2938         struct rte_eth_conf* conf = &dev->data->dev_conf;
2939
2940         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2941                      dev->data->port_id);
2942
2943         /*
2944          * VF has no ability to enable/disable HW CRC
2945          * Keep the persistent behavior the same as Host PF
2946          */
2947 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2948         if (!conf->rxmode.hw_strip_crc) {
2949                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2950                 conf->rxmode.hw_strip_crc = 1;
2951         }
2952 #else
2953         if (conf->rxmode.hw_strip_crc) {
2954                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2955                 conf->rxmode.hw_strip_crc = 0;
2956         }
2957 #endif
2958
2959         return 0;
2960 }
2961
2962 static int
2963 ixgbevf_dev_start(struct rte_eth_dev *dev)
2964 {
2965         struct ixgbe_hw *hw =
2966                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2967         int err, mask = 0;
2968
2969         PMD_INIT_FUNC_TRACE();
2970
2971         hw->mac.ops.reset_hw(hw);
2972         hw->mac.get_link_status = true;
2973
2974         /* negotiate mailbox API version to use with the PF. */
2975         ixgbevf_negotiate_api(hw);
2976
2977         ixgbevf_dev_tx_init(dev);
2978
2979         /* This can fail when allocating mbufs for descriptor rings */
2980         err = ixgbevf_dev_rx_init(dev);
2981         if (err) {
2982                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2983                 ixgbe_dev_clear_queues(dev);
2984                 return err;
2985         }
2986
2987         /* Set vfta */
2988         ixgbevf_set_vfta_all(dev,1);
2989
2990         /* Set HW strip */
2991         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2992                 ETH_VLAN_EXTEND_MASK;
2993         ixgbevf_vlan_offload_set(dev, mask);
2994
2995         ixgbevf_dev_rxtx_start(dev);
2996
2997         return 0;
2998 }
2999
3000 static void
3001 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3002 {
3003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3004
3005         PMD_INIT_FUNC_TRACE();
3006
3007         hw->adapter_stopped = TRUE;
3008         ixgbe_stop_adapter(hw);
3009
3010         /*
3011           * Clear what we set, but we still keep shadow_vfta to
3012           * restore after device starts
3013           */
3014         ixgbevf_set_vfta_all(dev,0);
3015
3016         /* Clear stored conf */
3017         dev->data->scattered_rx = 0;
3018
3019         ixgbe_dev_clear_queues(dev);
3020 }
3021
3022 static void
3023 ixgbevf_dev_close(struct rte_eth_dev *dev)
3024 {
3025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3026
3027         PMD_INIT_FUNC_TRACE();
3028
3029         ixgbe_reset_hw(hw);
3030
3031         ixgbevf_dev_stop(dev);
3032
3033         /* reprogram the RAR[0] in case user changed it. */
3034         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3035 }
3036
3037 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3038 {
3039         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3040         struct ixgbe_vfta * shadow_vfta =
3041                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3042         int i = 0, j = 0, vfta = 0, mask = 1;
3043
3044         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3045                 vfta = shadow_vfta->vfta[i];
3046                 if(vfta){
3047                         mask = 1;
3048                         for (j = 0; j < 32; j++){
3049                                 if(vfta & mask)
3050                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3051                                 mask<<=1;
3052                         }
3053                 }
3054         }
3055
3056 }
3057
3058 static int
3059 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3060 {
3061         struct ixgbe_hw *hw =
3062                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3063         struct ixgbe_vfta * shadow_vfta =
3064                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3065         uint32_t vid_idx = 0;
3066         uint32_t vid_bit = 0;
3067         int ret = 0;
3068
3069         PMD_INIT_FUNC_TRACE();
3070
3071         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3072         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3073         if(ret){
3074                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3075                 return ret;
3076         }
3077         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3078         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3079
3080         /* Save what we set and retore it after device reset */
3081         if (on)
3082                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3083         else
3084                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3085
3086         return 0;
3087 }
3088
3089 static void
3090 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3091 {
3092         struct ixgbe_hw *hw =
3093                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3094         uint32_t ctrl;
3095
3096         PMD_INIT_FUNC_TRACE();
3097
3098         if(queue >= hw->mac.max_rx_queues)
3099                 return;
3100
3101         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3102         if(on)
3103                 ctrl |= IXGBE_RXDCTL_VME;
3104         else
3105                 ctrl &= ~IXGBE_RXDCTL_VME;
3106         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3107
3108         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3109 }
3110
3111 static void
3112 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3113 {
3114         struct ixgbe_hw *hw =
3115                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3116         uint16_t i;
3117         int on = 0;
3118
3119         /* VF function only support hw strip feature, others are not support */
3120         if(mask & ETH_VLAN_STRIP_MASK){
3121                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3122
3123                 for(i=0; i < hw->mac.max_rx_queues; i++)
3124                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3125         }
3126 }
3127
3128 static int
3129 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3130 {
3131         uint32_t reg_val;
3132
3133         /* we only need to do this if VMDq is enabled */
3134         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3135         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3136                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3137                 return (-1);
3138         }
3139
3140         return 0;
3141 }
3142
3143 static uint32_t
3144 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3145 {
3146         uint32_t vector = 0;
3147         switch (hw->mac.mc_filter_type) {
3148         case 0:   /* use bits [47:36] of the address */
3149                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3150                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3151                 break;
3152         case 1:   /* use bits [46:35] of the address */
3153                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3154                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3155                 break;
3156         case 2:   /* use bits [45:34] of the address */
3157                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3158                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3159                 break;
3160         case 3:   /* use bits [43:32] of the address */
3161                 vector = ((uc_addr->addr_bytes[4]) |
3162                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3163                 break;
3164         default:  /* Invalid mc_filter_type */
3165                 break;
3166         }
3167
3168         /* vector can only be 12-bits or boundary will be exceeded */
3169         vector &= 0xFFF;
3170         return vector;
3171 }
3172
3173 static int
3174 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3175                                uint8_t on)
3176 {
3177         uint32_t vector;
3178         uint32_t uta_idx;
3179         uint32_t reg_val;
3180         uint32_t uta_shift;
3181         uint32_t rc;
3182         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3183         const uint32_t ixgbe_uta_bit_shift = 5;
3184         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3185         const uint32_t bit1 = 0x1;
3186
3187         struct ixgbe_hw *hw =
3188                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3189         struct ixgbe_uta_info *uta_info =
3190                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3191
3192         /* The UTA table only exists on 82599 hardware and newer */
3193         if (hw->mac.type < ixgbe_mac_82599EB)
3194                 return (-ENOTSUP);
3195
3196         vector = ixgbe_uta_vector(hw,mac_addr);
3197         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3198         uta_shift = vector & ixgbe_uta_bit_mask;
3199
3200         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3201         if(rc == on)
3202                 return 0;
3203
3204         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3205         if (on) {
3206                 uta_info->uta_in_use++;
3207                 reg_val |= (bit1 << uta_shift);
3208                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3209         } else {
3210                 uta_info->uta_in_use--;
3211                 reg_val &= ~(bit1 << uta_shift);
3212                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3213         }
3214
3215         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3216
3217         if (uta_info->uta_in_use > 0)
3218                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3219                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3220         else
3221                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3222
3223         return 0;
3224 }
3225
3226 static int
3227 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3228 {
3229         int i;
3230         struct ixgbe_hw *hw =
3231                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3232         struct ixgbe_uta_info *uta_info =
3233                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3234
3235         /* The UTA table only exists on 82599 hardware and newer */
3236         if (hw->mac.type < ixgbe_mac_82599EB)
3237                 return (-ENOTSUP);
3238
3239         if(on) {
3240                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3241                         uta_info->uta_shadow[i] = ~0;
3242                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3243                 }
3244         } else {
3245                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3246                         uta_info->uta_shadow[i] = 0;
3247                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3248                 }
3249         }
3250         return 0;
3251
3252 }
3253
3254 uint32_t
3255 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3256 {
3257         uint32_t new_val = orig_val;
3258
3259         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3260                 new_val |= IXGBE_VMOLR_AUPE;
3261         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3262                 new_val |= IXGBE_VMOLR_ROMPE;
3263         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3264                 new_val |= IXGBE_VMOLR_ROPE;
3265         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3266                 new_val |= IXGBE_VMOLR_BAM;
3267         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3268                 new_val |= IXGBE_VMOLR_MPE;
3269
3270         return new_val;
3271 }
3272
3273 static int
3274 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3275                                uint16_t rx_mask, uint8_t on)
3276 {
3277         int val = 0;
3278
3279         struct ixgbe_hw *hw =
3280                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3281         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3282
3283         if (hw->mac.type == ixgbe_mac_82598EB) {
3284                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3285                              " on 82599 hardware and newer");
3286                 return (-ENOTSUP);
3287         }
3288         if (ixgbe_vmdq_mode_check(hw) < 0)
3289                 return (-ENOTSUP);
3290
3291         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3292
3293         if (on)
3294                 vmolr |= val;
3295         else
3296                 vmolr &= ~val;
3297
3298         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3299
3300         return 0;
3301 }
3302
3303 static int
3304 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3305 {
3306         uint32_t reg,addr;
3307         uint32_t val;
3308         const uint8_t bit1 = 0x1;
3309
3310         struct ixgbe_hw *hw =
3311                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3312
3313         if (ixgbe_vmdq_mode_check(hw) < 0)
3314                 return (-ENOTSUP);
3315
3316         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3317         reg = IXGBE_READ_REG(hw, addr);
3318         val = bit1 << pool;
3319
3320         if (on)
3321                 reg |= val;
3322         else
3323                 reg &= ~val;
3324
3325         IXGBE_WRITE_REG(hw, addr,reg);
3326
3327         return 0;
3328 }
3329
3330 static int
3331 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3332 {
3333         uint32_t reg,addr;
3334         uint32_t val;
3335         const uint8_t bit1 = 0x1;
3336
3337         struct ixgbe_hw *hw =
3338                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3339
3340         if (ixgbe_vmdq_mode_check(hw) < 0)
3341                 return (-ENOTSUP);
3342
3343         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3344         reg = IXGBE_READ_REG(hw, addr);
3345         val = bit1 << pool;
3346
3347         if (on)
3348                 reg |= val;
3349         else
3350                 reg &= ~val;
3351
3352         IXGBE_WRITE_REG(hw, addr,reg);
3353
3354         return 0;
3355 }
3356
3357 static int
3358 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3359                         uint64_t pool_mask, uint8_t vlan_on)
3360 {
3361         int ret = 0;
3362         uint16_t pool_idx;
3363         struct ixgbe_hw *hw =
3364                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3365
3366         if (ixgbe_vmdq_mode_check(hw) < 0)
3367                 return (-ENOTSUP);
3368         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3369                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3370                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3371                         if (ret < 0)
3372                                 return ret;
3373         }
3374
3375         return ret;
3376 }
3377
3378 static int
3379 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3380                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3381                         uint8_t rule_id, uint8_t on)
3382 {
3383         uint32_t mr_ctl,vlvf;
3384         uint32_t mp_lsb = 0;
3385         uint32_t mv_msb = 0;
3386         uint32_t mv_lsb = 0;
3387         uint32_t mp_msb = 0;
3388         uint8_t i = 0;
3389         int reg_index = 0;
3390         uint64_t vlan_mask = 0;
3391
3392         const uint8_t pool_mask_offset = 32;
3393         const uint8_t vlan_mask_offset = 32;
3394         const uint8_t dst_pool_offset = 8;
3395         const uint8_t rule_mr_offset  = 4;
3396         const uint8_t mirror_rule_mask= 0x0F;
3397
3398         struct ixgbe_mirror_info *mr_info =
3399                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3400         struct ixgbe_hw *hw =
3401                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3402
3403         if (ixgbe_vmdq_mode_check(hw) < 0)
3404                 return (-ENOTSUP);
3405
3406         /* Check if vlan mask is valid */
3407         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3408                 if (mirror_conf->vlan.vlan_mask == 0)
3409                         return (-EINVAL);
3410         }
3411
3412         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3413         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3414                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3415                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3416                                 /* search vlan id related pool vlan filter index */
3417                                 reg_index = ixgbe_find_vlvf_slot(hw,
3418                                                 mirror_conf->vlan.vlan_id[i]);
3419                                 if(reg_index < 0)
3420                                         return (-EINVAL);
3421                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3422                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3423                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3424                                                 == mirror_conf->vlan.vlan_id[i]))
3425                                         vlan_mask |= (1ULL << reg_index);
3426                                 else
3427                                         return (-EINVAL);
3428                         }
3429                 }
3430
3431                 if (on) {
3432                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3433                         mv_msb = vlan_mask >> vlan_mask_offset;
3434
3435                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3436                                                 mirror_conf->vlan.vlan_mask;
3437                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3438                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3439                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3440                                                 mirror_conf->vlan.vlan_id[i];
3441                         }
3442                 } else {
3443                         mv_lsb = 0;
3444                         mv_msb = 0;
3445                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3446                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3447                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3448                 }
3449         }
3450
3451         /*
3452          * if enable pool mirror, write related pool mask register,if disable
3453          * pool mirror, clear PFMRVM register
3454          */
3455         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3456                 if (on) {
3457                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3458                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3459                         mr_info->mr_conf[rule_id].pool_mask =
3460                                         mirror_conf->pool_mask;
3461
3462                 } else {
3463                         mp_lsb = 0;
3464                         mp_msb = 0;
3465                         mr_info->mr_conf[rule_id].pool_mask = 0;
3466                 }
3467         }
3468
3469         /* read  mirror control register and recalculate it */
3470         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3471
3472         if (on) {
3473                 mr_ctl |= mirror_conf->rule_type_mask;
3474                 mr_ctl &= mirror_rule_mask;
3475                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3476         } else
3477                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3478
3479         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3480         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3481
3482         /* write mirrror control  register */
3483         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3484
3485         /* write pool mirrror control  register */
3486         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3487                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3488                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3489                                 mp_msb);
3490         }
3491         /* write VLAN mirrror control  register */
3492         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3493                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3494                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3495                                 mv_msb);
3496         }
3497
3498         return 0;
3499 }
3500
3501 static int
3502 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3503 {
3504         int mr_ctl = 0;
3505         uint32_t lsb_val = 0;
3506         uint32_t msb_val = 0;
3507         const uint8_t rule_mr_offset = 4;
3508
3509         struct ixgbe_hw *hw =
3510                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3511         struct ixgbe_mirror_info *mr_info =
3512                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3513
3514         if (ixgbe_vmdq_mode_check(hw) < 0)
3515                 return (-ENOTSUP);
3516
3517         memset(&mr_info->mr_conf[rule_id], 0,
3518                 sizeof(struct rte_eth_vmdq_mirror_conf));
3519
3520         /* clear PFVMCTL register */
3521         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3522
3523         /* clear pool mask register */
3524         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3525         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3526
3527         /* clear vlan mask register */
3528         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3529         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3530
3531         return 0;
3532 }
3533
3534 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3535         uint16_t queue_idx, uint16_t tx_rate)
3536 {
3537         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3538         uint32_t rf_dec, rf_int;
3539         uint32_t bcnrc_val;
3540         uint16_t link_speed = dev->data->dev_link.link_speed;
3541
3542         if (queue_idx >= hw->mac.max_tx_queues)
3543                 return -EINVAL;
3544
3545         if (tx_rate != 0) {
3546                 /* Calculate the rate factor values to set */
3547                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3548                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3549                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3550
3551                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3552                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3553                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3554                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3555         } else {
3556                 bcnrc_val = 0;
3557         }
3558
3559         /*
3560          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3561          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3562          * set as 0x4.
3563          */
3564         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3565                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3566                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3567                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3568                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3569         else
3570                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3571                         IXGBE_MMW_SIZE_DEFAULT);
3572
3573         /* Set RTTBCNRC of queue X */
3574         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3575         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3576         IXGBE_WRITE_FLUSH(hw);
3577
3578         return 0;
3579 }
3580
3581 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3582         uint16_t tx_rate, uint64_t q_msk)
3583 {
3584         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3585         struct ixgbe_vf_info *vfinfo =
3586                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3587         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3588         uint32_t queue_stride =
3589                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3590         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3591         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3592         uint16_t total_rate = 0;
3593
3594         if (queue_end >= hw->mac.max_tx_queues)
3595                 return -EINVAL;
3596
3597         if (vfinfo != NULL) {
3598                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3599                         if (vf_idx == vf)
3600                                 continue;
3601                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3602                                 idx++)
3603                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3604                 }
3605         } else
3606                 return -EINVAL;
3607
3608         /* Store tx_rate for this vf. */
3609         for (idx = 0; idx < nb_q_per_pool; idx++) {
3610                 if (((uint64_t)0x1 << idx) & q_msk) {
3611                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3612                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3613                         total_rate += tx_rate;
3614                 }
3615         }
3616
3617         if (total_rate > dev->data->dev_link.link_speed) {
3618                 /*
3619                  * Reset stored TX rate of the VF if it causes exceed
3620                  * link speed.
3621                  */
3622                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3623                 return -EINVAL;
3624         }
3625
3626         /* Set RTTBCNRC of each queue/pool for vf X  */
3627         for (; queue_idx <= queue_end; queue_idx++) {
3628                 if (0x1 & q_msk)
3629                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3630                 q_msk = q_msk >> 1;
3631         }
3632
3633         return 0;
3634 }
3635
3636 static void
3637 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3638                      __attribute__((unused)) uint32_t index,
3639                      __attribute__((unused)) uint32_t pool)
3640 {
3641         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3642         int diag;
3643
3644         /*
3645          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3646          * operation. Trap this case to avoid exhausting the [very limited]
3647          * set of PF resources used to store VF MAC addresses.
3648          */
3649         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3650                 return;
3651         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3652         if (diag == 0)
3653                 return;
3654         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3655 }
3656
3657 static void
3658 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3659 {
3660         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3661         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3662         struct ether_addr *mac_addr;
3663         uint32_t i;
3664         int diag;
3665
3666         /*
3667          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3668          * not support the deletion of a given MAC address.
3669          * Instead, it imposes to delete all MAC addresses, then to add again
3670          * all MAC addresses with the exception of the one to be deleted.
3671          */
3672         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3673
3674         /*
3675          * Add again all MAC addresses, with the exception of the deleted one
3676          * and of the permanent MAC address.
3677          */
3678         for (i = 0, mac_addr = dev->data->mac_addrs;
3679              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3680                 /* Skip the deleted MAC address */
3681                 if (i == index)
3682                         continue;
3683                 /* Skip NULL MAC addresses */
3684                 if (is_zero_ether_addr(mac_addr))
3685                         continue;
3686                 /* Skip the permanent MAC address */
3687                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3688                         continue;
3689                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3690                 if (diag != 0)
3691                         PMD_DRV_LOG(ERR,
3692                                     "Adding again MAC address "
3693                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3694                                     "diag=%d",
3695                                     mac_addr->addr_bytes[0],
3696                                     mac_addr->addr_bytes[1],
3697                                     mac_addr->addr_bytes[2],
3698                                     mac_addr->addr_bytes[3],
3699                                     mac_addr->addr_bytes[4],
3700                                     mac_addr->addr_bytes[5],
3701                                     diag);
3702         }
3703 }
3704
3705 #define MAC_TYPE_FILTER_SUP(type)    do {\
3706         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
3707                 (type) != ixgbe_mac_X550)\
3708                 return -ENOTSUP;\
3709 } while (0)
3710
3711 static int
3712 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
3713                         struct rte_eth_syn_filter *filter,
3714                         bool add)
3715 {
3716         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3717         uint32_t synqf;
3718
3719         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
3720                 return -EINVAL;
3721
3722         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3723
3724         if (add) {
3725                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3726                         return -EINVAL;
3727                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3728                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3729
3730                 if (filter->hig_pri)
3731                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
3732                 else
3733                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3734         } else {
3735                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
3736                         return -ENOENT;
3737                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3738         }
3739         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3740         IXGBE_WRITE_FLUSH(hw);
3741         return 0;
3742 }
3743
3744 static int
3745 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
3746                         struct rte_eth_syn_filter *filter)
3747 {
3748         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3749         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3750
3751         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3752                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3753                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3754                 return 0;
3755         }
3756         return -ENOENT;
3757 }
3758
3759 static int
3760 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
3761                         enum rte_filter_op filter_op,
3762                         void *arg)
3763 {
3764         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3765         int ret;
3766
3767         MAC_TYPE_FILTER_SUP(hw->mac.type);
3768
3769         if (filter_op == RTE_ETH_FILTER_NOP)
3770                 return 0;
3771
3772         if (arg == NULL) {
3773                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3774                             filter_op);
3775                 return -EINVAL;
3776         }
3777
3778         switch (filter_op) {
3779         case RTE_ETH_FILTER_ADD:
3780                 ret = ixgbe_syn_filter_set(dev,
3781                                 (struct rte_eth_syn_filter *)arg,
3782                                 TRUE);
3783                 break;
3784         case RTE_ETH_FILTER_DELETE:
3785                 ret = ixgbe_syn_filter_set(dev,
3786                                 (struct rte_eth_syn_filter *)arg,
3787                                 FALSE);
3788                 break;
3789         case RTE_ETH_FILTER_GET:
3790                 ret = ixgbe_syn_filter_get(dev,
3791                                 (struct rte_eth_syn_filter *)arg);
3792                 break;
3793         default:
3794                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3795                 ret = -EINVAL;
3796                 break;
3797         }
3798
3799         return ret;
3800 }
3801
3802
3803 static inline enum ixgbe_5tuple_protocol
3804 convert_protocol_type(uint8_t protocol_value)
3805 {
3806         if (protocol_value == IPPROTO_TCP)
3807                 return IXGBE_FILTER_PROTOCOL_TCP;
3808         else if (protocol_value == IPPROTO_UDP)
3809                 return IXGBE_FILTER_PROTOCOL_UDP;
3810         else if (protocol_value == IPPROTO_SCTP)
3811                 return IXGBE_FILTER_PROTOCOL_SCTP;
3812         else
3813                 return IXGBE_FILTER_PROTOCOL_NONE;
3814 }
3815
3816 /*
3817  * add a 5tuple filter
3818  *
3819  * @param
3820  * dev: Pointer to struct rte_eth_dev.
3821  * index: the index the filter allocates.
3822  * filter: ponter to the filter that will be added.
3823  * rx_queue: the queue id the filter assigned to.
3824  *
3825  * @return
3826  *    - On success, zero.
3827  *    - On failure, a negative value.
3828  */
3829 static int
3830 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3831                         struct ixgbe_5tuple_filter *filter)
3832 {
3833         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3834         struct ixgbe_filter_info *filter_info =
3835                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3836         int i, idx, shift;
3837         uint32_t ftqf, sdpqf;
3838         uint32_t l34timir = 0;
3839         uint8_t mask = 0xff;
3840
3841         /*
3842          * look for an unused 5tuple filter index,
3843          * and insert the filter to list.
3844          */
3845         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
3846                 idx = i / (sizeof(uint32_t) * NBBY);
3847                 shift = i % (sizeof(uint32_t) * NBBY);
3848                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3849                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3850                         filter->index = i;
3851                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3852                                           filter,
3853                                           entries);
3854                         break;
3855                 }
3856         }
3857         if (i >= IXGBE_MAX_FTQF_FILTERS) {
3858                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3859                 return -ENOSYS;
3860         }
3861
3862         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
3863                                 IXGBE_SDPQF_DSTPORT_SHIFT);
3864         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
3865
3866         ftqf = (uint32_t)(filter->filter_info.proto &
3867                 IXGBE_FTQF_PROTOCOL_MASK);
3868         ftqf |= (uint32_t)((filter->filter_info.priority &
3869                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
3870         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3871                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3872         if (filter->filter_info.dst_ip_mask == 0)
3873                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3874         if (filter->filter_info.src_port_mask == 0)
3875                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3876         if (filter->filter_info.dst_port_mask == 0)
3877                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3878         if (filter->filter_info.proto_mask == 0)
3879                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3880         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3881         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3882         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3883
3884         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
3885         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
3886         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
3887         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
3888
3889         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3890         l34timir |= (uint32_t)(filter->queue <<
3891                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
3892         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
3893         return 0;
3894 }
3895
3896 /*
3897  * remove a 5tuple filter
3898  *
3899  * @param
3900  * dev: Pointer to struct rte_eth_dev.
3901  * filter: the pointer of the filter will be removed.
3902  */
3903 static void
3904 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3905                         struct ixgbe_5tuple_filter *filter)
3906 {
3907         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3908         struct ixgbe_filter_info *filter_info =
3909                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3910         uint16_t index = filter->index;
3911
3912         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3913                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3914         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3915         rte_free(filter);
3916
3917         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3918         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3919         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3920         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3921         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3922 }
3923
3924 static int
3925 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3926 {
3927         struct ixgbe_hw *hw;
3928         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3929
3930         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3931
3932         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3933                 return -EINVAL;
3934
3935         /* refuse mtu that requires the support of scattered packets when this
3936          * feature has not been enabled before. */
3937         if (!dev->data->scattered_rx &&
3938             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3939              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3940                 return -EINVAL;
3941
3942         /*
3943          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3944          * request of the version 2.0 of the mailbox API.
3945          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3946          * of the mailbox API.
3947          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3948          * prior to 3.11.33 which contains the following change:
3949          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3950          */
3951         ixgbevf_rlpml_set_vf(hw, max_frame);
3952
3953         /* update max frame size */
3954         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
3955         return 0;
3956 }
3957
3958 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3959         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
3960                 return -ENOTSUP;\
3961 } while (0)
3962
3963 static inline struct ixgbe_5tuple_filter *
3964 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
3965                         struct ixgbe_5tuple_filter_info *key)
3966 {
3967         struct ixgbe_5tuple_filter *it;
3968
3969         TAILQ_FOREACH(it, filter_list, entries) {
3970                 if (memcmp(key, &it->filter_info,
3971                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
3972                         return it;
3973                 }
3974         }
3975         return NULL;
3976 }
3977
3978 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
3979 static inline int
3980 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3981                         struct ixgbe_5tuple_filter_info *filter_info)
3982 {
3983         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3984                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3985                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3986                 return -EINVAL;
3987
3988         switch (filter->dst_ip_mask) {
3989         case UINT32_MAX:
3990                 filter_info->dst_ip_mask = 0;
3991                 filter_info->dst_ip = filter->dst_ip;
3992                 break;
3993         case 0:
3994                 filter_info->dst_ip_mask = 1;
3995                 break;
3996         default:
3997                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3998                 return -EINVAL;
3999         }
4000
4001         switch (filter->src_ip_mask) {
4002         case UINT32_MAX:
4003                 filter_info->src_ip_mask = 0;
4004                 filter_info->src_ip = filter->src_ip;
4005                 break;
4006         case 0:
4007                 filter_info->src_ip_mask = 1;
4008                 break;
4009         default:
4010                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4011                 return -EINVAL;
4012         }
4013
4014         switch (filter->dst_port_mask) {
4015         case UINT16_MAX:
4016                 filter_info->dst_port_mask = 0;
4017                 filter_info->dst_port = filter->dst_port;
4018                 break;
4019         case 0:
4020                 filter_info->dst_port_mask = 1;
4021                 break;
4022         default:
4023                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4024                 return -EINVAL;
4025         }
4026
4027         switch (filter->src_port_mask) {
4028         case UINT16_MAX:
4029                 filter_info->src_port_mask = 0;
4030                 filter_info->src_port = filter->src_port;
4031                 break;
4032         case 0:
4033                 filter_info->src_port_mask = 1;
4034                 break;
4035         default:
4036                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4037                 return -EINVAL;
4038         }
4039
4040         switch (filter->proto_mask) {
4041         case UINT8_MAX:
4042                 filter_info->proto_mask = 0;
4043                 filter_info->proto =
4044                         convert_protocol_type(filter->proto);
4045                 break;
4046         case 0:
4047                 filter_info->proto_mask = 1;
4048                 break;
4049         default:
4050                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4051                 return -EINVAL;
4052         }
4053
4054         filter_info->priority = (uint8_t)filter->priority;
4055         return 0;
4056 }
4057
4058 /*
4059  * add or delete a ntuple filter
4060  *
4061  * @param
4062  * dev: Pointer to struct rte_eth_dev.
4063  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4064  * add: if true, add filter, if false, remove filter
4065  *
4066  * @return
4067  *    - On success, zero.
4068  *    - On failure, a negative value.
4069  */
4070 static int
4071 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4072                         struct rte_eth_ntuple_filter *ntuple_filter,
4073                         bool add)
4074 {
4075         struct ixgbe_filter_info *filter_info =
4076                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4077         struct ixgbe_5tuple_filter_info filter_5tuple;
4078         struct ixgbe_5tuple_filter *filter;
4079         int ret;
4080
4081         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4082                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4083                 return -EINVAL;
4084         }
4085
4086         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4087         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4088         if (ret < 0)
4089                 return ret;
4090
4091         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4092                                          &filter_5tuple);
4093         if (filter != NULL && add) {
4094                 PMD_DRV_LOG(ERR, "filter exists.");
4095                 return -EEXIST;
4096         }
4097         if (filter == NULL && !add) {
4098                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4099                 return -ENOENT;
4100         }
4101
4102         if (add) {
4103                 filter = rte_zmalloc("ixgbe_5tuple_filter",
4104                                 sizeof(struct ixgbe_5tuple_filter), 0);
4105                 if (filter == NULL)
4106                         return -ENOMEM;
4107                 (void)rte_memcpy(&filter->filter_info,
4108                                  &filter_5tuple,
4109                                  sizeof(struct ixgbe_5tuple_filter_info));
4110                 filter->queue = ntuple_filter->queue;
4111                 ret = ixgbe_add_5tuple_filter(dev, filter);
4112                 if (ret < 0) {
4113                         rte_free(filter);
4114                         return ret;
4115                 }
4116         } else
4117                 ixgbe_remove_5tuple_filter(dev, filter);
4118
4119         return 0;
4120 }
4121
4122 /*
4123  * get a ntuple filter
4124  *
4125  * @param
4126  * dev: Pointer to struct rte_eth_dev.
4127  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4128  *
4129  * @return
4130  *    - On success, zero.
4131  *    - On failure, a negative value.
4132  */
4133 static int
4134 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4135                         struct rte_eth_ntuple_filter *ntuple_filter)
4136 {
4137         struct ixgbe_filter_info *filter_info =
4138                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4139         struct ixgbe_5tuple_filter_info filter_5tuple;
4140         struct ixgbe_5tuple_filter *filter;
4141         int ret;
4142
4143         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4144                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4145                 return -EINVAL;
4146         }
4147
4148         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4149         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4150         if (ret < 0)
4151                 return ret;
4152
4153         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4154                                          &filter_5tuple);
4155         if (filter == NULL) {
4156                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4157                 return -ENOENT;
4158         }
4159         ntuple_filter->queue = filter->queue;
4160         return 0;
4161 }
4162
4163 /*
4164  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4165  * @dev: pointer to rte_eth_dev structure
4166  * @filter_op:operation will be taken.
4167  * @arg: a pointer to specific structure corresponding to the filter_op
4168  *
4169  * @return
4170  *    - On success, zero.
4171  *    - On failure, a negative value.
4172  */
4173 static int
4174 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4175                                 enum rte_filter_op filter_op,
4176                                 void *arg)
4177 {
4178         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4179         int ret;
4180
4181         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4182
4183         if (filter_op == RTE_ETH_FILTER_NOP)
4184                 return 0;
4185
4186         if (arg == NULL) {
4187                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4188                             filter_op);
4189                 return -EINVAL;
4190         }
4191
4192         switch (filter_op) {
4193         case RTE_ETH_FILTER_ADD:
4194                 ret = ixgbe_add_del_ntuple_filter(dev,
4195                         (struct rte_eth_ntuple_filter *)arg,
4196                         TRUE);
4197                 break;
4198         case RTE_ETH_FILTER_DELETE:
4199                 ret = ixgbe_add_del_ntuple_filter(dev,
4200                         (struct rte_eth_ntuple_filter *)arg,
4201                         FALSE);
4202                 break;
4203         case RTE_ETH_FILTER_GET:
4204                 ret = ixgbe_get_ntuple_filter(dev,
4205                         (struct rte_eth_ntuple_filter *)arg);
4206                 break;
4207         default:
4208                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4209                 ret = -EINVAL;
4210                 break;
4211         }
4212         return ret;
4213 }
4214
4215 static inline int
4216 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4217                         uint16_t ethertype)
4218 {
4219         int i;
4220
4221         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4222                 if (filter_info->ethertype_filters[i] == ethertype &&
4223                     (filter_info->ethertype_mask & (1 << i)))
4224                         return i;
4225         }
4226         return -1;
4227 }
4228
4229 static inline int
4230 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4231                         uint16_t ethertype)
4232 {
4233         int i;
4234
4235         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4236                 if (!(filter_info->ethertype_mask & (1 << i))) {
4237                         filter_info->ethertype_mask |= 1 << i;
4238                         filter_info->ethertype_filters[i] = ethertype;
4239                         return i;
4240                 }
4241         }
4242         return -1;
4243 }
4244
4245 static inline int
4246 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4247                         uint8_t idx)
4248 {
4249         if (idx >= IXGBE_MAX_ETQF_FILTERS)
4250                 return -1;
4251         filter_info->ethertype_mask &= ~(1 << idx);
4252         filter_info->ethertype_filters[idx] = 0;
4253         return idx;
4254 }
4255
4256 static int
4257 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4258                         struct rte_eth_ethertype_filter *filter,
4259                         bool add)
4260 {
4261         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4262         struct ixgbe_filter_info *filter_info =
4263                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4264         uint32_t etqf = 0;
4265         uint32_t etqs = 0;
4266         int ret;
4267
4268         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4269                 return -EINVAL;
4270
4271         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4272                 filter->ether_type == ETHER_TYPE_IPv6) {
4273                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4274                         " ethertype filter.", filter->ether_type);
4275                 return -EINVAL;
4276         }
4277
4278         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4279                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4280                 return -EINVAL;
4281         }
4282         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4283                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4284                 return -EINVAL;
4285         }
4286
4287         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4288         if (ret >= 0 && add) {
4289                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4290                             filter->ether_type);
4291                 return -EEXIST;
4292         }
4293         if (ret < 0 && !add) {
4294                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4295                             filter->ether_type);
4296                 return -ENOENT;
4297         }
4298
4299         if (add) {
4300                 ret = ixgbe_ethertype_filter_insert(filter_info,
4301                         filter->ether_type);
4302                 if (ret < 0) {
4303                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4304                         return -ENOSYS;
4305                 }
4306                 etqf = IXGBE_ETQF_FILTER_EN;
4307                 etqf |= (uint32_t)filter->ether_type;
4308                 etqs |= (uint32_t)((filter->queue <<
4309                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
4310                                     IXGBE_ETQS_RX_QUEUE);
4311                 etqs |= IXGBE_ETQS_QUEUE_EN;
4312         } else {
4313                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4314                 if (ret < 0)
4315                         return -ENOSYS;
4316         }
4317         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4318         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4319         IXGBE_WRITE_FLUSH(hw);
4320
4321         return 0;
4322 }
4323
4324 static int
4325 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4326                         struct rte_eth_ethertype_filter *filter)
4327 {
4328         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4329         struct ixgbe_filter_info *filter_info =
4330                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4331         uint32_t etqf, etqs;
4332         int ret;
4333
4334         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4335         if (ret < 0) {
4336                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4337                             filter->ether_type);
4338                 return -ENOENT;
4339         }
4340
4341         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4342         if (etqf & IXGBE_ETQF_FILTER_EN) {
4343                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4344                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4345                 filter->flags = 0;
4346                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4347                                IXGBE_ETQS_RX_QUEUE_SHIFT;
4348                 return 0;
4349         }
4350         return -ENOENT;
4351 }
4352
4353 /*
4354  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4355  * @dev: pointer to rte_eth_dev structure
4356  * @filter_op:operation will be taken.
4357  * @arg: a pointer to specific structure corresponding to the filter_op
4358  */
4359 static int
4360 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4361                                 enum rte_filter_op filter_op,
4362                                 void *arg)
4363 {
4364         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4365         int ret;
4366
4367         MAC_TYPE_FILTER_SUP(hw->mac.type);
4368
4369         if (filter_op == RTE_ETH_FILTER_NOP)
4370                 return 0;
4371
4372         if (arg == NULL) {
4373                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4374                             filter_op);
4375                 return -EINVAL;
4376         }
4377
4378         switch (filter_op) {
4379         case RTE_ETH_FILTER_ADD:
4380                 ret = ixgbe_add_del_ethertype_filter(dev,
4381                         (struct rte_eth_ethertype_filter *)arg,
4382                         TRUE);
4383                 break;
4384         case RTE_ETH_FILTER_DELETE:
4385                 ret = ixgbe_add_del_ethertype_filter(dev,
4386                         (struct rte_eth_ethertype_filter *)arg,
4387                         FALSE);
4388                 break;
4389         case RTE_ETH_FILTER_GET:
4390                 ret = ixgbe_get_ethertype_filter(dev,
4391                         (struct rte_eth_ethertype_filter *)arg);
4392                 break;
4393         default:
4394                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4395                 ret = -EINVAL;
4396                 break;
4397         }
4398         return ret;
4399 }
4400
4401 static int
4402 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4403                      enum rte_filter_type filter_type,
4404                      enum rte_filter_op filter_op,
4405                      void *arg)
4406 {
4407         int ret = -EINVAL;
4408
4409         switch (filter_type) {
4410         case RTE_ETH_FILTER_NTUPLE:
4411                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
4412                 break;
4413         case RTE_ETH_FILTER_ETHERTYPE:
4414                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4415                 break;
4416         case RTE_ETH_FILTER_SYN:
4417                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
4418                 break;
4419         case RTE_ETH_FILTER_FDIR:
4420                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4421                 break;
4422         default:
4423                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4424                                                         filter_type);
4425                 break;
4426         }
4427
4428         return ret;
4429 }
4430
4431 static struct rte_driver rte_ixgbe_driver = {
4432         .type = PMD_PDEV,
4433         .init = rte_ixgbe_pmd_init,
4434 };
4435
4436 static struct rte_driver rte_ixgbevf_driver = {
4437         .type = PMD_PDEV,
4438         .init = rte_ixgbevf_pmd_init,
4439 };
4440
4441 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4442 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);