lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "ixgbe/ixgbe_api.h"
  67 #include "ixgbe/ixgbe_vf.h"
  68 #include "ixgbe/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72
  73 /*
  74  * High threshold controlling when to start sending XOFF frames. Must be at
  75  * least 8 bytes less than receive packet buffer size. This value is in units
  76  * of 1024 bytes.
  77  */
  78 #define IXGBE_FC_HI    0x80
  79
  80 /*
  81  * Low threshold controlling when to start sending XON frames. This value is
  82  * in units of 1024 bytes.
  83  */
  84 #define IXGBE_FC_LO    0x40
  85
  86 /* Timer value included in XOFF frames. */
  87 #define IXGBE_FC_PAUSE 0x680
  88
  89 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  90 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  91 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  92
  93 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  94 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  95
  96 /*
  97  *  Default values for RX/TX configuration
  98  */
  99 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 100 #define IXGBE_DEFAULT_RX_PTHRESH      8
 101 #define IXGBE_DEFAULT_RX_HTHRESH      8
 102 #define IXGBE_DEFAULT_RX_WTHRESH      0
 103
 104 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 105 #define IXGBE_DEFAULT_TX_PTHRESH      32
 106 #define IXGBE_DEFAULT_TX_HTHRESH      0
 107 #define IXGBE_DEFAULT_TX_WTHRESH      0
 108 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 109
 110 /* Bit shift and mask */
 111 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 112 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 113 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 114 #define IXGBE_8_BIT_MASK   UINT8_MAX
 115
 116 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 117
 118 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 119
 120 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
 121                 struct rte_eth_dev *eth_dev);
 122 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 123 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 124 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 125 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 126 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 127 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 128 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 129 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 130 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 131 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 132 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 133                                 int wait_to_complete);
 134 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 135                                 struct rte_eth_stats *stats);
 136 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 137 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 138                                              uint16_t queue_id,
 139                                              uint8_t stat_idx,
 140                                              uint8_t is_rx);
 141 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 142                                struct rte_eth_dev_info *dev_info);
 143 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 144                                  struct rte_eth_dev_info *dev_info);
 145 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 146
 147 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 148                 uint16_t vlan_id, int on);
 149 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 150 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 151                 uint16_t queue, bool on);
 152 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 153                 int on);
 154 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 155 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 156 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 157 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 158 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 159
 160 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 161 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 162 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 163                                struct rte_eth_fc_conf *fc_conf);
 164 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 165                                struct rte_eth_fc_conf *fc_conf);
 166 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 167                 struct rte_eth_pfc_conf *pfc_conf);
 168 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 169                         struct rte_eth_rss_reta_entry64 *reta_conf,
 170                         uint16_t reta_size);
 171 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 172                         struct rte_eth_rss_reta_entry64 *reta_conf,
 173                         uint16_t reta_size);
 174 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 178 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 179                 void *param);
 180 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 181 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 182                 uint32_t index, uint32_t pool);
 183 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 184 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 185
 186 /* For Virtual Function support */
 187 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 188                 struct rte_eth_dev *eth_dev);
 189 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 190 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 191 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 192 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 193 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 194 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 195                 struct rte_eth_stats *stats);
 196 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 197 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 198                 uint16_t vlan_id, int on);
 199 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 200                 uint16_t queue, int on);
 201 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 202 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203
 204 /* For Eth VMDQ APIs support */
 205 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 206                 ether_addr* mac_addr,uint8_t on);
 207 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 208 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 209                 uint16_t rx_mask, uint8_t on);
 210 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 211 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 212 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 213                 uint64_t pool_mask,uint8_t vlan_on);
 214 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 215                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 216                 uint8_t rule_id, uint8_t on);
 217 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 218                 uint8_t rule_id);
 219
 220 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 221                 uint16_t queue_idx, uint16_t tx_rate);
 222 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 223                 uint16_t tx_rate, uint64_t q_msk);
 224
 225 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 226                                  struct ether_addr *mac_addr,
 227                                  uint32_t index, uint32_t pool);
 228 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 229 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
 230                         struct rte_syn_filter *filter, uint16_t rx_queue);
 231 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
 232 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
 233                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 234 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 235                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 236 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 237                         uint16_t index);
 238 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 239                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 240
 241 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 242 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 243                         struct rte_eth_ethertype_filter *filter,
 244                         bool add);
 245 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 246                                 enum rte_filter_op filter_op,
 247                                 void *arg);
 248 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 249                         struct rte_eth_ethertype_filter *filter);
 250 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 251                      enum rte_filter_type filter_type,
 252                      enum rte_filter_op filter_op,
 253                      void *arg);
 254
 255 /*
 256  * Define VF Stats MACRO for Non "cleared on read" register
 257  */
 258 #define UPDATE_VF_STAT(reg, last, cur)                          \
 259 {                                                               \
 260         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 261         cur += latest - last;                                   \
 262         last = latest;                                          \
 263 }
 264
 265 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 266 {                                                                \
 267         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 268         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 269         u64 latest = ((new_msb << 32) | new_lsb);                \
 270         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 271         last = latest;                                           \
 272 }
 273
 274 #define IXGBE_SET_HWSTRIP(h, q) do{\
 275                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 276                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 277                 (h)->bitmap[idx] |= 1 << bit;\
 278         }while(0)
 279
 280 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 281                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 282                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 283                 (h)->bitmap[idx] &= ~(1 << bit);\
 284         }while(0)
 285
 286 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 287                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 288                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 289                 (r) = (h)->bitmap[idx] >> bit & 1;\
 290         }while(0)
 291
 292 /*
 293  * The set of PCI devices this driver supports
 294  */
 295 static struct rte_pci_id pci_id_ixgbe_map[] = {
 296
 297 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 298 #include "rte_pci_dev_ids.h"
 299
 300 { .vendor_id = 0, /* sentinel */ },
 301 };
 302
 303
 304 /*
 305  * The set of PCI devices this driver supports (for 82599 VF)
 306  */
 307 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 308
 309 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 310 #include "rte_pci_dev_ids.h"
 311 { .vendor_id = 0, /* sentinel */ },
 312
 313 };
 314
 315 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 316         .dev_configure        = ixgbe_dev_configure,
 317         .dev_start            = ixgbe_dev_start,
 318         .dev_stop             = ixgbe_dev_stop,
 319         .dev_set_link_up    = ixgbe_dev_set_link_up,
 320         .dev_set_link_down  = ixgbe_dev_set_link_down,
 321         .dev_close            = ixgbe_dev_close,
 322         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 323         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 324         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 325         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 326         .link_update          = ixgbe_dev_link_update,
 327         .stats_get            = ixgbe_dev_stats_get,
 328         .stats_reset          = ixgbe_dev_stats_reset,
 329         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 330         .dev_infos_get        = ixgbe_dev_info_get,
 331         .mtu_set              = ixgbe_dev_mtu_set,
 332         .vlan_filter_set      = ixgbe_vlan_filter_set,
 333         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 334         .vlan_offload_set     = ixgbe_vlan_offload_set,
 335         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 336         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 337         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 338         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 339         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 340         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 341         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 342         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 343         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 344         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 345         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 346         .dev_led_on           = ixgbe_dev_led_on,
 347         .dev_led_off          = ixgbe_dev_led_off,
 348         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 349         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 350         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 351         .mac_addr_add         = ixgbe_add_rar,
 352         .mac_addr_remove      = ixgbe_remove_rar,
 353         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 354         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 355         .mirror_rule_set      = ixgbe_mirror_rule_set,
 356         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 357         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 358         .set_vf_rx            = ixgbe_set_pool_rx,
 359         .set_vf_tx            = ixgbe_set_pool_tx,
 360         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 361         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 362         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 363         .fdir_infos_get               = ixgbe_fdir_info_get,
 364         .fdir_set_masks               = ixgbe_fdir_set_masks,
 365         .reta_update          = ixgbe_dev_rss_reta_update,
 366         .reta_query           = ixgbe_dev_rss_reta_query,
 367 #ifdef RTE_NIC_BYPASS
 368         .bypass_init          = ixgbe_bypass_init,
 369         .bypass_state_set     = ixgbe_bypass_state_store,
 370         .bypass_state_show    = ixgbe_bypass_state_show,
 371         .bypass_event_set     = ixgbe_bypass_event_store,
 372         .bypass_event_show    = ixgbe_bypass_event_show,
 373         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 374         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 375         .bypass_ver_show      = ixgbe_bypass_ver_show,
 376         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 377 #endif /* RTE_NIC_BYPASS */
 378         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 379         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 380         .add_syn_filter          = ixgbe_add_syn_filter,
 381         .remove_syn_filter       = ixgbe_remove_syn_filter,
 382         .get_syn_filter          = ixgbe_get_syn_filter,
 383         .add_5tuple_filter       = ixgbe_add_5tuple_filter,
 384         .remove_5tuple_filter    = ixgbe_remove_5tuple_filter,
 385         .get_5tuple_filter       = ixgbe_get_5tuple_filter,
 386         .filter_ctrl             = ixgbe_dev_filter_ctrl,
 387 };
 388
 389 /*
 390  * dev_ops for virtual function, bare necessities for basic vf
 391  * operation have been implemented
 392  */
 393 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 394
 395         .dev_configure        = ixgbevf_dev_configure,
 396         .dev_start            = ixgbevf_dev_start,
 397         .dev_stop             = ixgbevf_dev_stop,
 398         .link_update          = ixgbe_dev_link_update,
 399         .stats_get            = ixgbevf_dev_stats_get,
 400         .stats_reset          = ixgbevf_dev_stats_reset,
 401         .dev_close            = ixgbevf_dev_close,
 402         .dev_infos_get        = ixgbevf_dev_info_get,
 403         .mtu_set              = ixgbevf_dev_set_mtu,
 404         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 405         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 406         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 407         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 408         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 409         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 410         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 411         .mac_addr_add         = ixgbevf_add_mac_addr,
 412         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 413 };
 414
 415 /**
 416  * Atomically reads the link status information from global
 417  * structure rte_eth_dev.
 418  *
 419  * @param dev
 420  *   - Pointer to the structure rte_eth_dev to read from.
 421  *   - Pointer to the buffer to be saved with the link status.
 422  *
 423  * @return
 424  *   - On success, zero.
 425  *   - On failure, negative value.
 426  */
 427 static inline int
 428 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 429                                 struct rte_eth_link *link)
 430 {
 431         struct rte_eth_link *dst = link;
 432         struct rte_eth_link *src = &(dev->data->dev_link);
 433
 434         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 435                                         *(uint64_t *)src) == 0)
 436                 return -1;
 437
 438         return 0;
 439 }
 440
 441 /**
 442  * Atomically writes the link status information into global
 443  * structure rte_eth_dev.
 444  *
 445  * @param dev
 446  *   - Pointer to the structure rte_eth_dev to read from.
 447  *   - Pointer to the buffer to be saved with the link status.
 448  *
 449  * @return
 450  *   - On success, zero.
 451  *   - On failure, negative value.
 452  */
 453 static inline int
 454 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 455                                 struct rte_eth_link *link)
 456 {
 457         struct rte_eth_link *dst = &(dev->data->dev_link);
 458         struct rte_eth_link *src = link;
 459
 460         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 461                                         *(uint64_t *)src) == 0)
 462                 return -1;
 463
 464         return 0;
 465 }
 466
 467 /*
 468  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 469  */
 470 static inline int
 471 ixgbe_is_sfp(struct ixgbe_hw *hw)
 472 {
 473         switch (hw->phy.type) {
 474         case ixgbe_phy_sfp_avago:
 475         case ixgbe_phy_sfp_ftl:
 476         case ixgbe_phy_sfp_intel:
 477         case ixgbe_phy_sfp_unknown:
 478         case ixgbe_phy_sfp_passive_tyco:
 479         case ixgbe_phy_sfp_passive_unknown:
 480                 return 1;
 481         default:
 482                 return 0;
 483         }
 484 }
 485
 486 static inline int32_t
 487 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 488 {
 489         uint32_t ctrl_ext;
 490         int32_t status;
 491
 492         status = ixgbe_reset_hw(hw);
 493
 494         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 495         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 496         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 497         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 498         IXGBE_WRITE_FLUSH(hw);
 499
 500         return status;
 501 }
 502
 503 static inline void
 504 ixgbe_enable_intr(struct rte_eth_dev *dev)
 505 {
 506         struct ixgbe_interrupt *intr =
 507                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 508         struct ixgbe_hw *hw =
 509                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 510
 511         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 512         IXGBE_WRITE_FLUSH(hw);
 513 }
 514
 515 /*
 516  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 517  */
 518 static void
 519 ixgbe_disable_intr(struct ixgbe_hw *hw)
 520 {
 521         PMD_INIT_FUNC_TRACE();
 522
 523         if (hw->mac.type == ixgbe_mac_82598EB) {
 524                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 525         } else {
 526                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 527                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 528                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 529         }
 530         IXGBE_WRITE_FLUSH(hw);
 531 }
 532
 533 /*
 534  * This function resets queue statistics mapping registers.
 535  * From Niantic datasheet, Initialization of Statistics section:
 536  * "...if software requires the queue counters, the RQSMR and TQSM registers
 537  * must be re-programmed following a device reset.
 538  */
 539 static void
 540 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 541 {
 542         uint32_t i;
 543
 544         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 545                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 546                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 547         }
 548 }
 549
 550
 551 static int
 552 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 553                                   uint16_t queue_id,
 554                                   uint8_t stat_idx,
 555                                   uint8_t is_rx)
 556 {
 557 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 558 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 559 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 560
 561         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 562         struct ixgbe_stat_mapping_registers *stat_mappings =
 563                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 564         uint32_t qsmr_mask = 0;
 565         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 566         uint32_t q_map;
 567         uint8_t n, offset;
 568
 569         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 570                 (hw->mac.type != ixgbe_mac_X540) &&
 571                 (hw->mac.type != ixgbe_mac_X550) &&
 572                 (hw->mac.type != ixgbe_mac_X550EM_x))
 573                 return -ENOSYS;
 574
 575         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 576                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 577                      queue_id, stat_idx);
 578
 579         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 580         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 581                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 582                 return -EIO;
 583         }
 584         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 585
 586         /* Now clear any previous stat_idx set */
 587         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 588         if (!is_rx)
 589                 stat_mappings->tqsm[n] &= ~clearing_mask;
 590         else
 591                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 592
 593         q_map = (uint32_t)stat_idx;
 594         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 595         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 596         if (!is_rx)
 597                 stat_mappings->tqsm[n] |= qsmr_mask;
 598         else
 599                 stat_mappings->rqsmr[n] |= qsmr_mask;
 600
 601         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 602                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 603                      queue_id, stat_idx);
 604         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 605                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 606
 607         /* Now write the mapping in the appropriate register */
 608         if (is_rx) {
 609                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 610                              stat_mappings->rqsmr[n], n);
 611                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 612         }
 613         else {
 614                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 615                              stat_mappings->tqsm[n], n);
 616                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 617         }
 618         return 0;
 619 }
 620
 621 static void
 622 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 623 {
 624         struct ixgbe_stat_mapping_registers *stat_mappings =
 625                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 626         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 627         int i;
 628
 629         /* write whatever was in stat mapping table to the NIC */
 630         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 631                 /* rx */
 632                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 633
 634                 /* tx */
 635                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 636         }
 637 }
 638
 639 static void
 640 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 641 {
 642         uint8_t i;
 643         struct ixgbe_dcb_tc_config *tc;
 644         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 645
 646         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 647         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 648         for (i = 0; i < dcb_max_tc; i++) {
 649                 tc = &dcb_config->tc_config[i];
 650                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 651                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 652                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 653                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 654                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 655                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 656                 tc->pfc = ixgbe_dcb_pfc_disabled;
 657         }
 658
 659         /* Initialize default user to priority mapping, UPx->TC0 */
 660         tc = &dcb_config->tc_config[0];
 661         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 662         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 663         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 664                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 665                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 666         }
 667         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 668         dcb_config->pfc_mode_enable = false;
 669         dcb_config->vt_mode = true;
 670         dcb_config->round_robin_enable = false;
 671         /* support all DCB capabilities in 82599 */
 672         dcb_config->support.capabilities = 0xFF;
 673
 674         /*we only support 4 Tcs for X540, X550 */
 675         if (hw->mac.type == ixgbe_mac_X540 ||
 676                 hw->mac.type == ixgbe_mac_X550 ||
 677                 hw->mac.type == ixgbe_mac_X550EM_x) {
 678                 dcb_config->num_tcs.pg_tcs = 4;
 679                 dcb_config->num_tcs.pfc_tcs = 4;
 680         }
 681 }
 682
 683 /*
 684  * Ensure that all locks are released before first NVM or PHY access
 685  */
 686 static void
 687 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 688 {
 689         uint16_t mask;
 690
 691         /*
 692          * Phy lock should not fail in this early stage. If this is the case,
 693          * it is due to an improper exit of the application.
 694          * So force the release of the faulty lock. Release of common lock
 695          * is done automatically by swfw_sync function.
 696          */
 697         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 698         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 699                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 700         }
 701         ixgbe_release_swfw_semaphore(hw, mask);
 702
 703         /*
 704          * These ones are more tricky since they are common to all ports; but
 705          * swfw_sync retries last long enough (1s) to be almost sure that if
 706          * lock can not be taken it is due to an improper lock of the
 707          * semaphore.
 708          */
 709         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 710         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 711                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 712         }
 713         ixgbe_release_swfw_semaphore(hw, mask);
 714 }
 715
 716 /*
 717  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 718  * It returns 0 on success.
 719  */
 720 static int
 721 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 722                      struct rte_eth_dev *eth_dev)
 723 {
 724         struct rte_pci_device *pci_dev;
 725         struct ixgbe_hw *hw =
 726                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 727         struct ixgbe_vfta * shadow_vfta =
 728                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 729         struct ixgbe_hwstrip *hwstrip =
 730                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 731         struct ixgbe_dcb_config *dcb_config =
 732                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 733         uint32_t ctrl_ext;
 734         uint16_t csum;
 735         int diag, i;
 736
 737         PMD_INIT_FUNC_TRACE();
 738
 739         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 740         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 741         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 742
 743         /*
 744          * For secondary processes, we don't initialise any further as primary
 745          * has already done this work. Only check we don't need a different
 746          * RX and TX function.
 747          */
 748         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 749                 struct igb_tx_queue *txq;
 750                 /* TX queue function in primary, set by last queue initialized
 751                  * Tx queue may not initialized by primary process */
 752                 if (eth_dev->data->tx_queues) {
 753                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 754                         set_tx_function(eth_dev, txq);
 755                 } else {
 756                         /* Use default TX function if we get here */
 757                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 758                                            "Using default TX function.");
 759                 }
 760
 761                 if (eth_dev->data->scattered_rx)
 762                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 763                 return 0;
 764         }
 765         pci_dev = eth_dev->pci_dev;
 766
 767         /* Vendor and Device ID need to be set before init of shared code */
 768         hw->device_id = pci_dev->id.device_id;
 769         hw->vendor_id = pci_dev->id.vendor_id;
 770         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 771         hw->allow_unsupported_sfp = 1;
 772
 773         /* Initialize the shared code (base driver) */
 774 #ifdef RTE_NIC_BYPASS
 775         diag = ixgbe_bypass_init_shared_code(hw);
 776 #else
 777         diag = ixgbe_init_shared_code(hw);
 778 #endif /* RTE_NIC_BYPASS */
 779
 780         if (diag != IXGBE_SUCCESS) {
 781                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 782                 return -EIO;
 783         }
 784
 785         /* pick up the PCI bus settings for reporting later */
 786         ixgbe_get_bus_info(hw);
 787
 788         /* Unlock any pending hardware semaphore */
 789         ixgbe_swfw_lock_reset(hw);
 790
 791         /* Initialize DCB configuration*/
 792         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 793         ixgbe_dcb_init(hw,dcb_config);
 794         /* Get Hardware Flow Control setting */
 795         hw->fc.requested_mode = ixgbe_fc_full;
 796         hw->fc.current_mode = ixgbe_fc_full;
 797         hw->fc.pause_time = IXGBE_FC_PAUSE;
 798         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 799                 hw->fc.low_water[i] = IXGBE_FC_LO;
 800                 hw->fc.high_water[i] = IXGBE_FC_HI;
 801         }
 802         hw->fc.send_xon = 1;
 803
 804         /* Make sure we have a good EEPROM before we read from it */
 805         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 806         if (diag != IXGBE_SUCCESS) {
 807                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 808                 return -EIO;
 809         }
 810
 811 #ifdef RTE_NIC_BYPASS
 812         diag = ixgbe_bypass_init_hw(hw);
 813 #else
 814         diag = ixgbe_init_hw(hw);
 815 #endif /* RTE_NIC_BYPASS */
 816
 817         /*
 818          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 819          * is called too soon after the kernel driver unbinding/binding occurs.
 820          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 821          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 822          * also called. See ixgbe_identify_phy_82599(). The reason for the
 823          * failure is not known, and only occuts when virtualisation features
 824          * are disabled in the bios. A delay of 100ms  was found to be enough by
 825          * trial-and-error, and is doubled to be safe.
 826          */
 827         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 828                 rte_delay_ms(200);
 829                 diag = ixgbe_init_hw(hw);
 830         }
 831
 832         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 833                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 834                     "LOM.  Please be aware there may be issues associated "
 835                     "with your hardware.");
 836                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 837                     "please contact your Intel or hardware representative "
 838                     "who provided you with this hardware.");
 839         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 840                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 841         if (diag) {
 842                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 843                 return -EIO;
 844         }
 845
 846         /* disable interrupt */
 847         ixgbe_disable_intr(hw);
 848
 849         /* reset mappings for queue statistics hw counters*/
 850         ixgbe_reset_qstat_mappings(hw);
 851
 852         /* Allocate memory for storing MAC addresses */
 853         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 854                         hw->mac.num_rar_entries, 0);
 855         if (eth_dev->data->mac_addrs == NULL) {
 856                 PMD_INIT_LOG(ERR,
 857                         "Failed to allocate %u bytes needed to store "
 858                         "MAC addresses",
 859                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 860                 return -ENOMEM;
 861         }
 862         /* Copy the permanent MAC address */
 863         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 864                         &eth_dev->data->mac_addrs[0]);
 865
 866         /* Allocate memory for storing hash filter MAC addresses */
 867         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 868                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 869         if (eth_dev->data->hash_mac_addrs == NULL) {
 870                 PMD_INIT_LOG(ERR,
 871                         "Failed to allocate %d bytes needed to store MAC addresses",
 872                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 873                 return -ENOMEM;
 874         }
 875
 876         /* initialize the vfta */
 877         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 878
 879         /* initialize the hw strip bitmap*/
 880         memset(hwstrip, 0, sizeof(*hwstrip));
 881
 882         /* initialize PF if max_vfs not zero */
 883         ixgbe_pf_host_init(eth_dev);
 884
 885         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 886         /* let hardware know driver is loaded */
 887         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 888         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 889         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 890         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 891         IXGBE_WRITE_FLUSH(hw);
 892
 893         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 894                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 895                              (int) hw->mac.type, (int) hw->phy.type,
 896                              (int) hw->phy.sfp_type);
 897         else
 898                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 899                              (int) hw->mac.type, (int) hw->phy.type);
 900
 901         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 902                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 903                         pci_dev->id.device_id);
 904
 905         rte_intr_callback_register(&(pci_dev->intr_handle),
 906                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 907
 908         /* enable uio intr after callback register */
 909         rte_intr_enable(&(pci_dev->intr_handle));
 910
 911         /* enable support intr */
 912         ixgbe_enable_intr(eth_dev);
 913
 914         return 0;
 915 }
 916
 917
 918 /*
 919  * Negotiate mailbox API version with the PF.
 920  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 921  * Then we try to negotiate starting with the most recent one.
 922  * If all negotiation attempts fail, then we will proceed with
 923  * the default one (ixgbe_mbox_api_10).
 924  */
 925 static void
 926 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 927 {
 928         int32_t i;
 929
 930         /* start with highest supported, proceed down */
 931         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 932                 ixgbe_mbox_api_11,
 933                 ixgbe_mbox_api_10,
 934         };
 935
 936         for (i = 0;
 937                         i != RTE_DIM(sup_ver) &&
 938                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 939                         i++)
 940                 ;
 941 }
 942
 943 static void
 944 generate_random_mac_addr(struct ether_addr *mac_addr)
 945 {
 946         uint64_t random;
 947
 948         /* Set Organizationally Unique Identifier (OUI) prefix. */
 949         mac_addr->addr_bytes[0] = 0x00;
 950         mac_addr->addr_bytes[1] = 0x09;
 951         mac_addr->addr_bytes[2] = 0xC0;
 952         /* Force indication of locally assigned MAC address. */
 953         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 954         /* Generate the last 3 bytes of the MAC address with a random number. */
 955         random = rte_rand();
 956         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 957 }
 958
 959 /*
 960  * Virtual Function device init
 961  */
 962 static int
 963 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 964                      struct rte_eth_dev *eth_dev)
 965 {
 966         int diag;
 967         uint32_t tc, tcs;
 968         struct rte_pci_device *pci_dev;
 969         struct ixgbe_hw *hw =
 970                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 971         struct ixgbe_vfta * shadow_vfta =
 972                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 973         struct ixgbe_hwstrip *hwstrip =
 974                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 975         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 976
 977         PMD_INIT_FUNC_TRACE();
 978
 979         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 980         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 981         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 982
 983         /* for secondary processes, we don't initialise any further as primary
 984          * has already done this work. Only check we don't need a different
 985          * RX function */
 986         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 987                 if (eth_dev->data->scattered_rx)
 988                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 989                 return 0;
 990         }
 991
 992         pci_dev = eth_dev->pci_dev;
 993
 994         hw->device_id = pci_dev->id.device_id;
 995         hw->vendor_id = pci_dev->id.vendor_id;
 996         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 997
 998         /* initialize the vfta */
 999         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1000
1001         /* initialize the hw strip bitmap*/
1002         memset(hwstrip, 0, sizeof(*hwstrip));
1003
1004         /* Initialize the shared code (base driver) */
1005         diag = ixgbe_init_shared_code(hw);
1006         if (diag != IXGBE_SUCCESS) {
1007                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1008                 return -EIO;
1009         }
1010
1011         /* init_mailbox_params */
1012         hw->mbx.ops.init_params(hw);
1013
1014         /* Disable the interrupts for VF */
1015         ixgbevf_intr_disable(hw);
1016
1017         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1018         diag = hw->mac.ops.reset_hw(hw);
1019
1020         /*
1021          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1022          * the underlying PF driver has not assigned a MAC address to the VF.
1023          * In this case, assign a random MAC address.
1024          */
1025         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1026                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1027                 return (diag);
1028         }
1029
1030         /* negotiate mailbox API version to use with the PF. */
1031         ixgbevf_negotiate_api(hw);
1032
1033         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1034         ixgbevf_get_queues(hw, &tcs, &tc);
1035
1036         /* Allocate memory for storing MAC addresses */
1037         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1038                         hw->mac.num_rar_entries, 0);
1039         if (eth_dev->data->mac_addrs == NULL) {
1040                 PMD_INIT_LOG(ERR,
1041                         "Failed to allocate %u bytes needed to store "
1042                         "MAC addresses",
1043                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1044                 return -ENOMEM;
1045         }
1046
1047         /* Generate a random MAC address, if none was assigned by PF. */
1048         if (is_zero_ether_addr(perm_addr)) {
1049                 generate_random_mac_addr(perm_addr);
1050                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1051                 if (diag) {
1052                         rte_free(eth_dev->data->mac_addrs);
1053                         eth_dev->data->mac_addrs = NULL;
1054                         return diag;
1055                 }
1056                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1057                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1058                              "%02x:%02x:%02x:%02x:%02x:%02x",
1059                              perm_addr->addr_bytes[0],
1060                              perm_addr->addr_bytes[1],
1061                              perm_addr->addr_bytes[2],
1062                              perm_addr->addr_bytes[3],
1063                              perm_addr->addr_bytes[4],
1064                              perm_addr->addr_bytes[5]);
1065         }
1066
1067         /* Copy the permanent MAC address */
1068         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1069
1070         /* reset the hardware with the new settings */
1071         diag = hw->mac.ops.start_hw(hw);
1072         switch (diag) {
1073                 case  0:
1074                         break;
1075
1076                 default:
1077                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1078                         return (-EIO);
1079         }
1080
1081         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1082                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1083                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1084
1085         return 0;
1086 }
1087
1088 static struct eth_driver rte_ixgbe_pmd = {
1089         {
1090                 .name = "rte_ixgbe_pmd",
1091                 .id_table = pci_id_ixgbe_map,
1092                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1093         },
1094         .eth_dev_init = eth_ixgbe_dev_init,
1095         .dev_private_size = sizeof(struct ixgbe_adapter),
1096 };
1097
1098 /*
1099  * virtual function driver struct
1100  */
1101 static struct eth_driver rte_ixgbevf_pmd = {
1102         {
1103                 .name = "rte_ixgbevf_pmd",
1104                 .id_table = pci_id_ixgbevf_map,
1105                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1106         },
1107         .eth_dev_init = eth_ixgbevf_dev_init,
1108         .dev_private_size = sizeof(struct ixgbe_adapter),
1109 };
1110
1111 /*
1112  * Driver initialization routine.
1113  * Invoked once at EAL init time.
1114  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1115  */
1116 static int
1117 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1118 {
1119         PMD_INIT_FUNC_TRACE();
1120
1121         rte_eth_driver_register(&rte_ixgbe_pmd);
1122         return 0;
1123 }
1124
1125 /*
1126  * VF Driver initialization routine.
1127  * Invoked one at EAL init time.
1128  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1129  */
1130 static int
1131 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1132 {
1133         PMD_INIT_FUNC_TRACE();
1134
1135         rte_eth_driver_register(&rte_ixgbevf_pmd);
1136         return (0);
1137 }
1138
1139 static int
1140 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1141 {
1142         struct ixgbe_hw *hw =
1143                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1144         struct ixgbe_vfta * shadow_vfta =
1145                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1146         uint32_t vfta;
1147         uint32_t vid_idx;
1148         uint32_t vid_bit;
1149
1150         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1151         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1152         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1153         if (on)
1154                 vfta |= vid_bit;
1155         else
1156                 vfta &= ~vid_bit;
1157         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1158
1159         /* update local VFTA copy */
1160         shadow_vfta->vfta[vid_idx] = vfta;
1161
1162         return 0;
1163 }
1164
1165 static void
1166 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1167 {
1168         if (on)
1169                 ixgbe_vlan_hw_strip_enable(dev, queue);
1170         else
1171                 ixgbe_vlan_hw_strip_disable(dev, queue);
1172 }
1173
1174 static void
1175 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1176 {
1177         struct ixgbe_hw *hw =
1178                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1179
1180         /* Only the high 16-bits is valid */
1181         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1182 }
1183
1184 void
1185 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1186 {
1187         struct ixgbe_hw *hw =
1188                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1189         uint32_t vlnctrl;
1190
1191         PMD_INIT_FUNC_TRACE();
1192
1193         /* Filter Table Disable */
1194         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1195         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1196
1197         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1198 }
1199
1200 void
1201 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1202 {
1203         struct ixgbe_hw *hw =
1204                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205         struct ixgbe_vfta * shadow_vfta =
1206                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1207         uint32_t vlnctrl;
1208         uint16_t i;
1209
1210         PMD_INIT_FUNC_TRACE();
1211
1212         /* Filter Table Enable */
1213         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1214         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1215         vlnctrl |= IXGBE_VLNCTRL_VFE;
1216
1217         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1218
1219         /* write whatever is in local vfta copy */
1220         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1221                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1222 }
1223
1224 static void
1225 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1226 {
1227         struct ixgbe_hwstrip *hwstrip =
1228                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1229
1230         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1231                 return;
1232
1233         if (on)
1234                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1235         else
1236                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1237 }
1238
1239 static void
1240 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1241 {
1242         struct ixgbe_hw *hw =
1243                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1244         uint32_t ctrl;
1245
1246         PMD_INIT_FUNC_TRACE();
1247
1248         if (hw->mac.type == ixgbe_mac_82598EB) {
1249                 /* No queue level support */
1250                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1251                 return;
1252         }
1253         else {
1254                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1255                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1256                 ctrl &= ~IXGBE_RXDCTL_VME;
1257                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1258         }
1259         /* record those setting for HW strip per queue */
1260         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1261 }
1262
1263 static void
1264 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1265 {
1266         struct ixgbe_hw *hw =
1267                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1268         uint32_t ctrl;
1269
1270         PMD_INIT_FUNC_TRACE();
1271
1272         if (hw->mac.type == ixgbe_mac_82598EB) {
1273                 /* No queue level supported */
1274                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1275                 return;
1276         }
1277         else {
1278                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1279                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1280                 ctrl |= IXGBE_RXDCTL_VME;
1281                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1282         }
1283         /* record those setting for HW strip per queue */
1284         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1285 }
1286
1287 void
1288 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1289 {
1290         struct ixgbe_hw *hw =
1291                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1292         uint32_t ctrl;
1293         uint16_t i;
1294
1295         PMD_INIT_FUNC_TRACE();
1296
1297         if (hw->mac.type == ixgbe_mac_82598EB) {
1298                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1299                 ctrl &= ~IXGBE_VLNCTRL_VME;
1300                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1301         }
1302         else {
1303                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1304                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1305                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1306                         ctrl &= ~IXGBE_RXDCTL_VME;
1307                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1308
1309                         /* record those setting for HW strip per queue */
1310                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1311                 }
1312         }
1313 }
1314
1315 void
1316 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1317 {
1318         struct ixgbe_hw *hw =
1319                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1320         uint32_t ctrl;
1321         uint16_t i;
1322
1323         PMD_INIT_FUNC_TRACE();
1324
1325         if (hw->mac.type == ixgbe_mac_82598EB) {
1326                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1327                 ctrl |= IXGBE_VLNCTRL_VME;
1328                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1329         }
1330         else {
1331                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1332                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1333                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1334                         ctrl |= IXGBE_RXDCTL_VME;
1335                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1336
1337                         /* record those setting for HW strip per queue */
1338                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1339                 }
1340         }
1341 }
1342
1343 static void
1344 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1345 {
1346         struct ixgbe_hw *hw =
1347                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348         uint32_t ctrl;
1349
1350         PMD_INIT_FUNC_TRACE();
1351
1352         /* DMATXCTRL: Geric Double VLAN Disable */
1353         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1354         ctrl &= ~IXGBE_DMATXCTL_GDV;
1355         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1356
1357         /* CTRL_EXT: Global Double VLAN Disable */
1358         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1359         ctrl &= ~IXGBE_EXTENDED_VLAN;
1360         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1361
1362 }
1363
1364 static void
1365 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1366 {
1367         struct ixgbe_hw *hw =
1368                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1369         uint32_t ctrl;
1370
1371         PMD_INIT_FUNC_TRACE();
1372
1373         /* DMATXCTRL: Geric Double VLAN Enable */
1374         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1375         ctrl |= IXGBE_DMATXCTL_GDV;
1376         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1377
1378         /* CTRL_EXT: Global Double VLAN Enable */
1379         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1380         ctrl |= IXGBE_EXTENDED_VLAN;
1381         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1382
1383         /*
1384          * VET EXT field in the EXVET register = 0x8100 by default
1385          * So no need to change. Same to VT field of DMATXCTL register
1386          */
1387 }
1388
1389 static void
1390 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1391 {
1392         if(mask & ETH_VLAN_STRIP_MASK){
1393                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1394                         ixgbe_vlan_hw_strip_enable_all(dev);
1395                 else
1396                         ixgbe_vlan_hw_strip_disable_all(dev);
1397         }
1398
1399         if(mask & ETH_VLAN_FILTER_MASK){
1400                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1401                         ixgbe_vlan_hw_filter_enable(dev);
1402                 else
1403                         ixgbe_vlan_hw_filter_disable(dev);
1404         }
1405
1406         if(mask & ETH_VLAN_EXTEND_MASK){
1407                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1408                         ixgbe_vlan_hw_extend_enable(dev);
1409                 else
1410                         ixgbe_vlan_hw_extend_disable(dev);
1411         }
1412 }
1413
1414 static void
1415 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1416 {
1417         struct ixgbe_hw *hw =
1418                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1419         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1420         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1421         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1422         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1423 }
1424
1425 static int
1426 ixgbe_dev_configure(struct rte_eth_dev *dev)
1427 {
1428         struct ixgbe_interrupt *intr =
1429                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1430
1431         PMD_INIT_FUNC_TRACE();
1432
1433         /* set flag to update link status after init */
1434         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1435
1436         return 0;
1437 }
1438
1439 /*
1440  * Configure device link speed and setup link.
1441  * It returns 0 on success.
1442  */
1443 static int
1444 ixgbe_dev_start(struct rte_eth_dev *dev)
1445 {
1446         struct ixgbe_hw *hw =
1447                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1448         struct ixgbe_vf_info *vfinfo =
1449                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1450         int err, link_up = 0, negotiate = 0;
1451         uint32_t speed = 0;
1452         int mask = 0;
1453         int status;
1454         uint16_t vf, idx;
1455
1456         PMD_INIT_FUNC_TRACE();
1457
1458         /* IXGBE devices don't support half duplex */
1459         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1460                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1461                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1462                              dev->data->dev_conf.link_duplex,
1463                              dev->data->port_id);
1464                 return -EINVAL;
1465         }
1466
1467         /* stop adapter */
1468         hw->adapter_stopped = FALSE;
1469         ixgbe_stop_adapter(hw);
1470
1471         /* reinitialize adapter
1472          * this calls reset and start */
1473         status = ixgbe_pf_reset_hw(hw);
1474         if (status != 0)
1475                 return -1;
1476         hw->mac.ops.start_hw(hw);
1477         hw->mac.get_link_status = true;
1478
1479         /* configure PF module if SRIOV enabled */
1480         ixgbe_pf_host_configure(dev);
1481
1482         /* initialize transmission unit */
1483         ixgbe_dev_tx_init(dev);
1484
1485         /* This can fail when allocating mbufs for descriptor rings */
1486         err = ixgbe_dev_rx_init(dev);
1487         if (err) {
1488                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1489                 goto error;
1490         }
1491
1492         err = ixgbe_dev_rxtx_start(dev);
1493         if (err < 0) {
1494                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1495                 goto error;
1496         }
1497
1498         /* Skip link setup if loopback mode is enabled for 82599. */
1499         if (hw->mac.type == ixgbe_mac_82599EB &&
1500                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1501                 goto skip_link_setup;
1502
1503         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1504                 err = hw->mac.ops.setup_sfp(hw);
1505                 if (err)
1506                         goto error;
1507         }
1508
1509         /* Turn on the laser */
1510         ixgbe_enable_tx_laser(hw);
1511
1512         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1513         if (err)
1514                 goto error;
1515         dev->data->dev_link.link_status = link_up;
1516
1517         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1518         if (err)
1519                 goto error;
1520
1521         switch(dev->data->dev_conf.link_speed) {
1522         case ETH_LINK_SPEED_AUTONEG:
1523                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1524                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1525                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1526                 break;
1527         case ETH_LINK_SPEED_100:
1528                 /*
1529                  * Invalid for 82598 but error will be detected by
1530                  * ixgbe_setup_link()
1531                  */
1532                 speed = IXGBE_LINK_SPEED_100_FULL;
1533                 break;
1534         case ETH_LINK_SPEED_1000:
1535                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1536                 break;
1537         case ETH_LINK_SPEED_10000:
1538                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1539                 break;
1540         default:
1541                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1542                              dev->data->dev_conf.link_speed,
1543                              dev->data->port_id);
1544                 goto error;
1545         }
1546
1547         err = ixgbe_setup_link(hw, speed, link_up);
1548         if (err)
1549                 goto error;
1550
1551 skip_link_setup:
1552
1553         /* check if lsc interrupt is enabled */
1554         if (dev->data->dev_conf.intr_conf.lsc != 0)
1555                 ixgbe_dev_lsc_interrupt_setup(dev);
1556
1557         /* resume enabled intr since hw reset */
1558         ixgbe_enable_intr(dev);
1559
1560         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1561                 ETH_VLAN_EXTEND_MASK;
1562         ixgbe_vlan_offload_set(dev, mask);
1563
1564         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1565                 /* Enable vlan filtering for VMDq */
1566                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1567         }
1568
1569         /* Configure DCB hw */
1570         ixgbe_configure_dcb(dev);
1571
1572         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1573                 err = ixgbe_fdir_configure(dev);
1574                 if (err)
1575                         goto error;
1576         }
1577
1578         /* Restore vf rate limit */
1579         if (vfinfo != NULL) {
1580                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1581                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1582                                 if (vfinfo[vf].tx_rate[idx] != 0)
1583                                         ixgbe_set_vf_rate_limit(dev, vf,
1584                                                 vfinfo[vf].tx_rate[idx],
1585                                                 1 << idx);
1586         }
1587
1588         ixgbe_restore_statistics_mapping(dev);
1589
1590         return (0);
1591
1592 error:
1593         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1594         ixgbe_dev_clear_queues(dev);
1595         return -EIO;
1596 }
1597
1598 /*
1599  * Stop device: disable rx and tx functions to allow for reconfiguring.
1600  */
1601 static void
1602 ixgbe_dev_stop(struct rte_eth_dev *dev)
1603 {
1604         struct rte_eth_link link;
1605         struct ixgbe_hw *hw =
1606                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1607         struct ixgbe_vf_info *vfinfo =
1608                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1609         int vf;
1610
1611         PMD_INIT_FUNC_TRACE();
1612
1613         /* disable interrupts */
1614         ixgbe_disable_intr(hw);
1615
1616         /* reset the NIC */
1617         ixgbe_pf_reset_hw(hw);
1618         hw->adapter_stopped = FALSE;
1619
1620         /* stop adapter */
1621         ixgbe_stop_adapter(hw);
1622
1623         for (vf = 0; vfinfo != NULL &&
1624                      vf < dev->pci_dev->max_vfs; vf++)
1625                 vfinfo[vf].clear_to_send = false;
1626
1627         /* Turn off the laser */
1628         ixgbe_disable_tx_laser(hw);
1629
1630         ixgbe_dev_clear_queues(dev);
1631
1632         /* Clear stored conf */
1633         dev->data->scattered_rx = 0;
1634
1635         /* Clear recorded link status */
1636         memset(&link, 0, sizeof(link));
1637         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1638 }
1639
1640 /*
1641  * Set device link up: enable tx laser.
1642  */
1643 static int
1644 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1645 {
1646         struct ixgbe_hw *hw =
1647                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1648         if (hw->mac.type == ixgbe_mac_82599EB) {
1649 #ifdef RTE_NIC_BYPASS
1650                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1651                         /* Not suported in bypass mode */
1652                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1653                                      "by device id 0x%x", hw->device_id);
1654                         return -ENOTSUP;
1655                 }
1656 #endif
1657                 /* Turn on the laser */
1658                 ixgbe_enable_tx_laser(hw);
1659                 return 0;
1660         }
1661
1662         PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1663                      hw->device_id);
1664         return -ENOTSUP;
1665 }
1666
1667 /*
1668  * Set device link down: disable tx laser.
1669  */
1670 static int
1671 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1672 {
1673         struct ixgbe_hw *hw =
1674                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1675         if (hw->mac.type == ixgbe_mac_82599EB) {
1676 #ifdef RTE_NIC_BYPASS
1677                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1678                         /* Not suported in bypass mode */
1679                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1680                                      "by device id 0x%x", hw->device_id);
1681                         return -ENOTSUP;
1682                 }
1683 #endif
1684                 /* Turn off the laser */
1685                 ixgbe_disable_tx_laser(hw);
1686                 return 0;
1687         }
1688
1689         PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1690                      hw->device_id);
1691         return -ENOTSUP;
1692 }
1693
1694 /*
1695  * Reest and stop device.
1696  */
1697 static void
1698 ixgbe_dev_close(struct rte_eth_dev *dev)
1699 {
1700         struct ixgbe_hw *hw =
1701                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1702
1703         PMD_INIT_FUNC_TRACE();
1704
1705         ixgbe_pf_reset_hw(hw);
1706
1707         ixgbe_dev_stop(dev);
1708         hw->adapter_stopped = 1;
1709
1710         ixgbe_disable_pcie_master(hw);
1711
1712         /* reprogram the RAR[0] in case user changed it. */
1713         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1714 }
1715
1716 /*
1717  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1718  */
1719 static void
1720 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1721 {
1722         struct ixgbe_hw *hw =
1723                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1724         struct ixgbe_hw_stats *hw_stats =
1725                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1726         uint32_t bprc, lxon, lxoff, total;
1727         uint64_t total_missed_rx, total_qbrc, total_qprc;
1728         unsigned i;
1729
1730         total_missed_rx = 0;
1731         total_qbrc = 0;
1732         total_qprc = 0;
1733
1734         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1735         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1736         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1737         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1738
1739         for (i = 0; i < 8; i++) {
1740                 uint32_t mp;
1741                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1742                 /* global total per queue */
1743                 hw_stats->mpc[i] += mp;
1744                 /* Running comprehensive total for stats display */
1745                 total_missed_rx += hw_stats->mpc[i];
1746                 if (hw->mac.type == ixgbe_mac_82598EB)
1747                         hw_stats->rnbc[i] +=
1748                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1749                 hw_stats->pxontxc[i] +=
1750                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1751                 hw_stats->pxonrxc[i] +=
1752                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1753                 hw_stats->pxofftxc[i] +=
1754                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1755                 hw_stats->pxoffrxc[i] +=
1756                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1757                 hw_stats->pxon2offc[i] +=
1758                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1759         }
1760         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1761                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1762                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1763                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1764                 hw_stats->qbrc[i] +=
1765                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1766                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1767                 hw_stats->qbtc[i] +=
1768                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1769                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1770
1771                 total_qprc += hw_stats->qprc[i];
1772                 total_qbrc += hw_stats->qbrc[i];
1773         }
1774         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1775         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1776         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1777
1778         /* Note that gprc counts missed packets */
1779         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1780
1781         if (hw->mac.type != ixgbe_mac_82598EB) {
1782                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1783                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1784                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1785                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1786                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1787                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1788                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1789                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1790         } else {
1791                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1792                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1793                 /* 82598 only has a counter in the high register */
1794                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1795                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1796                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1797         }
1798
1799         /*
1800          * Workaround: mprc hardware is incorrectly counting
1801          * broadcasts, so for now we subtract those.
1802          */
1803         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1804         hw_stats->bprc += bprc;
1805         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1806         if (hw->mac.type == ixgbe_mac_82598EB)
1807                 hw_stats->mprc -= bprc;
1808
1809         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1810         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1811         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1812         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1813         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1814         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1815
1816         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1817         hw_stats->lxontxc += lxon;
1818         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1819         hw_stats->lxofftxc += lxoff;
1820         total = lxon + lxoff;
1821
1822         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1823         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1824         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1825         hw_stats->gptc -= total;
1826         hw_stats->mptc -= total;
1827         hw_stats->ptc64 -= total;
1828         hw_stats->gotc -= total * ETHER_MIN_LEN;
1829
1830         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1831         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1832         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1833         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1834         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1835         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1836         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1837         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1838         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1839         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1840         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1841         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1842         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1843         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1844         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1845         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1846         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1847         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1848         /* Only read FCOE on 82599 */
1849         if (hw->mac.type != ixgbe_mac_82598EB) {
1850                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1851                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1852                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1853                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1854                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1855         }
1856
1857         if (stats == NULL)
1858                 return;
1859
1860         /* Fill out the rte_eth_stats statistics structure */
1861         stats->ipackets = total_qprc;
1862         stats->ibytes = total_qbrc;
1863         stats->opackets = hw_stats->gptc;
1864         stats->obytes = hw_stats->gotc;
1865         stats->imcasts = hw_stats->mprc;
1866
1867         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1868                 stats->q_ipackets[i] = hw_stats->qprc[i];
1869                 stats->q_opackets[i] = hw_stats->qptc[i];
1870                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1871                 stats->q_obytes[i] = hw_stats->qbtc[i];
1872                 stats->q_errors[i] = hw_stats->qprdc[i];
1873         }
1874
1875         /* Rx Errors */
1876         stats->ibadcrc  = hw_stats->crcerrs;
1877         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1878         stats->imissed  = total_missed_rx;
1879         stats->ierrors  = stats->ibadcrc +
1880                           stats->ibadlen +
1881                           stats->imissed +
1882                           hw_stats->illerrc + hw_stats->errbc;
1883
1884         /* Tx Errors */
1885         stats->oerrors  = 0;
1886
1887         /* XON/XOFF pause frames */
1888         stats->tx_pause_xon  = hw_stats->lxontxc;
1889         stats->rx_pause_xon  = hw_stats->lxonrxc;
1890         stats->tx_pause_xoff = hw_stats->lxofftxc;
1891         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1892
1893         /* Flow Director Stats registers */
1894         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1895         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1896         stats->fdirmatch = hw_stats->fdirmatch;
1897         stats->fdirmiss = hw_stats->fdirmiss;
1898 }
1899
1900 static void
1901 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1902 {
1903         struct ixgbe_hw_stats *stats =
1904                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1905
1906         /* HW registers are cleared on read */
1907         ixgbe_dev_stats_get(dev, NULL);
1908
1909         /* Reset software totals */
1910         memset(stats, 0, sizeof(*stats));
1911 }
1912
1913 static void
1914 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1915 {
1916         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1918                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1919
1920         /* Good Rx packet, include VF loopback */
1921         UPDATE_VF_STAT(IXGBE_VFGPRC,
1922             hw_stats->last_vfgprc, hw_stats->vfgprc);
1923
1924         /* Good Rx octets, include VF loopback */
1925         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1926             hw_stats->last_vfgorc, hw_stats->vfgorc);
1927
1928         /* Good Tx packet, include VF loopback */
1929         UPDATE_VF_STAT(IXGBE_VFGPTC,
1930             hw_stats->last_vfgptc, hw_stats->vfgptc);
1931
1932         /* Good Tx octets, include VF loopback */
1933         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1934             hw_stats->last_vfgotc, hw_stats->vfgotc);
1935
1936         /* Rx Multicst Packet */
1937         UPDATE_VF_STAT(IXGBE_VFMPRC,
1938             hw_stats->last_vfmprc, hw_stats->vfmprc);
1939
1940         if (stats == NULL)
1941                 return;
1942
1943         stats->ipackets = hw_stats->vfgprc;
1944         stats->ibytes = hw_stats->vfgorc;
1945         stats->opackets = hw_stats->vfgptc;
1946         stats->obytes = hw_stats->vfgotc;
1947         stats->imcasts = hw_stats->vfmprc;
1948 }
1949
1950 static void
1951 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1952 {
1953         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1954                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1955
1956         /* Sync HW register to the last stats */
1957         ixgbevf_dev_stats_get(dev, NULL);
1958
1959         /* reset HW current stats*/
1960         hw_stats->vfgprc = 0;
1961         hw_stats->vfgorc = 0;
1962         hw_stats->vfgptc = 0;
1963         hw_stats->vfgotc = 0;
1964         hw_stats->vfmprc = 0;
1965
1966 }
1967
1968 static void
1969 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1970 {
1971         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972
1973         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1974         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1975         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1976         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1977         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1978         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1979         dev_info->max_vfs = dev->pci_dev->max_vfs;
1980         if (hw->mac.type == ixgbe_mac_82598EB)
1981                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1982         else
1983                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1984         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
1985         dev_info->rx_offload_capa =
1986                 DEV_RX_OFFLOAD_VLAN_STRIP |
1987                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1988                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1989                 DEV_RX_OFFLOAD_TCP_CKSUM;
1990         dev_info->tx_offload_capa =
1991                 DEV_TX_OFFLOAD_VLAN_INSERT |
1992                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1993                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1994                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1995                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1996                 DEV_TX_OFFLOAD_TCP_TSO;
1997
1998         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1999                 .rx_thresh = {
2000                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2001                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2002                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2003                 },
2004                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2005                 .rx_drop_en = 0,
2006         };
2007
2008         dev_info->default_txconf = (struct rte_eth_txconf) {
2009                 .tx_thresh = {
2010                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2011                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2012                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2013                 },
2014                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2015                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2016                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2017                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2018         };
2019         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2020 }
2021
2022 static void
2023 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2024                      struct rte_eth_dev_info *dev_info)
2025 {
2026         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2027
2028         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2029         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2030         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2031         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2032         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2033         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2034         dev_info->max_vfs = dev->pci_dev->max_vfs;
2035         if (hw->mac.type == ixgbe_mac_82598EB)
2036                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2037         else
2038                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2039         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2040                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2041                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2042                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2043         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2044                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2045                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2046                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2047                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2048
2049         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2050                 .rx_thresh = {
2051                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2052                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2053                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2054                 },
2055                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2056                 .rx_drop_en = 0,
2057         };
2058
2059         dev_info->default_txconf = (struct rte_eth_txconf) {
2060                 .tx_thresh = {
2061                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2062                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2063                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2064                 },
2065                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2066                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2067                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2068                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2069         };
2070 }
2071
2072 /* return 0 means link status changed, -1 means not changed */
2073 static int
2074 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2075 {
2076         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077         struct rte_eth_link link, old;
2078         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2079         int link_up;
2080         int diag;
2081
2082         link.link_status = 0;
2083         link.link_speed = 0;
2084         link.link_duplex = 0;
2085         memset(&old, 0, sizeof(old));
2086         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2087
2088         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2089         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2090                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2091         else
2092                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2093         if (diag != 0) {
2094                 link.link_speed = ETH_LINK_SPEED_100;
2095                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2096                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2097                 if (link.link_status == old.link_status)
2098                         return -1;
2099                 return 0;
2100         }
2101
2102         if (link_speed == IXGBE_LINK_SPEED_UNKNOWN &&
2103             !hw->mac.get_link_status) {
2104                 memcpy(&link, &old, sizeof(link));
2105                 return -1;
2106         }
2107
2108         if (link_up == 0) {
2109                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2110                 if (link.link_status == old.link_status)
2111                         return -1;
2112                 return 0;
2113         }
2114         link.link_status = 1;
2115         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2116
2117         switch (link_speed) {
2118         default:
2119         case IXGBE_LINK_SPEED_UNKNOWN:
2120                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2121                 link.link_speed = ETH_LINK_SPEED_100;
2122                 break;
2123
2124         case IXGBE_LINK_SPEED_100_FULL:
2125                 link.link_speed = ETH_LINK_SPEED_100;
2126                 break;
2127
2128         case IXGBE_LINK_SPEED_1GB_FULL:
2129                 link.link_speed = ETH_LINK_SPEED_1000;
2130                 break;
2131
2132         case IXGBE_LINK_SPEED_10GB_FULL:
2133                 link.link_speed = ETH_LINK_SPEED_10000;
2134                 break;
2135         }
2136         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2137
2138         if (link.link_status == old.link_status)
2139                 return -1;
2140
2141         return 0;
2142 }
2143
2144 static void
2145 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2146 {
2147         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148         uint32_t fctrl;
2149
2150         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2151         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2152         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2153 }
2154
2155 static void
2156 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2157 {
2158         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2159         uint32_t fctrl;
2160
2161         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2162         fctrl &= (~IXGBE_FCTRL_UPE);
2163         if (dev->data->all_multicast == 1)
2164                 fctrl |= IXGBE_FCTRL_MPE;
2165         else
2166                 fctrl &= (~IXGBE_FCTRL_MPE);
2167         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2168 }
2169
2170 static void
2171 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2172 {
2173         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2174         uint32_t fctrl;
2175
2176         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2177         fctrl |= IXGBE_FCTRL_MPE;
2178         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2179 }
2180
2181 static void
2182 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2183 {
2184         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2185         uint32_t fctrl;
2186
2187         if (dev->data->promiscuous == 1)
2188                 return; /* must remain in all_multicast mode */
2189
2190         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2191         fctrl &= (~IXGBE_FCTRL_MPE);
2192         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2193 }
2194
2195 /**
2196  * It clears the interrupt causes and enables the interrupt.
2197  * It will be called once only during nic initialized.
2198  *
2199  * @param dev
2200  *  Pointer to struct rte_eth_dev.
2201  *
2202  * @return
2203  *  - On success, zero.
2204  *  - On failure, a negative value.
2205  */
2206 static int
2207 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2208 {
2209         struct ixgbe_interrupt *intr =
2210                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2211
2212         ixgbe_dev_link_status_print(dev);
2213         intr->mask |= IXGBE_EICR_LSC;
2214
2215         return 0;
2216 }
2217
2218 /*
2219  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2220  *
2221  * @param dev
2222  *  Pointer to struct rte_eth_dev.
2223  *
2224  * @return
2225  *  - On success, zero.
2226  *  - On failure, a negative value.
2227  */
2228 static int
2229 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2230 {
2231         uint32_t eicr;
2232         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2233         struct ixgbe_interrupt *intr =
2234                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2235
2236         /* clear all cause mask */
2237         ixgbe_disable_intr(hw);
2238
2239         /* read-on-clear nic registers here */
2240         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2241         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2242
2243         intr->flags = 0;
2244         if (eicr & IXGBE_EICR_LSC) {
2245                 /* set flag for async link update */
2246                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2247         }
2248
2249         if (eicr & IXGBE_EICR_MAILBOX)
2250                 intr->flags |= IXGBE_FLAG_MAILBOX;
2251
2252         return 0;
2253 }
2254
2255 /**
2256  * It gets and then prints the link status.
2257  *
2258  * @param dev
2259  *  Pointer to struct rte_eth_dev.
2260  *
2261  * @return
2262  *  - On success, zero.
2263  *  - On failure, a negative value.
2264  */
2265 static void
2266 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2267 {
2268         struct rte_eth_link link;
2269
2270         memset(&link, 0, sizeof(link));
2271         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2272         if (link.link_status) {
2273                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2274                                         (int)(dev->data->port_id),
2275                                         (unsigned)link.link_speed,
2276                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2277                                         "full-duplex" : "half-duplex");
2278         } else {
2279                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2280                                 (int)(dev->data->port_id));
2281         }
2282         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2283                                 dev->pci_dev->addr.domain,
2284                                 dev->pci_dev->addr.bus,
2285                                 dev->pci_dev->addr.devid,
2286                                 dev->pci_dev->addr.function);
2287 }
2288
2289 /*
2290  * It executes link_update after knowing an interrupt occurred.
2291  *
2292  * @param dev
2293  *  Pointer to struct rte_eth_dev.
2294  *
2295  * @return
2296  *  - On success, zero.
2297  *  - On failure, a negative value.
2298  */
2299 static int
2300 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2301 {
2302         struct ixgbe_interrupt *intr =
2303                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2304         int64_t timeout;
2305         struct rte_eth_link link;
2306         int intr_enable_delay = false;
2307
2308         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2309
2310         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2311                 ixgbe_pf_mbx_process(dev);
2312                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2313         }
2314
2315         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2316                 /* get the link status before link update, for predicting later */
2317                 memset(&link, 0, sizeof(link));
2318                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2319
2320                 ixgbe_dev_link_update(dev, 0);
2321
2322                 /* likely to up */
2323                 if (!link.link_status)
2324                         /* handle it 1 sec later, wait it being stable */
2325                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2326                 /* likely to down */
2327                 else
2328                         /* handle it 4 sec later, wait it being stable */
2329                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2330
2331                 ixgbe_dev_link_status_print(dev);
2332
2333                 intr_enable_delay = true;
2334         }
2335
2336         if (intr_enable_delay) {
2337                 if (rte_eal_alarm_set(timeout * 1000,
2338                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2339                         PMD_DRV_LOG(ERR, "Error setting alarm");
2340         } else {
2341                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2342                 ixgbe_enable_intr(dev);
2343                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2344         }
2345
2346
2347         return 0;
2348 }
2349
2350 /**
2351  * Interrupt handler which shall be registered for alarm callback for delayed
2352  * handling specific interrupt to wait for the stable nic state. As the
2353  * NIC interrupt state is not stable for ixgbe after link is just down,
2354  * it needs to wait 4 seconds to get the stable status.
2355  *
2356  * @param handle
2357  *  Pointer to interrupt handle.
2358  * @param param
2359  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2360  *
2361  * @return
2362  *  void
2363  */
2364 static void
2365 ixgbe_dev_interrupt_delayed_handler(void *param)
2366 {
2367         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2368         struct ixgbe_interrupt *intr =
2369                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2370         struct ixgbe_hw *hw =
2371                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2372         uint32_t eicr;
2373
2374         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2375         if (eicr & IXGBE_EICR_MAILBOX)
2376                 ixgbe_pf_mbx_process(dev);
2377
2378         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2379                 ixgbe_dev_link_update(dev, 0);
2380                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2381                 ixgbe_dev_link_status_print(dev);
2382                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2383         }
2384
2385         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2386         ixgbe_enable_intr(dev);
2387         rte_intr_enable(&(dev->pci_dev->intr_handle));
2388 }
2389
2390 /**
2391  * Interrupt handler triggered by NIC  for handling
2392  * specific interrupt.
2393  *
2394  * @param handle
2395  *  Pointer to interrupt handle.
2396  * @param param
2397  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2398  *
2399  * @return
2400  *  void
2401  */
2402 static void
2403 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2404                                                         void *param)
2405 {
2406         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2407         ixgbe_dev_interrupt_get_status(dev);
2408         ixgbe_dev_interrupt_action(dev);
2409 }
2410
2411 static int
2412 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2413 {
2414         struct ixgbe_hw *hw;
2415
2416         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2417         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2418 }
2419
2420 static int
2421 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2422 {
2423         struct ixgbe_hw *hw;
2424
2425         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2426         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2427 }
2428
2429 static int
2430 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2431 {
2432         struct ixgbe_hw *hw;
2433         uint32_t mflcn_reg;
2434         uint32_t fccfg_reg;
2435         int rx_pause;
2436         int tx_pause;
2437
2438         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439
2440         fc_conf->pause_time = hw->fc.pause_time;
2441         fc_conf->high_water = hw->fc.high_water[0];
2442         fc_conf->low_water = hw->fc.low_water[0];
2443         fc_conf->send_xon = hw->fc.send_xon;
2444         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2445
2446         /*
2447          * Return rx_pause status according to actual setting of
2448          * MFLCN register.
2449          */
2450         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2451         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2452                 rx_pause = 1;
2453         else
2454                 rx_pause = 0;
2455
2456         /*
2457          * Return tx_pause status according to actual setting of
2458          * FCCFG register.
2459          */
2460         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2461         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2462                 tx_pause = 1;
2463         else
2464                 tx_pause = 0;
2465
2466         if (rx_pause && tx_pause)
2467                 fc_conf->mode = RTE_FC_FULL;
2468         else if (rx_pause)
2469                 fc_conf->mode = RTE_FC_RX_PAUSE;
2470         else if (tx_pause)
2471                 fc_conf->mode = RTE_FC_TX_PAUSE;
2472         else
2473                 fc_conf->mode = RTE_FC_NONE;
2474
2475         return 0;
2476 }
2477
2478 static int
2479 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2480 {
2481         struct ixgbe_hw *hw;
2482         int err;
2483         uint32_t rx_buf_size;
2484         uint32_t max_high_water;
2485         uint32_t mflcn;
2486         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2487                 ixgbe_fc_none,
2488                 ixgbe_fc_rx_pause,
2489                 ixgbe_fc_tx_pause,
2490                 ixgbe_fc_full
2491         };
2492
2493         PMD_INIT_FUNC_TRACE();
2494
2495         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2496         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2497                 return -ENOTSUP;
2498         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2499         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2500
2501         /*
2502          * At least reserve one Ethernet frame for watermark
2503          * high_water/low_water in kilo bytes for ixgbe
2504          */
2505         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2506         if ((fc_conf->high_water > max_high_water) ||
2507                 (fc_conf->high_water < fc_conf->low_water)) {
2508                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2509                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2510                 return (-EINVAL);
2511         }
2512
2513         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2514         hw->fc.pause_time     = fc_conf->pause_time;
2515         hw->fc.high_water[0]  = fc_conf->high_water;
2516         hw->fc.low_water[0]   = fc_conf->low_water;
2517         hw->fc.send_xon       = fc_conf->send_xon;
2518
2519         err = ixgbe_fc_enable(hw);
2520
2521         /* Not negotiated is not an error case */
2522         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2523
2524                 /* check if we want to forward MAC frames - driver doesn't have native
2525                  * capability to do that, so we'll write the registers ourselves */
2526
2527                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2528
2529                 /* set or clear MFLCN.PMCF bit depending on configuration */
2530                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2531                         mflcn |= IXGBE_MFLCN_PMCF;
2532                 else
2533                         mflcn &= ~IXGBE_MFLCN_PMCF;
2534
2535                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2536                 IXGBE_WRITE_FLUSH(hw);
2537
2538                 return 0;
2539         }
2540
2541         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2542         return -EIO;
2543 }
2544
2545 /**
2546  *  ixgbe_pfc_enable_generic - Enable flow control
2547  *  @hw: pointer to hardware structure
2548  *  @tc_num: traffic class number
2549  *  Enable flow control according to the current settings.
2550  */
2551 static int
2552 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2553 {
2554         int ret_val = 0;
2555         uint32_t mflcn_reg, fccfg_reg;
2556         uint32_t reg;
2557         uint32_t fcrtl, fcrth;
2558         uint8_t i;
2559         uint8_t nb_rx_en;
2560
2561         /* Validate the water mark configuration */
2562         if (!hw->fc.pause_time) {
2563                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2564                 goto out;
2565         }
2566
2567         /* Low water mark of zero causes XOFF floods */
2568         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2569                  /* High/Low water can not be 0 */
2570                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2571                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2572                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2573                         goto out;
2574                 }
2575
2576                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2577                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2578                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2579                         goto out;
2580                 }
2581         }
2582         /* Negotiate the fc mode to use */
2583         ixgbe_fc_autoneg(hw);
2584
2585         /* Disable any previous flow control settings */
2586         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2587         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2588
2589         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2590         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2591
2592         switch (hw->fc.current_mode) {
2593         case ixgbe_fc_none:
2594                 /*
2595                  * If the count of enabled RX Priority Flow control >1,
2596                  * and the TX pause can not be disabled
2597                  */
2598                 nb_rx_en = 0;
2599                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2600                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2601                         if (reg & IXGBE_FCRTH_FCEN)
2602                                 nb_rx_en++;
2603                 }
2604                 if (nb_rx_en > 1)
2605                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2606                 break;
2607         case ixgbe_fc_rx_pause:
2608                 /*
2609                  * Rx Flow control is enabled and Tx Flow control is
2610                  * disabled by software override. Since there really
2611                  * isn't a way to advertise that we are capable of RX
2612                  * Pause ONLY, we will advertise that we support both
2613                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2614                  * disable the adapter's ability to send PAUSE frames.
2615                  */
2616                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2617                 /*
2618                  * If the count of enabled RX Priority Flow control >1,
2619                  * and the TX pause can not be disabled
2620                  */
2621                 nb_rx_en = 0;
2622                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2623                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2624                         if (reg & IXGBE_FCRTH_FCEN)
2625                                 nb_rx_en++;
2626                 }
2627                 if (nb_rx_en > 1)
2628                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2629                 break;
2630         case ixgbe_fc_tx_pause:
2631                 /*
2632                  * Tx Flow control is enabled, and Rx Flow control is
2633                  * disabled by software override.
2634                  */
2635                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2636                 break;
2637         case ixgbe_fc_full:
2638                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2639                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2640                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2641                 break;
2642         default:
2643                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2644                 ret_val = IXGBE_ERR_CONFIG;
2645                 goto out;
2646                 break;
2647         }
2648
2649         /* Set 802.3x based flow control settings. */
2650         mflcn_reg |= IXGBE_MFLCN_DPF;
2651         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2652         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2653
2654         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2655         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2656                 hw->fc.high_water[tc_num]) {
2657                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2658                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2659                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2660         } else {
2661                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2662                 /*
2663                  * In order to prevent Tx hangs when the internal Tx
2664                  * switch is enabled we must set the high water mark
2665                  * to the maximum FCRTH value.  This allows the Tx
2666                  * switch to function even under heavy Rx workloads.
2667                  */
2668                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2669         }
2670         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2671
2672         /* Configure pause time (2 TCs per register) */
2673         reg = hw->fc.pause_time * 0x00010001;
2674         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2675                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2676
2677         /* Configure flow control refresh threshold value */
2678         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2679
2680 out:
2681         return ret_val;
2682 }
2683
2684 static int
2685 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2686 {
2687         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2688         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2689
2690         if(hw->mac.type != ixgbe_mac_82598EB) {
2691                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2692         }
2693         return ret_val;
2694 }
2695
2696 static int
2697 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2698 {
2699         int err;
2700         uint32_t rx_buf_size;
2701         uint32_t max_high_water;
2702         uint8_t tc_num;
2703         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2704         struct ixgbe_hw *hw =
2705                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2706         struct ixgbe_dcb_config *dcb_config =
2707                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2708
2709         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2710                 ixgbe_fc_none,
2711                 ixgbe_fc_rx_pause,
2712                 ixgbe_fc_tx_pause,
2713                 ixgbe_fc_full
2714         };
2715
2716         PMD_INIT_FUNC_TRACE();
2717
2718         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2719         tc_num = map[pfc_conf->priority];
2720         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2721         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2722         /*
2723          * At least reserve one Ethernet frame for watermark
2724          * high_water/low_water in kilo bytes for ixgbe
2725          */
2726         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2727         if ((pfc_conf->fc.high_water > max_high_water) ||
2728             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2729                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2730                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2731                 return (-EINVAL);
2732         }
2733
2734         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2735         hw->fc.pause_time = pfc_conf->fc.pause_time;
2736         hw->fc.send_xon = pfc_conf->fc.send_xon;
2737         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2738         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2739
2740         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2741
2742         /* Not negotiated is not an error case */
2743         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2744                 return 0;
2745
2746         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2747         return -EIO;
2748 }
2749
2750 static int
2751 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2752                           struct rte_eth_rss_reta_entry64 *reta_conf,
2753                           uint16_t reta_size)
2754 {
2755         uint8_t i, j, mask;
2756         uint32_t reta, r;
2757         uint16_t idx, shift;
2758         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2759
2760         PMD_INIT_FUNC_TRACE();
2761         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2762                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2763                         "(%d) doesn't match the number hardware can supported "
2764                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2765                 return -EINVAL;
2766         }
2767
2768         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2769                 idx = i / RTE_RETA_GROUP_SIZE;
2770                 shift = i % RTE_RETA_GROUP_SIZE;
2771                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2772                                                 IXGBE_4_BIT_MASK);
2773                 if (!mask)
2774                         continue;
2775                 if (mask == IXGBE_4_BIT_MASK)
2776                         r = 0;
2777                 else
2778                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2779                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2780                         if (mask & (0x1 << j))
2781                                 reta |= reta_conf[idx].reta[shift + j] <<
2782                                                         (CHAR_BIT * j);
2783                         else
2784                                 reta |= r & (IXGBE_8_BIT_MASK <<
2785                                                 (CHAR_BIT * j));
2786                 }
2787                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2788         }
2789
2790         return 0;
2791 }
2792
2793 static int
2794 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2795                          struct rte_eth_rss_reta_entry64 *reta_conf,
2796                          uint16_t reta_size)
2797 {
2798         uint8_t i, j, mask;
2799         uint32_t reta;
2800         uint16_t idx, shift;
2801         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2802
2803         PMD_INIT_FUNC_TRACE();
2804         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2805                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2806                         "(%d) doesn't match the number hardware can supported "
2807                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2808                 return -EINVAL;
2809         }
2810
2811         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2812                 idx = i / RTE_RETA_GROUP_SIZE;
2813                 shift = i % RTE_RETA_GROUP_SIZE;
2814                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2815                                                 IXGBE_4_BIT_MASK);
2816                 if (!mask)
2817                         continue;
2818
2819                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2820                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2821                         if (mask & (0x1 << j))
2822                                 reta_conf[idx].reta[shift + j] =
2823                                         ((reta >> (CHAR_BIT * j)) &
2824                                                 IXGBE_8_BIT_MASK);
2825                 }
2826         }
2827
2828         return 0;
2829 }
2830
2831 static void
2832 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2833                                 uint32_t index, uint32_t pool)
2834 {
2835         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2836         uint32_t enable_addr = 1;
2837
2838         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2839 }
2840
2841 static void
2842 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2843 {
2844         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2845
2846         ixgbe_clear_rar(hw, index);
2847 }
2848
2849 static int
2850 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2851 {
2852         uint32_t hlreg0;
2853         uint32_t maxfrs;
2854         struct ixgbe_hw *hw;
2855         struct rte_eth_dev_info dev_info;
2856         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2857
2858         ixgbe_dev_info_get(dev, &dev_info);
2859
2860         /* check that mtu is within the allowed range */
2861         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2862                 return -EINVAL;
2863
2864         /* refuse mtu that requires the support of scattered packets when this
2865          * feature has not been enabled before. */
2866         if (!dev->data->scattered_rx &&
2867             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2868              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2869                 return -EINVAL;
2870
2871         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2872         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2873
2874         /* switch to jumbo mode if needed */
2875         if (frame_size > ETHER_MAX_LEN) {
2876                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2877                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2878         } else {
2879                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2880                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2881         }
2882         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2883
2884         /* update max frame size */
2885         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2886
2887         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2888         maxfrs &= 0x0000FFFF;
2889         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2890         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2891
2892         return 0;
2893 }
2894
2895 /*
2896  * Virtual Function operations
2897  */
2898 static void
2899 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2900 {
2901         PMD_INIT_FUNC_TRACE();
2902
2903         /* Clear interrupt mask to stop from interrupts being generated */
2904         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2905
2906         IXGBE_WRITE_FLUSH(hw);
2907 }
2908
2909 static int
2910 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2911 {
2912         struct rte_eth_conf* conf = &dev->data->dev_conf;
2913
2914         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2915                      dev->data->port_id);
2916
2917         /*
2918          * VF has no ability to enable/disable HW CRC
2919          * Keep the persistent behavior the same as Host PF
2920          */
2921 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2922         if (!conf->rxmode.hw_strip_crc) {
2923                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2924                 conf->rxmode.hw_strip_crc = 1;
2925         }
2926 #else
2927         if (conf->rxmode.hw_strip_crc) {
2928                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2929                 conf->rxmode.hw_strip_crc = 0;
2930         }
2931 #endif
2932
2933         return 0;
2934 }
2935
2936 static int
2937 ixgbevf_dev_start(struct rte_eth_dev *dev)
2938 {
2939         struct ixgbe_hw *hw =
2940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2941         int err, mask = 0;
2942
2943         PMD_INIT_FUNC_TRACE();
2944
2945         hw->mac.ops.reset_hw(hw);
2946         hw->mac.get_link_status = true;
2947
2948         /* negotiate mailbox API version to use with the PF. */
2949         ixgbevf_negotiate_api(hw);
2950
2951         ixgbevf_dev_tx_init(dev);
2952
2953         /* This can fail when allocating mbufs for descriptor rings */
2954         err = ixgbevf_dev_rx_init(dev);
2955         if (err) {
2956                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2957                 ixgbe_dev_clear_queues(dev);
2958                 return err;
2959         }
2960
2961         /* Set vfta */
2962         ixgbevf_set_vfta_all(dev,1);
2963
2964         /* Set HW strip */
2965         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2966                 ETH_VLAN_EXTEND_MASK;
2967         ixgbevf_vlan_offload_set(dev, mask);
2968
2969         ixgbevf_dev_rxtx_start(dev);
2970
2971         return 0;
2972 }
2973
2974 static void
2975 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2976 {
2977         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2978
2979         PMD_INIT_FUNC_TRACE();
2980
2981         hw->adapter_stopped = TRUE;
2982         ixgbe_stop_adapter(hw);
2983
2984         /*
2985           * Clear what we set, but we still keep shadow_vfta to
2986           * restore after device starts
2987           */
2988         ixgbevf_set_vfta_all(dev,0);
2989
2990         /* Clear stored conf */
2991         dev->data->scattered_rx = 0;
2992
2993         ixgbe_dev_clear_queues(dev);
2994 }
2995
2996 static void
2997 ixgbevf_dev_close(struct rte_eth_dev *dev)
2998 {
2999         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3000
3001         PMD_INIT_FUNC_TRACE();
3002
3003         ixgbe_reset_hw(hw);
3004
3005         ixgbevf_dev_stop(dev);
3006
3007         /* reprogram the RAR[0] in case user changed it. */
3008         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3009 }
3010
3011 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3012 {
3013         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3014         struct ixgbe_vfta * shadow_vfta =
3015                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3016         int i = 0, j = 0, vfta = 0, mask = 1;
3017
3018         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3019                 vfta = shadow_vfta->vfta[i];
3020                 if(vfta){
3021                         mask = 1;
3022                         for (j = 0; j < 32; j++){
3023                                 if(vfta & mask)
3024                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3025                                 mask<<=1;
3026                         }
3027                 }
3028         }
3029
3030 }
3031
3032 static int
3033 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3034 {
3035         struct ixgbe_hw *hw =
3036                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3037         struct ixgbe_vfta * shadow_vfta =
3038                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3039         uint32_t vid_idx = 0;
3040         uint32_t vid_bit = 0;
3041         int ret = 0;
3042
3043         PMD_INIT_FUNC_TRACE();
3044
3045         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3046         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3047         if(ret){
3048                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3049                 return ret;
3050         }
3051         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3052         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3053
3054         /* Save what we set and retore it after device reset */
3055         if (on)
3056                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3057         else
3058                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3059
3060         return 0;
3061 }
3062
3063 static void
3064 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3065 {
3066         struct ixgbe_hw *hw =
3067                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068         uint32_t ctrl;
3069
3070         PMD_INIT_FUNC_TRACE();
3071
3072         if(queue >= hw->mac.max_rx_queues)
3073                 return;
3074
3075         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3076         if(on)
3077                 ctrl |= IXGBE_RXDCTL_VME;
3078         else
3079                 ctrl &= ~IXGBE_RXDCTL_VME;
3080         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3081
3082         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3083 }
3084
3085 static void
3086 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3087 {
3088         struct ixgbe_hw *hw =
3089                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3090         uint16_t i;
3091         int on = 0;
3092
3093         /* VF function only support hw strip feature, others are not support */
3094         if(mask & ETH_VLAN_STRIP_MASK){
3095                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3096
3097                 for(i=0; i < hw->mac.max_rx_queues; i++)
3098                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3099         }
3100 }
3101
3102 static int
3103 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3104 {
3105         uint32_t reg_val;
3106
3107         /* we only need to do this if VMDq is enabled */
3108         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3109         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3110                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3111                 return (-1);
3112         }
3113
3114         return 0;
3115 }
3116
3117 static uint32_t
3118 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3119 {
3120         uint32_t vector = 0;
3121         switch (hw->mac.mc_filter_type) {
3122         case 0:   /* use bits [47:36] of the address */
3123                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3124                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3125                 break;
3126         case 1:   /* use bits [46:35] of the address */
3127                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3128                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3129                 break;
3130         case 2:   /* use bits [45:34] of the address */
3131                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3132                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3133                 break;
3134         case 3:   /* use bits [43:32] of the address */
3135                 vector = ((uc_addr->addr_bytes[4]) |
3136                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3137                 break;
3138         default:  /* Invalid mc_filter_type */
3139                 break;
3140         }
3141
3142         /* vector can only be 12-bits or boundary will be exceeded */
3143         vector &= 0xFFF;
3144         return vector;
3145 }
3146
3147 static int
3148 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3149                                uint8_t on)
3150 {
3151         uint32_t vector;
3152         uint32_t uta_idx;
3153         uint32_t reg_val;
3154         uint32_t uta_shift;
3155         uint32_t rc;
3156         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3157         const uint32_t ixgbe_uta_bit_shift = 5;
3158         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3159         const uint32_t bit1 = 0x1;
3160
3161         struct ixgbe_hw *hw =
3162                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3163         struct ixgbe_uta_info *uta_info =
3164                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3165
3166         /* The UTA table only exists on 82599 hardware and newer */
3167         if (hw->mac.type < ixgbe_mac_82599EB)
3168                 return (-ENOTSUP);
3169
3170         vector = ixgbe_uta_vector(hw,mac_addr);
3171         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3172         uta_shift = vector & ixgbe_uta_bit_mask;
3173
3174         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3175         if(rc == on)
3176                 return 0;
3177
3178         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3179         if (on) {
3180                 uta_info->uta_in_use++;
3181                 reg_val |= (bit1 << uta_shift);
3182                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3183         } else {
3184                 uta_info->uta_in_use--;
3185                 reg_val &= ~(bit1 << uta_shift);
3186                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3187         }
3188
3189         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3190
3191         if (uta_info->uta_in_use > 0)
3192                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3193                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3194         else
3195                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3196
3197         return 0;
3198 }
3199
3200 static int
3201 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3202 {
3203         int i;
3204         struct ixgbe_hw *hw =
3205                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3206         struct ixgbe_uta_info *uta_info =
3207                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3208
3209         /* The UTA table only exists on 82599 hardware and newer */
3210         if (hw->mac.type < ixgbe_mac_82599EB)
3211                 return (-ENOTSUP);
3212
3213         if(on) {
3214                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3215                         uta_info->uta_shadow[i] = ~0;
3216                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3217                 }
3218         } else {
3219                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3220                         uta_info->uta_shadow[i] = 0;
3221                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3222                 }
3223         }
3224         return 0;
3225
3226 }
3227
3228 uint32_t
3229 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3230 {
3231         uint32_t new_val = orig_val;
3232
3233         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3234                 new_val |= IXGBE_VMOLR_AUPE;
3235         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3236                 new_val |= IXGBE_VMOLR_ROMPE;
3237         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3238                 new_val |= IXGBE_VMOLR_ROPE;
3239         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3240                 new_val |= IXGBE_VMOLR_BAM;
3241         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3242                 new_val |= IXGBE_VMOLR_MPE;
3243
3244         return new_val;
3245 }
3246
3247 static int
3248 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3249                                uint16_t rx_mask, uint8_t on)
3250 {
3251         int val = 0;
3252
3253         struct ixgbe_hw *hw =
3254                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3255         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3256
3257         if (hw->mac.type == ixgbe_mac_82598EB) {
3258                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3259                              " on 82599 hardware and newer");
3260                 return (-ENOTSUP);
3261         }
3262         if (ixgbe_vmdq_mode_check(hw) < 0)
3263                 return (-ENOTSUP);
3264
3265         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3266
3267         if (on)
3268                 vmolr |= val;
3269         else
3270                 vmolr &= ~val;
3271
3272         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3273
3274         return 0;
3275 }
3276
3277 static int
3278 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3279 {
3280         uint32_t reg,addr;
3281         uint32_t val;
3282         const uint8_t bit1 = 0x1;
3283
3284         struct ixgbe_hw *hw =
3285                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3286
3287         if (ixgbe_vmdq_mode_check(hw) < 0)
3288                 return (-ENOTSUP);
3289
3290         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3291         reg = IXGBE_READ_REG(hw, addr);
3292         val = bit1 << pool;
3293
3294         if (on)
3295                 reg |= val;
3296         else
3297                 reg &= ~val;
3298
3299         IXGBE_WRITE_REG(hw, addr,reg);
3300
3301         return 0;
3302 }
3303
3304 static int
3305 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3306 {
3307         uint32_t reg,addr;
3308         uint32_t val;
3309         const uint8_t bit1 = 0x1;
3310
3311         struct ixgbe_hw *hw =
3312                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3313
3314         if (ixgbe_vmdq_mode_check(hw) < 0)
3315                 return (-ENOTSUP);
3316
3317         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3318         reg = IXGBE_READ_REG(hw, addr);
3319         val = bit1 << pool;
3320
3321         if (on)
3322                 reg |= val;
3323         else
3324                 reg &= ~val;
3325
3326         IXGBE_WRITE_REG(hw, addr,reg);
3327
3328         return 0;
3329 }
3330
3331 static int
3332 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3333                         uint64_t pool_mask, uint8_t vlan_on)
3334 {
3335         int ret = 0;
3336         uint16_t pool_idx;
3337         struct ixgbe_hw *hw =
3338                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3339
3340         if (ixgbe_vmdq_mode_check(hw) < 0)
3341                 return (-ENOTSUP);
3342         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3343                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3344                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3345                         if (ret < 0)
3346                                 return ret;
3347         }
3348
3349         return ret;
3350 }
3351
3352 static int
3353 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3354                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3355                         uint8_t rule_id, uint8_t on)
3356 {
3357         uint32_t mr_ctl,vlvf;
3358         uint32_t mp_lsb = 0;
3359         uint32_t mv_msb = 0;
3360         uint32_t mv_lsb = 0;
3361         uint32_t mp_msb = 0;
3362         uint8_t i = 0;
3363         int reg_index = 0;
3364         uint64_t vlan_mask = 0;
3365
3366         const uint8_t pool_mask_offset = 32;
3367         const uint8_t vlan_mask_offset = 32;
3368         const uint8_t dst_pool_offset = 8;
3369         const uint8_t rule_mr_offset  = 4;
3370         const uint8_t mirror_rule_mask= 0x0F;
3371
3372         struct ixgbe_mirror_info *mr_info =
3373                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3374         struct ixgbe_hw *hw =
3375                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3376
3377         if (ixgbe_vmdq_mode_check(hw) < 0)
3378                 return (-ENOTSUP);
3379
3380         /* Check if vlan mask is valid */
3381         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3382                 if (mirror_conf->vlan.vlan_mask == 0)
3383                         return (-EINVAL);
3384         }
3385
3386         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3387         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3388                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3389                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3390                                 /* search vlan id related pool vlan filter index */
3391                                 reg_index = ixgbe_find_vlvf_slot(hw,
3392                                                 mirror_conf->vlan.vlan_id[i]);
3393                                 if(reg_index < 0)
3394                                         return (-EINVAL);
3395                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3396                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3397                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3398                                                 == mirror_conf->vlan.vlan_id[i]))
3399                                         vlan_mask |= (1ULL << reg_index);
3400                                 else
3401                                         return (-EINVAL);
3402                         }
3403                 }
3404
3405                 if (on) {
3406                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3407                         mv_msb = vlan_mask >> vlan_mask_offset;
3408
3409                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3410                                                 mirror_conf->vlan.vlan_mask;
3411                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3412                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3413                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3414                                                 mirror_conf->vlan.vlan_id[i];
3415                         }
3416                 } else {
3417                         mv_lsb = 0;
3418                         mv_msb = 0;
3419                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3420                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3421                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3422                 }
3423         }
3424
3425         /*
3426          * if enable pool mirror, write related pool mask register,if disable
3427          * pool mirror, clear PFMRVM register
3428          */
3429         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3430                 if (on) {
3431                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3432                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3433                         mr_info->mr_conf[rule_id].pool_mask =
3434                                         mirror_conf->pool_mask;
3435
3436                 } else {
3437                         mp_lsb = 0;
3438                         mp_msb = 0;
3439                         mr_info->mr_conf[rule_id].pool_mask = 0;
3440                 }
3441         }
3442
3443         /* read  mirror control register and recalculate it */
3444         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3445
3446         if (on) {
3447                 mr_ctl |= mirror_conf->rule_type_mask;
3448                 mr_ctl &= mirror_rule_mask;
3449                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3450         } else
3451                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3452
3453         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3454         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3455
3456         /* write mirrror control  register */
3457         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3458
3459         /* write pool mirrror control  register */
3460         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3461                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3462                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3463                                 mp_msb);
3464         }
3465         /* write VLAN mirrror control  register */
3466         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3467                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3468                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3469                                 mv_msb);
3470         }
3471
3472         return 0;
3473 }
3474
3475 static int
3476 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3477 {
3478         int mr_ctl = 0;
3479         uint32_t lsb_val = 0;
3480         uint32_t msb_val = 0;
3481         const uint8_t rule_mr_offset = 4;
3482
3483         struct ixgbe_hw *hw =
3484                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3485         struct ixgbe_mirror_info *mr_info =
3486                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3487
3488         if (ixgbe_vmdq_mode_check(hw) < 0)
3489                 return (-ENOTSUP);
3490
3491         memset(&mr_info->mr_conf[rule_id], 0,
3492                 sizeof(struct rte_eth_vmdq_mirror_conf));
3493
3494         /* clear PFVMCTL register */
3495         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3496
3497         /* clear pool mask register */
3498         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3499         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3500
3501         /* clear vlan mask register */
3502         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3503         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3504
3505         return 0;
3506 }
3507
3508 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3509         uint16_t queue_idx, uint16_t tx_rate)
3510 {
3511         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3512         uint32_t rf_dec, rf_int;
3513         uint32_t bcnrc_val;
3514         uint16_t link_speed = dev->data->dev_link.link_speed;
3515
3516         if (queue_idx >= hw->mac.max_tx_queues)
3517                 return -EINVAL;
3518
3519         if (tx_rate != 0) {
3520                 /* Calculate the rate factor values to set */
3521                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3522                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3523                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3524
3525                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3526                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3527                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3528                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3529         } else {
3530                 bcnrc_val = 0;
3531         }
3532
3533         /*
3534          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3535          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3536          * set as 0x4.
3537          */
3538         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3539                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3540                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3541                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3542                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3543         else
3544                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3545                         IXGBE_MMW_SIZE_DEFAULT);
3546
3547         /* Set RTTBCNRC of queue X */
3548         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3549         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3550         IXGBE_WRITE_FLUSH(hw);
3551
3552         return 0;
3553 }
3554
3555 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3556         uint16_t tx_rate, uint64_t q_msk)
3557 {
3558         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3559         struct ixgbe_vf_info *vfinfo =
3560                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3561         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3562         uint32_t queue_stride =
3563                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3564         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3565         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3566         uint16_t total_rate = 0;
3567
3568         if (queue_end >= hw->mac.max_tx_queues)
3569                 return -EINVAL;
3570
3571         if (vfinfo != NULL) {
3572                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3573                         if (vf_idx == vf)
3574                                 continue;
3575                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3576                                 idx++)
3577                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3578                 }
3579         } else
3580                 return -EINVAL;
3581
3582         /* Store tx_rate for this vf. */
3583         for (idx = 0; idx < nb_q_per_pool; idx++) {
3584                 if (((uint64_t)0x1 << idx) & q_msk) {
3585                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3586                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3587                         total_rate += tx_rate;
3588                 }
3589         }
3590
3591         if (total_rate > dev->data->dev_link.link_speed) {
3592                 /*
3593                  * Reset stored TX rate of the VF if it causes exceed
3594                  * link speed.
3595                  */
3596                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3597                 return -EINVAL;
3598         }
3599
3600         /* Set RTTBCNRC of each queue/pool for vf X  */
3601         for (; queue_idx <= queue_end; queue_idx++) {
3602                 if (0x1 & q_msk)
3603                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3604                 q_msk = q_msk >> 1;
3605         }
3606
3607         return 0;
3608 }
3609
3610 static void
3611 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3612                      __attribute__((unused)) uint32_t index,
3613                      __attribute__((unused)) uint32_t pool)
3614 {
3615         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3616         int diag;
3617
3618         /*
3619          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3620          * operation. Trap this case to avoid exhausting the [very limited]
3621          * set of PF resources used to store VF MAC addresses.
3622          */
3623         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3624                 return;
3625         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3626         if (diag == 0)
3627                 return;
3628         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3629 }
3630
3631 static void
3632 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3633 {
3634         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3635         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3636         struct ether_addr *mac_addr;
3637         uint32_t i;
3638         int diag;
3639
3640         /*
3641          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3642          * not support the deletion of a given MAC address.
3643          * Instead, it imposes to delete all MAC addresses, then to add again
3644          * all MAC addresses with the exception of the one to be deleted.
3645          */
3646         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3647
3648         /*
3649          * Add again all MAC addresses, with the exception of the deleted one
3650          * and of the permanent MAC address.
3651          */
3652         for (i = 0, mac_addr = dev->data->mac_addrs;
3653              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3654                 /* Skip the deleted MAC address */
3655                 if (i == index)
3656                         continue;
3657                 /* Skip NULL MAC addresses */
3658                 if (is_zero_ether_addr(mac_addr))
3659                         continue;
3660                 /* Skip the permanent MAC address */
3661                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3662                         continue;
3663                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3664                 if (diag != 0)
3665                         PMD_DRV_LOG(ERR,
3666                                     "Adding again MAC address "
3667                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3668                                     "diag=%d",
3669                                     mac_addr->addr_bytes[0],
3670                                     mac_addr->addr_bytes[1],
3671                                     mac_addr->addr_bytes[2],
3672                                     mac_addr->addr_bytes[3],
3673                                     mac_addr->addr_bytes[4],
3674                                     mac_addr->addr_bytes[5],
3675                                     diag);
3676         }
3677 }
3678
3679 /*
3680  * add syn filter
3681  *
3682  * @param
3683  * dev: Pointer to struct rte_eth_dev.
3684  * filter: ponter to the filter that will be added.
3685  * rx_queue: the queue id the filter assigned to.
3686  *
3687  * @return
3688  *    - On success, zero.
3689  *    - On failure, a negative value.
3690  */
3691 static int
3692 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3693                         struct rte_syn_filter *filter, uint16_t rx_queue)
3694 {
3695         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3696         uint32_t synqf;
3697
3698         if (hw->mac.type != ixgbe_mac_82599EB)
3699                 return -ENOSYS;
3700
3701         if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3702                 return -EINVAL;
3703
3704         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3705
3706         if (synqf & IXGBE_SYN_FILTER_ENABLE)
3707                 return -EINVAL;
3708
3709         synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3710                 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3711
3712         if (filter->hig_pri)
3713                 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3714         else
3715                 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3716
3717         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3718         return 0;
3719 }
3720
3721 /*
3722  * remove syn filter
3723  *
3724  * @param
3725  * dev: Pointer to struct rte_eth_dev.
3726  *
3727  * @return
3728  *    - On success, zero.
3729  *    - On failure, a negative value.
3730  */
3731 static int
3732 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3733 {
3734         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3735         uint32_t synqf;
3736
3737         if (hw->mac.type != ixgbe_mac_82599EB)
3738                 return -ENOSYS;
3739
3740         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3741
3742         synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3743
3744         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3745         return 0;
3746 }
3747
3748 /*
3749  * get the syn filter's info
3750  *
3751  * @param
3752  * dev: Pointer to struct rte_eth_dev.
3753  * filter: ponter to the filter that returns.
3754  * *rx_queue: pointer to the queue id the filter assigned to.
3755  *
3756  * @return
3757  *    - On success, zero.
3758  *    - On failure, a negative value.
3759  */
3760 static int
3761 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3762                         struct rte_syn_filter *filter, uint16_t *rx_queue)
3763
3764 {
3765         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3766         uint32_t synqf;
3767
3768         if (hw->mac.type != ixgbe_mac_82599EB)
3769                 return -ENOSYS;
3770
3771         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3772         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3773                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3774                 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3775                 return 0;
3776         }
3777         return -ENOENT;
3778 }
3779
3780 static inline enum ixgbe_5tuple_protocol
3781 convert_protocol_type(uint8_t protocol_value)
3782 {
3783         if (protocol_value == IPPROTO_TCP)
3784                 return IXGBE_FILTER_PROTOCOL_TCP;
3785         else if (protocol_value == IPPROTO_UDP)
3786                 return IXGBE_FILTER_PROTOCOL_UDP;
3787         else if (protocol_value == IPPROTO_SCTP)
3788                 return IXGBE_FILTER_PROTOCOL_SCTP;
3789         else
3790                 return IXGBE_FILTER_PROTOCOL_NONE;
3791 }
3792
3793 static inline uint8_t
3794 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3795 {
3796         if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3797                 return IPPROTO_TCP;
3798         else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3799                 return IPPROTO_UDP;
3800         else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3801                 return IPPROTO_SCTP;
3802         else
3803                 return 0;
3804 }
3805
3806 /*
3807  * add a 5tuple filter
3808  *
3809  * @param
3810  * dev: Pointer to struct rte_eth_dev.
3811  * index: the index the filter allocates.
3812  * filter: ponter to the filter that will be added.
3813  * rx_queue: the queue id the filter assigned to.
3814  *
3815  * @return
3816  *    - On success, zero.
3817  *    - On failure, a negative value.
3818  */
3819 static int
3820 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3821                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
3822 {
3823         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3824         uint32_t ftqf, sdpqf = 0;
3825         uint32_t l34timir = 0;
3826         uint8_t mask = 0xff;
3827
3828         if (hw->mac.type != ixgbe_mac_82599EB)
3829                 return -ENOSYS;
3830
3831         if (index >= IXGBE_MAX_FTQF_FILTERS ||
3832                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3833                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3834                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3835                 return -EINVAL;  /* filter index is out of range. */
3836
3837         if (filter->tcp_flags) {
3838                 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3839                 return -EINVAL;
3840         }
3841
3842         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3843         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3844                 return -EINVAL;  /* filter index is in use. */
3845
3846         ftqf = 0;
3847         sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3848         sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3849
3850         ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3851                 IXGBE_FTQF_PROTOCOL_MASK);
3852         ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3853                 IXGBE_FTQF_PRIORITY_SHIFT);
3854         if (filter->src_ip_mask == 0) /* 0 means compare. */
3855                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3856         if (filter->dst_ip_mask == 0)
3857                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3858         if (filter->src_port_mask == 0)
3859                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3860         if (filter->dst_port_mask == 0)
3861                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3862         if (filter->protocol_mask == 0)
3863                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3864         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3865         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3866         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3867
3868         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3869         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3870         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3871         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3872
3873         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3874         l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3875         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3876         return 0;
3877 }
3878
3879 /*
3880  * remove a 5tuple filter
3881  *
3882  * @param
3883  * dev: Pointer to struct rte_eth_dev.
3884  * index: the index the filter allocates.
3885  *
3886  * @return
3887  *    - On success, zero.
3888  *    - On failure, a negative value.
3889  */
3890 static int
3891 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3892                         uint16_t index)
3893 {
3894         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3895
3896         if (hw->mac.type != ixgbe_mac_82599EB)
3897                 return -ENOSYS;
3898
3899         if (index >= IXGBE_MAX_FTQF_FILTERS)
3900                 return -EINVAL;  /* filter index is out of range. */
3901
3902         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3903         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3904         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3905         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3906         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3907         return 0;
3908 }
3909
3910 /*
3911  * get a 5tuple filter
3912  *
3913  * @param
3914  * dev: Pointer to struct rte_eth_dev.
3915  * index: the index the filter allocates
3916  * filter: ponter to the filter that returns.
3917  * *rx_queue: pointer of the queue id the filter assigned to.
3918  *
3919  * @return
3920  *    - On success, zero.
3921  *    - On failure, a negative value.
3922  */
3923 static int
3924 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3925                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3926 {
3927         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3928         uint32_t sdpqf, ftqf, l34timir;
3929         uint8_t mask;
3930         enum ixgbe_5tuple_protocol proto;
3931
3932         if (hw->mac.type != ixgbe_mac_82599EB)
3933                 return -ENOSYS;
3934
3935         if (index >= IXGBE_MAX_FTQF_FILTERS)
3936                 return -EINVAL;  /* filter index is out of range. */
3937
3938         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3939         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
3940                 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
3941                 filter->protocol = revert_protocol_type(proto);
3942                 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
3943                                         IXGBE_FTQF_PRIORITY_MASK;
3944                 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
3945                                         IXGBE_FTQF_5TUPLE_MASK_MASK);
3946                 filter->src_ip_mask =
3947                         (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3948                 filter->dst_ip_mask =
3949                         (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3950                 filter->src_port_mask =
3951                         (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3952                 filter->dst_port_mask =
3953                         (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
3954                 filter->protocol_mask =
3955                         (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3956
3957                 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
3958                 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
3959                                         IXGBE_SDPQF_DSTPORT_SHIFT;
3960                 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
3961                 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
3962                 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
3963
3964                 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
3965                 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
3966                                         IXGBE_L34T_IMIR_QUEUE_SHIFT;
3967                 return 0;
3968         }
3969         return -ENOENT;
3970 }
3971
3972 static int
3973 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3974 {
3975         struct ixgbe_hw *hw;
3976         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3977
3978         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3979
3980         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3981                 return -EINVAL;
3982
3983         /* refuse mtu that requires the support of scattered packets when this
3984          * feature has not been enabled before. */
3985         if (!dev->data->scattered_rx &&
3986             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3987              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3988                 return -EINVAL;
3989
3990         /*
3991          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3992          * request of the version 2.0 of the mailbox API.
3993          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3994          * of the mailbox API.
3995          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3996          * prior to 3.11.33 which contains the following change:
3997          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3998          */
3999         ixgbevf_rlpml_set_vf(hw, max_frame);
4000
4001         /* update max frame size */
4002         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4003         return 0;
4004 }
4005
4006 #define MAC_TYPE_FILTER_SUP(type)    do {\
4007         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4008                 (type) != ixgbe_mac_X550)\
4009                 return -ENOTSUP;\
4010 } while (0)
4011
4012 static inline int
4013 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4014                         uint16_t ethertype)
4015 {
4016         int i;
4017
4018         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4019                 if (filter_info->ethertype_filters[i] == ethertype &&
4020                     (filter_info->ethertype_mask & (1 << i)))
4021                         return i;
4022         }
4023         return -1;
4024 }
4025
4026 static inline int
4027 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4028                         uint16_t ethertype)
4029 {
4030         int i;
4031
4032         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4033                 if (!(filter_info->ethertype_mask & (1 << i))) {
4034                         filter_info->ethertype_mask |= 1 << i;
4035                         filter_info->ethertype_filters[i] = ethertype;
4036                         return i;
4037                 }
4038         }
4039         return -1;
4040 }
4041
4042 static inline int
4043 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4044                         uint8_t idx)
4045 {
4046         if (idx >= IXGBE_MAX_ETQF_FILTERS)
4047                 return -1;
4048         filter_info->ethertype_mask &= ~(1 << idx);
4049         filter_info->ethertype_filters[idx] = 0;
4050         return idx;
4051 }
4052
4053 static int
4054 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4055                         struct rte_eth_ethertype_filter *filter,
4056                         bool add)
4057 {
4058         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4059         struct ixgbe_filter_info *filter_info =
4060                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4061         uint32_t etqf = 0;
4062         uint32_t etqs = 0;
4063         int ret;
4064
4065         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4066                 return -EINVAL;
4067
4068         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4069                 filter->ether_type == ETHER_TYPE_IPv6) {
4070                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4071                         " ethertype filter.", filter->ether_type);
4072                 return -EINVAL;
4073         }
4074
4075         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4076                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4077                 return -EINVAL;
4078         }
4079         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4080                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4081                 return -EINVAL;
4082         }
4083
4084         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4085         if (ret >= 0 && add) {
4086                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4087                             filter->ether_type);
4088                 return -EEXIST;
4089         }
4090         if (ret < 0 && !add) {
4091                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4092                             filter->ether_type);
4093                 return -ENOENT;
4094         }
4095
4096         if (add) {
4097                 ret = ixgbe_ethertype_filter_insert(filter_info,
4098                         filter->ether_type);
4099                 if (ret < 0) {
4100                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4101                         return -ENOSYS;
4102                 }
4103                 etqf = IXGBE_ETQF_FILTER_EN;
4104                 etqf |= (uint32_t)filter->ether_type;
4105                 etqs |= (uint32_t)((filter->queue <<
4106                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
4107                                     IXGBE_ETQS_RX_QUEUE);
4108                 etqs |= IXGBE_ETQS_QUEUE_EN;
4109         } else {
4110                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4111                 if (ret < 0)
4112                         return -ENOSYS;
4113         }
4114         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4115         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4116         IXGBE_WRITE_FLUSH(hw);
4117
4118         return 0;
4119 }
4120
4121 static int
4122 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4123                         struct rte_eth_ethertype_filter *filter)
4124 {
4125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4126         struct ixgbe_filter_info *filter_info =
4127                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4128         uint32_t etqf, etqs;
4129         int ret;
4130
4131         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4132         if (ret < 0) {
4133                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4134                             filter->ether_type);
4135                 return -ENOENT;
4136         }
4137
4138         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4139         if (etqf & IXGBE_ETQF_FILTER_EN) {
4140                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4141                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4142                 filter->flags = 0;
4143                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4144                                IXGBE_ETQS_RX_QUEUE_SHIFT;
4145                 return 0;
4146         }
4147         return -ENOENT;
4148 }
4149
4150 /*
4151  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4152  * @dev: pointer to rte_eth_dev structure
4153  * @filter_op:operation will be taken.
4154  * @arg: a pointer to specific structure corresponding to the filter_op
4155  */
4156 static int
4157 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4158                                 enum rte_filter_op filter_op,
4159                                 void *arg)
4160 {
4161         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4162         int ret;
4163
4164         MAC_TYPE_FILTER_SUP(hw->mac.type);
4165
4166         if (filter_op == RTE_ETH_FILTER_NOP)
4167                 return 0;
4168
4169         if (arg == NULL) {
4170                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4171                             filter_op);
4172                 return -EINVAL;
4173         }
4174
4175         switch (filter_op) {
4176         case RTE_ETH_FILTER_ADD:
4177                 ret = ixgbe_add_del_ethertype_filter(dev,
4178                         (struct rte_eth_ethertype_filter *)arg,
4179                         TRUE);
4180                 break;
4181         case RTE_ETH_FILTER_DELETE:
4182                 ret = ixgbe_add_del_ethertype_filter(dev,
4183                         (struct rte_eth_ethertype_filter *)arg,
4184                         FALSE);
4185                 break;
4186         case RTE_ETH_FILTER_GET:
4187                 ret = ixgbe_get_ethertype_filter(dev,
4188                         (struct rte_eth_ethertype_filter *)arg);
4189                 break;
4190         default:
4191                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4192                 ret = -EINVAL;
4193                 break;
4194         }
4195         return ret;
4196 }
4197
4198 static int
4199 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4200                      enum rte_filter_type filter_type,
4201                      enum rte_filter_op filter_op,
4202                      void *arg)
4203 {
4204         int ret = -EINVAL;
4205
4206         switch (filter_type) {
4207         case RTE_ETH_FILTER_ETHERTYPE:
4208                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4209                 break;
4210         case RTE_ETH_FILTER_FDIR:
4211                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4212                 break;
4213         default:
4214                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4215                                                         filter_type);
4216                 break;
4217         }
4218
4219         return ret;
4220 }
4221
4222 static struct rte_driver rte_ixgbe_driver = {
4223         .type = PMD_PDEV,
4224         .init = rte_ixgbe_pmd_init,
4225 };
4226
4227 static struct rte_driver rte_ixgbevf_driver = {
4228         .type = PMD_PDEV,
4229         .init = rte_ixgbevf_pmd_init,
4230 };
4231
4232 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4233 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);