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38 #include <sys/queue.h>
40 #include <rte_interrupts.h>
42 #include <rte_debug.h>
44 #include <rte_ether.h>
45 #include <rte_ethdev.h>
47 #include "ixgbe_logs.h"
48 #include "ixgbe/ixgbe_api.h"
49 #include "ixgbe/ixgbe_common.h"
50 #include "ixgbe_ethdev.h"
52 /* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */
53 #define FDIRCTRL_PBALLOC_MASK 0x03
55 /* For calculating memory required for FDIR filters */
56 #define PBALLOC_SIZE_SHIFT 15
58 /* Number of bits used to mask bucket hash for different pballoc sizes */
59 #define PERFECT_BUCKET_64KB_HASH_MASK 0x07FF /* 11 bits */
60 #define PERFECT_BUCKET_128KB_HASH_MASK 0x0FFF /* 12 bits */
61 #define PERFECT_BUCKET_256KB_HASH_MASK 0x1FFF /* 13 bits */
62 #define SIG_BUCKET_64KB_HASH_MASK 0x1FFF /* 13 bits */
63 #define SIG_BUCKET_128KB_HASH_MASK 0x3FFF /* 14 bits */
64 #define SIG_BUCKET_256KB_HASH_MASK 0x7FFF /* 15 bits */
65 #define IXGBE_DEFAULT_FLEXBYTES_OFFSET 12 /* default flexbytes offset in bytes */
66 #define IXGBE_FDIR_MAX_FLEX_LEN 2 /* len in bytes of flexbytes */
67 #define IXGBE_MAX_FLX_SOURCE_OFF 62
68 #define IXGBE_FDIRCTRL_FLEX_MASK (0x1F << IXGBE_FDIRCTRL_FLEX_SHIFT)
69 #define IXGBE_FDIRCMD_CMD_INTERVAL_US 10
71 #define IXGBE_FDIR_FLOW_TYPES ( \
72 (1 << RTE_ETH_FLOW_TYPE_UDPV4) | \
73 (1 << RTE_ETH_FLOW_TYPE_TCPV4) | \
74 (1 << RTE_ETH_FLOW_TYPE_SCTPV4) | \
75 (1 << RTE_ETH_FLOW_TYPE_IPV4_OTHER) | \
76 (1 << RTE_ETH_FLOW_TYPE_UDPV6) | \
77 (1 << RTE_ETH_FLOW_TYPE_TCPV6) | \
78 (1 << RTE_ETH_FLOW_TYPE_SCTPV6) | \
79 (1 << RTE_ETH_FLOW_TYPE_IPV6_OTHER))
81 #define IPV6_ADDR_TO_MASK(ipaddr, ipv6m) do { \
82 uint8_t ipv6_addr[16]; \
84 rte_memcpy(ipv6_addr, (ipaddr), sizeof(ipv6_addr));\
86 for (i = 0; i < sizeof(ipv6_addr); i++) { \
87 if (ipv6_addr[i] == UINT8_MAX) \
89 else if (ipv6_addr[i] != 0) { \
90 PMD_DRV_LOG(ERR, " invalid IPv6 address mask."); \
96 #define IPV6_MASK_TO_ADDR(ipv6m, ipaddr) do { \
97 uint8_t ipv6_addr[16]; \
99 for (i = 0; i < sizeof(ipv6_addr); i++) { \
100 if ((ipv6m) & (1 << i)) \
101 ipv6_addr[i] = UINT8_MAX; \
105 rte_memcpy((ipaddr), ipv6_addr, sizeof(ipv6_addr));\
108 static int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash);
109 static int fdir_set_input_mask_82599(struct rte_eth_dev *dev,
110 const struct rte_eth_fdir_masks *input_mask);
111 static int ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
112 const struct rte_eth_fdir_flex_conf *conf);
113 static int fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl);
114 static int ixgbe_fdir_filter_to_atr_input(
115 const struct rte_eth_fdir_filter *fdir_filter,
116 union ixgbe_atr_input *input);
117 static uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
119 static uint32_t atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
120 enum rte_fdir_pballoc_type pballoc);
121 static uint32_t atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
122 enum rte_fdir_pballoc_type pballoc);
123 static int fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
124 union ixgbe_atr_input *input, uint8_t queue,
125 uint32_t fdircmd, uint32_t fdirhash);
126 static int fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
127 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
129 static int ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
130 const struct rte_eth_fdir_filter *fdir_filter,
133 static void ixgbe_fdir_info_get(struct rte_eth_dev *dev,
134 struct rte_eth_fdir_info *fdir_info);
135 static void ixgbe_fdir_stats_get(struct rte_eth_dev *dev,
136 struct rte_eth_fdir_stats *fdir_stats);
139 * This function is based on ixgbe_fdir_enable_82599() in ixgbe/ixgbe_82599.c.
140 * It adds extra configuration of fdirctrl that is common for all filter types.
142 * Initialize Flow Director control registers
143 * @hw: pointer to hardware structure
144 * @fdirctrl: value to write to flow director control register
147 fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl)
151 PMD_INIT_FUNC_TRACE();
153 /* Prime the keys for hashing */
154 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
155 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
158 * Continue setup of fdirctrl register bits:
159 * Set the maximum length per hash bucket to 0xA filters
160 * Send interrupt when 64 filters are left
162 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
163 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
166 * Poll init-done after we write the register. Estimated times:
167 * 10G: PBALLOC = 11b, timing is 60us
168 * 1G: PBALLOC = 11b, timing is 600us
169 * 100M: PBALLOC = 11b, timing is 6ms
171 * Multiple these timings by 4 if under full Rx load
173 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
174 * 1 msec per poll time. If we're at line rate and drop to 100M, then
175 * this might not finish in our poll time, but we can live with that
178 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
179 IXGBE_WRITE_FLUSH(hw);
180 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
181 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
182 IXGBE_FDIRCTRL_INIT_DONE)
187 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
188 PMD_INIT_LOG(ERR, "Flow Director poll time exceeded "
196 * Set appropriate bits in fdirctrl for: variable reporting levels, moving
197 * flexbytes matching field, and drop queue (only for perfect matching mode).
200 configure_fdir_flags(const struct rte_fdir_conf *conf, uint32_t *fdirctrl)
204 switch (conf->pballoc) {
205 case RTE_FDIR_PBALLOC_64K:
206 /* 8k - 1 signature filters */
207 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
209 case RTE_FDIR_PBALLOC_128K:
210 /* 16k - 1 signature filters */
211 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
213 case RTE_FDIR_PBALLOC_256K:
214 /* 32k - 1 signature filters */
215 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
219 PMD_INIT_LOG(ERR, "Invalid fdir_conf->pballoc value");
223 /* status flags: write hash & swindex in the rx descriptor */
224 switch (conf->status) {
225 case RTE_FDIR_NO_REPORT_STATUS:
226 /* do nothing, default mode */
228 case RTE_FDIR_REPORT_STATUS:
229 /* report status when the packet matches a fdir rule */
230 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
232 case RTE_FDIR_REPORT_STATUS_ALWAYS:
233 /* always report status */
234 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS;
238 PMD_INIT_LOG(ERR, "Invalid fdir_conf->status value");
242 *fdirctrl |= (IXGBE_DEFAULT_FLEXBYTES_OFFSET / sizeof(uint16_t)) <<
243 IXGBE_FDIRCTRL_FLEX_SHIFT;
245 if (conf->mode == RTE_FDIR_MODE_PERFECT) {
246 *fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
247 *fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
250 * Continue setup of fdirctrl register bits:
251 * Set the maximum length per hash bucket to 0xA filters
252 * Send interrupt when 64 filters are left
254 *fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
255 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
261 * Reverse the bits in FDIR registers that store 2 x 16 bit masks.
263 * @hi_dword: Bits 31:16 mask to be bit swapped.
264 * @lo_dword: Bits 15:0 mask to be bit swapped.
266 * Flow director uses several registers to store 2 x 16 bit masks with the
267 * bits reversed such as FDIRTCPM, FDIRUDPM. The LS bit of the
268 * mask affects the MS bit/byte of the target. This function reverses the
269 * bits in these masks.
271 static inline uint32_t
272 reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)
274 uint32_t mask = hi_dword << 16;
276 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
277 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
278 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
279 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
283 * This is based on ixgbe_fdir_set_input_mask_82599() in ixgbe/ixgbe_82599.c,
284 * but makes use of the rte_fdir_masks structure to see which bits to set.
287 fdir_set_input_mask_82599(struct rte_eth_dev *dev,
288 const struct rte_eth_fdir_masks *input_mask)
290 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
291 struct ixgbe_hw_fdir_info *info =
292 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
294 * mask VM pool and DIPv6 since there are currently not supported
295 * mask FLEX byte, it will be set in flex_conf
297 uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 | IXGBE_FDIRM_FLEX;
298 uint32_t fdirtcpm; /* TCP source and destination port masks. */
299 uint32_t fdiripv6m; /* IPv6 source and destination masks. */
300 uint16_t dst_ipv6m = 0;
301 uint16_t src_ipv6m = 0;
303 PMD_INIT_FUNC_TRACE();
306 * Program the relevant mask registers. If src/dst_port or src/dst_addr
307 * are zero, then assume a full mask for that field. Also assume that
308 * a VLAN of 0 is unspecified, so mask that out as well. L4type
309 * cannot be masked out in this implementation.
311 if (input_mask->dst_port_mask == 0 && input_mask->src_port_mask == 0)
312 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
313 fdirm |= IXGBE_FDIRM_L4P;
315 if (input_mask->vlan_tci_mask == 0x0FFF)
316 /* mask VLAN Priority */
317 fdirm |= IXGBE_FDIRM_VLANP;
318 else if (input_mask->vlan_tci_mask == 0xE000)
320 fdirm |= IXGBE_FDIRM_VLANID;
321 else if (input_mask->vlan_tci_mask == 0)
322 /* mask VLAN ID and Priority */
323 fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
324 else if (input_mask->vlan_tci_mask != 0xEFFF) {
325 PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
328 info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
330 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
332 /* store the TCP/UDP port masks, bit reversed from port layout */
333 fdirtcpm = reverse_fdir_bitmasks(input_mask->dst_port_mask,
334 input_mask->src_port_mask);
336 /* write both the same so that UDP and TCP use the same mask */
337 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
338 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
339 info->mask.src_port_mask = input_mask->src_port_mask;
340 info->mask.dst_port_mask = input_mask->dst_port_mask;
342 /* Store source and destination IPv4 masks (big-endian) */
343 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, ~(input_mask->ipv4_mask.src_ip));
344 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, ~(input_mask->ipv4_mask.dst_ip));
345 info->mask.src_ipv4_mask = input_mask->ipv4_mask.src_ip;
346 info->mask.dst_ipv4_mask = input_mask->ipv4_mask.dst_ip;
348 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE) {
350 * IPv6 mask is only meaningful in signature mode
351 * Store source and destination IPv6 masks (bit reversed)
353 IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.src_ip, src_ipv6m);
354 IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.dst_ip, dst_ipv6m);
355 fdiripv6m = (dst_ipv6m << 16) | src_ipv6m;
357 IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m);
358 info->mask.src_ipv6_mask = src_ipv6m;
359 info->mask.dst_ipv6_mask = dst_ipv6m;
362 return IXGBE_SUCCESS;
366 * ixgbe_check_fdir_flex_conf -check if the flex payload and mask configuration
367 * arguments are valid
370 ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
371 const struct rte_eth_fdir_flex_conf *conf)
373 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
374 struct ixgbe_hw_fdir_info *info =
375 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
376 const struct rte_eth_flex_payload_cfg *flex_cfg;
377 const struct rte_eth_fdir_flex_mask *flex_mask;
378 uint32_t fdirctrl, fdirm;
379 uint16_t flexbytes = 0;
382 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
383 fdirm = IXGBE_READ_REG(hw, IXGBE_FDIRM);
386 PMD_DRV_LOG(INFO, "NULL pointer.");
390 for (i = 0; i < conf->nb_payloads; i++) {
391 flex_cfg = &conf->flex_set[i];
392 if (flex_cfg->type != RTE_ETH_RAW_PAYLOAD) {
393 PMD_DRV_LOG(ERR, "unsupported payload type.");
396 if (((flex_cfg->src_offset[0] & 0x1) == 0) &&
397 (flex_cfg->src_offset[1] == flex_cfg->src_offset[0] + 1) &&
398 (flex_cfg->src_offset[0] <= IXGBE_MAX_FLX_SOURCE_OFF)) {
399 fdirctrl &= ~IXGBE_FDIRCTRL_FLEX_MASK;
400 fdirctrl |= (flex_cfg->src_offset[0] / sizeof(uint16_t)) <<
401 IXGBE_FDIRCTRL_FLEX_SHIFT;
403 PMD_DRV_LOG(ERR, "invalid flexbytes arguments.");
408 for (i = 0; i < conf->nb_flexmasks; i++) {
409 flex_mask = &conf->flex_mask[i];
410 if (flex_mask->flow_type != RTE_ETH_FLOW_TYPE_RAW) {
411 PMD_DRV_LOG(ERR, "unsupported flow type.");
414 flexbytes = (uint16_t)(((flex_mask->mask[0] << 8) & 0xFF00) |
415 ((flex_mask->mask[1]) & 0xFF));
416 if (flexbytes == UINT16_MAX)
417 fdirm &= ~IXGBE_FDIRM_FLEX;
418 else if (flexbytes != 0) {
419 /* IXGBE_FDIRM_FLEX is set by default when set mask */
420 PMD_DRV_LOG(ERR, " invalid flexbytes mask arguments.");
424 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
425 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
426 info->mask.flex_bytes_mask = flexbytes ? UINT16_MAX : 0;
427 info->flex_bytes_offset = (uint8_t)((fdirctrl &
428 IXGBE_FDIRCTRL_FLEX_MASK) >>
429 IXGBE_FDIRCTRL_FLEX_SHIFT);
434 ixgbe_fdir_configure(struct rte_eth_dev *dev)
436 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
438 uint32_t fdirctrl, pbsize;
441 PMD_INIT_FUNC_TRACE();
443 if (hw->mac.type != ixgbe_mac_82599EB &&
444 hw->mac.type != ixgbe_mac_X540 &&
445 hw->mac.type != ixgbe_mac_X550 &&
446 hw->mac.type != ixgbe_mac_X550EM_x)
449 err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
454 * Before enabling Flow Director, the Rx Packet Buffer size
455 * must be reduced. The new value is the current size minus
456 * flow director memory usage size.
458 pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
459 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
460 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
463 * The defaults in the HW for RX PB 1-7 are not zero and so should be
464 * intialized to zero for non DCB mode otherwise actual total RX PB
465 * would be bigger than programmed and filter space would run into
468 for (i = 1; i < 8; i++)
469 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
471 err = fdir_set_input_mask_82599(dev, &dev->data->dev_conf.fdir_conf.mask);
473 PMD_INIT_LOG(ERR, " Error on setting FD mask");
476 err = ixgbe_set_fdir_flex_conf(dev,
477 &dev->data->dev_conf.fdir_conf.flex_conf);
479 PMD_INIT_LOG(ERR, " Error on setting FD flexible arguments.");
483 err = fdir_enable_82599(hw, fdirctrl);
485 PMD_INIT_LOG(ERR, " Error on enabling FD.");
492 * Convert DPDK rte_eth_fdir_filter struct to ixgbe_atr_input union that is used
493 * by the IXGBE driver code.
496 ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,
497 union ixgbe_atr_input *input)
499 input->formatted.vlan_id = fdir_filter->input.flow_ext.vlan_tci;
500 input->formatted.flex_bytes = (uint16_t)(
501 (fdir_filter->input.flow_ext.flexbytes[1] << 8 & 0xFF00) |
502 (fdir_filter->input.flow_ext.flexbytes[0] & 0xFF));
504 switch (fdir_filter->input.flow_type) {
505 case RTE_ETH_FLOW_TYPE_UDPV4:
506 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
508 case RTE_ETH_FLOW_TYPE_TCPV4:
509 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
511 case RTE_ETH_FLOW_TYPE_SCTPV4:
512 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
514 case RTE_ETH_FLOW_TYPE_IPV4_OTHER:
515 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
517 case RTE_ETH_FLOW_TYPE_UDPV6:
518 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV6;
520 case RTE_ETH_FLOW_TYPE_TCPV6:
521 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
523 case RTE_ETH_FLOW_TYPE_SCTPV6:
524 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV6;
526 case RTE_ETH_FLOW_TYPE_IPV6_OTHER:
527 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV6;
530 PMD_DRV_LOG(ERR, " Error on flow_type input");
534 switch (fdir_filter->input.flow_type) {
535 case RTE_ETH_FLOW_TYPE_UDPV4:
536 case RTE_ETH_FLOW_TYPE_TCPV4:
537 input->formatted.src_port =
538 fdir_filter->input.flow.udp4_flow.src_port;
539 input->formatted.dst_port =
540 fdir_filter->input.flow.udp4_flow.dst_port;
541 /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
542 case RTE_ETH_FLOW_TYPE_SCTPV4:
543 case RTE_ETH_FLOW_TYPE_IPV4_OTHER:
544 input->formatted.src_ip[0] =
545 fdir_filter->input.flow.ip4_flow.src_ip;
546 input->formatted.dst_ip[0] =
547 fdir_filter->input.flow.ip4_flow.dst_ip;
550 case RTE_ETH_FLOW_TYPE_UDPV6:
551 case RTE_ETH_FLOW_TYPE_TCPV6:
552 input->formatted.src_port =
553 fdir_filter->input.flow.udp6_flow.src_port;
554 input->formatted.dst_port =
555 fdir_filter->input.flow.udp6_flow.dst_port;
556 /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
557 case RTE_ETH_FLOW_TYPE_SCTPV6:
558 case RTE_ETH_FLOW_TYPE_IPV6_OTHER:
559 rte_memcpy(input->formatted.src_ip,
560 fdir_filter->input.flow.ipv6_flow.src_ip,
561 sizeof(input->formatted.src_ip));
562 rte_memcpy(input->formatted.dst_ip,
563 fdir_filter->input.flow.ipv6_flow.dst_ip,
564 sizeof(input->formatted.dst_ip));
567 PMD_DRV_LOG(ERR, " Error on flow_type input");
575 * The below function is taken from the FreeBSD IXGBE drivers release
576 * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK
577 * before returning, as the signature hash can use 16bits.
579 * The newer driver has optimised functions for calculating bucket and
580 * signature hashes. However they don't support IPv6 type packets for signature
581 * filters so are not used here.
583 * Note that the bkt_hash field in the ixgbe_atr_input structure is also never
586 * Compute the hashes for SW ATR
587 * @stream: input bitstream to compute the hash on
588 * @key: 32-bit hash key
591 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
595 * The algorithm is as follows:
596 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
597 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
598 * and A[n] x B[n] is bitwise AND between same length strings
600 * K[n] is 16 bits, defined as:
601 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
602 * for n modulo 32 < 15, K[n] =
603 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
605 * S[n] is 16 bits, defined as:
606 * for n >= 15, S[n] = S[n:n - 15]
607 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
609 * To simplify for programming, the algorithm is implemented
610 * in software this way:
612 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
614 * for (i = 0; i < 352; i+=32)
615 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
617 * lo_hash_dword[15:0] ^= Stream[15:0];
618 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
619 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
621 * hi_hash_dword[31:0] ^= Stream[351:320];
624 * hash[15:0] ^= Stream[15:0];
626 * for (i = 0; i < 16; i++) {
628 * hash[15:0] ^= lo_hash_dword[(i+15):i];
630 * hash[15:0] ^= hi_hash_dword[(i+15):i];
634 __be32 common_hash_dword = 0;
635 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
639 /* record the flow_vm_vlan bits as they are a key part to the hash */
640 flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
642 /* generate common hash dword */
643 for (i = 1; i <= 13; i++)
644 common_hash_dword ^= atr_input->dword_stream[i];
646 hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
648 /* low dword is word swapped version of common */
649 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
651 /* apply flow ID/VM pool/VLAN ID bits to hash words */
652 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
654 /* Process bits 0 and 16 */
655 if (key & 0x0001) hash_result ^= lo_hash_dword;
656 if (key & 0x00010000) hash_result ^= hi_hash_dword;
659 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
660 * delay this because bit 0 of the stream should not be processed
661 * so we do not add the vlan until after bit 0 was processed
663 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
666 /* process the remaining 30 bits in the key 2 bits at a time */
667 for (i = 15; i; i-- ) {
668 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
669 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
676 atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
677 enum rte_fdir_pballoc_type pballoc)
679 if (pballoc == RTE_FDIR_PBALLOC_256K)
680 return ixgbe_atr_compute_hash_82599(input,
681 IXGBE_ATR_BUCKET_HASH_KEY) &
682 PERFECT_BUCKET_256KB_HASH_MASK;
683 else if (pballoc == RTE_FDIR_PBALLOC_128K)
684 return ixgbe_atr_compute_hash_82599(input,
685 IXGBE_ATR_BUCKET_HASH_KEY) &
686 PERFECT_BUCKET_128KB_HASH_MASK;
688 return ixgbe_atr_compute_hash_82599(input,
689 IXGBE_ATR_BUCKET_HASH_KEY) &
690 PERFECT_BUCKET_64KB_HASH_MASK;
694 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
695 * @hw: pointer to hardware structure
698 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, uint32_t *fdircmd)
702 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
703 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
704 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
706 rte_delay_us(IXGBE_FDIRCMD_CMD_INTERVAL_US);
713 * Calculate the hash value needed for signature-match filters. In the FreeBSD
714 * driver, this is done by the optimised function
715 * ixgbe_atr_compute_sig_hash_82599(). However that can't be used here as it
716 * doesn't support calculating a hash for an IPv6 filter.
719 atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
720 enum rte_fdir_pballoc_type pballoc)
722 uint32_t bucket_hash, sig_hash;
724 if (pballoc == RTE_FDIR_PBALLOC_256K)
725 bucket_hash = ixgbe_atr_compute_hash_82599(input,
726 IXGBE_ATR_BUCKET_HASH_KEY) &
727 SIG_BUCKET_256KB_HASH_MASK;
728 else if (pballoc == RTE_FDIR_PBALLOC_128K)
729 bucket_hash = ixgbe_atr_compute_hash_82599(input,
730 IXGBE_ATR_BUCKET_HASH_KEY) &
731 SIG_BUCKET_128KB_HASH_MASK;
733 bucket_hash = ixgbe_atr_compute_hash_82599(input,
734 IXGBE_ATR_BUCKET_HASH_KEY) &
735 SIG_BUCKET_64KB_HASH_MASK;
737 sig_hash = ixgbe_atr_compute_hash_82599(input,
738 IXGBE_ATR_SIGNATURE_HASH_KEY);
740 return (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash;
744 * This is based on ixgbe_fdir_write_perfect_filter_82599() in
745 * ixgbe/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register
746 * added, and IPv6 support also added. The hash value is also pre-calculated
747 * as the pballoc value is needed to do it.
750 fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
751 union ixgbe_atr_input *input, uint8_t queue,
752 uint32_t fdircmd, uint32_t fdirhash)
754 uint32_t fdirport, fdirvlan;
757 /* record the IPv4 address (big-endian) */
758 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
759 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
761 /* record source and destination port (little-endian)*/
762 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
763 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
764 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
765 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
767 /* record vlan (little-endian) and flex_bytes(big-endian) */
768 fdirvlan = input->formatted.flex_bytes;
769 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
770 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
771 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
773 /* configure FDIRHASH register */
774 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
777 * flush all previous writes to make certain registers are
778 * programmed prior to issuing the command
780 IXGBE_WRITE_FLUSH(hw);
782 /* configure FDIRCMD register */
783 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
784 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
785 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
786 fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
787 fdircmd |= (uint32_t)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
789 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
791 PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
793 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
795 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
801 * This function is based on ixgbe_atr_add_signature_filter_82599() in
802 * ixgbe/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports
803 * setting extra fields in the FDIRCMD register, and removes the code that was
804 * verifying the flow_type field. According to the documentation, a flow type of
805 * 00 (i.e. not TCP, UDP, or SCTP) is not supported, however it appears to
808 * Adds a signature hash filter
809 * @hw: pointer to hardware structure
810 * @input: unique input dword
811 * @queue: queue index to direct traffic to
812 * @fdircmd: any extra flags to set in fdircmd register
813 * @fdirhash: pre-calculated hash value for the filter
816 fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
817 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
822 PMD_INIT_FUNC_TRACE();
824 /* configure FDIRCMD register */
825 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
826 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
827 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
828 fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
830 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
831 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
833 PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
835 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
837 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
843 * This is based on ixgbe_fdir_erase_perfect_filter_82599() in
844 * ixgbe/ixgbe_82599.c. It is modified to take in the hash as a parameter so
845 * that it can be used for removing signature and perfect filters.
848 fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash)
850 uint32_t fdircmd = 0;
853 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
855 /* flush hash to HW */
856 IXGBE_WRITE_FLUSH(hw);
858 /* Query if filter is present */
859 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
861 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
863 PMD_INIT_LOG(ERR, "Timeout querying for flow director filter.");
867 /* if filter exists in hardware then remove it */
868 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
869 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
870 IXGBE_WRITE_FLUSH(hw);
871 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
872 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
874 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
876 PMD_INIT_LOG(ERR, "Timeout erasing flow director filter.");
882 * ixgbe_add_del_fdir_filter - add or remove a flow diretor filter.
883 * @dev: pointer to the structure rte_eth_dev
884 * @fdir_filter: fdir filter entry
885 * @del: 1 - delete, 0 - add
886 * @update: 1 - update
889 ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
890 const struct rte_eth_fdir_filter *fdir_filter,
894 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
895 uint32_t fdircmd_flags;
897 union ixgbe_atr_input input;
899 bool is_perfect = FALSE;
902 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_NONE)
905 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
908 memset(&input, 0, sizeof(input));
910 err = ixgbe_fdir_filter_to_atr_input(fdir_filter, &input);
915 if (input.formatted.flow_type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
916 PMD_DRV_LOG(ERR, "IPv6 is not supported in"
920 fdirhash = atr_compute_perfect_hash_82599(&input,
921 dev->data->dev_conf.fdir_conf.pballoc);
922 fdirhash |= fdir_filter->soft_id <<
923 IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
925 fdirhash = atr_compute_sig_hash_82599(&input,
926 dev->data->dev_conf.fdir_conf.pballoc);
929 err = fdir_erase_filter_82599(hw, fdirhash);
931 PMD_DRV_LOG(ERR, "Fail to delete FDIR filter!");
933 PMD_DRV_LOG(DEBUG, "Success to delete FDIR filter!");
936 /* add or update an fdir filter*/
937 fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
938 if (fdir_filter->action.behavior == RTE_ETH_FDIR_REJECT) {
940 queue = dev->data->dev_conf.fdir_conf.drop_queue;
941 fdircmd_flags |= IXGBE_FDIRCMD_DROP;
943 PMD_DRV_LOG(ERR, "Drop option is not supported in"
947 } else if (fdir_filter->action.rx_queue < IXGBE_MAX_RX_QUEUE_NUM)
948 queue = (uint8_t)fdir_filter->action.rx_queue;
953 err = fdir_write_perfect_filter_82599(hw, &input, queue,
954 fdircmd_flags, fdirhash);
956 err = fdir_add_signature_filter_82599(hw, &input, queue,
957 fdircmd_flags, fdirhash);
960 PMD_DRV_LOG(ERR, "Fail to add FDIR filter!");
962 PMD_DRV_LOG(DEBUG, "Success to add FDIR filter");
967 #define FDIRENTRIES_NUM_SHIFT 10
969 ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info)
971 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
972 struct ixgbe_hw_fdir_info *info =
973 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
974 uint32_t fdirctrl, max_num;
977 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
978 offset = ((fdirctrl & IXGBE_FDIRCTRL_FLEX_MASK) >>
979 IXGBE_FDIRCTRL_FLEX_SHIFT) * sizeof(uint16_t);
981 fdir_info->mode = dev->data->dev_conf.fdir_conf.mode;
982 max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
983 (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
984 if (fdir_info->mode == RTE_FDIR_MODE_PERFECT)
985 fdir_info->guarant_spc = max_num;
986 else if (fdir_info->mode == RTE_FDIR_MODE_SIGNATURE)
987 fdir_info->guarant_spc = max_num * 4;
989 fdir_info->mask.vlan_tci_mask = info->mask.vlan_tci_mask;
990 fdir_info->mask.ipv4_mask.src_ip = info->mask.src_ipv4_mask;
991 fdir_info->mask.ipv4_mask.dst_ip = info->mask.dst_ipv4_mask;
992 IPV6_MASK_TO_ADDR(info->mask.src_ipv6_mask,
993 fdir_info->mask.ipv6_mask.src_ip);
994 IPV6_MASK_TO_ADDR(info->mask.dst_ipv6_mask,
995 fdir_info->mask.ipv6_mask.dst_ip);
996 fdir_info->mask.src_port_mask = info->mask.src_port_mask;
997 fdir_info->mask.dst_port_mask = info->mask.dst_port_mask;
998 fdir_info->max_flexpayload = IXGBE_FDIR_MAX_FLEX_LEN;
999 fdir_info->flow_types_mask[0] = IXGBE_FDIR_FLOW_TYPES;
1000 fdir_info->flex_payload_unit = sizeof(uint16_t);
1001 fdir_info->max_flex_payload_segment_num = 1;
1002 fdir_info->flex_payload_limit = 62;
1003 fdir_info->flex_conf.nb_payloads = 1;
1004 fdir_info->flex_conf.flex_set[0].type = RTE_ETH_RAW_PAYLOAD;
1005 fdir_info->flex_conf.flex_set[0].src_offset[0] = offset;
1006 fdir_info->flex_conf.flex_set[0].src_offset[1] = offset + 1;
1007 fdir_info->flex_conf.nb_flexmasks = 1;
1008 fdir_info->flex_conf.flex_mask[0].flow_type = RTE_ETH_FLOW_TYPE_RAW;
1009 fdir_info->flex_conf.flex_mask[0].mask[0] =
1010 (uint8_t)(info->mask.flex_bytes_mask & 0x00FF);
1011 fdir_info->flex_conf.flex_mask[0].mask[1] =
1012 (uint8_t)((info->mask.flex_bytes_mask & 0xFF00) >> 8);
1016 ixgbe_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *fdir_stats)
1018 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1019 struct ixgbe_hw_fdir_info *info =
1020 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1021 uint32_t reg, max_num;
1023 /* Get the information from registers */
1024 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE);
1025 info->collision = (uint16_t)((reg & IXGBE_FDIRFREE_COLL_MASK) >>
1026 IXGBE_FDIRFREE_COLL_SHIFT);
1027 info->free = (uint16_t)((reg & IXGBE_FDIRFREE_FREE_MASK) >>
1028 IXGBE_FDIRFREE_FREE_SHIFT);
1030 reg = IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1031 info->maxhash = (uint16_t)((reg & IXGBE_FDIRLEN_MAXHASH_MASK) >>
1032 IXGBE_FDIRLEN_MAXHASH_SHIFT);
1033 info->maxlen = (uint8_t)((reg & IXGBE_FDIRLEN_MAXLEN_MASK) >>
1034 IXGBE_FDIRLEN_MAXLEN_SHIFT);
1036 reg = IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1037 info->remove += (reg & IXGBE_FDIRUSTAT_REMOVE_MASK) >>
1038 IXGBE_FDIRUSTAT_REMOVE_SHIFT;
1039 info->add += (reg & IXGBE_FDIRUSTAT_ADD_MASK) >>
1040 IXGBE_FDIRUSTAT_ADD_SHIFT;
1042 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT) & 0xFFFF;
1043 info->f_remove += (reg & IXGBE_FDIRFSTAT_FREMOVE_MASK) >>
1044 IXGBE_FDIRFSTAT_FREMOVE_SHIFT;
1045 info->f_add += (reg & IXGBE_FDIRFSTAT_FADD_MASK) >>
1046 IXGBE_FDIRFSTAT_FADD_SHIFT;
1048 /* Copy the new information in the fdir parameter */
1049 fdir_stats->collision = info->collision;
1050 fdir_stats->free = info->free;
1051 fdir_stats->maxhash = info->maxhash;
1052 fdir_stats->maxlen = info->maxlen;
1053 fdir_stats->remove = info->remove;
1054 fdir_stats->add = info->add;
1055 fdir_stats->f_remove = info->f_remove;
1056 fdir_stats->f_add = info->f_add;
1058 reg = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1059 max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
1060 (reg & FDIRCTRL_PBALLOC_MASK)));
1061 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1062 fdir_stats->guarant_cnt = max_num - fdir_stats->free;
1063 else if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE)
1064 fdir_stats->guarant_cnt = max_num * 4 - fdir_stats->free;
1069 * ixgbe_fdir_ctrl_func - deal with all operations on flow director.
1070 * @dev: pointer to the structure rte_eth_dev
1071 * @filter_op:operation will be taken
1072 * @arg: a pointer to specific structure corresponding to the filter_op
1075 ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
1076 enum rte_filter_op filter_op, void *arg)
1078 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1081 if (hw->mac.type != ixgbe_mac_82599EB &&
1082 hw->mac.type != ixgbe_mac_X540 &&
1083 hw->mac.type != ixgbe_mac_X550 &&
1084 hw->mac.type != ixgbe_mac_X550EM_x)
1087 if (filter_op == RTE_ETH_FILTER_NOP)
1090 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1093 switch (filter_op) {
1094 case RTE_ETH_FILTER_ADD:
1095 ret = ixgbe_add_del_fdir_filter(dev,
1096 (struct rte_eth_fdir_filter *)arg, FALSE, FALSE);
1098 case RTE_ETH_FILTER_UPDATE:
1099 ret = ixgbe_add_del_fdir_filter(dev,
1100 (struct rte_eth_fdir_filter *)arg, FALSE, TRUE);
1102 case RTE_ETH_FILTER_DELETE:
1103 ret = ixgbe_add_del_fdir_filter(dev,
1104 (struct rte_eth_fdir_filter *)arg, TRUE, FALSE);
1106 case RTE_ETH_FILTER_INFO:
1107 ixgbe_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1109 case RTE_ETH_FILTER_STATS:
1110 ixgbe_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1113 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);