lib/librte_sched/rte_sched.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <string.h>
  36
  37 #include <rte_common.h>
  38 #include <rte_log.h>
  39 #include <rte_memory.h>
  40 #include <rte_malloc.h>
  41 #include <rte_cycles.h>
  42 #include <rte_prefetch.h>
  43 #include <rte_branch_prediction.h>
  44 #include <rte_mbuf.h>
  45
  46 #include "rte_sched.h"
  47 #include "rte_bitmap.h"
  48 #include "rte_sched_common.h"
  49 #include "rte_approx.h"
  50
  51 #ifdef __INTEL_COMPILER
  52 #pragma warning(disable:2259) /* conversion may lose significant bits */
  53 #endif
  54
  55 #ifdef RTE_SCHED_VECTOR
  56 #include <immintrin.h>
  57 #endif
  58
  59 #define RTE_SCHED_TB_RATE_CONFIG_ERR          (1e-7)
  60 #define RTE_SCHED_WRR_SHIFT                   3
  61 #define RTE_SCHED_GRINDER_PCACHE_SIZE         (64 / RTE_SCHED_QUEUES_PER_PIPE)
  62 #define RTE_SCHED_PIPE_INVALID                UINT32_MAX
  63 #define RTE_SCHED_BMP_POS_INVALID             UINT32_MAX
  64
  65 struct rte_sched_subport {
  66         /* Token bucket (TB) */
  67         uint64_t tb_time; /* time of last update */
  68         uint32_t tb_period;
  69         uint32_t tb_credits_per_period;
  70         uint32_t tb_size;
  71         uint32_t tb_credits;
  72
  73         /* Traffic classes (TCs) */
  74         uint64_t tc_time; /* time of next update */
  75         uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
  76         uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
  77         uint32_t tc_period;
  78
  79         /* TC oversubscription */
  80         uint32_t tc_ov_wm;
  81         uint32_t tc_ov_wm_min;
  82         uint32_t tc_ov_wm_max;
  83         uint8_t tc_ov_period_id;
  84         uint8_t tc_ov;
  85         uint32_t tc_ov_n;
  86         double tc_ov_rate;
  87
  88         /* Statistics */
  89         struct rte_sched_subport_stats stats;
  90 };
  91
  92 struct rte_sched_pipe_profile {
  93         /* Token bucket (TB) */
  94         uint32_t tb_period;
  95         uint32_t tb_credits_per_period;
  96         uint32_t tb_size;
  97
  98         /* Pipe traffic classes */
  99         uint32_t tc_period;
 100         uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
 101         uint8_t tc_ov_weight;
 102
 103         /* Pipe queues */
 104         uint8_t  wrr_cost[RTE_SCHED_QUEUES_PER_PIPE];
 105 };
 106
 107 struct rte_sched_pipe {
 108         /* Token bucket (TB) */
 109         uint64_t tb_time; /* time of last update */
 110         uint32_t tb_credits;
 111
 112         /* Pipe profile and flags */
 113         uint32_t profile;
 114
 115         /* Traffic classes (TCs) */
 116         uint64_t tc_time; /* time of next update */
 117         uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
 118
 119         /* Weighted Round Robin (WRR) */
 120         uint8_t wrr_tokens[RTE_SCHED_QUEUES_PER_PIPE];
 121
 122         /* TC oversubscription */
 123         uint32_t tc_ov_credits;
 124         uint8_t tc_ov_period_id;
 125         uint8_t reserved[3];
 126 } __rte_cache_aligned;
 127
 128 struct rte_sched_queue {
 129         uint16_t qw;
 130         uint16_t qr;
 131 };
 132
 133 struct rte_sched_queue_extra {
 134         struct rte_sched_queue_stats stats;
 135 #ifdef RTE_SCHED_RED
 136         struct rte_red red;
 137 #endif
 138 };
 139
 140 enum grinder_state {
 141         e_GRINDER_PREFETCH_PIPE = 0,
 142         e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS,
 143         e_GRINDER_PREFETCH_MBUF,
 144         e_GRINDER_READ_MBUF
 145 };
 146
 147 /*
 148  * Path through the scheduler hierarchy used by the scheduler enqueue
 149  * operation to identify the destination queue for the current
 150  * packet. Stored in the field pkt.hash.sched of struct rte_mbuf of
 151  * each packet, typically written by the classification stage and read
 152  * by scheduler enqueue.
 153  */
 154 struct rte_sched_port_hierarchy {
 155         uint16_t queue:2;                /**< Queue ID (0 .. 3) */
 156         uint16_t traffic_class:2;        /**< Traffic class ID (0 .. 3)*/
 157         uint32_t color:2;                /**< Color */
 158         uint16_t unused:10;
 159         uint16_t subport;                /**< Subport ID */
 160         uint32_t pipe;                   /**< Pipe ID */
 161 };
 162
 163 struct rte_sched_grinder {
 164         /* Pipe cache */
 165         uint16_t pcache_qmask[RTE_SCHED_GRINDER_PCACHE_SIZE];
 166         uint32_t pcache_qindex[RTE_SCHED_GRINDER_PCACHE_SIZE];
 167         uint32_t pcache_w;
 168         uint32_t pcache_r;
 169
 170         /* Current pipe */
 171         enum grinder_state state;
 172         uint32_t productive;
 173         uint32_t pindex;
 174         struct rte_sched_subport *subport;
 175         struct rte_sched_pipe *pipe;
 176         struct rte_sched_pipe_profile *pipe_params;
 177
 178         /* TC cache */
 179         uint8_t tccache_qmask[4];
 180         uint32_t tccache_qindex[4];
 181         uint32_t tccache_w;
 182         uint32_t tccache_r;
 183
 184         /* Current TC */
 185         uint32_t tc_index;
 186         struct rte_sched_queue *queue[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
 187         struct rte_mbuf **qbase[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
 188         uint32_t qindex[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
 189         uint16_t qsize;
 190         uint32_t qmask;
 191         uint32_t qpos;
 192         struct rte_mbuf *pkt;
 193
 194         /* WRR */
 195         uint16_t wrr_tokens[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
 196         uint16_t wrr_mask[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
 197         uint8_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
 198 };
 199
 200 struct rte_sched_port {
 201         /* User parameters */
 202         uint32_t n_subports_per_port;
 203         uint32_t n_pipes_per_subport;
 204         uint32_t rate;
 205         uint32_t mtu;
 206         uint32_t frame_overhead;
 207         uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
 208         uint32_t n_pipe_profiles;
 209         uint32_t pipe_tc3_rate_max;
 210 #ifdef RTE_SCHED_RED
 211         struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][e_RTE_METER_COLORS];
 212 #endif
 213
 214         /* Timing */
 215         uint64_t time_cpu_cycles;     /* Current CPU time measured in CPU cyles */
 216         uint64_t time_cpu_bytes;      /* Current CPU time measured in bytes */
 217         uint64_t time;                /* Current NIC TX time measured in bytes */
 218         double cycles_per_byte;       /* CPU cycles per byte */
 219
 220         /* Scheduling loop detection */
 221         uint32_t pipe_loop;
 222         uint32_t pipe_exhaustion;
 223
 224         /* Bitmap */
 225         struct rte_bitmap *bmp;
 226         uint32_t grinder_base_bmp_pos[RTE_SCHED_PORT_N_GRINDERS] __rte_aligned_16;
 227
 228         /* Grinders */
 229         struct rte_sched_grinder grinder[RTE_SCHED_PORT_N_GRINDERS];
 230         uint32_t busy_grinders;
 231         struct rte_mbuf **pkts_out;
 232         uint32_t n_pkts_out;
 233
 234         /* Queue base calculation */
 235         uint32_t qsize_add[RTE_SCHED_QUEUES_PER_PIPE];
 236         uint32_t qsize_sum;
 237
 238         /* Large data structures */
 239         struct rte_sched_subport *subport;
 240         struct rte_sched_pipe *pipe;
 241         struct rte_sched_queue *queue;
 242         struct rte_sched_queue_extra *queue_extra;
 243         struct rte_sched_pipe_profile *pipe_profiles;
 244         uint8_t *bmp_array;
 245         struct rte_mbuf **queue_array;
 246         uint8_t memory[0] __rte_cache_aligned;
 247 } __rte_cache_aligned;
 248
 249 enum rte_sched_port_array {
 250         e_RTE_SCHED_PORT_ARRAY_SUBPORT = 0,
 251         e_RTE_SCHED_PORT_ARRAY_PIPE,
 252         e_RTE_SCHED_PORT_ARRAY_QUEUE,
 253         e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA,
 254         e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES,
 255         e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY,
 256         e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY,
 257         e_RTE_SCHED_PORT_ARRAY_TOTAL,
 258 };
 259
 260 #ifdef RTE_SCHED_COLLECT_STATS
 261
 262 static inline uint32_t
 263 rte_sched_port_queues_per_subport(struct rte_sched_port *port)
 264 {
 265         return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport;
 266 }
 267
 268 #endif
 269
 270 static inline uint32_t
 271 rte_sched_port_queues_per_port(struct rte_sched_port *port)
 272 {
 273         return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport * port->n_subports_per_port;
 274 }
 275
 276 static inline struct rte_mbuf **
 277 rte_sched_port_qbase(struct rte_sched_port *port, uint32_t qindex)
 278 {
 279         uint32_t pindex = qindex >> 4;
 280         uint32_t qpos = qindex & 0xF;
 281
 282         return (port->queue_array + pindex *
 283                 port->qsize_sum + port->qsize_add[qpos]);
 284 }
 285
 286 static inline uint16_t
 287 rte_sched_port_qsize(struct rte_sched_port *port, uint32_t qindex)
 288 {
 289         uint32_t tc = (qindex >> 2) & 0x3;
 290
 291         return port->qsize[tc];
 292 }
 293
 294 static int
 295 rte_sched_port_check_params(struct rte_sched_port_params *params)
 296 {
 297         uint32_t i, j;
 298
 299         if (params == NULL)
 300                 return -1;
 301
 302         /* socket */
 303         if ((params->socket < 0) || (params->socket >= RTE_MAX_NUMA_NODES))
 304                 return -3;
 305
 306         /* rate */
 307         if (params->rate == 0)
 308                 return -4;
 309
 310         /* mtu */
 311         if (params->mtu == 0)
 312                 return -5;
 313
 314         /* n_subports_per_port: non-zero, limited to 16 bits, power of 2 */
 315         if (params->n_subports_per_port == 0 ||
 316             params->n_subports_per_port > 1u << 16 ||
 317             !rte_is_power_of_2(params->n_subports_per_port))
 318                 return -6;
 319
 320         /* n_pipes_per_subport: non-zero, power of 2 */
 321         if (params->n_pipes_per_subport == 0 ||
 322             !rte_is_power_of_2(params->n_pipes_per_subport))
 323                 return -7;
 324
 325         /* qsize: non-zero, power of 2,
 326          * no bigger than 32K (due to 16-bit read/write pointers)
 327          */
 328         for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
 329                 uint16_t qsize = params->qsize[i];
 330
 331                 if (qsize == 0 || !rte_is_power_of_2(qsize))
 332                         return -8;
 333         }
 334
 335         /* pipe_profiles and n_pipe_profiles */
 336         if (params->pipe_profiles == NULL ||
 337             params->n_pipe_profiles == 0 ||
 338             params->n_pipe_profiles > RTE_SCHED_PIPE_PROFILES_PER_PORT)
 339                 return -9;
 340
 341         for (i = 0; i < params->n_pipe_profiles; i++) {
 342                 struct rte_sched_pipe_params *p = params->pipe_profiles + i;
 343
 344                 /* TB rate: non-zero, not greater than port rate */
 345                 if (p->tb_rate == 0 || p->tb_rate > params->rate)
 346                         return -10;
 347
 348                 /* TB size: non-zero */
 349                 if (p->tb_size == 0)
 350                         return -11;
 351
 352                 /* TC rate: non-zero, less than pipe rate */
 353                 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
 354                         if (p->tc_rate[j] == 0 || p->tc_rate[j] > p->tb_rate)
 355                                 return -12;
 356                 }
 357
 358                 /* TC period: non-zero */
 359                 if (p->tc_period == 0)
 360                         return -13;
 361
 362 #ifdef RTE_SCHED_SUBPORT_TC_OV
 363                 /* TC3 oversubscription weight: non-zero */
 364                 if (p->tc_ov_weight == 0)
 365                         return -14;
 366 #endif
 367
 368                 /* Queue WRR weights: non-zero */
 369                 for (j = 0; j < RTE_SCHED_QUEUES_PER_PIPE; j++) {
 370                         if (p->wrr_weights[j] == 0)
 371                                 return -15;
 372                 }
 373         }
 374
 375         return 0;
 376 }
 377
 378 static uint32_t
 379 rte_sched_port_get_array_base(struct rte_sched_port_params *params, enum rte_sched_port_array array)
 380 {
 381         uint32_t n_subports_per_port = params->n_subports_per_port;
 382         uint32_t n_pipes_per_subport = params->n_pipes_per_subport;
 383         uint32_t n_pipes_per_port = n_pipes_per_subport * n_subports_per_port;
 384         uint32_t n_queues_per_port = RTE_SCHED_QUEUES_PER_PIPE * n_pipes_per_subport * n_subports_per_port;
 385
 386         uint32_t size_subport = n_subports_per_port * sizeof(struct rte_sched_subport);
 387         uint32_t size_pipe = n_pipes_per_port * sizeof(struct rte_sched_pipe);
 388         uint32_t size_queue = n_queues_per_port * sizeof(struct rte_sched_queue);
 389         uint32_t size_queue_extra
 390                 = n_queues_per_port * sizeof(struct rte_sched_queue_extra);
 391         uint32_t size_pipe_profiles
 392                 = RTE_SCHED_PIPE_PROFILES_PER_PORT * sizeof(struct rte_sched_pipe_profile);
 393         uint32_t size_bmp_array = rte_bitmap_get_memory_footprint(n_queues_per_port);
 394         uint32_t size_per_pipe_queue_array, size_queue_array;
 395
 396         uint32_t base, i;
 397
 398         size_per_pipe_queue_array = 0;
 399         for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
 400                 size_per_pipe_queue_array += RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS
 401                         * params->qsize[i] * sizeof(struct rte_mbuf *);
 402         }
 403         size_queue_array = n_pipes_per_port * size_per_pipe_queue_array;
 404
 405         base = 0;
 406
 407         if (array == e_RTE_SCHED_PORT_ARRAY_SUBPORT)
 408                 return base;
 409         base += RTE_CACHE_LINE_ROUNDUP(size_subport);
 410
 411         if (array == e_RTE_SCHED_PORT_ARRAY_PIPE)
 412                 return base;
 413         base += RTE_CACHE_LINE_ROUNDUP(size_pipe);
 414
 415         if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE)
 416                 return base;
 417         base += RTE_CACHE_LINE_ROUNDUP(size_queue);
 418
 419         if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA)
 420                 return base;
 421         base += RTE_CACHE_LINE_ROUNDUP(size_queue_extra);
 422
 423         if (array == e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES)
 424                 return base;
 425         base += RTE_CACHE_LINE_ROUNDUP(size_pipe_profiles);
 426
 427         if (array == e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY)
 428                 return base;
 429         base += RTE_CACHE_LINE_ROUNDUP(size_bmp_array);
 430
 431         if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY)
 432                 return base;
 433         base += RTE_CACHE_LINE_ROUNDUP(size_queue_array);
 434
 435         return base;
 436 }
 437
 438 uint32_t
 439 rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)
 440 {
 441         uint32_t size0, size1;
 442         int status;
 443
 444         status = rte_sched_port_check_params(params);
 445         if (status != 0) {
 446                 RTE_LOG(NOTICE, SCHED,
 447                         "Port scheduler params check failed (%d)\n", status);
 448
 449                 return 0;
 450         }
 451
 452         size0 = sizeof(struct rte_sched_port);
 453         size1 = rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_TOTAL);
 454
 455         return (size0 + size1);
 456 }
 457
 458 static void
 459 rte_sched_port_config_qsize(struct rte_sched_port *port)
 460 {
 461         /* TC 0 */
 462         port->qsize_add[0] = 0;
 463         port->qsize_add[1] = port->qsize_add[0] + port->qsize[0];
 464         port->qsize_add[2] = port->qsize_add[1] + port->qsize[0];
 465         port->qsize_add[3] = port->qsize_add[2] + port->qsize[0];
 466
 467         /* TC 1 */
 468         port->qsize_add[4] = port->qsize_add[3] + port->qsize[0];
 469         port->qsize_add[5] = port->qsize_add[4] + port->qsize[1];
 470         port->qsize_add[6] = port->qsize_add[5] + port->qsize[1];
 471         port->qsize_add[7] = port->qsize_add[6] + port->qsize[1];
 472
 473         /* TC 2 */
 474         port->qsize_add[8] = port->qsize_add[7] + port->qsize[1];
 475         port->qsize_add[9] = port->qsize_add[8] + port->qsize[2];
 476         port->qsize_add[10] = port->qsize_add[9] + port->qsize[2];
 477         port->qsize_add[11] = port->qsize_add[10] + port->qsize[2];
 478
 479         /* TC 3 */
 480         port->qsize_add[12] = port->qsize_add[11] + port->qsize[2];
 481         port->qsize_add[13] = port->qsize_add[12] + port->qsize[3];
 482         port->qsize_add[14] = port->qsize_add[13] + port->qsize[3];
 483         port->qsize_add[15] = port->qsize_add[14] + port->qsize[3];
 484
 485         port->qsize_sum = port->qsize_add[15] + port->qsize[3];
 486 }
 487
 488 static void
 489 rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)
 490 {
 491         struct rte_sched_pipe_profile *p = port->pipe_profiles + i;
 492
 493         RTE_LOG(DEBUG, SCHED, "Low level config for pipe profile %u:\n"
 494                 "    Token bucket: period = %u, credits per period = %u, size = %u\n"
 495                 "    Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\n"
 496                 "    Traffic class 3 oversubscription: weight = %hhu\n"
 497                 "    WRR cost: [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu]\n",
 498                 i,
 499
 500                 /* Token bucket */
 501                 p->tb_period,
 502                 p->tb_credits_per_period,
 503                 p->tb_size,
 504
 505                 /* Traffic classes */
 506                 p->tc_period,
 507                 p->tc_credits_per_period[0],
 508                 p->tc_credits_per_period[1],
 509                 p->tc_credits_per_period[2],
 510                 p->tc_credits_per_period[3],
 511
 512                 /* Traffic class 3 oversubscription */
 513                 p->tc_ov_weight,
 514
 515                 /* WRR */
 516                 p->wrr_cost[ 0], p->wrr_cost[ 1], p->wrr_cost[ 2], p->wrr_cost[ 3],
 517                 p->wrr_cost[ 4], p->wrr_cost[ 5], p->wrr_cost[ 6], p->wrr_cost[ 7],
 518                 p->wrr_cost[ 8], p->wrr_cost[ 9], p->wrr_cost[10], p->wrr_cost[11],
 519                 p->wrr_cost[12], p->wrr_cost[13], p->wrr_cost[14], p->wrr_cost[15]);
 520 }
 521
 522 static inline uint64_t
 523 rte_sched_time_ms_to_bytes(uint32_t time_ms, uint32_t rate)
 524 {
 525         uint64_t time = time_ms;
 526
 527         time = (time * rate) / 1000;
 528
 529         return time;
 530 }
 531
 532 static void
 533 rte_sched_port_config_pipe_profile_table(struct rte_sched_port *port, struct rte_sched_port_params *params)
 534 {
 535         uint32_t i, j;
 536
 537         for (i = 0; i < port->n_pipe_profiles; i++) {
 538                 struct rte_sched_pipe_params *src = params->pipe_profiles + i;
 539                 struct rte_sched_pipe_profile *dst = port->pipe_profiles + i;
 540
 541                 /* Token Bucket */
 542                 if (src->tb_rate == params->rate) {
 543                         dst->tb_credits_per_period = 1;
 544                         dst->tb_period = 1;
 545                 } else {
 546                         double tb_rate = (double) src->tb_rate
 547                                 / (double) params->rate;
 548                         double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
 549
 550                         rte_approx(tb_rate, d,
 551                                    &dst->tb_credits_per_period, &dst->tb_period);
 552                 }
 553                 dst->tb_size = src->tb_size;
 554
 555                 /* Traffic Classes */
 556                 dst->tc_period = rte_sched_time_ms_to_bytes(src->tc_period,
 557                                                             params->rate);
 558
 559                 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++)
 560                         dst->tc_credits_per_period[j]
 561                                 = rte_sched_time_ms_to_bytes(src->tc_period,
 562                                                              src->tc_rate[j]);
 563
 564 #ifdef RTE_SCHED_SUBPORT_TC_OV
 565                 dst->tc_ov_weight = src->tc_ov_weight;
 566 #endif
 567
 568                 /* WRR */
 569                 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
 570                         uint32_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
 571                         uint32_t lcd, lcd1, lcd2;
 572                         uint32_t qindex;
 573
 574                         qindex = j * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS;
 575
 576                         wrr_cost[0] = src->wrr_weights[qindex];
 577                         wrr_cost[1] = src->wrr_weights[qindex + 1];
 578                         wrr_cost[2] = src->wrr_weights[qindex + 2];
 579                         wrr_cost[3] = src->wrr_weights[qindex + 3];
 580
 581                         lcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]);
 582                         lcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]);
 583                         lcd = rte_get_lcd(lcd1, lcd2);
 584
 585                         wrr_cost[0] = lcd / wrr_cost[0];
 586                         wrr_cost[1] = lcd / wrr_cost[1];
 587                         wrr_cost[2] = lcd / wrr_cost[2];
 588                         wrr_cost[3] = lcd / wrr_cost[3];
 589
 590                         dst->wrr_cost[qindex] = (uint8_t) wrr_cost[0];
 591                         dst->wrr_cost[qindex + 1] = (uint8_t) wrr_cost[1];
 592                         dst->wrr_cost[qindex + 2] = (uint8_t) wrr_cost[2];
 593                         dst->wrr_cost[qindex + 3] = (uint8_t) wrr_cost[3];
 594                 }
 595
 596                 rte_sched_port_log_pipe_profile(port, i);
 597         }
 598
 599         port->pipe_tc3_rate_max = 0;
 600         for (i = 0; i < port->n_pipe_profiles; i++) {
 601                 struct rte_sched_pipe_params *src = params->pipe_profiles + i;
 602                 uint32_t pipe_tc3_rate = src->tc_rate[3];
 603
 604                 if (port->pipe_tc3_rate_max < pipe_tc3_rate)
 605                         port->pipe_tc3_rate_max = pipe_tc3_rate;
 606         }
 607 }
 608
 609 struct rte_sched_port *
 610 rte_sched_port_config(struct rte_sched_port_params *params)
 611 {
 612         struct rte_sched_port *port = NULL;
 613         uint32_t mem_size, bmp_mem_size, n_queues_per_port, i;
 614
 615         /* Check user parameters. Determine the amount of memory to allocate */
 616         mem_size = rte_sched_port_get_memory_footprint(params);
 617         if (mem_size == 0)
 618                 return NULL;
 619
 620         /* Allocate memory to store the data structures */
 621         port = rte_zmalloc("qos_params", mem_size, RTE_CACHE_LINE_SIZE);
 622         if (port == NULL)
 623                 return NULL;
 624
 625         /* compile time checks */
 626         RTE_BUILD_BUG_ON(RTE_SCHED_PORT_N_GRINDERS == 0);
 627         RTE_BUILD_BUG_ON(RTE_SCHED_PORT_N_GRINDERS & (RTE_SCHED_PORT_N_GRINDERS - 1));
 628
 629         /* User parameters */
 630         port->n_subports_per_port = params->n_subports_per_port;
 631         port->n_pipes_per_subport = params->n_pipes_per_subport;
 632         port->rate = params->rate;
 633         port->mtu = params->mtu + params->frame_overhead;
 634         port->frame_overhead = params->frame_overhead;
 635         memcpy(port->qsize, params->qsize, sizeof(params->qsize));
 636         port->n_pipe_profiles = params->n_pipe_profiles;
 637
 638 #ifdef RTE_SCHED_RED
 639         for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
 640                 uint32_t j;
 641
 642                 for (j = 0; j < e_RTE_METER_COLORS; j++) {
 643                         /* if min/max are both zero, then RED is disabled */
 644                         if ((params->red_params[i][j].min_th |
 645                              params->red_params[i][j].max_th) == 0) {
 646                                 continue;
 647                         }
 648
 649                         if (rte_red_config_init(&port->red_config[i][j],
 650                                 params->red_params[i][j].wq_log2,
 651                                 params->red_params[i][j].min_th,
 652                                 params->red_params[i][j].max_th,
 653                                 params->red_params[i][j].maxp_inv) != 0) {
 654                                 return NULL;
 655                         }
 656                 }
 657         }
 658 #endif
 659
 660         /* Timing */
 661         port->time_cpu_cycles = rte_get_tsc_cycles();
 662         port->time_cpu_bytes = 0;
 663         port->time = 0;
 664         port->cycles_per_byte = ((double) rte_get_tsc_hz()) / ((double) params->rate);
 665
 666         /* Scheduling loop detection */
 667         port->pipe_loop = RTE_SCHED_PIPE_INVALID;
 668         port->pipe_exhaustion = 0;
 669
 670         /* Grinders */
 671         port->busy_grinders = 0;
 672         port->pkts_out = NULL;
 673         port->n_pkts_out = 0;
 674
 675         /* Queue base calculation */
 676         rte_sched_port_config_qsize(port);
 677
 678         /* Large data structures */
 679         port->subport = (struct rte_sched_subport *)
 680                 (port->memory + rte_sched_port_get_array_base(params,
 681                                                               e_RTE_SCHED_PORT_ARRAY_SUBPORT));
 682         port->pipe = (struct rte_sched_pipe *)
 683                 (port->memory + rte_sched_port_get_array_base(params,
 684                                                               e_RTE_SCHED_PORT_ARRAY_PIPE));
 685         port->queue = (struct rte_sched_queue *)
 686                 (port->memory + rte_sched_port_get_array_base(params,
 687                                                               e_RTE_SCHED_PORT_ARRAY_QUEUE));
 688         port->queue_extra = (struct rte_sched_queue_extra *)
 689                 (port->memory + rte_sched_port_get_array_base(params,
 690                                                               e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA));
 691         port->pipe_profiles = (struct rte_sched_pipe_profile *)
 692                 (port->memory + rte_sched_port_get_array_base(params,
 693                                                               e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES));
 694         port->bmp_array =  port->memory
 695                 + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY);
 696         port->queue_array = (struct rte_mbuf **)
 697                 (port->memory + rte_sched_port_get_array_base(params,
 698                                                               e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY));
 699
 700         /* Pipe profile table */
 701         rte_sched_port_config_pipe_profile_table(port, params);
 702
 703         /* Bitmap */
 704         n_queues_per_port = rte_sched_port_queues_per_port(port);
 705         bmp_mem_size = rte_bitmap_get_memory_footprint(n_queues_per_port);
 706         port->bmp = rte_bitmap_init(n_queues_per_port, port->bmp_array,
 707                                     bmp_mem_size);
 708         if (port->bmp == NULL) {
 709                 RTE_LOG(ERR, SCHED, "Bitmap init error\n");
 710                 return NULL;
 711         }
 712
 713         for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i++)
 714                 port->grinder_base_bmp_pos[i] = RTE_SCHED_PIPE_INVALID;
 715
 716
 717         return port;
 718 }
 719
 720 void
 721 rte_sched_port_free(struct rte_sched_port *port)
 722 {
 723         unsigned int queue;
 724
 725         /* Check user parameters */
 726         if (port == NULL)
 727                 return;
 728
 729         /* Free enqueued mbufs */
 730         for (queue = 0; queue < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; queue++) {
 731                 struct rte_mbuf **mbufs = rte_sched_port_qbase(port, queue);
 732                 unsigned int i;
 733
 734                 for (i = 0; i < rte_sched_port_qsize(port, queue); i++)
 735                         rte_pktmbuf_free(mbufs[i]);
 736         }
 737
 738         rte_bitmap_free(port->bmp);
 739         rte_free(port);
 740 }
 741
 742 static void
 743 rte_sched_port_log_subport_config(struct rte_sched_port *port, uint32_t i)
 744 {
 745         struct rte_sched_subport *s = port->subport + i;
 746
 747         RTE_LOG(DEBUG, SCHED, "Low level config for subport %u:\n"
 748                 "    Token bucket: period = %u, credits per period = %u, size = %u\n"
 749                 "    Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\n"
 750                 "    Traffic class 3 oversubscription: wm min = %u, wm max = %u\n",
 751                 i,
 752
 753                 /* Token bucket */
 754                 s->tb_period,
 755                 s->tb_credits_per_period,
 756                 s->tb_size,
 757
 758                 /* Traffic classes */
 759                 s->tc_period,
 760                 s->tc_credits_per_period[0],
 761                 s->tc_credits_per_period[1],
 762                 s->tc_credits_per_period[2],
 763                 s->tc_credits_per_period[3],
 764
 765                 /* Traffic class 3 oversubscription */
 766                 s->tc_ov_wm_min,
 767                 s->tc_ov_wm_max);
 768 }
 769
 770 int
 771 rte_sched_subport_config(struct rte_sched_port *port,
 772         uint32_t subport_id,
 773         struct rte_sched_subport_params *params)
 774 {
 775         struct rte_sched_subport *s;
 776         uint32_t i;
 777
 778         /* Check user parameters */
 779         if (port == NULL ||
 780             subport_id >= port->n_subports_per_port ||
 781             params == NULL)
 782                 return -1;
 783
 784         if (params->tb_rate == 0 || params->tb_rate > port->rate)
 785                 return -2;
 786
 787         if (params->tb_size == 0)
 788                 return -3;
 789
 790         for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
 791                 if (params->tc_rate[i] == 0 ||
 792                     params->tc_rate[i] > params->tb_rate)
 793                         return -4;
 794         }
 795
 796         if (params->tc_period == 0)
 797                 return -5;
 798
 799         s = port->subport + subport_id;
 800
 801         /* Token Bucket (TB) */
 802         if (params->tb_rate == port->rate) {
 803                 s->tb_credits_per_period = 1;
 804                 s->tb_period = 1;
 805         } else {
 806                 double tb_rate = ((double) params->tb_rate) / ((double) port->rate);
 807                 double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
 808
 809                 rte_approx(tb_rate, d, &s->tb_credits_per_period, &s->tb_period);
 810         }
 811
 812         s->tb_size = params->tb_size;
 813         s->tb_time = port->time;
 814         s->tb_credits = s->tb_size / 2;
 815
 816         /* Traffic Classes (TCs) */
 817         s->tc_period = rte_sched_time_ms_to_bytes(params->tc_period, port->rate);
 818         for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
 819                 s->tc_credits_per_period[i]
 820                         = rte_sched_time_ms_to_bytes(params->tc_period,
 821                                                      params->tc_rate[i]);
 822         }
 823         s->tc_time = port->time + s->tc_period;
 824         for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)
 825                 s->tc_credits[i] = s->tc_credits_per_period[i];
 826
 827 #ifdef RTE_SCHED_SUBPORT_TC_OV
 828         /* TC oversubscription */
 829         s->tc_ov_wm_min = port->mtu;
 830         s->tc_ov_wm_max = rte_sched_time_ms_to_bytes(params->tc_period,
 831                                                      port->pipe_tc3_rate_max);
 832         s->tc_ov_wm = s->tc_ov_wm_max;
 833         s->tc_ov_period_id = 0;
 834         s->tc_ov = 0;
 835         s->tc_ov_n = 0;
 836         s->tc_ov_rate = 0;
 837 #endif
 838
 839         rte_sched_port_log_subport_config(port, subport_id);
 840
 841         return 0;
 842 }
 843
 844 int
 845 rte_sched_pipe_config(struct rte_sched_port *port,
 846         uint32_t subport_id,
 847         uint32_t pipe_id,
 848         int32_t pipe_profile)
 849 {
 850         struct rte_sched_subport *s;
 851         struct rte_sched_pipe *p;
 852         struct rte_sched_pipe_profile *params;
 853         uint32_t deactivate, profile, i;
 854
 855         /* Check user parameters */
 856         profile = (uint32_t) pipe_profile;
 857         deactivate = (pipe_profile < 0);
 858
 859         if (port == NULL ||
 860             subport_id >= port->n_subports_per_port ||
 861             pipe_id >= port->n_pipes_per_subport ||
 862             (!deactivate && profile >= port->n_pipe_profiles))
 863                 return -1;
 864
 865
 866         /* Check that subport configuration is valid */
 867         s = port->subport + subport_id;
 868         if (s->tb_period == 0)
 869                 return -2;
 870
 871         p = port->pipe + (subport_id * port->n_pipes_per_subport + pipe_id);
 872
 873         /* Handle the case when pipe already has a valid configuration */
 874         if (p->tb_time) {
 875                 params = port->pipe_profiles + p->profile;
 876
 877 #ifdef RTE_SCHED_SUBPORT_TC_OV
 878                 double subport_tc3_rate = (double) s->tc_credits_per_period[3]
 879                         / (double) s->tc_period;
 880                 double pipe_tc3_rate = (double) params->tc_credits_per_period[3]
 881                         / (double) params->tc_period;
 882                 uint32_t tc3_ov = s->tc_ov;
 883
 884                 /* Unplug pipe from its subport */
 885                 s->tc_ov_n -= params->tc_ov_weight;
 886                 s->tc_ov_rate -= pipe_tc3_rate;
 887                 s->tc_ov = s->tc_ov_rate > subport_tc3_rate;
 888
 889                 if (s->tc_ov != tc3_ov) {
 890                         RTE_LOG(DEBUG, SCHED,
 891                                 "Subport %u TC3 oversubscription is OFF (%.4lf >= %.4lf)\n",
 892                                 subport_id, subport_tc3_rate, s->tc_ov_rate);
 893                 }
 894 #endif
 895
 896                 /* Reset the pipe */
 897                 memset(p, 0, sizeof(struct rte_sched_pipe));
 898         }
 899
 900         if (deactivate)
 901                 return 0;
 902
 903         /* Apply the new pipe configuration */
 904         p->profile = profile;
 905         params = port->pipe_profiles + p->profile;
 906
 907         /* Token Bucket (TB) */
 908         p->tb_time = port->time;
 909         p->tb_credits = params->tb_size / 2;
 910
 911         /* Traffic Classes (TCs) */
 912         p->tc_time = port->time + params->tc_period;
 913         for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)
 914                 p->tc_credits[i] = params->tc_credits_per_period[i];
 915
 916 #ifdef RTE_SCHED_SUBPORT_TC_OV
 917         {
 918                 /* Subport TC3 oversubscription */
 919                 double subport_tc3_rate = (double) s->tc_credits_per_period[3]
 920                         / (double) s->tc_period;
 921                 double pipe_tc3_rate = (double) params->tc_credits_per_period[3]
 922                         / (double) params->tc_period;
 923                 uint32_t tc3_ov = s->tc_ov;
 924
 925                 s->tc_ov_n += params->tc_ov_weight;
 926                 s->tc_ov_rate += pipe_tc3_rate;
 927                 s->tc_ov = s->tc_ov_rate > subport_tc3_rate;
 928
 929                 if (s->tc_ov != tc3_ov) {
 930                         RTE_LOG(DEBUG, SCHED,
 931                                 "Subport %u TC3 oversubscription is ON (%.4lf < %.4lf)\n",
 932                                 subport_id, subport_tc3_rate, s->tc_ov_rate);
 933                 }
 934                 p->tc_ov_period_id = s->tc_ov_period_id;
 935                 p->tc_ov_credits = s->tc_ov_wm;
 936         }
 937 #endif
 938
 939         return 0;
 940 }
 941
 942 void
 943 rte_sched_port_pkt_write(struct rte_mbuf *pkt,
 944                          uint32_t subport, uint32_t pipe, uint32_t traffic_class,
 945                          uint32_t queue, enum rte_meter_color color)
 946 {
 947         struct rte_sched_port_hierarchy *sched
 948                 = (struct rte_sched_port_hierarchy *) &pkt->hash.sched;
 949
 950         RTE_BUILD_BUG_ON(sizeof(*sched) > sizeof(pkt->hash.sched));
 951
 952         sched->color = (uint32_t) color;
 953         sched->subport = subport;
 954         sched->pipe = pipe;
 955         sched->traffic_class = traffic_class;
 956         sched->queue = queue;
 957 }
 958
 959 void
 960 rte_sched_port_pkt_read_tree_path(const struct rte_mbuf *pkt,
 961                                   uint32_t *subport, uint32_t *pipe,
 962                                   uint32_t *traffic_class, uint32_t *queue)
 963 {
 964         const struct rte_sched_port_hierarchy *sched
 965                 = (const struct rte_sched_port_hierarchy *) &pkt->hash.sched;
 966
 967         *subport = sched->subport;
 968         *pipe = sched->pipe;
 969         *traffic_class = sched->traffic_class;
 970         *queue = sched->queue;
 971 }
 972
 973 enum rte_meter_color
 974 rte_sched_port_pkt_read_color(const struct rte_mbuf *pkt)
 975 {
 976         const struct rte_sched_port_hierarchy *sched
 977                 = (const struct rte_sched_port_hierarchy *) &pkt->hash.sched;
 978
 979         return (enum rte_meter_color) sched->color;
 980 }
 981
 982 int
 983 rte_sched_subport_read_stats(struct rte_sched_port *port,
 984                              uint32_t subport_id,
 985                              struct rte_sched_subport_stats *stats,
 986                              uint32_t *tc_ov)
 987 {
 988         struct rte_sched_subport *s;
 989
 990         /* Check user parameters */
 991         if (port == NULL || subport_id >= port->n_subports_per_port ||
 992             stats == NULL || tc_ov == NULL)
 993                 return -1;
 994
 995         s = port->subport + subport_id;
 996
 997         /* Copy subport stats and clear */
 998         memcpy(stats, &s->stats, sizeof(struct rte_sched_subport_stats));
 999         memset(&s->stats, 0, sizeof(struct rte_sched_subport_stats));
1000
1001         /* Subport TC ovesubscription status */
1002         *tc_ov = s->tc_ov;
1003
1004         return 0;
1005 }
1006
1007 int
1008 rte_sched_queue_read_stats(struct rte_sched_port *port,
1009         uint32_t queue_id,
1010         struct rte_sched_queue_stats *stats,
1011         uint16_t *qlen)
1012 {
1013         struct rte_sched_queue *q;
1014         struct rte_sched_queue_extra *qe;
1015
1016         /* Check user parameters */
1017         if ((port == NULL) ||
1018             (queue_id >= rte_sched_port_queues_per_port(port)) ||
1019                 (stats == NULL) ||
1020                 (qlen == NULL)) {
1021                 return -1;
1022         }
1023         q = port->queue + queue_id;
1024         qe = port->queue_extra + queue_id;
1025
1026         /* Copy queue stats and clear */
1027         memcpy(stats, &qe->stats, sizeof(struct rte_sched_queue_stats));
1028         memset(&qe->stats, 0, sizeof(struct rte_sched_queue_stats));
1029
1030         /* Queue length */
1031         *qlen = q->qw - q->qr;
1032
1033         return 0;
1034 }
1035
1036 static inline uint32_t
1037 rte_sched_port_qindex(struct rte_sched_port *port, uint32_t subport, uint32_t pipe, uint32_t traffic_class, uint32_t queue)
1038 {
1039         uint32_t result;
1040
1041         result = subport * port->n_pipes_per_subport + pipe;
1042         result = result * RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE + traffic_class;
1043         result = result * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS + queue;
1044
1045         return result;
1046 }
1047
1048 #ifdef RTE_SCHED_DEBUG
1049
1050 static inline int
1051 rte_sched_port_queue_is_empty(struct rte_sched_port *port, uint32_t qindex)
1052 {
1053         struct rte_sched_queue *queue = port->queue + qindex;
1054
1055         return (queue->qr == queue->qw);
1056 }
1057
1058 static inline int
1059 rte_sched_port_queue_is_full(struct rte_sched_port *port, uint32_t qindex)
1060 {
1061         struct rte_sched_queue *queue = port->queue + qindex;
1062         uint16_t qsize = rte_sched_port_qsize(port, qindex);
1063         uint16_t qlen = queue->qw - queue->qr;
1064
1065         return (qlen >= qsize);
1066 }
1067
1068 #endif /* RTE_SCHED_DEBUG */
1069
1070 #ifdef RTE_SCHED_COLLECT_STATS
1071
1072 static inline void
1073 rte_sched_port_update_subport_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1074 {
1075         struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1076         uint32_t tc_index = (qindex >> 2) & 0x3;
1077         uint32_t pkt_len = pkt->pkt_len;
1078
1079         s->stats.n_pkts_tc[tc_index] += 1;
1080         s->stats.n_bytes_tc[tc_index] += pkt_len;
1081 }
1082
1083 static inline void
1084 rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1085 {
1086         struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1087         uint32_t tc_index = (qindex >> 2) & 0x3;
1088         uint32_t pkt_len = pkt->pkt_len;
1089
1090         s->stats.n_pkts_tc_dropped[tc_index] += 1;
1091         s->stats.n_bytes_tc_dropped[tc_index] += pkt_len;
1092 }
1093
1094 static inline void
1095 rte_sched_port_update_queue_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1096 {
1097         struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1098         uint32_t pkt_len = pkt->pkt_len;
1099
1100         qe->stats.n_pkts += 1;
1101         qe->stats.n_bytes += pkt_len;
1102 }
1103
1104 static inline void
1105 rte_sched_port_update_queue_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1106 {
1107         struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1108         uint32_t pkt_len = pkt->pkt_len;
1109
1110         qe->stats.n_pkts_dropped += 1;
1111         qe->stats.n_bytes_dropped += pkt_len;
1112 }
1113
1114 #endif /* RTE_SCHED_COLLECT_STATS */
1115
1116 #ifdef RTE_SCHED_RED
1117
1118 static inline int
1119 rte_sched_port_red_drop(struct rte_sched_port *port, struct rte_mbuf *pkt, uint32_t qindex, uint16_t qlen)
1120 {
1121         struct rte_sched_queue_extra *qe;
1122         struct rte_red_config *red_cfg;
1123         struct rte_red *red;
1124         uint32_t tc_index;
1125         enum rte_meter_color color;
1126
1127         tc_index = (qindex >> 2) & 0x3;
1128         color = rte_sched_port_pkt_read_color(pkt);
1129         red_cfg = &port->red_config[tc_index][color];
1130
1131         if ((red_cfg->min_th | red_cfg->max_th) == 0)
1132                 return 0;
1133
1134         qe = port->queue_extra + qindex;
1135         red = &qe->red;
1136
1137         return rte_red_enqueue(red_cfg, red, qlen, port->time);
1138 }
1139
1140 static inline void
1141 rte_sched_port_set_queue_empty_timestamp(struct rte_sched_port *port, uint32_t qindex)
1142 {
1143         struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1144         struct rte_red *red = &qe->red;
1145
1146         rte_red_mark_queue_empty(red, port->time);
1147 }
1148
1149 #else
1150
1151 #define rte_sched_port_red_drop(port, pkt, qindex, qlen)             0
1152
1153 #define rte_sched_port_set_queue_empty_timestamp(port, qindex)
1154
1155 #endif /* RTE_SCHED_RED */
1156
1157 #ifdef RTE_SCHED_DEBUG
1158
1159 static inline int
1160 debug_pipe_is_empty(struct rte_sched_port *port, uint32_t pindex)
1161 {
1162         uint32_t qindex, i;
1163
1164         qindex = pindex << 4;
1165
1166         for (i = 0; i < 16; i++) {
1167                 uint32_t queue_empty = rte_sched_port_queue_is_empty(port, qindex + i);
1168                 uint32_t bmp_bit_clear = (rte_bitmap_get(port->bmp, qindex + i) == 0);
1169
1170                 if (queue_empty != bmp_bit_clear)
1171                         rte_panic("Queue status mismatch for queue %u of pipe %u\n", i, pindex);
1172
1173                 if (!queue_empty)
1174                         return 0;
1175         }
1176
1177         return 1;
1178 }
1179
1180 static inline void
1181 debug_check_queue_slab(struct rte_sched_port *port, uint32_t bmp_pos,
1182                        uint64_t bmp_slab)
1183 {
1184         uint64_t mask;
1185         uint32_t i, panic;
1186
1187         if (bmp_slab == 0)
1188                 rte_panic("Empty slab at position %u\n", bmp_pos);
1189
1190         panic = 0;
1191         for (i = 0, mask = 1; i < 64; i++, mask <<= 1) {
1192                 if (mask & bmp_slab) {
1193                         if (rte_sched_port_queue_is_empty(port, bmp_pos + i)) {
1194                                 printf("Queue %u (slab offset %u) is empty\n", bmp_pos + i, i);
1195                                 panic = 1;
1196                         }
1197                 }
1198         }
1199
1200         if (panic)
1201                 rte_panic("Empty queues in slab 0x%" PRIx64 "starting at position %u\n",
1202                         bmp_slab, bmp_pos);
1203 }
1204
1205 #endif /* RTE_SCHED_DEBUG */
1206
1207 static inline uint32_t
1208 rte_sched_port_enqueue_qptrs_prefetch0(struct rte_sched_port *port,
1209                                        struct rte_mbuf *pkt)
1210 {
1211         struct rte_sched_queue *q;
1212 #ifdef RTE_SCHED_COLLECT_STATS
1213         struct rte_sched_queue_extra *qe;
1214 #endif
1215         uint32_t subport, pipe, traffic_class, queue, qindex;
1216
1217         rte_sched_port_pkt_read_tree_path(pkt, &subport, &pipe, &traffic_class, &queue);
1218
1219         qindex = rte_sched_port_qindex(port, subport, pipe, traffic_class, queue);
1220         q = port->queue + qindex;
1221         rte_prefetch0(q);
1222 #ifdef RTE_SCHED_COLLECT_STATS
1223         qe = port->queue_extra + qindex;
1224         rte_prefetch0(qe);
1225 #endif
1226
1227         return qindex;
1228 }
1229
1230 static inline void
1231 rte_sched_port_enqueue_qwa_prefetch0(struct rte_sched_port *port,
1232                                      uint32_t qindex, struct rte_mbuf **qbase)
1233 {
1234         struct rte_sched_queue *q;
1235         struct rte_mbuf **q_qw;
1236         uint16_t qsize;
1237
1238         q = port->queue + qindex;
1239         qsize = rte_sched_port_qsize(port, qindex);
1240         q_qw = qbase + (q->qw & (qsize - 1));
1241
1242         rte_prefetch0(q_qw);
1243         rte_bitmap_prefetch0(port->bmp, qindex);
1244 }
1245
1246 static inline int
1247 rte_sched_port_enqueue_qwa(struct rte_sched_port *port, uint32_t qindex,
1248                            struct rte_mbuf **qbase, struct rte_mbuf *pkt)
1249 {
1250         struct rte_sched_queue *q;
1251         uint16_t qsize;
1252         uint16_t qlen;
1253
1254         q = port->queue + qindex;
1255         qsize = rte_sched_port_qsize(port, qindex);
1256         qlen = q->qw - q->qr;
1257
1258         /* Drop the packet (and update drop stats) when queue is full */
1259         if (unlikely(rte_sched_port_red_drop(port, pkt, qindex, qlen) ||
1260                      (qlen >= qsize))) {
1261                 rte_pktmbuf_free(pkt);
1262 #ifdef RTE_SCHED_COLLECT_STATS
1263                 rte_sched_port_update_subport_stats_on_drop(port, qindex, pkt);
1264                 rte_sched_port_update_queue_stats_on_drop(port, qindex, pkt);
1265 #endif
1266                 return 0;
1267         }
1268
1269         /* Enqueue packet */
1270         qbase[q->qw & (qsize - 1)] = pkt;
1271         q->qw++;
1272
1273         /* Activate queue in the port bitmap */
1274         rte_bitmap_set(port->bmp, qindex);
1275
1276         /* Statistics */
1277 #ifdef RTE_SCHED_COLLECT_STATS
1278         rte_sched_port_update_subport_stats(port, qindex, pkt);
1279         rte_sched_port_update_queue_stats(port, qindex, pkt);
1280 #endif
1281
1282         return 1;
1283 }
1284
1285
1286 /*
1287  * The enqueue function implements a 4-level pipeline with each stage
1288  * processing two different packets. The purpose of using a pipeline
1289  * is to hide the latency of prefetching the data structures. The
1290  * naming convention is presented in the diagram below:
1291  *
1292  *   p00  _______   p10  _______   p20  _______   p30  _______
1293  * ----->|       |----->|       |----->|       |----->|       |----->
1294  *       |   0   |      |   1   |      |   2   |      |   3   |
1295  * ----->|_______|----->|_______|----->|_______|----->|_______|----->
1296  *   p01            p11            p21            p31
1297  *
1298  */
1299 int
1300 rte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts,
1301                        uint32_t n_pkts)
1302 {
1303         struct rte_mbuf *pkt00, *pkt01, *pkt10, *pkt11, *pkt20, *pkt21,
1304                 *pkt30, *pkt31, *pkt_last;
1305         struct rte_mbuf **q00_base, **q01_base, **q10_base, **q11_base,
1306                 **q20_base, **q21_base, **q30_base, **q31_base, **q_last_base;
1307         uint32_t q00, q01, q10, q11, q20, q21, q30, q31, q_last;
1308         uint32_t r00, r01, r10, r11, r20, r21, r30, r31, r_last;
1309         uint32_t result, i;
1310
1311         result = 0;
1312
1313         /*
1314          * Less then 6 input packets available, which is not enough to
1315          * feed the pipeline
1316          */
1317         if (unlikely(n_pkts < 6)) {
1318                 struct rte_mbuf **q_base[5];
1319                 uint32_t q[5];
1320
1321                 /* Prefetch the mbuf structure of each packet */
1322                 for (i = 0; i < n_pkts; i++)
1323                         rte_prefetch0(pkts[i]);
1324
1325                 /* Prefetch the queue structure for each queue */
1326                 for (i = 0; i < n_pkts; i++)
1327                         q[i] = rte_sched_port_enqueue_qptrs_prefetch0(port,
1328                                                                       pkts[i]);
1329
1330                 /* Prefetch the write pointer location of each queue */
1331                 for (i = 0; i < n_pkts; i++) {
1332                         q_base[i] = rte_sched_port_qbase(port, q[i]);
1333                         rte_sched_port_enqueue_qwa_prefetch0(port, q[i],
1334                                                              q_base[i]);
1335                 }
1336
1337                 /* Write each packet to its queue */
1338                 for (i = 0; i < n_pkts; i++)
1339                         result += rte_sched_port_enqueue_qwa(port, q[i],
1340                                                              q_base[i], pkts[i]);
1341
1342                 return result;
1343         }
1344
1345         /* Feed the first 3 stages of the pipeline (6 packets needed) */
1346         pkt20 = pkts[0];
1347         pkt21 = pkts[1];
1348         rte_prefetch0(pkt20);
1349         rte_prefetch0(pkt21);
1350
1351         pkt10 = pkts[2];
1352         pkt11 = pkts[3];
1353         rte_prefetch0(pkt10);
1354         rte_prefetch0(pkt11);
1355
1356         q20 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt20);
1357         q21 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt21);
1358
1359         pkt00 = pkts[4];
1360         pkt01 = pkts[5];
1361         rte_prefetch0(pkt00);
1362         rte_prefetch0(pkt01);
1363
1364         q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1365         q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1366
1367         q20_base = rte_sched_port_qbase(port, q20);
1368         q21_base = rte_sched_port_qbase(port, q21);
1369         rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1370         rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1371
1372         /* Run the pipeline */
1373         for (i = 6; i < (n_pkts & (~1)); i += 2) {
1374                 /* Propagate stage inputs */
1375                 pkt30 = pkt20;
1376                 pkt31 = pkt21;
1377                 pkt20 = pkt10;
1378                 pkt21 = pkt11;
1379                 pkt10 = pkt00;
1380                 pkt11 = pkt01;
1381                 q30 = q20;
1382                 q31 = q21;
1383                 q20 = q10;
1384                 q21 = q11;
1385                 q30_base = q20_base;
1386                 q31_base = q21_base;
1387
1388                 /* Stage 0: Get packets in */
1389                 pkt00 = pkts[i];
1390                 pkt01 = pkts[i + 1];
1391                 rte_prefetch0(pkt00);
1392                 rte_prefetch0(pkt01);
1393
1394                 /* Stage 1: Prefetch queue structure storing queue pointers */
1395                 q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1396                 q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1397
1398                 /* Stage 2: Prefetch queue write location */
1399                 q20_base = rte_sched_port_qbase(port, q20);
1400                 q21_base = rte_sched_port_qbase(port, q21);
1401                 rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1402                 rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1403
1404                 /* Stage 3: Write packet to queue and activate queue */
1405                 r30 = rte_sched_port_enqueue_qwa(port, q30, q30_base, pkt30);
1406                 r31 = rte_sched_port_enqueue_qwa(port, q31, q31_base, pkt31);
1407                 result += r30 + r31;
1408         }
1409
1410         /*
1411          * Drain the pipeline (exactly 6 packets).
1412          * Handle the last packet in the case
1413          * of an odd number of input packets.
1414          */
1415         pkt_last = pkts[n_pkts - 1];
1416         rte_prefetch0(pkt_last);
1417
1418         q00 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt00);
1419         q01 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt01);
1420
1421         q10_base = rte_sched_port_qbase(port, q10);
1422         q11_base = rte_sched_port_qbase(port, q11);
1423         rte_sched_port_enqueue_qwa_prefetch0(port, q10, q10_base);
1424         rte_sched_port_enqueue_qwa_prefetch0(port, q11, q11_base);
1425
1426         r20 = rte_sched_port_enqueue_qwa(port, q20, q20_base, pkt20);
1427         r21 = rte_sched_port_enqueue_qwa(port, q21, q21_base, pkt21);
1428         result += r20 + r21;
1429
1430         q_last = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt_last);
1431
1432         q00_base = rte_sched_port_qbase(port, q00);
1433         q01_base = rte_sched_port_qbase(port, q01);
1434         rte_sched_port_enqueue_qwa_prefetch0(port, q00, q00_base);
1435         rte_sched_port_enqueue_qwa_prefetch0(port, q01, q01_base);
1436
1437         r10 = rte_sched_port_enqueue_qwa(port, q10, q10_base, pkt10);
1438         r11 = rte_sched_port_enqueue_qwa(port, q11, q11_base, pkt11);
1439         result += r10 + r11;
1440
1441         q_last_base = rte_sched_port_qbase(port, q_last);
1442         rte_sched_port_enqueue_qwa_prefetch0(port, q_last, q_last_base);
1443
1444         r00 = rte_sched_port_enqueue_qwa(port, q00, q00_base, pkt00);
1445         r01 = rte_sched_port_enqueue_qwa(port, q01, q01_base, pkt01);
1446         result += r00 + r01;
1447
1448         if (n_pkts & 1) {
1449                 r_last = rte_sched_port_enqueue_qwa(port, q_last, q_last_base, pkt_last);
1450                 result += r_last;
1451         }
1452
1453         return result;
1454 }
1455
1456 #ifndef RTE_SCHED_SUBPORT_TC_OV
1457
1458 static inline void
1459 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1460 {
1461         struct rte_sched_grinder *grinder = port->grinder + pos;
1462         struct rte_sched_subport *subport = grinder->subport;
1463         struct rte_sched_pipe *pipe = grinder->pipe;
1464         struct rte_sched_pipe_profile *params = grinder->pipe_params;
1465         uint64_t n_periods;
1466
1467         /* Subport TB */
1468         n_periods = (port->time - subport->tb_time) / subport->tb_period;
1469         subport->tb_credits += n_periods * subport->tb_credits_per_period;
1470         subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1471         subport->tb_time += n_periods * subport->tb_period;
1472
1473         /* Pipe TB */
1474         n_periods = (port->time - pipe->tb_time) / params->tb_period;
1475         pipe->tb_credits += n_periods * params->tb_credits_per_period;
1476         pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1477         pipe->tb_time += n_periods * params->tb_period;
1478
1479         /* Subport TCs */
1480         if (unlikely(port->time >= subport->tc_time)) {
1481                 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1482                 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1483                 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1484                 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1485                 subport->tc_time = port->time + subport->tc_period;
1486         }
1487
1488         /* Pipe TCs */
1489         if (unlikely(port->time >= pipe->tc_time)) {
1490                 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1491                 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1492                 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1493                 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1494                 pipe->tc_time = port->time + params->tc_period;
1495         }
1496 }
1497
1498 #else
1499
1500 static inline uint32_t
1501 grinder_tc_ov_credits_update(struct rte_sched_port *port, uint32_t pos)
1502 {
1503         struct rte_sched_grinder *grinder = port->grinder + pos;
1504         struct rte_sched_subport *subport = grinder->subport;
1505         uint32_t tc_ov_consumption[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
1506         uint32_t tc_ov_consumption_max;
1507         uint32_t tc_ov_wm = subport->tc_ov_wm;
1508
1509         if (subport->tc_ov == 0)
1510                 return subport->tc_ov_wm_max;
1511
1512         tc_ov_consumption[0] = subport->tc_credits_per_period[0] - subport->tc_credits[0];
1513         tc_ov_consumption[1] = subport->tc_credits_per_period[1] - subport->tc_credits[1];
1514         tc_ov_consumption[2] = subport->tc_credits_per_period[2] - subport->tc_credits[2];
1515         tc_ov_consumption[3] = subport->tc_credits_per_period[3] - subport->tc_credits[3];
1516
1517         tc_ov_consumption_max = subport->tc_credits_per_period[3] -
1518                 (tc_ov_consumption[0] + tc_ov_consumption[1] + tc_ov_consumption[2]);
1519
1520         if (tc_ov_consumption[3] > (tc_ov_consumption_max - port->mtu)) {
1521                 tc_ov_wm  -= tc_ov_wm >> 7;
1522                 if (tc_ov_wm < subport->tc_ov_wm_min)
1523                         tc_ov_wm = subport->tc_ov_wm_min;
1524
1525                 return tc_ov_wm;
1526         }
1527
1528         tc_ov_wm += (tc_ov_wm >> 7) + 1;
1529         if (tc_ov_wm > subport->tc_ov_wm_max)
1530                 tc_ov_wm = subport->tc_ov_wm_max;
1531
1532         return tc_ov_wm;
1533 }
1534
1535 static inline void
1536 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1537 {
1538         struct rte_sched_grinder *grinder = port->grinder + pos;
1539         struct rte_sched_subport *subport = grinder->subport;
1540         struct rte_sched_pipe *pipe = grinder->pipe;
1541         struct rte_sched_pipe_profile *params = grinder->pipe_params;
1542         uint64_t n_periods;
1543
1544         /* Subport TB */
1545         n_periods = (port->time - subport->tb_time) / subport->tb_period;
1546         subport->tb_credits += n_periods * subport->tb_credits_per_period;
1547         subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1548         subport->tb_time += n_periods * subport->tb_period;
1549
1550         /* Pipe TB */
1551         n_periods = (port->time - pipe->tb_time) / params->tb_period;
1552         pipe->tb_credits += n_periods * params->tb_credits_per_period;
1553         pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1554         pipe->tb_time += n_periods * params->tb_period;
1555
1556         /* Subport TCs */
1557         if (unlikely(port->time >= subport->tc_time)) {
1558                 subport->tc_ov_wm = grinder_tc_ov_credits_update(port, pos);
1559
1560                 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1561                 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1562                 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1563                 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1564
1565                 subport->tc_time = port->time + subport->tc_period;
1566                 subport->tc_ov_period_id++;
1567         }
1568
1569         /* Pipe TCs */
1570         if (unlikely(port->time >= pipe->tc_time)) {
1571                 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1572                 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1573                 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1574                 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1575                 pipe->tc_time = port->time + params->tc_period;
1576         }
1577
1578         /* Pipe TCs - Oversubscription */
1579         if (unlikely(pipe->tc_ov_period_id != subport->tc_ov_period_id)) {
1580                 pipe->tc_ov_credits = subport->tc_ov_wm * params->tc_ov_weight;
1581
1582                 pipe->tc_ov_period_id = subport->tc_ov_period_id;
1583         }
1584 }
1585
1586 #endif /* RTE_SCHED_TS_CREDITS_UPDATE, RTE_SCHED_SUBPORT_TC_OV */
1587
1588
1589 #ifndef RTE_SCHED_SUBPORT_TC_OV
1590
1591 static inline int
1592 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1593 {
1594         struct rte_sched_grinder *grinder = port->grinder + pos;
1595         struct rte_sched_subport *subport = grinder->subport;
1596         struct rte_sched_pipe *pipe = grinder->pipe;
1597         struct rte_mbuf *pkt = grinder->pkt;
1598         uint32_t tc_index = grinder->tc_index;
1599         uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1600         uint32_t subport_tb_credits = subport->tb_credits;
1601         uint32_t subport_tc_credits = subport->tc_credits[tc_index];
1602         uint32_t pipe_tb_credits = pipe->tb_credits;
1603         uint32_t pipe_tc_credits = pipe->tc_credits[tc_index];
1604         int enough_credits;
1605
1606         /* Check queue credits */
1607         enough_credits = (pkt_len <= subport_tb_credits) &&
1608                 (pkt_len <= subport_tc_credits) &&
1609                 (pkt_len <= pipe_tb_credits) &&
1610                 (pkt_len <= pipe_tc_credits);
1611
1612         if (!enough_credits)
1613                 return 0;
1614
1615         /* Update port credits */
1616         subport->tb_credits -= pkt_len;
1617         subport->tc_credits[tc_index] -= pkt_len;
1618         pipe->tb_credits -= pkt_len;
1619         pipe->tc_credits[tc_index] -= pkt_len;
1620
1621         return 1;
1622 }
1623
1624 #else
1625
1626 static inline int
1627 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1628 {
1629         struct rte_sched_grinder *grinder = port->grinder + pos;
1630         struct rte_sched_subport *subport = grinder->subport;
1631         struct rte_sched_pipe *pipe = grinder->pipe;
1632         struct rte_mbuf *pkt = grinder->pkt;
1633         uint32_t tc_index = grinder->tc_index;
1634         uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1635         uint32_t subport_tb_credits = subport->tb_credits;
1636         uint32_t subport_tc_credits = subport->tc_credits[tc_index];
1637         uint32_t pipe_tb_credits = pipe->tb_credits;
1638         uint32_t pipe_tc_credits = pipe->tc_credits[tc_index];
1639         uint32_t pipe_tc_ov_mask1[] = {UINT32_MAX, UINT32_MAX, UINT32_MAX, pipe->tc_ov_credits};
1640         uint32_t pipe_tc_ov_mask2[] = {0, 0, 0, UINT32_MAX};
1641         uint32_t pipe_tc_ov_credits = pipe_tc_ov_mask1[tc_index];
1642         int enough_credits;
1643
1644         /* Check pipe and subport credits */
1645         enough_credits = (pkt_len <= subport_tb_credits) &&
1646                 (pkt_len <= subport_tc_credits) &&
1647                 (pkt_len <= pipe_tb_credits) &&
1648                 (pkt_len <= pipe_tc_credits) &&
1649                 (pkt_len <= pipe_tc_ov_credits);
1650
1651         if (!enough_credits)
1652                 return 0;
1653
1654         /* Update pipe and subport credits */
1655         subport->tb_credits -= pkt_len;
1656         subport->tc_credits[tc_index] -= pkt_len;
1657         pipe->tb_credits -= pkt_len;
1658         pipe->tc_credits[tc_index] -= pkt_len;
1659         pipe->tc_ov_credits -= pipe_tc_ov_mask2[tc_index] & pkt_len;
1660
1661         return 1;
1662 }
1663
1664 #endif /* RTE_SCHED_SUBPORT_TC_OV */
1665
1666
1667 static inline int
1668 grinder_schedule(struct rte_sched_port *port, uint32_t pos)
1669 {
1670         struct rte_sched_grinder *grinder = port->grinder + pos;
1671         struct rte_sched_queue *queue = grinder->queue[grinder->qpos];
1672         struct rte_mbuf *pkt = grinder->pkt;
1673         uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1674
1675         if (!grinder_credits_check(port, pos))
1676                 return 0;
1677
1678         /* Advance port time */
1679         port->time += pkt_len;
1680
1681         /* Send packet */
1682         port->pkts_out[port->n_pkts_out++] = pkt;
1683         queue->qr++;
1684         grinder->wrr_tokens[grinder->qpos] += pkt_len * grinder->wrr_cost[grinder->qpos];
1685         if (queue->qr == queue->qw) {
1686                 uint32_t qindex = grinder->qindex[grinder->qpos];
1687
1688                 rte_bitmap_clear(port->bmp, qindex);
1689                 grinder->qmask &= ~(1 << grinder->qpos);
1690                 grinder->wrr_mask[grinder->qpos] = 0;
1691                 rte_sched_port_set_queue_empty_timestamp(port, qindex);
1692         }
1693
1694         /* Reset pipe loop detection */
1695         port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1696         grinder->productive = 1;
1697
1698         return 1;
1699 }
1700
1701 #ifdef RTE_SCHED_VECTOR
1702
1703 static inline int
1704 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1705 {
1706         __m128i index = _mm_set1_epi32(base_pipe);
1707         __m128i pipes = _mm_load_si128((__m128i *)port->grinder_base_bmp_pos);
1708         __m128i res = _mm_cmpeq_epi32(pipes, index);
1709
1710         pipes = _mm_load_si128((__m128i *)(port->grinder_base_bmp_pos + 4));
1711         pipes = _mm_cmpeq_epi32(pipes, index);
1712         res = _mm_or_si128(res, pipes);
1713
1714         if (_mm_testz_si128(res, res))
1715                 return 0;
1716
1717         return 1;
1718 }
1719
1720 #else
1721
1722 static inline int
1723 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1724 {
1725         uint32_t i;
1726
1727         for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i++) {
1728                 if (port->grinder_base_bmp_pos[i] == base_pipe)
1729                         return 1;
1730         }
1731
1732         return 0;
1733 }
1734
1735 #endif /* RTE_SCHED_OPTIMIZATIONS */
1736
1737 static inline void
1738 grinder_pcache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t bmp_pos, uint64_t bmp_slab)
1739 {
1740         struct rte_sched_grinder *grinder = port->grinder + pos;
1741         uint16_t w[4];
1742
1743         grinder->pcache_w = 0;
1744         grinder->pcache_r = 0;
1745
1746         w[0] = (uint16_t) bmp_slab;
1747         w[1] = (uint16_t) (bmp_slab >> 16);
1748         w[2] = (uint16_t) (bmp_slab >> 32);
1749         w[3] = (uint16_t) (bmp_slab >> 48);
1750
1751         grinder->pcache_qmask[grinder->pcache_w] = w[0];
1752         grinder->pcache_qindex[grinder->pcache_w] = bmp_pos;
1753         grinder->pcache_w += (w[0] != 0);
1754
1755         grinder->pcache_qmask[grinder->pcache_w] = w[1];
1756         grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 16;
1757         grinder->pcache_w += (w[1] != 0);
1758
1759         grinder->pcache_qmask[grinder->pcache_w] = w[2];
1760         grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 32;
1761         grinder->pcache_w += (w[2] != 0);
1762
1763         grinder->pcache_qmask[grinder->pcache_w] = w[3];
1764         grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 48;
1765         grinder->pcache_w += (w[3] != 0);
1766 }
1767
1768 static inline void
1769 grinder_tccache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t qindex, uint16_t qmask)
1770 {
1771         struct rte_sched_grinder *grinder = port->grinder + pos;
1772         uint8_t b[4];
1773
1774         grinder->tccache_w = 0;
1775         grinder->tccache_r = 0;
1776
1777         b[0] = (uint8_t) (qmask & 0xF);
1778         b[1] = (uint8_t) ((qmask >> 4) & 0xF);
1779         b[2] = (uint8_t) ((qmask >> 8) & 0xF);
1780         b[3] = (uint8_t) ((qmask >> 12) & 0xF);
1781
1782         grinder->tccache_qmask[grinder->tccache_w] = b[0];
1783         grinder->tccache_qindex[grinder->tccache_w] = qindex;
1784         grinder->tccache_w += (b[0] != 0);
1785
1786         grinder->tccache_qmask[grinder->tccache_w] = b[1];
1787         grinder->tccache_qindex[grinder->tccache_w] = qindex + 4;
1788         grinder->tccache_w += (b[1] != 0);
1789
1790         grinder->tccache_qmask[grinder->tccache_w] = b[2];
1791         grinder->tccache_qindex[grinder->tccache_w] = qindex + 8;
1792         grinder->tccache_w += (b[2] != 0);
1793
1794         grinder->tccache_qmask[grinder->tccache_w] = b[3];
1795         grinder->tccache_qindex[grinder->tccache_w] = qindex + 12;
1796         grinder->tccache_w += (b[3] != 0);
1797 }
1798
1799 static inline int
1800 grinder_next_tc(struct rte_sched_port *port, uint32_t pos)
1801 {
1802         struct rte_sched_grinder *grinder = port->grinder + pos;
1803         struct rte_mbuf **qbase;
1804         uint32_t qindex;
1805         uint16_t qsize;
1806
1807         if (grinder->tccache_r == grinder->tccache_w)
1808                 return 0;
1809
1810         qindex = grinder->tccache_qindex[grinder->tccache_r];
1811         qbase = rte_sched_port_qbase(port, qindex);
1812         qsize = rte_sched_port_qsize(port, qindex);
1813
1814         grinder->tc_index = (qindex >> 2) & 0x3;
1815         grinder->qmask = grinder->tccache_qmask[grinder->tccache_r];
1816         grinder->qsize = qsize;
1817
1818         grinder->qindex[0] = qindex;
1819         grinder->qindex[1] = qindex + 1;
1820         grinder->qindex[2] = qindex + 2;
1821         grinder->qindex[3] = qindex + 3;
1822
1823         grinder->queue[0] = port->queue + qindex;
1824         grinder->queue[1] = port->queue + qindex + 1;
1825         grinder->queue[2] = port->queue + qindex + 2;
1826         grinder->queue[3] = port->queue + qindex + 3;
1827
1828         grinder->qbase[0] = qbase;
1829         grinder->qbase[1] = qbase + qsize;
1830         grinder->qbase[2] = qbase + 2 * qsize;
1831         grinder->qbase[3] = qbase + 3 * qsize;
1832
1833         grinder->tccache_r++;
1834         return 1;
1835 }
1836
1837 static inline int
1838 grinder_next_pipe(struct rte_sched_port *port, uint32_t pos)
1839 {
1840         struct rte_sched_grinder *grinder = port->grinder + pos;
1841         uint32_t pipe_qindex;
1842         uint16_t pipe_qmask;
1843
1844         if (grinder->pcache_r < grinder->pcache_w) {
1845                 pipe_qmask = grinder->pcache_qmask[grinder->pcache_r];
1846                 pipe_qindex = grinder->pcache_qindex[grinder->pcache_r];
1847                 grinder->pcache_r++;
1848         } else {
1849                 uint64_t bmp_slab = 0;
1850                 uint32_t bmp_pos = 0;
1851
1852                 /* Get another non-empty pipe group */
1853                 if (unlikely(rte_bitmap_scan(port->bmp, &bmp_pos, &bmp_slab) <= 0))
1854                         return 0;
1855
1856 #ifdef RTE_SCHED_DEBUG
1857                 debug_check_queue_slab(port, bmp_pos, bmp_slab);
1858 #endif
1859
1860                 /* Return if pipe group already in one of the other grinders */
1861                 port->grinder_base_bmp_pos[pos] = RTE_SCHED_BMP_POS_INVALID;
1862                 if (unlikely(grinder_pipe_exists(port, bmp_pos)))
1863                         return 0;
1864
1865                 port->grinder_base_bmp_pos[pos] = bmp_pos;
1866
1867                 /* Install new pipe group into grinder's pipe cache */
1868                 grinder_pcache_populate(port, pos, bmp_pos, bmp_slab);
1869
1870                 pipe_qmask = grinder->pcache_qmask[0];
1871                 pipe_qindex = grinder->pcache_qindex[0];
1872                 grinder->pcache_r = 1;
1873         }
1874
1875         /* Install new pipe in the grinder */
1876         grinder->pindex = pipe_qindex >> 4;
1877         grinder->subport = port->subport + (grinder->pindex / port->n_pipes_per_subport);
1878         grinder->pipe = port->pipe + grinder->pindex;
1879         grinder->pipe_params = NULL; /* to be set after the pipe structure is prefetched */
1880         grinder->productive = 0;
1881
1882         grinder_tccache_populate(port, pos, pipe_qindex, pipe_qmask);
1883         grinder_next_tc(port, pos);
1884
1885         /* Check for pipe exhaustion */
1886         if (grinder->pindex == port->pipe_loop) {
1887                 port->pipe_exhaustion = 1;
1888                 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1889         }
1890
1891         return 1;
1892 }
1893
1894
1895 static inline void
1896 grinder_wrr_load(struct rte_sched_port *port, uint32_t pos)
1897 {
1898         struct rte_sched_grinder *grinder = port->grinder + pos;
1899         struct rte_sched_pipe *pipe = grinder->pipe;
1900         struct rte_sched_pipe_profile *pipe_params = grinder->pipe_params;
1901         uint32_t tc_index = grinder->tc_index;
1902         uint32_t qmask = grinder->qmask;
1903         uint32_t qindex;
1904
1905         qindex = tc_index * 4;
1906
1907         grinder->wrr_tokens[0] = ((uint16_t) pipe->wrr_tokens[qindex]) << RTE_SCHED_WRR_SHIFT;
1908         grinder->wrr_tokens[1] = ((uint16_t) pipe->wrr_tokens[qindex + 1]) << RTE_SCHED_WRR_SHIFT;
1909         grinder->wrr_tokens[2] = ((uint16_t) pipe->wrr_tokens[qindex + 2]) << RTE_SCHED_WRR_SHIFT;
1910         grinder->wrr_tokens[3] = ((uint16_t) pipe->wrr_tokens[qindex + 3]) << RTE_SCHED_WRR_SHIFT;
1911
1912         grinder->wrr_mask[0] = (qmask & 0x1) * 0xFFFF;
1913         grinder->wrr_mask[1] = ((qmask >> 1) & 0x1) * 0xFFFF;
1914         grinder->wrr_mask[2] = ((qmask >> 2) & 0x1) * 0xFFFF;
1915         grinder->wrr_mask[3] = ((qmask >> 3) & 0x1) * 0xFFFF;
1916
1917         grinder->wrr_cost[0] = pipe_params->wrr_cost[qindex];
1918         grinder->wrr_cost[1] = pipe_params->wrr_cost[qindex + 1];
1919         grinder->wrr_cost[2] = pipe_params->wrr_cost[qindex + 2];
1920         grinder->wrr_cost[3] = pipe_params->wrr_cost[qindex + 3];
1921 }
1922
1923 static inline void
1924 grinder_wrr_store(struct rte_sched_port *port, uint32_t pos)
1925 {
1926         struct rte_sched_grinder *grinder = port->grinder + pos;
1927         struct rte_sched_pipe *pipe = grinder->pipe;
1928         uint32_t tc_index = grinder->tc_index;
1929         uint32_t qindex;
1930
1931         qindex = tc_index * 4;
1932
1933         pipe->wrr_tokens[qindex] = (grinder->wrr_tokens[0] & grinder->wrr_mask[0])
1934                 >> RTE_SCHED_WRR_SHIFT;
1935         pipe->wrr_tokens[qindex + 1] = (grinder->wrr_tokens[1] & grinder->wrr_mask[1])
1936                 >> RTE_SCHED_WRR_SHIFT;
1937         pipe->wrr_tokens[qindex + 2] = (grinder->wrr_tokens[2] & grinder->wrr_mask[2])
1938                 >> RTE_SCHED_WRR_SHIFT;
1939         pipe->wrr_tokens[qindex + 3] = (grinder->wrr_tokens[3] & grinder->wrr_mask[3])
1940                 >> RTE_SCHED_WRR_SHIFT;
1941 }
1942
1943 static inline void
1944 grinder_wrr(struct rte_sched_port *port, uint32_t pos)
1945 {
1946         struct rte_sched_grinder *grinder = port->grinder + pos;
1947         uint16_t wrr_tokens_min;
1948
1949         grinder->wrr_tokens[0] |= ~grinder->wrr_mask[0];
1950         grinder->wrr_tokens[1] |= ~grinder->wrr_mask[1];
1951         grinder->wrr_tokens[2] |= ~grinder->wrr_mask[2];
1952         grinder->wrr_tokens[3] |= ~grinder->wrr_mask[3];
1953
1954         grinder->qpos = rte_min_pos_4_u16(grinder->wrr_tokens);
1955         wrr_tokens_min = grinder->wrr_tokens[grinder->qpos];
1956
1957         grinder->wrr_tokens[0] -= wrr_tokens_min;
1958         grinder->wrr_tokens[1] -= wrr_tokens_min;
1959         grinder->wrr_tokens[2] -= wrr_tokens_min;
1960         grinder->wrr_tokens[3] -= wrr_tokens_min;
1961 }
1962
1963
1964 #define grinder_evict(port, pos)
1965
1966 static inline void
1967 grinder_prefetch_pipe(struct rte_sched_port *port, uint32_t pos)
1968 {
1969         struct rte_sched_grinder *grinder = port->grinder + pos;
1970
1971         rte_prefetch0(grinder->pipe);
1972         rte_prefetch0(grinder->queue[0]);
1973 }
1974
1975 static inline void
1976 grinder_prefetch_tc_queue_arrays(struct rte_sched_port *port, uint32_t pos)
1977 {
1978         struct rte_sched_grinder *grinder = port->grinder + pos;
1979         uint16_t qsize, qr[4];
1980
1981         qsize = grinder->qsize;
1982         qr[0] = grinder->queue[0]->qr & (qsize - 1);
1983         qr[1] = grinder->queue[1]->qr & (qsize - 1);
1984         qr[2] = grinder->queue[2]->qr & (qsize - 1);
1985         qr[3] = grinder->queue[3]->qr & (qsize - 1);
1986
1987         rte_prefetch0(grinder->qbase[0] + qr[0]);
1988         rte_prefetch0(grinder->qbase[1] + qr[1]);
1989
1990         grinder_wrr_load(port, pos);
1991         grinder_wrr(port, pos);
1992
1993         rte_prefetch0(grinder->qbase[2] + qr[2]);
1994         rte_prefetch0(grinder->qbase[3] + qr[3]);
1995 }
1996
1997 static inline void
1998 grinder_prefetch_mbuf(struct rte_sched_port *port, uint32_t pos)
1999 {
2000         struct rte_sched_grinder *grinder = port->grinder + pos;
2001         uint32_t qpos = grinder->qpos;
2002         struct rte_mbuf **qbase = grinder->qbase[qpos];
2003         uint16_t qsize = grinder->qsize;
2004         uint16_t qr = grinder->queue[qpos]->qr & (qsize - 1);
2005
2006         grinder->pkt = qbase[qr];
2007         rte_prefetch0(grinder->pkt);
2008
2009         if (unlikely((qr & 0x7) == 7)) {
2010                 uint16_t qr_next = (grinder->queue[qpos]->qr + 1) & (qsize - 1);
2011
2012                 rte_prefetch0(qbase + qr_next);
2013         }
2014 }
2015
2016 static inline uint32_t
2017 grinder_handle(struct rte_sched_port *port, uint32_t pos)
2018 {
2019         struct rte_sched_grinder *grinder = port->grinder + pos;
2020
2021         switch (grinder->state) {
2022         case e_GRINDER_PREFETCH_PIPE:
2023         {
2024                 if (grinder_next_pipe(port, pos)) {
2025                         grinder_prefetch_pipe(port, pos);
2026                         port->busy_grinders++;
2027
2028                         grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2029                         return 0;
2030                 }
2031
2032                 return 0;
2033         }
2034
2035         case e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS:
2036         {
2037                 struct rte_sched_pipe *pipe = grinder->pipe;
2038
2039                 grinder->pipe_params = port->pipe_profiles + pipe->profile;
2040                 grinder_prefetch_tc_queue_arrays(port, pos);
2041                 grinder_credits_update(port, pos);
2042
2043                 grinder->state = e_GRINDER_PREFETCH_MBUF;
2044                 return 0;
2045         }
2046
2047         case e_GRINDER_PREFETCH_MBUF:
2048         {
2049                 grinder_prefetch_mbuf(port, pos);
2050
2051                 grinder->state = e_GRINDER_READ_MBUF;
2052                 return 0;
2053         }
2054
2055         case e_GRINDER_READ_MBUF:
2056         {
2057                 uint32_t result = 0;
2058
2059                 result = grinder_schedule(port, pos);
2060
2061                 /* Look for next packet within the same TC */
2062                 if (result && grinder->qmask) {
2063                         grinder_wrr(port, pos);
2064                         grinder_prefetch_mbuf(port, pos);
2065
2066                         return 1;
2067                 }
2068                 grinder_wrr_store(port, pos);
2069
2070                 /* Look for another active TC within same pipe */
2071                 if (grinder_next_tc(port, pos)) {
2072                         grinder_prefetch_tc_queue_arrays(port, pos);
2073
2074                         grinder->state = e_GRINDER_PREFETCH_MBUF;
2075                         return result;
2076                 }
2077
2078                 if (grinder->productive == 0 &&
2079                     port->pipe_loop == RTE_SCHED_PIPE_INVALID)
2080                         port->pipe_loop = grinder->pindex;
2081
2082                 grinder_evict(port, pos);
2083
2084                 /* Look for another active pipe */
2085                 if (grinder_next_pipe(port, pos)) {
2086                         grinder_prefetch_pipe(port, pos);
2087
2088                         grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2089                         return result;
2090                 }
2091
2092                 /* No active pipe found */
2093                 port->busy_grinders--;
2094
2095                 grinder->state = e_GRINDER_PREFETCH_PIPE;
2096                 return result;
2097         }
2098
2099         default:
2100                 rte_panic("Algorithmic error (invalid state)\n");
2101                 return 0;
2102         }
2103 }
2104
2105 static inline void
2106 rte_sched_port_time_resync(struct rte_sched_port *port)
2107 {
2108         uint64_t cycles = rte_get_tsc_cycles();
2109         uint64_t cycles_diff = cycles - port->time_cpu_cycles;
2110         double bytes_diff = ((double) cycles_diff) / port->cycles_per_byte;
2111
2112         /* Advance port time */
2113         port->time_cpu_cycles = cycles;
2114         port->time_cpu_bytes += (uint64_t) bytes_diff;
2115         if (port->time < port->time_cpu_bytes)
2116                 port->time = port->time_cpu_bytes;
2117
2118         /* Reset pipe loop detection */
2119         port->pipe_loop = RTE_SCHED_PIPE_INVALID;
2120 }
2121
2122 static inline int
2123 rte_sched_port_exceptions(struct rte_sched_port *port, int second_pass)
2124 {
2125         int exceptions;
2126
2127         /* Check if any exception flag is set */
2128         exceptions = (second_pass && port->busy_grinders == 0) ||
2129                 (port->pipe_exhaustion == 1);
2130
2131         /* Clear exception flags */
2132         port->pipe_exhaustion = 0;
2133
2134         return exceptions;
2135 }
2136
2137 int
2138 rte_sched_port_dequeue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
2139 {
2140         uint32_t i, count;
2141
2142         port->pkts_out = pkts;
2143         port->n_pkts_out = 0;
2144
2145         rte_sched_port_time_resync(port);
2146
2147         /* Take each queue in the grinder one step further */
2148         for (i = 0, count = 0; ; i++)  {
2149                 count += grinder_handle(port, i & (RTE_SCHED_PORT_N_GRINDERS - 1));
2150                 if ((count == n_pkts) ||
2151                     rte_sched_port_exceptions(port, i >= RTE_SCHED_PORT_N_GRINDERS)) {
2152                         break;
2153                 }
2154         }
2155
2156         return count;
2157 }