lib/librte_sched/rte_sched.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <string.h>
  36
  37 #include <rte_common.h>
  38 #include <rte_log.h>
  39 #include <rte_memory.h>
  40 #include <rte_malloc.h>
  41 #include <rte_cycles.h>
  42 #include <rte_prefetch.h>
  43 #include <rte_branch_prediction.h>
  44 #include <rte_mbuf.h>
  45
  46 #include "rte_sched.h"
  47 #include "rte_bitmap.h"
  48 #include "rte_sched_common.h"
  49 #include "rte_approx.h"
  50
  51 #ifdef __INTEL_COMPILER
  52 #pragma warning(disable:2259) /* conversion may lose significant bits */
  53 #endif
  54
  55 #ifdef RTE_SCHED_VECTOR
  56 #include <rte_vect.h>
  57
  58 #if defined(__SSE4__)
  59 #define SCHED_VECTOR_SSE4
  60 #endif
  61
  62 #endif
  63
  64 #define RTE_SCHED_TB_RATE_CONFIG_ERR          (1e-7)
  65 #define RTE_SCHED_WRR_SHIFT                   3
  66 #define RTE_SCHED_GRINDER_PCACHE_SIZE         (64 / RTE_SCHED_QUEUES_PER_PIPE)
  67 #define RTE_SCHED_PIPE_INVALID                UINT32_MAX
  68 #define RTE_SCHED_BMP_POS_INVALID             UINT32_MAX
  69
  70 struct rte_sched_subport {
  71         /* Token bucket (TB) */
  72         uint64_t tb_time; /* time of last update */
  73         uint32_t tb_period;
  74         uint32_t tb_credits_per_period;
  75         uint32_t tb_size;
  76         uint32_t tb_credits;
  77
  78         /* Traffic classes (TCs) */
  79         uint64_t tc_time; /* time of next update */
  80         uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
  81         uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
  82         uint32_t tc_period;
  83
  84         /* TC oversubscription */
  85         uint32_t tc_ov_wm;
  86         uint32_t tc_ov_wm_min;
  87         uint32_t tc_ov_wm_max;
  88         uint8_t tc_ov_period_id;
  89         uint8_t tc_ov;
  90         uint32_t tc_ov_n;
  91         double tc_ov_rate;
  92
  93         /* Statistics */
  94         struct rte_sched_subport_stats stats;
  95 };
  96
  97 struct rte_sched_pipe_profile {
  98         /* Token bucket (TB) */
  99         uint32_t tb_period;
 100         uint32_t tb_credits_per_period;
 101         uint32_t tb_size;
 102
 103         /* Pipe traffic classes */
 104         uint32_t tc_period;
 105         uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
 106         uint8_t tc_ov_weight;
 107
 108         /* Pipe queues */
 109         uint8_t  wrr_cost[RTE_SCHED_QUEUES_PER_PIPE];
 110 };
 111
 112 struct rte_sched_pipe {
 113         /* Token bucket (TB) */
 114         uint64_t tb_time; /* time of last update */
 115         uint32_t tb_credits;
 116
 117         /* Pipe profile and flags */
 118         uint32_t profile;
 119
 120         /* Traffic classes (TCs) */
 121         uint64_t tc_time; /* time of next update */
 122         uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
 123
 124         /* Weighted Round Robin (WRR) */
 125         uint8_t wrr_tokens[RTE_SCHED_QUEUES_PER_PIPE];
 126
 127         /* TC oversubscription */
 128         uint32_t tc_ov_credits;
 129         uint8_t tc_ov_period_id;
 130         uint8_t reserved[3];
 131 } __rte_cache_aligned;
 132
 133 struct rte_sched_queue {
 134         uint16_t qw;
 135         uint16_t qr;
 136 };
 137
 138 struct rte_sched_queue_extra {
 139         struct rte_sched_queue_stats stats;
 140 #ifdef RTE_SCHED_RED
 141         struct rte_red red;
 142 #endif
 143 };
 144
 145 enum grinder_state {
 146         e_GRINDER_PREFETCH_PIPE = 0,
 147         e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS,
 148         e_GRINDER_PREFETCH_MBUF,
 149         e_GRINDER_READ_MBUF
 150 };
 151
 152 /*
 153  * Path through the scheduler hierarchy used by the scheduler enqueue
 154  * operation to identify the destination queue for the current
 155  * packet. Stored in the field pkt.hash.sched of struct rte_mbuf of
 156  * each packet, typically written by the classification stage and read
 157  * by scheduler enqueue.
 158  */
 159 struct rte_sched_port_hierarchy {
 160         uint16_t queue:2;                /**< Queue ID (0 .. 3) */
 161         uint16_t traffic_class:2;        /**< Traffic class ID (0 .. 3)*/
 162         uint32_t color:2;                /**< Color */
 163         uint16_t unused:10;
 164         uint16_t subport;                /**< Subport ID */
 165         uint32_t pipe;                   /**< Pipe ID */
 166 };
 167
 168 struct rte_sched_grinder {
 169         /* Pipe cache */
 170         uint16_t pcache_qmask[RTE_SCHED_GRINDER_PCACHE_SIZE];
 171         uint32_t pcache_qindex[RTE_SCHED_GRINDER_PCACHE_SIZE];
 172         uint32_t pcache_w;
 173         uint32_t pcache_r;
 174
 175         /* Current pipe */
 176         enum grinder_state state;
 177         uint32_t productive;
 178         uint32_t pindex;
 179         struct rte_sched_subport *subport;
 180         struct rte_sched_pipe *pipe;
 181         struct rte_sched_pipe_profile *pipe_params;
 182
 183         /* TC cache */
 184         uint8_t tccache_qmask[4];
 185         uint32_t tccache_qindex[4];
 186         uint32_t tccache_w;
 187         uint32_t tccache_r;
 188
 189         /* Current TC */
 190         uint32_t tc_index;
 191         struct rte_sched_queue *queue[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
 192         struct rte_mbuf **qbase[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
 193         uint32_t qindex[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
 194         uint16_t qsize;
 195         uint32_t qmask;
 196         uint32_t qpos;
 197         struct rte_mbuf *pkt;
 198
 199         /* WRR */
 200         uint16_t wrr_tokens[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
 201         uint16_t wrr_mask[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
 202         uint8_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
 203 };
 204
 205 struct rte_sched_port {
 206         /* User parameters */
 207         uint32_t n_subports_per_port;
 208         uint32_t n_pipes_per_subport;
 209         uint32_t rate;
 210         uint32_t mtu;
 211         uint32_t frame_overhead;
 212         uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
 213         uint32_t n_pipe_profiles;
 214         uint32_t pipe_tc3_rate_max;
 215 #ifdef RTE_SCHED_RED
 216         struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][e_RTE_METER_COLORS];
 217 #endif
 218
 219         /* Timing */
 220         uint64_t time_cpu_cycles;     /* Current CPU time measured in CPU cyles */
 221         uint64_t time_cpu_bytes;      /* Current CPU time measured in bytes */
 222         uint64_t time;                /* Current NIC TX time measured in bytes */
 223         double cycles_per_byte;       /* CPU cycles per byte */
 224
 225         /* Scheduling loop detection */
 226         uint32_t pipe_loop;
 227         uint32_t pipe_exhaustion;
 228
 229         /* Bitmap */
 230         struct rte_bitmap *bmp;
 231         uint32_t grinder_base_bmp_pos[RTE_SCHED_PORT_N_GRINDERS] __rte_aligned_16;
 232
 233         /* Grinders */
 234         struct rte_sched_grinder grinder[RTE_SCHED_PORT_N_GRINDERS];
 235         uint32_t busy_grinders;
 236         struct rte_mbuf **pkts_out;
 237         uint32_t n_pkts_out;
 238
 239         /* Queue base calculation */
 240         uint32_t qsize_add[RTE_SCHED_QUEUES_PER_PIPE];
 241         uint32_t qsize_sum;
 242
 243         /* Large data structures */
 244         struct rte_sched_subport *subport;
 245         struct rte_sched_pipe *pipe;
 246         struct rte_sched_queue *queue;
 247         struct rte_sched_queue_extra *queue_extra;
 248         struct rte_sched_pipe_profile *pipe_profiles;
 249         uint8_t *bmp_array;
 250         struct rte_mbuf **queue_array;
 251         uint8_t memory[0] __rte_cache_aligned;
 252 } __rte_cache_aligned;
 253
 254 enum rte_sched_port_array {
 255         e_RTE_SCHED_PORT_ARRAY_SUBPORT = 0,
 256         e_RTE_SCHED_PORT_ARRAY_PIPE,
 257         e_RTE_SCHED_PORT_ARRAY_QUEUE,
 258         e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA,
 259         e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES,
 260         e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY,
 261         e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY,
 262         e_RTE_SCHED_PORT_ARRAY_TOTAL,
 263 };
 264
 265 #ifdef RTE_SCHED_COLLECT_STATS
 266
 267 static inline uint32_t
 268 rte_sched_port_queues_per_subport(struct rte_sched_port *port)
 269 {
 270         return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport;
 271 }
 272
 273 #endif
 274
 275 static inline uint32_t
 276 rte_sched_port_queues_per_port(struct rte_sched_port *port)
 277 {
 278         return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport * port->n_subports_per_port;
 279 }
 280
 281 static inline struct rte_mbuf **
 282 rte_sched_port_qbase(struct rte_sched_port *port, uint32_t qindex)
 283 {
 284         uint32_t pindex = qindex >> 4;
 285         uint32_t qpos = qindex & 0xF;
 286
 287         return (port->queue_array + pindex *
 288                 port->qsize_sum + port->qsize_add[qpos]);
 289 }
 290
 291 static inline uint16_t
 292 rte_sched_port_qsize(struct rte_sched_port *port, uint32_t qindex)
 293 {
 294         uint32_t tc = (qindex >> 2) & 0x3;
 295
 296         return port->qsize[tc];
 297 }
 298
 299 static int
 300 rte_sched_port_check_params(struct rte_sched_port_params *params)
 301 {
 302         uint32_t i, j;
 303
 304         if (params == NULL)
 305                 return -1;
 306
 307         /* socket */
 308         if ((params->socket < 0) || (params->socket >= RTE_MAX_NUMA_NODES))
 309                 return -3;
 310
 311         /* rate */
 312         if (params->rate == 0)
 313                 return -4;
 314
 315         /* mtu */
 316         if (params->mtu == 0)
 317                 return -5;
 318
 319         /* n_subports_per_port: non-zero, limited to 16 bits, power of 2 */
 320         if (params->n_subports_per_port == 0 ||
 321             params->n_subports_per_port > 1u << 16 ||
 322             !rte_is_power_of_2(params->n_subports_per_port))
 323                 return -6;
 324
 325         /* n_pipes_per_subport: non-zero, power of 2 */
 326         if (params->n_pipes_per_subport == 0 ||
 327             !rte_is_power_of_2(params->n_pipes_per_subport))
 328                 return -7;
 329
 330         /* qsize: non-zero, power of 2,
 331          * no bigger than 32K (due to 16-bit read/write pointers)
 332          */
 333         for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
 334                 uint16_t qsize = params->qsize[i];
 335
 336                 if (qsize == 0 || !rte_is_power_of_2(qsize))
 337                         return -8;
 338         }
 339
 340         /* pipe_profiles and n_pipe_profiles */
 341         if (params->pipe_profiles == NULL ||
 342             params->n_pipe_profiles == 0 ||
 343             params->n_pipe_profiles > RTE_SCHED_PIPE_PROFILES_PER_PORT)
 344                 return -9;
 345
 346         for (i = 0; i < params->n_pipe_profiles; i++) {
 347                 struct rte_sched_pipe_params *p = params->pipe_profiles + i;
 348
 349                 /* TB rate: non-zero, not greater than port rate */
 350                 if (p->tb_rate == 0 || p->tb_rate > params->rate)
 351                         return -10;
 352
 353                 /* TB size: non-zero */
 354                 if (p->tb_size == 0)
 355                         return -11;
 356
 357                 /* TC rate: non-zero, less than pipe rate */
 358                 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
 359                         if (p->tc_rate[j] == 0 || p->tc_rate[j] > p->tb_rate)
 360                                 return -12;
 361                 }
 362
 363                 /* TC period: non-zero */
 364                 if (p->tc_period == 0)
 365                         return -13;
 366
 367 #ifdef RTE_SCHED_SUBPORT_TC_OV
 368                 /* TC3 oversubscription weight: non-zero */
 369                 if (p->tc_ov_weight == 0)
 370                         return -14;
 371 #endif
 372
 373                 /* Queue WRR weights: non-zero */
 374                 for (j = 0; j < RTE_SCHED_QUEUES_PER_PIPE; j++) {
 375                         if (p->wrr_weights[j] == 0)
 376                                 return -15;
 377                 }
 378         }
 379
 380         return 0;
 381 }
 382
 383 static uint32_t
 384 rte_sched_port_get_array_base(struct rte_sched_port_params *params, enum rte_sched_port_array array)
 385 {
 386         uint32_t n_subports_per_port = params->n_subports_per_port;
 387         uint32_t n_pipes_per_subport = params->n_pipes_per_subport;
 388         uint32_t n_pipes_per_port = n_pipes_per_subport * n_subports_per_port;
 389         uint32_t n_queues_per_port = RTE_SCHED_QUEUES_PER_PIPE * n_pipes_per_subport * n_subports_per_port;
 390
 391         uint32_t size_subport = n_subports_per_port * sizeof(struct rte_sched_subport);
 392         uint32_t size_pipe = n_pipes_per_port * sizeof(struct rte_sched_pipe);
 393         uint32_t size_queue = n_queues_per_port * sizeof(struct rte_sched_queue);
 394         uint32_t size_queue_extra
 395                 = n_queues_per_port * sizeof(struct rte_sched_queue_extra);
 396         uint32_t size_pipe_profiles
 397                 = RTE_SCHED_PIPE_PROFILES_PER_PORT * sizeof(struct rte_sched_pipe_profile);
 398         uint32_t size_bmp_array = rte_bitmap_get_memory_footprint(n_queues_per_port);
 399         uint32_t size_per_pipe_queue_array, size_queue_array;
 400
 401         uint32_t base, i;
 402
 403         size_per_pipe_queue_array = 0;
 404         for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
 405                 size_per_pipe_queue_array += RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS
 406                         * params->qsize[i] * sizeof(struct rte_mbuf *);
 407         }
 408         size_queue_array = n_pipes_per_port * size_per_pipe_queue_array;
 409
 410         base = 0;
 411
 412         if (array == e_RTE_SCHED_PORT_ARRAY_SUBPORT)
 413                 return base;
 414         base += RTE_CACHE_LINE_ROUNDUP(size_subport);
 415
 416         if (array == e_RTE_SCHED_PORT_ARRAY_PIPE)
 417                 return base;
 418         base += RTE_CACHE_LINE_ROUNDUP(size_pipe);
 419
 420         if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE)
 421                 return base;
 422         base += RTE_CACHE_LINE_ROUNDUP(size_queue);
 423
 424         if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA)
 425                 return base;
 426         base += RTE_CACHE_LINE_ROUNDUP(size_queue_extra);
 427
 428         if (array == e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES)
 429                 return base;
 430         base += RTE_CACHE_LINE_ROUNDUP(size_pipe_profiles);
 431
 432         if (array == e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY)
 433                 return base;
 434         base += RTE_CACHE_LINE_ROUNDUP(size_bmp_array);
 435
 436         if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY)
 437                 return base;
 438         base += RTE_CACHE_LINE_ROUNDUP(size_queue_array);
 439
 440         return base;
 441 }
 442
 443 uint32_t
 444 rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)
 445 {
 446         uint32_t size0, size1;
 447         int status;
 448
 449         status = rte_sched_port_check_params(params);
 450         if (status != 0) {
 451                 RTE_LOG(NOTICE, SCHED,
 452                         "Port scheduler params check failed (%d)\n", status);
 453
 454                 return 0;
 455         }
 456
 457         size0 = sizeof(struct rte_sched_port);
 458         size1 = rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_TOTAL);
 459
 460         return size0 + size1;
 461 }
 462
 463 static void
 464 rte_sched_port_config_qsize(struct rte_sched_port *port)
 465 {
 466         /* TC 0 */
 467         port->qsize_add[0] = 0;
 468         port->qsize_add[1] = port->qsize_add[0] + port->qsize[0];
 469         port->qsize_add[2] = port->qsize_add[1] + port->qsize[0];
 470         port->qsize_add[3] = port->qsize_add[2] + port->qsize[0];
 471
 472         /* TC 1 */
 473         port->qsize_add[4] = port->qsize_add[3] + port->qsize[0];
 474         port->qsize_add[5] = port->qsize_add[4] + port->qsize[1];
 475         port->qsize_add[6] = port->qsize_add[5] + port->qsize[1];
 476         port->qsize_add[7] = port->qsize_add[6] + port->qsize[1];
 477
 478         /* TC 2 */
 479         port->qsize_add[8] = port->qsize_add[7] + port->qsize[1];
 480         port->qsize_add[9] = port->qsize_add[8] + port->qsize[2];
 481         port->qsize_add[10] = port->qsize_add[9] + port->qsize[2];
 482         port->qsize_add[11] = port->qsize_add[10] + port->qsize[2];
 483
 484         /* TC 3 */
 485         port->qsize_add[12] = port->qsize_add[11] + port->qsize[2];
 486         port->qsize_add[13] = port->qsize_add[12] + port->qsize[3];
 487         port->qsize_add[14] = port->qsize_add[13] + port->qsize[3];
 488         port->qsize_add[15] = port->qsize_add[14] + port->qsize[3];
 489
 490         port->qsize_sum = port->qsize_add[15] + port->qsize[3];
 491 }
 492
 493 static void
 494 rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)
 495 {
 496         struct rte_sched_pipe_profile *p = port->pipe_profiles + i;
 497
 498         RTE_LOG(DEBUG, SCHED, "Low level config for pipe profile %u:\n"
 499                 "    Token bucket: period = %u, credits per period = %u, size = %u\n"
 500                 "    Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\n"
 501                 "    Traffic class 3 oversubscription: weight = %hhu\n"
 502                 "    WRR cost: [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu]\n",
 503                 i,
 504
 505                 /* Token bucket */
 506                 p->tb_period,
 507                 p->tb_credits_per_period,
 508                 p->tb_size,
 509
 510                 /* Traffic classes */
 511                 p->tc_period,
 512                 p->tc_credits_per_period[0],
 513                 p->tc_credits_per_period[1],
 514                 p->tc_credits_per_period[2],
 515                 p->tc_credits_per_period[3],
 516
 517                 /* Traffic class 3 oversubscription */
 518                 p->tc_ov_weight,
 519
 520                 /* WRR */
 521                 p->wrr_cost[ 0], p->wrr_cost[ 1], p->wrr_cost[ 2], p->wrr_cost[ 3],
 522                 p->wrr_cost[ 4], p->wrr_cost[ 5], p->wrr_cost[ 6], p->wrr_cost[ 7],
 523                 p->wrr_cost[ 8], p->wrr_cost[ 9], p->wrr_cost[10], p->wrr_cost[11],
 524                 p->wrr_cost[12], p->wrr_cost[13], p->wrr_cost[14], p->wrr_cost[15]);
 525 }
 526
 527 static inline uint64_t
 528 rte_sched_time_ms_to_bytes(uint32_t time_ms, uint32_t rate)
 529 {
 530         uint64_t time = time_ms;
 531
 532         time = (time * rate) / 1000;
 533
 534         return time;
 535 }
 536
 537 static void
 538 rte_sched_port_config_pipe_profile_table(struct rte_sched_port *port, struct rte_sched_port_params *params)
 539 {
 540         uint32_t i, j;
 541
 542         for (i = 0; i < port->n_pipe_profiles; i++) {
 543                 struct rte_sched_pipe_params *src = params->pipe_profiles + i;
 544                 struct rte_sched_pipe_profile *dst = port->pipe_profiles + i;
 545
 546                 /* Token Bucket */
 547                 if (src->tb_rate == params->rate) {
 548                         dst->tb_credits_per_period = 1;
 549                         dst->tb_period = 1;
 550                 } else {
 551                         double tb_rate = (double) src->tb_rate
 552                                 / (double) params->rate;
 553                         double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
 554
 555                         rte_approx(tb_rate, d,
 556                                    &dst->tb_credits_per_period, &dst->tb_period);
 557                 }
 558                 dst->tb_size = src->tb_size;
 559
 560                 /* Traffic Classes */
 561                 dst->tc_period = rte_sched_time_ms_to_bytes(src->tc_period,
 562                                                             params->rate);
 563
 564                 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++)
 565                         dst->tc_credits_per_period[j]
 566                                 = rte_sched_time_ms_to_bytes(src->tc_period,
 567                                                              src->tc_rate[j]);
 568
 569 #ifdef RTE_SCHED_SUBPORT_TC_OV
 570                 dst->tc_ov_weight = src->tc_ov_weight;
 571 #endif
 572
 573                 /* WRR */
 574                 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
 575                         uint32_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
 576                         uint32_t lcd, lcd1, lcd2;
 577                         uint32_t qindex;
 578
 579                         qindex = j * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS;
 580
 581                         wrr_cost[0] = src->wrr_weights[qindex];
 582                         wrr_cost[1] = src->wrr_weights[qindex + 1];
 583                         wrr_cost[2] = src->wrr_weights[qindex + 2];
 584                         wrr_cost[3] = src->wrr_weights[qindex + 3];
 585
 586                         lcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]);
 587                         lcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]);
 588                         lcd = rte_get_lcd(lcd1, lcd2);
 589
 590                         wrr_cost[0] = lcd / wrr_cost[0];
 591                         wrr_cost[1] = lcd / wrr_cost[1];
 592                         wrr_cost[2] = lcd / wrr_cost[2];
 593                         wrr_cost[3] = lcd / wrr_cost[3];
 594
 595                         dst->wrr_cost[qindex] = (uint8_t) wrr_cost[0];
 596                         dst->wrr_cost[qindex + 1] = (uint8_t) wrr_cost[1];
 597                         dst->wrr_cost[qindex + 2] = (uint8_t) wrr_cost[2];
 598                         dst->wrr_cost[qindex + 3] = (uint8_t) wrr_cost[3];
 599                 }
 600
 601                 rte_sched_port_log_pipe_profile(port, i);
 602         }
 603
 604         port->pipe_tc3_rate_max = 0;
 605         for (i = 0; i < port->n_pipe_profiles; i++) {
 606                 struct rte_sched_pipe_params *src = params->pipe_profiles + i;
 607                 uint32_t pipe_tc3_rate = src->tc_rate[3];
 608
 609                 if (port->pipe_tc3_rate_max < pipe_tc3_rate)
 610                         port->pipe_tc3_rate_max = pipe_tc3_rate;
 611         }
 612 }
 613
 614 struct rte_sched_port *
 615 rte_sched_port_config(struct rte_sched_port_params *params)
 616 {
 617         struct rte_sched_port *port = NULL;
 618         uint32_t mem_size, bmp_mem_size, n_queues_per_port, i;
 619
 620         /* Check user parameters. Determine the amount of memory to allocate */
 621         mem_size = rte_sched_port_get_memory_footprint(params);
 622         if (mem_size == 0)
 623                 return NULL;
 624
 625         /* Allocate memory to store the data structures */
 626         port = rte_zmalloc("qos_params", mem_size, RTE_CACHE_LINE_SIZE);
 627         if (port == NULL)
 628                 return NULL;
 629
 630         /* compile time checks */
 631         RTE_BUILD_BUG_ON(RTE_SCHED_PORT_N_GRINDERS == 0);
 632         RTE_BUILD_BUG_ON(RTE_SCHED_PORT_N_GRINDERS & (RTE_SCHED_PORT_N_GRINDERS - 1));
 633
 634         /* User parameters */
 635         port->n_subports_per_port = params->n_subports_per_port;
 636         port->n_pipes_per_subport = params->n_pipes_per_subport;
 637         port->rate = params->rate;
 638         port->mtu = params->mtu + params->frame_overhead;
 639         port->frame_overhead = params->frame_overhead;
 640         memcpy(port->qsize, params->qsize, sizeof(params->qsize));
 641         port->n_pipe_profiles = params->n_pipe_profiles;
 642
 643 #ifdef RTE_SCHED_RED
 644         for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
 645                 uint32_t j;
 646
 647                 for (j = 0; j < e_RTE_METER_COLORS; j++) {
 648                         /* if min/max are both zero, then RED is disabled */
 649                         if ((params->red_params[i][j].min_th |
 650                              params->red_params[i][j].max_th) == 0) {
 651                                 continue;
 652                         }
 653
 654                         if (rte_red_config_init(&port->red_config[i][j],
 655                                 params->red_params[i][j].wq_log2,
 656                                 params->red_params[i][j].min_th,
 657                                 params->red_params[i][j].max_th,
 658                                 params->red_params[i][j].maxp_inv) != 0) {
 659                                 return NULL;
 660                         }
 661                 }
 662         }
 663 #endif
 664
 665         /* Timing */
 666         port->time_cpu_cycles = rte_get_tsc_cycles();
 667         port->time_cpu_bytes = 0;
 668         port->time = 0;
 669         port->cycles_per_byte = ((double) rte_get_tsc_hz()) / ((double) params->rate);
 670
 671         /* Scheduling loop detection */
 672         port->pipe_loop = RTE_SCHED_PIPE_INVALID;
 673         port->pipe_exhaustion = 0;
 674
 675         /* Grinders */
 676         port->busy_grinders = 0;
 677         port->pkts_out = NULL;
 678         port->n_pkts_out = 0;
 679
 680         /* Queue base calculation */
 681         rte_sched_port_config_qsize(port);
 682
 683         /* Large data structures */
 684         port->subport = (struct rte_sched_subport *)
 685                 (port->memory + rte_sched_port_get_array_base(params,
 686                                                               e_RTE_SCHED_PORT_ARRAY_SUBPORT));
 687         port->pipe = (struct rte_sched_pipe *)
 688                 (port->memory + rte_sched_port_get_array_base(params,
 689                                                               e_RTE_SCHED_PORT_ARRAY_PIPE));
 690         port->queue = (struct rte_sched_queue *)
 691                 (port->memory + rte_sched_port_get_array_base(params,
 692                                                               e_RTE_SCHED_PORT_ARRAY_QUEUE));
 693         port->queue_extra = (struct rte_sched_queue_extra *)
 694                 (port->memory + rte_sched_port_get_array_base(params,
 695                                                               e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA));
 696         port->pipe_profiles = (struct rte_sched_pipe_profile *)
 697                 (port->memory + rte_sched_port_get_array_base(params,
 698                                                               e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES));
 699         port->bmp_array =  port->memory
 700                 + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY);
 701         port->queue_array = (struct rte_mbuf **)
 702                 (port->memory + rte_sched_port_get_array_base(params,
 703                                                               e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY));
 704
 705         /* Pipe profile table */
 706         rte_sched_port_config_pipe_profile_table(port, params);
 707
 708         /* Bitmap */
 709         n_queues_per_port = rte_sched_port_queues_per_port(port);
 710         bmp_mem_size = rte_bitmap_get_memory_footprint(n_queues_per_port);
 711         port->bmp = rte_bitmap_init(n_queues_per_port, port->bmp_array,
 712                                     bmp_mem_size);
 713         if (port->bmp == NULL) {
 714                 RTE_LOG(ERR, SCHED, "Bitmap init error\n");
 715                 return NULL;
 716         }
 717
 718         for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i++)
 719                 port->grinder_base_bmp_pos[i] = RTE_SCHED_PIPE_INVALID;
 720
 721
 722         return port;
 723 }
 724
 725 void
 726 rte_sched_port_free(struct rte_sched_port *port)
 727 {
 728         unsigned int queue;
 729
 730         /* Check user parameters */
 731         if (port == NULL)
 732                 return;
 733
 734         /* Free enqueued mbufs */
 735         for (queue = 0; queue < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; queue++) {
 736                 struct rte_mbuf **mbufs = rte_sched_port_qbase(port, queue);
 737                 unsigned int i;
 738
 739                 for (i = 0; i < rte_sched_port_qsize(port, queue); i++)
 740                         rte_pktmbuf_free(mbufs[i]);
 741         }
 742
 743         rte_bitmap_free(port->bmp);
 744         rte_free(port);
 745 }
 746
 747 static void
 748 rte_sched_port_log_subport_config(struct rte_sched_port *port, uint32_t i)
 749 {
 750         struct rte_sched_subport *s = port->subport + i;
 751
 752         RTE_LOG(DEBUG, SCHED, "Low level config for subport %u:\n"
 753                 "    Token bucket: period = %u, credits per period = %u, size = %u\n"
 754                 "    Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\n"
 755                 "    Traffic class 3 oversubscription: wm min = %u, wm max = %u\n",
 756                 i,
 757
 758                 /* Token bucket */
 759                 s->tb_period,
 760                 s->tb_credits_per_period,
 761                 s->tb_size,
 762
 763                 /* Traffic classes */
 764                 s->tc_period,
 765                 s->tc_credits_per_period[0],
 766                 s->tc_credits_per_period[1],
 767                 s->tc_credits_per_period[2],
 768                 s->tc_credits_per_period[3],
 769
 770                 /* Traffic class 3 oversubscription */
 771                 s->tc_ov_wm_min,
 772                 s->tc_ov_wm_max);
 773 }
 774
 775 int
 776 rte_sched_subport_config(struct rte_sched_port *port,
 777         uint32_t subport_id,
 778         struct rte_sched_subport_params *params)
 779 {
 780         struct rte_sched_subport *s;
 781         uint32_t i;
 782
 783         /* Check user parameters */
 784         if (port == NULL ||
 785             subport_id >= port->n_subports_per_port ||
 786             params == NULL)
 787                 return -1;
 788
 789         if (params->tb_rate == 0 || params->tb_rate > port->rate)
 790                 return -2;
 791
 792         if (params->tb_size == 0)
 793                 return -3;
 794
 795         for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
 796                 if (params->tc_rate[i] == 0 ||
 797                     params->tc_rate[i] > params->tb_rate)
 798                         return -4;
 799         }
 800
 801         if (params->tc_period == 0)
 802                 return -5;
 803
 804         s = port->subport + subport_id;
 805
 806         /* Token Bucket (TB) */
 807         if (params->tb_rate == port->rate) {
 808                 s->tb_credits_per_period = 1;
 809                 s->tb_period = 1;
 810         } else {
 811                 double tb_rate = ((double) params->tb_rate) / ((double) port->rate);
 812                 double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
 813
 814                 rte_approx(tb_rate, d, &s->tb_credits_per_period, &s->tb_period);
 815         }
 816
 817         s->tb_size = params->tb_size;
 818         s->tb_time = port->time;
 819         s->tb_credits = s->tb_size / 2;
 820
 821         /* Traffic Classes (TCs) */
 822         s->tc_period = rte_sched_time_ms_to_bytes(params->tc_period, port->rate);
 823         for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
 824                 s->tc_credits_per_period[i]
 825                         = rte_sched_time_ms_to_bytes(params->tc_period,
 826                                                      params->tc_rate[i]);
 827         }
 828         s->tc_time = port->time + s->tc_period;
 829         for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)
 830                 s->tc_credits[i] = s->tc_credits_per_period[i];
 831
 832 #ifdef RTE_SCHED_SUBPORT_TC_OV
 833         /* TC oversubscription */
 834         s->tc_ov_wm_min = port->mtu;
 835         s->tc_ov_wm_max = rte_sched_time_ms_to_bytes(params->tc_period,
 836                                                      port->pipe_tc3_rate_max);
 837         s->tc_ov_wm = s->tc_ov_wm_max;
 838         s->tc_ov_period_id = 0;
 839         s->tc_ov = 0;
 840         s->tc_ov_n = 0;
 841         s->tc_ov_rate = 0;
 842 #endif
 843
 844         rte_sched_port_log_subport_config(port, subport_id);
 845
 846         return 0;
 847 }
 848
 849 int
 850 rte_sched_pipe_config(struct rte_sched_port *port,
 851         uint32_t subport_id,
 852         uint32_t pipe_id,
 853         int32_t pipe_profile)
 854 {
 855         struct rte_sched_subport *s;
 856         struct rte_sched_pipe *p;
 857         struct rte_sched_pipe_profile *params;
 858         uint32_t deactivate, profile, i;
 859
 860         /* Check user parameters */
 861         profile = (uint32_t) pipe_profile;
 862         deactivate = (pipe_profile < 0);
 863
 864         if (port == NULL ||
 865             subport_id >= port->n_subports_per_port ||
 866             pipe_id >= port->n_pipes_per_subport ||
 867             (!deactivate && profile >= port->n_pipe_profiles))
 868                 return -1;
 869
 870
 871         /* Check that subport configuration is valid */
 872         s = port->subport + subport_id;
 873         if (s->tb_period == 0)
 874                 return -2;
 875
 876         p = port->pipe + (subport_id * port->n_pipes_per_subport + pipe_id);
 877
 878         /* Handle the case when pipe already has a valid configuration */
 879         if (p->tb_time) {
 880                 params = port->pipe_profiles + p->profile;
 881
 882 #ifdef RTE_SCHED_SUBPORT_TC_OV
 883                 double subport_tc3_rate = (double) s->tc_credits_per_period[3]
 884                         / (double) s->tc_period;
 885                 double pipe_tc3_rate = (double) params->tc_credits_per_period[3]
 886                         / (double) params->tc_period;
 887                 uint32_t tc3_ov = s->tc_ov;
 888
 889                 /* Unplug pipe from its subport */
 890                 s->tc_ov_n -= params->tc_ov_weight;
 891                 s->tc_ov_rate -= pipe_tc3_rate;
 892                 s->tc_ov = s->tc_ov_rate > subport_tc3_rate;
 893
 894                 if (s->tc_ov != tc3_ov) {
 895                         RTE_LOG(DEBUG, SCHED,
 896                                 "Subport %u TC3 oversubscription is OFF (%.4lf >= %.4lf)\n",
 897                                 subport_id, subport_tc3_rate, s->tc_ov_rate);
 898                 }
 899 #endif
 900
 901                 /* Reset the pipe */
 902                 memset(p, 0, sizeof(struct rte_sched_pipe));
 903         }
 904
 905         if (deactivate)
 906                 return 0;
 907
 908         /* Apply the new pipe configuration */
 909         p->profile = profile;
 910         params = port->pipe_profiles + p->profile;
 911
 912         /* Token Bucket (TB) */
 913         p->tb_time = port->time;
 914         p->tb_credits = params->tb_size / 2;
 915
 916         /* Traffic Classes (TCs) */
 917         p->tc_time = port->time + params->tc_period;
 918         for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)
 919                 p->tc_credits[i] = params->tc_credits_per_period[i];
 920
 921 #ifdef RTE_SCHED_SUBPORT_TC_OV
 922         {
 923                 /* Subport TC3 oversubscription */
 924                 double subport_tc3_rate = (double) s->tc_credits_per_period[3]
 925                         / (double) s->tc_period;
 926                 double pipe_tc3_rate = (double) params->tc_credits_per_period[3]
 927                         / (double) params->tc_period;
 928                 uint32_t tc3_ov = s->tc_ov;
 929
 930                 s->tc_ov_n += params->tc_ov_weight;
 931                 s->tc_ov_rate += pipe_tc3_rate;
 932                 s->tc_ov = s->tc_ov_rate > subport_tc3_rate;
 933
 934                 if (s->tc_ov != tc3_ov) {
 935                         RTE_LOG(DEBUG, SCHED,
 936                                 "Subport %u TC3 oversubscription is ON (%.4lf < %.4lf)\n",
 937                                 subport_id, subport_tc3_rate, s->tc_ov_rate);
 938                 }
 939                 p->tc_ov_period_id = s->tc_ov_period_id;
 940                 p->tc_ov_credits = s->tc_ov_wm;
 941         }
 942 #endif
 943
 944         return 0;
 945 }
 946
 947 void
 948 rte_sched_port_pkt_write(struct rte_mbuf *pkt,
 949                          uint32_t subport, uint32_t pipe, uint32_t traffic_class,
 950                          uint32_t queue, enum rte_meter_color color)
 951 {
 952         struct rte_sched_port_hierarchy *sched
 953                 = (struct rte_sched_port_hierarchy *) &pkt->hash.sched;
 954
 955         RTE_BUILD_BUG_ON(sizeof(*sched) > sizeof(pkt->hash.sched));
 956
 957         sched->color = (uint32_t) color;
 958         sched->subport = subport;
 959         sched->pipe = pipe;
 960         sched->traffic_class = traffic_class;
 961         sched->queue = queue;
 962 }
 963
 964 void
 965 rte_sched_port_pkt_read_tree_path(const struct rte_mbuf *pkt,
 966                                   uint32_t *subport, uint32_t *pipe,
 967                                   uint32_t *traffic_class, uint32_t *queue)
 968 {
 969         const struct rte_sched_port_hierarchy *sched
 970                 = (const struct rte_sched_port_hierarchy *) &pkt->hash.sched;
 971
 972         *subport = sched->subport;
 973         *pipe = sched->pipe;
 974         *traffic_class = sched->traffic_class;
 975         *queue = sched->queue;
 976 }
 977
 978 enum rte_meter_color
 979 rte_sched_port_pkt_read_color(const struct rte_mbuf *pkt)
 980 {
 981         const struct rte_sched_port_hierarchy *sched
 982                 = (const struct rte_sched_port_hierarchy *) &pkt->hash.sched;
 983
 984         return (enum rte_meter_color) sched->color;
 985 }
 986
 987 int
 988 rte_sched_subport_read_stats(struct rte_sched_port *port,
 989                              uint32_t subport_id,
 990                              struct rte_sched_subport_stats *stats,
 991                              uint32_t *tc_ov)
 992 {
 993         struct rte_sched_subport *s;
 994
 995         /* Check user parameters */
 996         if (port == NULL || subport_id >= port->n_subports_per_port ||
 997             stats == NULL || tc_ov == NULL)
 998                 return -1;
 999
1000         s = port->subport + subport_id;
1001
1002         /* Copy subport stats and clear */
1003         memcpy(stats, &s->stats, sizeof(struct rte_sched_subport_stats));
1004         memset(&s->stats, 0, sizeof(struct rte_sched_subport_stats));
1005
1006         /* Subport TC ovesubscription status */
1007         *tc_ov = s->tc_ov;
1008
1009         return 0;
1010 }
1011
1012 int
1013 rte_sched_queue_read_stats(struct rte_sched_port *port,
1014         uint32_t queue_id,
1015         struct rte_sched_queue_stats *stats,
1016         uint16_t *qlen)
1017 {
1018         struct rte_sched_queue *q;
1019         struct rte_sched_queue_extra *qe;
1020
1021         /* Check user parameters */
1022         if ((port == NULL) ||
1023             (queue_id >= rte_sched_port_queues_per_port(port)) ||
1024                 (stats == NULL) ||
1025                 (qlen == NULL)) {
1026                 return -1;
1027         }
1028         q = port->queue + queue_id;
1029         qe = port->queue_extra + queue_id;
1030
1031         /* Copy queue stats and clear */
1032         memcpy(stats, &qe->stats, sizeof(struct rte_sched_queue_stats));
1033         memset(&qe->stats, 0, sizeof(struct rte_sched_queue_stats));
1034
1035         /* Queue length */
1036         *qlen = q->qw - q->qr;
1037
1038         return 0;
1039 }
1040
1041 static inline uint32_t
1042 rte_sched_port_qindex(struct rte_sched_port *port, uint32_t subport, uint32_t pipe, uint32_t traffic_class, uint32_t queue)
1043 {
1044         uint32_t result;
1045
1046         result = subport * port->n_pipes_per_subport + pipe;
1047         result = result * RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE + traffic_class;
1048         result = result * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS + queue;
1049
1050         return result;
1051 }
1052
1053 #ifdef RTE_SCHED_DEBUG
1054
1055 static inline int
1056 rte_sched_port_queue_is_empty(struct rte_sched_port *port, uint32_t qindex)
1057 {
1058         struct rte_sched_queue *queue = port->queue + qindex;
1059
1060         return queue->qr == queue->qw;
1061 }
1062
1063 #endif /* RTE_SCHED_DEBUG */
1064
1065 #ifdef RTE_SCHED_COLLECT_STATS
1066
1067 static inline void
1068 rte_sched_port_update_subport_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1069 {
1070         struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1071         uint32_t tc_index = (qindex >> 2) & 0x3;
1072         uint32_t pkt_len = pkt->pkt_len;
1073
1074         s->stats.n_pkts_tc[tc_index] += 1;
1075         s->stats.n_bytes_tc[tc_index] += pkt_len;
1076 }
1077
1078 static inline void
1079 rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port,
1080                                             uint32_t qindex,
1081                                             struct rte_mbuf *pkt, uint32_t red)
1082 {
1083         struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1084         uint32_t tc_index = (qindex >> 2) & 0x3;
1085         uint32_t pkt_len = pkt->pkt_len;
1086
1087         s->stats.n_pkts_tc_dropped[tc_index] += 1;
1088         s->stats.n_bytes_tc_dropped[tc_index] += pkt_len;
1089 #ifdef RTE_SCHED_RED
1090         s->stats.n_pkts_red_dropped[tc_index] += red;
1091 #endif
1092 }
1093
1094 static inline void
1095 rte_sched_port_update_queue_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1096 {
1097         struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1098         uint32_t pkt_len = pkt->pkt_len;
1099
1100         qe->stats.n_pkts += 1;
1101         qe->stats.n_bytes += pkt_len;
1102 }
1103
1104 static inline void
1105 rte_sched_port_update_queue_stats_on_drop(struct rte_sched_port *port,
1106                                           uint32_t qindex,
1107                                           struct rte_mbuf *pkt, uint32_t red)
1108 {
1109         struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1110         uint32_t pkt_len = pkt->pkt_len;
1111
1112         qe->stats.n_pkts_dropped += 1;
1113         qe->stats.n_bytes_dropped += pkt_len;
1114 #ifdef RTE_SCHED_RED
1115         qe->stats.n_pkts_red_dropped += red;
1116 #endif
1117 }
1118
1119 #endif /* RTE_SCHED_COLLECT_STATS */
1120
1121 #ifdef RTE_SCHED_RED
1122
1123 static inline int
1124 rte_sched_port_red_drop(struct rte_sched_port *port, struct rte_mbuf *pkt, uint32_t qindex, uint16_t qlen)
1125 {
1126         struct rte_sched_queue_extra *qe;
1127         struct rte_red_config *red_cfg;
1128         struct rte_red *red;
1129         uint32_t tc_index;
1130         enum rte_meter_color color;
1131
1132         tc_index = (qindex >> 2) & 0x3;
1133         color = rte_sched_port_pkt_read_color(pkt);
1134         red_cfg = &port->red_config[tc_index][color];
1135
1136         if ((red_cfg->min_th | red_cfg->max_th) == 0)
1137                 return 0;
1138
1139         qe = port->queue_extra + qindex;
1140         red = &qe->red;
1141
1142         return rte_red_enqueue(red_cfg, red, qlen, port->time);
1143 }
1144
1145 static inline void
1146 rte_sched_port_set_queue_empty_timestamp(struct rte_sched_port *port, uint32_t qindex)
1147 {
1148         struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1149         struct rte_red *red = &qe->red;
1150
1151         rte_red_mark_queue_empty(red, port->time);
1152 }
1153
1154 #else
1155
1156 #define rte_sched_port_red_drop(port, pkt, qindex, qlen)             0
1157
1158 #define rte_sched_port_set_queue_empty_timestamp(port, qindex)
1159
1160 #endif /* RTE_SCHED_RED */
1161
1162 #ifdef RTE_SCHED_DEBUG
1163
1164 static inline void
1165 debug_check_queue_slab(struct rte_sched_port *port, uint32_t bmp_pos,
1166                        uint64_t bmp_slab)
1167 {
1168         uint64_t mask;
1169         uint32_t i, panic;
1170
1171         if (bmp_slab == 0)
1172                 rte_panic("Empty slab at position %u\n", bmp_pos);
1173
1174         panic = 0;
1175         for (i = 0, mask = 1; i < 64; i++, mask <<= 1) {
1176                 if (mask & bmp_slab) {
1177                         if (rte_sched_port_queue_is_empty(port, bmp_pos + i)) {
1178                                 printf("Queue %u (slab offset %u) is empty\n", bmp_pos + i, i);
1179                                 panic = 1;
1180                         }
1181                 }
1182         }
1183
1184         if (panic)
1185                 rte_panic("Empty queues in slab 0x%" PRIx64 "starting at position %u\n",
1186                         bmp_slab, bmp_pos);
1187 }
1188
1189 #endif /* RTE_SCHED_DEBUG */
1190
1191 static inline uint32_t
1192 rte_sched_port_enqueue_qptrs_prefetch0(struct rte_sched_port *port,
1193                                        struct rte_mbuf *pkt)
1194 {
1195         struct rte_sched_queue *q;
1196 #ifdef RTE_SCHED_COLLECT_STATS
1197         struct rte_sched_queue_extra *qe;
1198 #endif
1199         uint32_t subport, pipe, traffic_class, queue, qindex;
1200
1201         rte_sched_port_pkt_read_tree_path(pkt, &subport, &pipe, &traffic_class, &queue);
1202
1203         qindex = rte_sched_port_qindex(port, subport, pipe, traffic_class, queue);
1204         q = port->queue + qindex;
1205         rte_prefetch0(q);
1206 #ifdef RTE_SCHED_COLLECT_STATS
1207         qe = port->queue_extra + qindex;
1208         rte_prefetch0(qe);
1209 #endif
1210
1211         return qindex;
1212 }
1213
1214 static inline void
1215 rte_sched_port_enqueue_qwa_prefetch0(struct rte_sched_port *port,
1216                                      uint32_t qindex, struct rte_mbuf **qbase)
1217 {
1218         struct rte_sched_queue *q;
1219         struct rte_mbuf **q_qw;
1220         uint16_t qsize;
1221
1222         q = port->queue + qindex;
1223         qsize = rte_sched_port_qsize(port, qindex);
1224         q_qw = qbase + (q->qw & (qsize - 1));
1225
1226         rte_prefetch0(q_qw);
1227         rte_bitmap_prefetch0(port->bmp, qindex);
1228 }
1229
1230 static inline int
1231 rte_sched_port_enqueue_qwa(struct rte_sched_port *port, uint32_t qindex,
1232                            struct rte_mbuf **qbase, struct rte_mbuf *pkt)
1233 {
1234         struct rte_sched_queue *q;
1235         uint16_t qsize;
1236         uint16_t qlen;
1237
1238         q = port->queue + qindex;
1239         qsize = rte_sched_port_qsize(port, qindex);
1240         qlen = q->qw - q->qr;
1241
1242         /* Drop the packet (and update drop stats) when queue is full */
1243         if (unlikely(rte_sched_port_red_drop(port, pkt, qindex, qlen) ||
1244                      (qlen >= qsize))) {
1245                 rte_pktmbuf_free(pkt);
1246 #ifdef RTE_SCHED_COLLECT_STATS
1247                 rte_sched_port_update_subport_stats_on_drop(port, qindex, pkt,
1248                                                             qlen < qsize);
1249                 rte_sched_port_update_queue_stats_on_drop(port, qindex, pkt,
1250                                                           qlen < qsize);
1251 #endif
1252                 return 0;
1253         }
1254
1255         /* Enqueue packet */
1256         qbase[q->qw & (qsize - 1)] = pkt;
1257         q->qw++;
1258
1259         /* Activate queue in the port bitmap */
1260         rte_bitmap_set(port->bmp, qindex);
1261
1262         /* Statistics */
1263 #ifdef RTE_SCHED_COLLECT_STATS
1264         rte_sched_port_update_subport_stats(port, qindex, pkt);
1265         rte_sched_port_update_queue_stats(port, qindex, pkt);
1266 #endif
1267
1268         return 1;
1269 }
1270
1271
1272 /*
1273  * The enqueue function implements a 4-level pipeline with each stage
1274  * processing two different packets. The purpose of using a pipeline
1275  * is to hide the latency of prefetching the data structures. The
1276  * naming convention is presented in the diagram below:
1277  *
1278  *   p00  _______   p10  _______   p20  _______   p30  _______
1279  * ----->|       |----->|       |----->|       |----->|       |----->
1280  *       |   0   |      |   1   |      |   2   |      |   3   |
1281  * ----->|_______|----->|_______|----->|_______|----->|_______|----->
1282  *   p01            p11            p21            p31
1283  *
1284  */
1285 int
1286 rte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts,
1287                        uint32_t n_pkts)
1288 {
1289         struct rte_mbuf *pkt00, *pkt01, *pkt10, *pkt11, *pkt20, *pkt21,
1290                 *pkt30, *pkt31, *pkt_last;
1291         struct rte_mbuf **q00_base, **q01_base, **q10_base, **q11_base,
1292                 **q20_base, **q21_base, **q30_base, **q31_base, **q_last_base;
1293         uint32_t q00, q01, q10, q11, q20, q21, q30, q31, q_last;
1294         uint32_t r00, r01, r10, r11, r20, r21, r30, r31, r_last;
1295         uint32_t result, i;
1296
1297         result = 0;
1298
1299         /*
1300          * Less then 6 input packets available, which is not enough to
1301          * feed the pipeline
1302          */
1303         if (unlikely(n_pkts < 6)) {
1304                 struct rte_mbuf **q_base[5];
1305                 uint32_t q[5];
1306
1307                 /* Prefetch the mbuf structure of each packet */
1308                 for (i = 0; i < n_pkts; i++)
1309                         rte_prefetch0(pkts[i]);
1310
1311                 /* Prefetch the queue structure for each queue */
1312                 for (i = 0; i < n_pkts; i++)
1313                         q[i] = rte_sched_port_enqueue_qptrs_prefetch0(port,
1314                                                                       pkts[i]);
1315
1316                 /* Prefetch the write pointer location of each queue */
1317                 for (i = 0; i < n_pkts; i++) {
1318                         q_base[i] = rte_sched_port_qbase(port, q[i]);
1319                         rte_sched_port_enqueue_qwa_prefetch0(port, q[i],
1320                                                              q_base[i]);
1321                 }
1322
1323                 /* Write each packet to its queue */
1324                 for (i = 0; i < n_pkts; i++)
1325                         result += rte_sched_port_enqueue_qwa(port, q[i],
1326                                                              q_base[i], pkts[i]);
1327
1328                 return result;
1329         }
1330
1331         /* Feed the first 3 stages of the pipeline (6 packets needed) */
1332         pkt20 = pkts[0];
1333         pkt21 = pkts[1];
1334         rte_prefetch0(pkt20);
1335         rte_prefetch0(pkt21);
1336
1337         pkt10 = pkts[2];
1338         pkt11 = pkts[3];
1339         rte_prefetch0(pkt10);
1340         rte_prefetch0(pkt11);
1341
1342         q20 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt20);
1343         q21 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt21);
1344
1345         pkt00 = pkts[4];
1346         pkt01 = pkts[5];
1347         rte_prefetch0(pkt00);
1348         rte_prefetch0(pkt01);
1349
1350         q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1351         q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1352
1353         q20_base = rte_sched_port_qbase(port, q20);
1354         q21_base = rte_sched_port_qbase(port, q21);
1355         rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1356         rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1357
1358         /* Run the pipeline */
1359         for (i = 6; i < (n_pkts & (~1)); i += 2) {
1360                 /* Propagate stage inputs */
1361                 pkt30 = pkt20;
1362                 pkt31 = pkt21;
1363                 pkt20 = pkt10;
1364                 pkt21 = pkt11;
1365                 pkt10 = pkt00;
1366                 pkt11 = pkt01;
1367                 q30 = q20;
1368                 q31 = q21;
1369                 q20 = q10;
1370                 q21 = q11;
1371                 q30_base = q20_base;
1372                 q31_base = q21_base;
1373
1374                 /* Stage 0: Get packets in */
1375                 pkt00 = pkts[i];
1376                 pkt01 = pkts[i + 1];
1377                 rte_prefetch0(pkt00);
1378                 rte_prefetch0(pkt01);
1379
1380                 /* Stage 1: Prefetch queue structure storing queue pointers */
1381                 q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1382                 q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1383
1384                 /* Stage 2: Prefetch queue write location */
1385                 q20_base = rte_sched_port_qbase(port, q20);
1386                 q21_base = rte_sched_port_qbase(port, q21);
1387                 rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1388                 rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1389
1390                 /* Stage 3: Write packet to queue and activate queue */
1391                 r30 = rte_sched_port_enqueue_qwa(port, q30, q30_base, pkt30);
1392                 r31 = rte_sched_port_enqueue_qwa(port, q31, q31_base, pkt31);
1393                 result += r30 + r31;
1394         }
1395
1396         /*
1397          * Drain the pipeline (exactly 6 packets).
1398          * Handle the last packet in the case
1399          * of an odd number of input packets.
1400          */
1401         pkt_last = pkts[n_pkts - 1];
1402         rte_prefetch0(pkt_last);
1403
1404         q00 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt00);
1405         q01 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt01);
1406
1407         q10_base = rte_sched_port_qbase(port, q10);
1408         q11_base = rte_sched_port_qbase(port, q11);
1409         rte_sched_port_enqueue_qwa_prefetch0(port, q10, q10_base);
1410         rte_sched_port_enqueue_qwa_prefetch0(port, q11, q11_base);
1411
1412         r20 = rte_sched_port_enqueue_qwa(port, q20, q20_base, pkt20);
1413         r21 = rte_sched_port_enqueue_qwa(port, q21, q21_base, pkt21);
1414         result += r20 + r21;
1415
1416         q_last = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt_last);
1417
1418         q00_base = rte_sched_port_qbase(port, q00);
1419         q01_base = rte_sched_port_qbase(port, q01);
1420         rte_sched_port_enqueue_qwa_prefetch0(port, q00, q00_base);
1421         rte_sched_port_enqueue_qwa_prefetch0(port, q01, q01_base);
1422
1423         r10 = rte_sched_port_enqueue_qwa(port, q10, q10_base, pkt10);
1424         r11 = rte_sched_port_enqueue_qwa(port, q11, q11_base, pkt11);
1425         result += r10 + r11;
1426
1427         q_last_base = rte_sched_port_qbase(port, q_last);
1428         rte_sched_port_enqueue_qwa_prefetch0(port, q_last, q_last_base);
1429
1430         r00 = rte_sched_port_enqueue_qwa(port, q00, q00_base, pkt00);
1431         r01 = rte_sched_port_enqueue_qwa(port, q01, q01_base, pkt01);
1432         result += r00 + r01;
1433
1434         if (n_pkts & 1) {
1435                 r_last = rte_sched_port_enqueue_qwa(port, q_last, q_last_base, pkt_last);
1436                 result += r_last;
1437         }
1438
1439         return result;
1440 }
1441
1442 #ifndef RTE_SCHED_SUBPORT_TC_OV
1443
1444 static inline void
1445 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1446 {
1447         struct rte_sched_grinder *grinder = port->grinder + pos;
1448         struct rte_sched_subport *subport = grinder->subport;
1449         struct rte_sched_pipe *pipe = grinder->pipe;
1450         struct rte_sched_pipe_profile *params = grinder->pipe_params;
1451         uint64_t n_periods;
1452
1453         /* Subport TB */
1454         n_periods = (port->time - subport->tb_time) / subport->tb_period;
1455         subport->tb_credits += n_periods * subport->tb_credits_per_period;
1456         subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1457         subport->tb_time += n_periods * subport->tb_period;
1458
1459         /* Pipe TB */
1460         n_periods = (port->time - pipe->tb_time) / params->tb_period;
1461         pipe->tb_credits += n_periods * params->tb_credits_per_period;
1462         pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1463         pipe->tb_time += n_periods * params->tb_period;
1464
1465         /* Subport TCs */
1466         if (unlikely(port->time >= subport->tc_time)) {
1467                 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1468                 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1469                 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1470                 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1471                 subport->tc_time = port->time + subport->tc_period;
1472         }
1473
1474         /* Pipe TCs */
1475         if (unlikely(port->time >= pipe->tc_time)) {
1476                 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1477                 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1478                 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1479                 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1480                 pipe->tc_time = port->time + params->tc_period;
1481         }
1482 }
1483
1484 #else
1485
1486 static inline uint32_t
1487 grinder_tc_ov_credits_update(struct rte_sched_port *port, uint32_t pos)
1488 {
1489         struct rte_sched_grinder *grinder = port->grinder + pos;
1490         struct rte_sched_subport *subport = grinder->subport;
1491         uint32_t tc_ov_consumption[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
1492         uint32_t tc_ov_consumption_max;
1493         uint32_t tc_ov_wm = subport->tc_ov_wm;
1494
1495         if (subport->tc_ov == 0)
1496                 return subport->tc_ov_wm_max;
1497
1498         tc_ov_consumption[0] = subport->tc_credits_per_period[0] - subport->tc_credits[0];
1499         tc_ov_consumption[1] = subport->tc_credits_per_period[1] - subport->tc_credits[1];
1500         tc_ov_consumption[2] = subport->tc_credits_per_period[2] - subport->tc_credits[2];
1501         tc_ov_consumption[3] = subport->tc_credits_per_period[3] - subport->tc_credits[3];
1502
1503         tc_ov_consumption_max = subport->tc_credits_per_period[3] -
1504                 (tc_ov_consumption[0] + tc_ov_consumption[1] + tc_ov_consumption[2]);
1505
1506         if (tc_ov_consumption[3] > (tc_ov_consumption_max - port->mtu)) {
1507                 tc_ov_wm  -= tc_ov_wm >> 7;
1508                 if (tc_ov_wm < subport->tc_ov_wm_min)
1509                         tc_ov_wm = subport->tc_ov_wm_min;
1510
1511                 return tc_ov_wm;
1512         }
1513
1514         tc_ov_wm += (tc_ov_wm >> 7) + 1;
1515         if (tc_ov_wm > subport->tc_ov_wm_max)
1516                 tc_ov_wm = subport->tc_ov_wm_max;
1517
1518         return tc_ov_wm;
1519 }
1520
1521 static inline void
1522 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1523 {
1524         struct rte_sched_grinder *grinder = port->grinder + pos;
1525         struct rte_sched_subport *subport = grinder->subport;
1526         struct rte_sched_pipe *pipe = grinder->pipe;
1527         struct rte_sched_pipe_profile *params = grinder->pipe_params;
1528         uint64_t n_periods;
1529
1530         /* Subport TB */
1531         n_periods = (port->time - subport->tb_time) / subport->tb_period;
1532         subport->tb_credits += n_periods * subport->tb_credits_per_period;
1533         subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1534         subport->tb_time += n_periods * subport->tb_period;
1535
1536         /* Pipe TB */
1537         n_periods = (port->time - pipe->tb_time) / params->tb_period;
1538         pipe->tb_credits += n_periods * params->tb_credits_per_period;
1539         pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1540         pipe->tb_time += n_periods * params->tb_period;
1541
1542         /* Subport TCs */
1543         if (unlikely(port->time >= subport->tc_time)) {
1544                 subport->tc_ov_wm = grinder_tc_ov_credits_update(port, pos);
1545
1546                 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1547                 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1548                 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1549                 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1550
1551                 subport->tc_time = port->time + subport->tc_period;
1552                 subport->tc_ov_period_id++;
1553         }
1554
1555         /* Pipe TCs */
1556         if (unlikely(port->time >= pipe->tc_time)) {
1557                 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1558                 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1559                 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1560                 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1561                 pipe->tc_time = port->time + params->tc_period;
1562         }
1563
1564         /* Pipe TCs - Oversubscription */
1565         if (unlikely(pipe->tc_ov_period_id != subport->tc_ov_period_id)) {
1566                 pipe->tc_ov_credits = subport->tc_ov_wm * params->tc_ov_weight;
1567
1568                 pipe->tc_ov_period_id = subport->tc_ov_period_id;
1569         }
1570 }
1571
1572 #endif /* RTE_SCHED_TS_CREDITS_UPDATE, RTE_SCHED_SUBPORT_TC_OV */
1573
1574
1575 #ifndef RTE_SCHED_SUBPORT_TC_OV
1576
1577 static inline int
1578 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1579 {
1580         struct rte_sched_grinder *grinder = port->grinder + pos;
1581         struct rte_sched_subport *subport = grinder->subport;
1582         struct rte_sched_pipe *pipe = grinder->pipe;
1583         struct rte_mbuf *pkt = grinder->pkt;
1584         uint32_t tc_index = grinder->tc_index;
1585         uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1586         uint32_t subport_tb_credits = subport->tb_credits;
1587         uint32_t subport_tc_credits = subport->tc_credits[tc_index];
1588         uint32_t pipe_tb_credits = pipe->tb_credits;
1589         uint32_t pipe_tc_credits = pipe->tc_credits[tc_index];
1590         int enough_credits;
1591
1592         /* Check queue credits */
1593         enough_credits = (pkt_len <= subport_tb_credits) &&
1594                 (pkt_len <= subport_tc_credits) &&
1595                 (pkt_len <= pipe_tb_credits) &&
1596                 (pkt_len <= pipe_tc_credits);
1597
1598         if (!enough_credits)
1599                 return 0;
1600
1601         /* Update port credits */
1602         subport->tb_credits -= pkt_len;
1603         subport->tc_credits[tc_index] -= pkt_len;
1604         pipe->tb_credits -= pkt_len;
1605         pipe->tc_credits[tc_index] -= pkt_len;
1606
1607         return 1;
1608 }
1609
1610 #else
1611
1612 static inline int
1613 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1614 {
1615         struct rte_sched_grinder *grinder = port->grinder + pos;
1616         struct rte_sched_subport *subport = grinder->subport;
1617         struct rte_sched_pipe *pipe = grinder->pipe;
1618         struct rte_mbuf *pkt = grinder->pkt;
1619         uint32_t tc_index = grinder->tc_index;
1620         uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1621         uint32_t subport_tb_credits = subport->tb_credits;
1622         uint32_t subport_tc_credits = subport->tc_credits[tc_index];
1623         uint32_t pipe_tb_credits = pipe->tb_credits;
1624         uint32_t pipe_tc_credits = pipe->tc_credits[tc_index];
1625         uint32_t pipe_tc_ov_mask1[] = {UINT32_MAX, UINT32_MAX, UINT32_MAX, pipe->tc_ov_credits};
1626         uint32_t pipe_tc_ov_mask2[] = {0, 0, 0, UINT32_MAX};
1627         uint32_t pipe_tc_ov_credits = pipe_tc_ov_mask1[tc_index];
1628         int enough_credits;
1629
1630         /* Check pipe and subport credits */
1631         enough_credits = (pkt_len <= subport_tb_credits) &&
1632                 (pkt_len <= subport_tc_credits) &&
1633                 (pkt_len <= pipe_tb_credits) &&
1634                 (pkt_len <= pipe_tc_credits) &&
1635                 (pkt_len <= pipe_tc_ov_credits);
1636
1637         if (!enough_credits)
1638                 return 0;
1639
1640         /* Update pipe and subport credits */
1641         subport->tb_credits -= pkt_len;
1642         subport->tc_credits[tc_index] -= pkt_len;
1643         pipe->tb_credits -= pkt_len;
1644         pipe->tc_credits[tc_index] -= pkt_len;
1645         pipe->tc_ov_credits -= pipe_tc_ov_mask2[tc_index] & pkt_len;
1646
1647         return 1;
1648 }
1649
1650 #endif /* RTE_SCHED_SUBPORT_TC_OV */
1651
1652
1653 static inline int
1654 grinder_schedule(struct rte_sched_port *port, uint32_t pos)
1655 {
1656         struct rte_sched_grinder *grinder = port->grinder + pos;
1657         struct rte_sched_queue *queue = grinder->queue[grinder->qpos];
1658         struct rte_mbuf *pkt = grinder->pkt;
1659         uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1660
1661         if (!grinder_credits_check(port, pos))
1662                 return 0;
1663
1664         /* Advance port time */
1665         port->time += pkt_len;
1666
1667         /* Send packet */
1668         port->pkts_out[port->n_pkts_out++] = pkt;
1669         queue->qr++;
1670         grinder->wrr_tokens[grinder->qpos] += pkt_len * grinder->wrr_cost[grinder->qpos];
1671         if (queue->qr == queue->qw) {
1672                 uint32_t qindex = grinder->qindex[grinder->qpos];
1673
1674                 rte_bitmap_clear(port->bmp, qindex);
1675                 grinder->qmask &= ~(1 << grinder->qpos);
1676                 grinder->wrr_mask[grinder->qpos] = 0;
1677                 rte_sched_port_set_queue_empty_timestamp(port, qindex);
1678         }
1679
1680         /* Reset pipe loop detection */
1681         port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1682         grinder->productive = 1;
1683
1684         return 1;
1685 }
1686
1687 #ifdef SCHED_VECTOR_SSE4
1688
1689 static inline int
1690 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1691 {
1692         __m128i index = _mm_set1_epi32(base_pipe);
1693         __m128i pipes = _mm_load_si128((__m128i *)port->grinder_base_bmp_pos);
1694         __m128i res = _mm_cmpeq_epi32(pipes, index);
1695
1696         pipes = _mm_load_si128((__m128i *)(port->grinder_base_bmp_pos + 4));
1697         pipes = _mm_cmpeq_epi32(pipes, index);
1698         res = _mm_or_si128(res, pipes);
1699
1700         if (_mm_testz_si128(res, res))
1701                 return 0;
1702
1703         return 1;
1704 }
1705
1706 #else
1707
1708 static inline int
1709 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1710 {
1711         uint32_t i;
1712
1713         for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i++) {
1714                 if (port->grinder_base_bmp_pos[i] == base_pipe)
1715                         return 1;
1716         }
1717
1718         return 0;
1719 }
1720
1721 #endif /* RTE_SCHED_OPTIMIZATIONS */
1722
1723 static inline void
1724 grinder_pcache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t bmp_pos, uint64_t bmp_slab)
1725 {
1726         struct rte_sched_grinder *grinder = port->grinder + pos;
1727         uint16_t w[4];
1728
1729         grinder->pcache_w = 0;
1730         grinder->pcache_r = 0;
1731
1732         w[0] = (uint16_t) bmp_slab;
1733         w[1] = (uint16_t) (bmp_slab >> 16);
1734         w[2] = (uint16_t) (bmp_slab >> 32);
1735         w[3] = (uint16_t) (bmp_slab >> 48);
1736
1737         grinder->pcache_qmask[grinder->pcache_w] = w[0];
1738         grinder->pcache_qindex[grinder->pcache_w] = bmp_pos;
1739         grinder->pcache_w += (w[0] != 0);
1740
1741         grinder->pcache_qmask[grinder->pcache_w] = w[1];
1742         grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 16;
1743         grinder->pcache_w += (w[1] != 0);
1744
1745         grinder->pcache_qmask[grinder->pcache_w] = w[2];
1746         grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 32;
1747         grinder->pcache_w += (w[2] != 0);
1748
1749         grinder->pcache_qmask[grinder->pcache_w] = w[3];
1750         grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 48;
1751         grinder->pcache_w += (w[3] != 0);
1752 }
1753
1754 static inline void
1755 grinder_tccache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t qindex, uint16_t qmask)
1756 {
1757         struct rte_sched_grinder *grinder = port->grinder + pos;
1758         uint8_t b[4];
1759
1760         grinder->tccache_w = 0;
1761         grinder->tccache_r = 0;
1762
1763         b[0] = (uint8_t) (qmask & 0xF);
1764         b[1] = (uint8_t) ((qmask >> 4) & 0xF);
1765         b[2] = (uint8_t) ((qmask >> 8) & 0xF);
1766         b[3] = (uint8_t) ((qmask >> 12) & 0xF);
1767
1768         grinder->tccache_qmask[grinder->tccache_w] = b[0];
1769         grinder->tccache_qindex[grinder->tccache_w] = qindex;
1770         grinder->tccache_w += (b[0] != 0);
1771
1772         grinder->tccache_qmask[grinder->tccache_w] = b[1];
1773         grinder->tccache_qindex[grinder->tccache_w] = qindex + 4;
1774         grinder->tccache_w += (b[1] != 0);
1775
1776         grinder->tccache_qmask[grinder->tccache_w] = b[2];
1777         grinder->tccache_qindex[grinder->tccache_w] = qindex + 8;
1778         grinder->tccache_w += (b[2] != 0);
1779
1780         grinder->tccache_qmask[grinder->tccache_w] = b[3];
1781         grinder->tccache_qindex[grinder->tccache_w] = qindex + 12;
1782         grinder->tccache_w += (b[3] != 0);
1783 }
1784
1785 static inline int
1786 grinder_next_tc(struct rte_sched_port *port, uint32_t pos)
1787 {
1788         struct rte_sched_grinder *grinder = port->grinder + pos;
1789         struct rte_mbuf **qbase;
1790         uint32_t qindex;
1791         uint16_t qsize;
1792
1793         if (grinder->tccache_r == grinder->tccache_w)
1794                 return 0;
1795
1796         qindex = grinder->tccache_qindex[grinder->tccache_r];
1797         qbase = rte_sched_port_qbase(port, qindex);
1798         qsize = rte_sched_port_qsize(port, qindex);
1799
1800         grinder->tc_index = (qindex >> 2) & 0x3;
1801         grinder->qmask = grinder->tccache_qmask[grinder->tccache_r];
1802         grinder->qsize = qsize;
1803
1804         grinder->qindex[0] = qindex;
1805         grinder->qindex[1] = qindex + 1;
1806         grinder->qindex[2] = qindex + 2;
1807         grinder->qindex[3] = qindex + 3;
1808
1809         grinder->queue[0] = port->queue + qindex;
1810         grinder->queue[1] = port->queue + qindex + 1;
1811         grinder->queue[2] = port->queue + qindex + 2;
1812         grinder->queue[3] = port->queue + qindex + 3;
1813
1814         grinder->qbase[0] = qbase;
1815         grinder->qbase[1] = qbase + qsize;
1816         grinder->qbase[2] = qbase + 2 * qsize;
1817         grinder->qbase[3] = qbase + 3 * qsize;
1818
1819         grinder->tccache_r++;
1820         return 1;
1821 }
1822
1823 static inline int
1824 grinder_next_pipe(struct rte_sched_port *port, uint32_t pos)
1825 {
1826         struct rte_sched_grinder *grinder = port->grinder + pos;
1827         uint32_t pipe_qindex;
1828         uint16_t pipe_qmask;
1829
1830         if (grinder->pcache_r < grinder->pcache_w) {
1831                 pipe_qmask = grinder->pcache_qmask[grinder->pcache_r];
1832                 pipe_qindex = grinder->pcache_qindex[grinder->pcache_r];
1833                 grinder->pcache_r++;
1834         } else {
1835                 uint64_t bmp_slab = 0;
1836                 uint32_t bmp_pos = 0;
1837
1838                 /* Get another non-empty pipe group */
1839                 if (unlikely(rte_bitmap_scan(port->bmp, &bmp_pos, &bmp_slab) <= 0))
1840                         return 0;
1841
1842 #ifdef RTE_SCHED_DEBUG
1843                 debug_check_queue_slab(port, bmp_pos, bmp_slab);
1844 #endif
1845
1846                 /* Return if pipe group already in one of the other grinders */
1847                 port->grinder_base_bmp_pos[pos] = RTE_SCHED_BMP_POS_INVALID;
1848                 if (unlikely(grinder_pipe_exists(port, bmp_pos)))
1849                         return 0;
1850
1851                 port->grinder_base_bmp_pos[pos] = bmp_pos;
1852
1853                 /* Install new pipe group into grinder's pipe cache */
1854                 grinder_pcache_populate(port, pos, bmp_pos, bmp_slab);
1855
1856                 pipe_qmask = grinder->pcache_qmask[0];
1857                 pipe_qindex = grinder->pcache_qindex[0];
1858                 grinder->pcache_r = 1;
1859         }
1860
1861         /* Install new pipe in the grinder */
1862         grinder->pindex = pipe_qindex >> 4;
1863         grinder->subport = port->subport + (grinder->pindex / port->n_pipes_per_subport);
1864         grinder->pipe = port->pipe + grinder->pindex;
1865         grinder->pipe_params = NULL; /* to be set after the pipe structure is prefetched */
1866         grinder->productive = 0;
1867
1868         grinder_tccache_populate(port, pos, pipe_qindex, pipe_qmask);
1869         grinder_next_tc(port, pos);
1870
1871         /* Check for pipe exhaustion */
1872         if (grinder->pindex == port->pipe_loop) {
1873                 port->pipe_exhaustion = 1;
1874                 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1875         }
1876
1877         return 1;
1878 }
1879
1880
1881 static inline void
1882 grinder_wrr_load(struct rte_sched_port *port, uint32_t pos)
1883 {
1884         struct rte_sched_grinder *grinder = port->grinder + pos;
1885         struct rte_sched_pipe *pipe = grinder->pipe;
1886         struct rte_sched_pipe_profile *pipe_params = grinder->pipe_params;
1887         uint32_t tc_index = grinder->tc_index;
1888         uint32_t qmask = grinder->qmask;
1889         uint32_t qindex;
1890
1891         qindex = tc_index * 4;
1892
1893         grinder->wrr_tokens[0] = ((uint16_t) pipe->wrr_tokens[qindex]) << RTE_SCHED_WRR_SHIFT;
1894         grinder->wrr_tokens[1] = ((uint16_t) pipe->wrr_tokens[qindex + 1]) << RTE_SCHED_WRR_SHIFT;
1895         grinder->wrr_tokens[2] = ((uint16_t) pipe->wrr_tokens[qindex + 2]) << RTE_SCHED_WRR_SHIFT;
1896         grinder->wrr_tokens[3] = ((uint16_t) pipe->wrr_tokens[qindex + 3]) << RTE_SCHED_WRR_SHIFT;
1897
1898         grinder->wrr_mask[0] = (qmask & 0x1) * 0xFFFF;
1899         grinder->wrr_mask[1] = ((qmask >> 1) & 0x1) * 0xFFFF;
1900         grinder->wrr_mask[2] = ((qmask >> 2) & 0x1) * 0xFFFF;
1901         grinder->wrr_mask[3] = ((qmask >> 3) & 0x1) * 0xFFFF;
1902
1903         grinder->wrr_cost[0] = pipe_params->wrr_cost[qindex];
1904         grinder->wrr_cost[1] = pipe_params->wrr_cost[qindex + 1];
1905         grinder->wrr_cost[2] = pipe_params->wrr_cost[qindex + 2];
1906         grinder->wrr_cost[3] = pipe_params->wrr_cost[qindex + 3];
1907 }
1908
1909 static inline void
1910 grinder_wrr_store(struct rte_sched_port *port, uint32_t pos)
1911 {
1912         struct rte_sched_grinder *grinder = port->grinder + pos;
1913         struct rte_sched_pipe *pipe = grinder->pipe;
1914         uint32_t tc_index = grinder->tc_index;
1915         uint32_t qindex;
1916
1917         qindex = tc_index * 4;
1918
1919         pipe->wrr_tokens[qindex] = (grinder->wrr_tokens[0] & grinder->wrr_mask[0])
1920                 >> RTE_SCHED_WRR_SHIFT;
1921         pipe->wrr_tokens[qindex + 1] = (grinder->wrr_tokens[1] & grinder->wrr_mask[1])
1922                 >> RTE_SCHED_WRR_SHIFT;
1923         pipe->wrr_tokens[qindex + 2] = (grinder->wrr_tokens[2] & grinder->wrr_mask[2])
1924                 >> RTE_SCHED_WRR_SHIFT;
1925         pipe->wrr_tokens[qindex + 3] = (grinder->wrr_tokens[3] & grinder->wrr_mask[3])
1926                 >> RTE_SCHED_WRR_SHIFT;
1927 }
1928
1929 static inline void
1930 grinder_wrr(struct rte_sched_port *port, uint32_t pos)
1931 {
1932         struct rte_sched_grinder *grinder = port->grinder + pos;
1933         uint16_t wrr_tokens_min;
1934
1935         grinder->wrr_tokens[0] |= ~grinder->wrr_mask[0];
1936         grinder->wrr_tokens[1] |= ~grinder->wrr_mask[1];
1937         grinder->wrr_tokens[2] |= ~grinder->wrr_mask[2];
1938         grinder->wrr_tokens[3] |= ~grinder->wrr_mask[3];
1939
1940         grinder->qpos = rte_min_pos_4_u16(grinder->wrr_tokens);
1941         wrr_tokens_min = grinder->wrr_tokens[grinder->qpos];
1942
1943         grinder->wrr_tokens[0] -= wrr_tokens_min;
1944         grinder->wrr_tokens[1] -= wrr_tokens_min;
1945         grinder->wrr_tokens[2] -= wrr_tokens_min;
1946         grinder->wrr_tokens[3] -= wrr_tokens_min;
1947 }
1948
1949
1950 #define grinder_evict(port, pos)
1951
1952 static inline void
1953 grinder_prefetch_pipe(struct rte_sched_port *port, uint32_t pos)
1954 {
1955         struct rte_sched_grinder *grinder = port->grinder + pos;
1956
1957         rte_prefetch0(grinder->pipe);
1958         rte_prefetch0(grinder->queue[0]);
1959 }
1960
1961 static inline void
1962 grinder_prefetch_tc_queue_arrays(struct rte_sched_port *port, uint32_t pos)
1963 {
1964         struct rte_sched_grinder *grinder = port->grinder + pos;
1965         uint16_t qsize, qr[4];
1966
1967         qsize = grinder->qsize;
1968         qr[0] = grinder->queue[0]->qr & (qsize - 1);
1969         qr[1] = grinder->queue[1]->qr & (qsize - 1);
1970         qr[2] = grinder->queue[2]->qr & (qsize - 1);
1971         qr[3] = grinder->queue[3]->qr & (qsize - 1);
1972
1973         rte_prefetch0(grinder->qbase[0] + qr[0]);
1974         rte_prefetch0(grinder->qbase[1] + qr[1]);
1975
1976         grinder_wrr_load(port, pos);
1977         grinder_wrr(port, pos);
1978
1979         rte_prefetch0(grinder->qbase[2] + qr[2]);
1980         rte_prefetch0(grinder->qbase[3] + qr[3]);
1981 }
1982
1983 static inline void
1984 grinder_prefetch_mbuf(struct rte_sched_port *port, uint32_t pos)
1985 {
1986         struct rte_sched_grinder *grinder = port->grinder + pos;
1987         uint32_t qpos = grinder->qpos;
1988         struct rte_mbuf **qbase = grinder->qbase[qpos];
1989         uint16_t qsize = grinder->qsize;
1990         uint16_t qr = grinder->queue[qpos]->qr & (qsize - 1);
1991
1992         grinder->pkt = qbase[qr];
1993         rte_prefetch0(grinder->pkt);
1994
1995         if (unlikely((qr & 0x7) == 7)) {
1996                 uint16_t qr_next = (grinder->queue[qpos]->qr + 1) & (qsize - 1);
1997
1998                 rte_prefetch0(qbase + qr_next);
1999         }
2000 }
2001
2002 static inline uint32_t
2003 grinder_handle(struct rte_sched_port *port, uint32_t pos)
2004 {
2005         struct rte_sched_grinder *grinder = port->grinder + pos;
2006
2007         switch (grinder->state) {
2008         case e_GRINDER_PREFETCH_PIPE:
2009         {
2010                 if (grinder_next_pipe(port, pos)) {
2011                         grinder_prefetch_pipe(port, pos);
2012                         port->busy_grinders++;
2013
2014                         grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2015                         return 0;
2016                 }
2017
2018                 return 0;
2019         }
2020
2021         case e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS:
2022         {
2023                 struct rte_sched_pipe *pipe = grinder->pipe;
2024
2025                 grinder->pipe_params = port->pipe_profiles + pipe->profile;
2026                 grinder_prefetch_tc_queue_arrays(port, pos);
2027                 grinder_credits_update(port, pos);
2028
2029                 grinder->state = e_GRINDER_PREFETCH_MBUF;
2030                 return 0;
2031         }
2032
2033         case e_GRINDER_PREFETCH_MBUF:
2034         {
2035                 grinder_prefetch_mbuf(port, pos);
2036
2037                 grinder->state = e_GRINDER_READ_MBUF;
2038                 return 0;
2039         }
2040
2041         case e_GRINDER_READ_MBUF:
2042         {
2043                 uint32_t result = 0;
2044
2045                 result = grinder_schedule(port, pos);
2046
2047                 /* Look for next packet within the same TC */
2048                 if (result && grinder->qmask) {
2049                         grinder_wrr(port, pos);
2050                         grinder_prefetch_mbuf(port, pos);
2051
2052                         return 1;
2053                 }
2054                 grinder_wrr_store(port, pos);
2055
2056                 /* Look for another active TC within same pipe */
2057                 if (grinder_next_tc(port, pos)) {
2058                         grinder_prefetch_tc_queue_arrays(port, pos);
2059
2060                         grinder->state = e_GRINDER_PREFETCH_MBUF;
2061                         return result;
2062                 }
2063
2064                 if (grinder->productive == 0 &&
2065                     port->pipe_loop == RTE_SCHED_PIPE_INVALID)
2066                         port->pipe_loop = grinder->pindex;
2067
2068                 grinder_evict(port, pos);
2069
2070                 /* Look for another active pipe */
2071                 if (grinder_next_pipe(port, pos)) {
2072                         grinder_prefetch_pipe(port, pos);
2073
2074                         grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2075                         return result;
2076                 }
2077
2078                 /* No active pipe found */
2079                 port->busy_grinders--;
2080
2081                 grinder->state = e_GRINDER_PREFETCH_PIPE;
2082                 return result;
2083         }
2084
2085         default:
2086                 rte_panic("Algorithmic error (invalid state)\n");
2087                 return 0;
2088         }
2089 }
2090
2091 static inline void
2092 rte_sched_port_time_resync(struct rte_sched_port *port)
2093 {
2094         uint64_t cycles = rte_get_tsc_cycles();
2095         uint64_t cycles_diff = cycles - port->time_cpu_cycles;
2096         double bytes_diff = ((double) cycles_diff) / port->cycles_per_byte;
2097
2098         /* Advance port time */
2099         port->time_cpu_cycles = cycles;
2100         port->time_cpu_bytes += (uint64_t) bytes_diff;
2101         if (port->time < port->time_cpu_bytes)
2102                 port->time = port->time_cpu_bytes;
2103
2104         /* Reset pipe loop detection */
2105         port->pipe_loop = RTE_SCHED_PIPE_INVALID;
2106 }
2107
2108 static inline int
2109 rte_sched_port_exceptions(struct rte_sched_port *port, int second_pass)
2110 {
2111         int exceptions;
2112
2113         /* Check if any exception flag is set */
2114         exceptions = (second_pass && port->busy_grinders == 0) ||
2115                 (port->pipe_exhaustion == 1);
2116
2117         /* Clear exception flags */
2118         port->pipe_exhaustion = 0;
2119
2120         return exceptions;
2121 }
2122
2123 int
2124 rte_sched_port_dequeue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
2125 {
2126         uint32_t i, count;
2127
2128         port->pkts_out = pkts;
2129         port->n_pkts_out = 0;
2130
2131         rte_sched_port_time_resync(port);
2132
2133         /* Take each queue in the grinder one step further */
2134         for (i = 0, count = 0; ; i++)  {
2135                 count += grinder_handle(port, i & (RTE_SCHED_PORT_N_GRINDERS - 1));
2136                 if ((count == n_pkts) ||
2137                     rte_sched_port_exceptions(port, i >= RTE_SCHED_PORT_N_GRINDERS)) {
2138                         break;
2139                 }
2140         }
2141
2142         return count;
2143 }