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- * modification, are permitted provided that the following conditions
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
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- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
- * * Neither the name of Intel Corporation nor the names of its
- * contributors may be used to endorse or promote products derived
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
static rte_spinlock_t sl, sl_try;
static rte_spinlock_t sl_tab[RTE_MAX_LCORE];
static rte_spinlock_recursive_t slr;
static rte_spinlock_t sl, sl_try;
static rte_spinlock_t sl_tab[RTE_MAX_LCORE];
static rte_spinlock_recursive_t slr;
- uint64_t end, begin;
- begin = rte_get_hpet_cycles();
- unsigned int i = 0;
- for ( i = 0; i < max; i++) {
- rte_spinlock_lock(&lk);
- count1++;
- rte_spinlock_unlock(&lk);
- count2++;
+ uint64_t time_diff = 0, begin;
+ uint64_t hz = rte_get_timer_hz();
+ uint64_t lcount = 0;
+ const int use_lock = *(int*)func_param;
+ const unsigned lcore = rte_lcore_id();
+
+ /* wait synchro for slaves */
+ if (lcore != rte_get_master_lcore())
+ while (rte_atomic32_read(&synchro) == 0);
+
+ begin = rte_get_timer_cycles();
+ while (time_diff / hz < TIME_S) {
+ if (use_lock)
+ rte_spinlock_lock(&lk);
+ lcount++;
+ if (use_lock)
+ rte_spinlock_unlock(&lk);
+ /* delay to make lock duty cycle slighlty realistic */
+ rte_delay_us(1);
+ time_diff = rte_get_timer_cycles() - begin;
- if (rte_lcore_count()<= 1) {
- printf("no cores counted\n");
- return -1;
- }
- printf ("Running %u tests.......\n", max);
- printf ("Number of cores = %u\n", rte_lcore_count());
+ unsigned int i;
+ uint64_t total = 0;
+ int lock = 0;
+ const unsigned lcore = rte_lcore_id();
- rte_eal_mp_remote_launch(load_loop_fn, NULL , CALL_MASTER);
- rte_eal_mp_wait_lcore();
+ printf("\nTest with no lock on single core...\n");
+ load_loop_fn(&lock);
+ printf("Core [%u] count = %"PRIu64"\n", lcore, lock_count[lcore]);
+ memset(lock_count, 0, sizeof(lock_count));
- unsigned int k = 0;
- uint64_t avgtime = 0;
+ printf("\nTest with lock on single core...\n");
+ lock = 1;
+ load_loop_fn(&lock);
+ printf("Core [%u] count = %"PRIu64"\n", lcore, lock_count[lcore]);
+ memset(lock_count, 0, sizeof(lock_count));
- RTE_LCORE_FOREACH(k) {
- printf("Core [%u] time = %"PRIu64"\n", k, looptime[k]);
- avgtime += looptime[k];
- }
+ printf("\nTest with lock on %u cores...\n", rte_lcore_count());
- avgtime = avgtime / rte_lcore_count();
- printf("Average time = %"PRIu64"\n", avgtime);
+ /* Clear synchro and start slaves */
+ rte_atomic32_set(&synchro, 0);
+ rte_eal_mp_remote_launch(load_loop_fn, &lock, SKIP_MASTER);
- int check = 0;
- check = max * rte_lcore_count();
- if (count1 == check && count2 != check)
- printf("Passed Load test\n");
- else {
- printf("Failed load test\n");
- return -1;
+ /* start synchro and launch test on master */
+ rte_atomic32_set(&synchro, 1);
+ load_loop_fn(&lock);
+
+ rte_eal_mp_wait_lcore();
+
+ RTE_LCORE_FOREACH(i) {
+ printf("Core [%u] count = %"PRIu64"\n", i, lock_count[i]);
+ total += lock_count[i];
* Test rte_eal_get_lcore_state() in addition to spinlocks
* as we have "waiting" then "running" lcores.
*/
* Test rte_eal_get_lcore_state() in addition to spinlocks
* as we have "waiting" then "running" lcores.
*/
+
+static struct test_command spinlock_cmd = {
+ .command = "spinlock_autotest",
+ .callback = test_spinlock,
+};
+REGISTER_TEST_COMMAND(spinlock_cmd);