+/*
+ * Function to handle the post processing of the computed
+ * fields for the interface.
+ */
+static void
+bnxt_ulp_comp_fld_intf_update(struct ulp_rte_parser_params *params)
+{
+ uint32_t ifindex;
+ uint16_t port_id, parif;
+ uint32_t mtype;
+ enum bnxt_ulp_direction_type dir;
+
+ /* get the direction details */
+ dir = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_DIRECTION);
+
+ /* read the port id details */
+ port_id = ULP_COMP_FLD_IDX_RD(params,
+ BNXT_ULP_CF_IDX_INCOMING_IF);
+ if (ulp_port_db_dev_port_to_ulp_index(params->ulp_ctx,
+ port_id,
+ &ifindex)) {
+ BNXT_TF_DBG(ERR, "ParseErr:Portid is not valid\n");
+ return;
+ }
+
+ if (dir == BNXT_ULP_DIR_INGRESS) {
+ /* Set port PARIF */
+ if (ulp_port_db_parif_get(params->ulp_ctx, ifindex,
+ BNXT_ULP_PHY_PORT_PARIF, &parif)) {
+ BNXT_TF_DBG(ERR, "ParseErr:ifindex is not valid\n");
+ return;
+ }
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
+ parif);
+ } else {
+ /* Get the match port type */
+ mtype = ULP_COMP_FLD_IDX_RD(params,
+ BNXT_ULP_CF_IDX_MATCH_PORT_TYPE);
+ if (mtype == BNXT_ULP_INTF_TYPE_VF_REP) {
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP,
+ 1);
+ /* Set VF func PARIF */
+ if (ulp_port_db_parif_get(params->ulp_ctx, ifindex,
+ BNXT_ULP_VF_FUNC_PARIF,
+ &parif)) {
+ BNXT_TF_DBG(ERR,
+ "ParseErr:ifindex is not valid\n");
+ return;
+ }
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_VF_FUNC_PARIF,
+ parif);
+ } else {
+ /* Set DRV func PARIF */
+ if (ulp_port_db_parif_get(params->ulp_ctx, ifindex,
+ BNXT_ULP_DRV_FUNC_PARIF,
+ &parif)) {
+ BNXT_TF_DBG(ERR,
+ "ParseErr:ifindex is not valid\n");
+ return;
+ }
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+ parif);
+ }
+ }
+}
+
+/*
+ * Function to handle the post processing of the parsing details
+ */
+int32_t
+bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params)
+{
+ enum bnxt_ulp_direction_type dir;
+ enum bnxt_ulp_intf_type match_port_type, act_port_type;
+ uint32_t act_port_set;
+
+ /* Get the computed details */
+ dir = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_DIRECTION);
+ match_port_type = ULP_COMP_FLD_IDX_RD(params,
+ BNXT_ULP_CF_IDX_MATCH_PORT_TYPE);
+ act_port_type = ULP_COMP_FLD_IDX_RD(params,
+ BNXT_ULP_CF_IDX_ACT_PORT_TYPE);
+ act_port_set = ULP_COMP_FLD_IDX_RD(params,
+ BNXT_ULP_CF_IDX_ACT_PORT_IS_SET);
+
+ /* set the flow direction in the proto and action header */
+ if (dir == BNXT_ULP_DIR_EGRESS) {
+ ULP_BITMAP_SET(params->hdr_bitmap.bits,
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR);
+ ULP_BITMAP_SET(params->act_bitmap.bits,
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR);
+ }
+
+ /* calculate the VF to VF flag */
+ if (act_port_set && act_port_type == BNXT_ULP_INTF_TYPE_VF_REP &&
+ match_port_type == BNXT_ULP_INTF_TYPE_VF_REP)
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_VF_TO_VF, 1);
+
+ /* Update the decrement ttl computational fields */
+ if (ULP_BITMAP_ISSET(params->act_bitmap.bits,
+ BNXT_ULP_ACTION_BIT_DEC_TTL)) {
+ /*
+ * Check that vxlan proto is included and vxlan decap
+ * action is not set then decrement tunnel ttl.
+ * Similarly add GRE and NVGRE in future.
+ */
+ if ((ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+ BNXT_ULP_HDR_BIT_T_VXLAN) &&
+ !ULP_BITMAP_ISSET(params->act_bitmap.bits,
+ BNXT_ULP_ACTION_BIT_VXLAN_DECAP))) {
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL, 1);
+ } else {
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL, 1);
+ }
+ }
+
+ /* Merge the hdr_fp_bit into the proto header bit */
+ params->hdr_bitmap.bits |= params->hdr_fp_bit.bits;
+
+ /* Update the computed interface parameters */
+ bnxt_ulp_comp_fld_intf_update(params);
+
+ /* TBD: Handle the flow rejection scenarios */
+ return 0;
+}
+
+/*
+ * Function to compute the flow direction based on the match port details
+ */
+static void
+bnxt_ulp_rte_parser_direction_compute(struct ulp_rte_parser_params *params)
+{
+ enum bnxt_ulp_intf_type match_port_type;
+
+ /* Get the match port type */
+ match_port_type = ULP_COMP_FLD_IDX_RD(params,
+ BNXT_ULP_CF_IDX_MATCH_PORT_TYPE);
+
+ /* If ingress flow and matchport is vf rep then dir is egress*/
+ if ((params->dir_attr & BNXT_ULP_FLOW_ATTR_INGRESS) &&
+ match_port_type == BNXT_ULP_INTF_TYPE_VF_REP) {
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_DIRECTION,
+ BNXT_ULP_DIR_EGRESS);
+ } else {
+ /* Assign the input direction */
+ if (params->dir_attr & BNXT_ULP_FLOW_ATTR_INGRESS)
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_DIRECTION,
+ BNXT_ULP_DIR_INGRESS);
+ else
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_DIRECTION,
+ BNXT_ULP_DIR_EGRESS);
+ }
+}
+