doc: update metadata feature in mlx5 guide

[dpdk.git] / doc / guides / nics / mlx5.rst

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 3651e82..2080766 100644 (file)
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -207,6 +207,8 @@ Limitations
   - KEEP_CRC offload cannot be supported with LRO.
   - The first mbuf length, without head-room,  must be big enough to include the
     TCP header (122B).
+  - Rx queue with LRO offload enabled, receiving a non-LRO packet, can forward
+    it with size limited to max LRO size, not to max RX packet length.
 
 Statistics
 ----------
@@ -552,6 +554,39 @@ Run-time configuration
   Also, if minimal data inlining is requested by non-zero ``txq_inline_min``
   option or reported by the NIC, the eMPW feature is disengaged.
 
+- ``tx_db_nc`` parameter [int]
+
+  The rdma core library can map doorbell register in two ways, depending on the
+  environment variable "MLX5_SHUT_UP_BF":
+
+  - As regular cached memory, if the variable is either missing or set to zero.
+  - As non-cached memory, if the variable is present and set to not "0" value.
+
+  The type of mapping may slightly affect the Tx performance, the optimal choice
+  is strongly relied on the host architecture and should be deduced practically.
+
+  If ``tx_db_nc`` is set to zero, the doorbell is forced to be mapped to regular
+  memory, the PMD will perform the extra write memory barrier after writing to
+  doorbell, it might increase the needed CPU clocks per packet to send, but
+  latency might be improved.
+
+  If ``tx_db_nc`` is set to one, the doorbell is forced to be mapped to non
+  cached memory, the PMD will not perform the extra write memory barrier
+  after writing to doorbell, on some architectures it might improve the
+  performance.
+
+  If ``tx_db_nc`` is set to two, the doorbell is forced to be mapped to regular
+  memory, the PMD will use heuristics to decide whether write memory barrier
+  should be performed. For bursts with size multiple of recommended one (64 pkts)
+  it is supposed the next burst is coming and no need to issue the extra memory
+  barrier (it is supposed to be issued in the next coming burst, at least after
+  descriptor writing). It might increase latency (on some hosts till next
+  packets transmit) and should be used with care.
+
+  If ``tx_db_nc`` is omitted or set to zero, the preset (if any) environment
+  variable "MLX5_SHUT_UP_BF" value is used. If there is no "MLX5_SHUT_UP_BF",
+  the default ``tx_db_nc`` value is zero for ARM64 hosts and one for others.
+
 - ``tx_vec_en`` parameter [int]
 
   A nonzero value enables Tx vector on ConnectX-5, ConnectX-6, ConnectX-6 DX
@@ -631,12 +666,16 @@ Run-time configuration
 
   Disabled by default (set to 0).
 
+  The Direct Verbs/Rules (engaged with ``dv_flow_en`` = 1) supports all
+  of the extensive metadata features. The legacy Verbs supports FLAG and
+  MARK metadata actions over NIC Rx steering domain only.
+
 - ``dv_flow_en`` parameter [int]
 
   A nonzero value enables the DV flow steering assuming it is supported
   by the driver.
 
-  Disabled by default.
+  Enabled by default if supported.
 
 - ``dv_esw_en`` parameter [int]