-.. BSD LICENSE
- Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2010-2015 Intel Corporation.
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- modification, are permitted provided that the following conditions
- are met:
-
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- notice, this list of conditions and the following disclaimer in
- the documentation and/or other materials provided with the
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-
-Sample Applications User Guide
-==============================
-
-June 2014
-
-INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS.
-NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
-EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS,
-INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY,
-RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
-MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
-
-A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death.
-SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES,
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-AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY,
-OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION,
-WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN,
-MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS.
-
-Intel may make changes to specifications and product descriptions at any time, without notice.
-Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined".
-Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
-The information here is subject to change without notice.
-Do not finalize a design with this information.
-
-The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
-Current characterized errata are available on request.
-
-Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
-
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-`http://www.intel.com/design/literature.htm <http://www.intel.com/design/literature.htm>`_.
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-Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
-
-\*Other names and brands may be claimed as the property of others.
-
-Copyright © 2012 - 2014, Intel Corporation. All rights reserved.
-
-**Contents**
+Sample Applications User Guides
+===============================
.. toctree::
:maxdepth: 2
:numbered:
intro
+ compiling
cmd_line
- exception_path
+ ethtool
hello_world
+ skeleton
+ rxtx_callbacks
+ flow_classify
+ flow_filtering
ip_frag
ipv4_multicast
ip_reassembly
kernel_nic_interface
+ keep_alive
+ ioat
+ l2_forward_crypto
+ l2_forward_job_stats
l2_forward_real_virtual
+ l2_forward_event
+ l2_forward_cat
l3_forward
+ l3_forward_graph
l3_forward_power_man
l3_forward_access_ctrl
- l3_forward_virtual
link_status_intr
- load_balancer
+ server_node_efd
+ service_cores
multi_process
qos_metering
qos_scheduler
- intel_quickassist
- quota_watermark
timer
+ packet_ordering
vmdq_dcb_forwarding
+ vmdq_forwarding
vhost
- netmap_compatibility
- internet_proto_ip_pipeline
+ vhost_blk
+ vhost_crypto
+ vdpa
+ ip_pipeline
test_pipeline
+ eventdev_pipeline
dist_app
-
-**Figures**
-
-:ref:`Figure 1.Packet Flow <figure_1>`
-
-:ref:`Figure 2.Kernel NIC Application Packet Flow <figure_2>`
-
-:ref:`Figure 3.Performance Benchmark Setup (Basic Environment) <figure_3>`
-
-:ref:`Figure 4.Performance Benchmark Setup (Virtualized Environment) <figure_4>`
-
-:ref:`Figure 5.Load Balancer Application Architecture <figure_5>`
-
-:ref:`Figure 5.Example Rules File <figure_5_1>`
-
-:ref:`Figure 6.Example Data Flow in a Symmetric Multi-process Application <figure_6>`
-
-:ref:`Figure 7.Example Data Flow in a Client-Server Symmetric Multi-process Application <figure_7>`
-
-:ref:`Figure 8.Master-slave Process Workflow <figure_8>`
-
-:ref:`Figure 9.Slave Process Recovery Process Flow <figure_9>`
-
-:ref:`Figure 10.QoS Scheduler Application Architecture <figure_10>`
-
-:ref:`Figure 11.Intel®QuickAssist Technology Application Block Diagram <figure_11>`
-
-:ref:`Figure 12.Pipeline Overview <figure_12>`
-
-:ref:`Figure 13.Ring-based Processing Pipeline Performance Setup <figure_13>`
-
-:ref:`Figure 14.Threads and Pipelines <figure_14>`
-
-:ref:`Figure 15.Packet Flow Through the VMDQ and DCB Sample Application <figure_15>`
-
-:ref:`Figure 16.QEMU Virtio-net (prior to vhost-net) <figure_16>`
-
-:ref:`Figure 17.Virtio with Linux* Kernel Vhost <figure_17>`
-
-:ref:`Figure 18.Vhost-net Architectural Overview <figure_18>`
-
-:ref:`Figure 19.Packet Flow Through the vhost-net Sample Application <figure_19>`
-
-:ref:`Figure 20.Packet Flow on TX in DPDK-testpmd <figure_20>`
-
-:ref:`Figure 21.Test Pipeline Application <figure_21>`
-
-:ref:`Figure 22.Performance Benchmarking Setup (Basic Environment) <figure_22>`
-
-:ref:`Figure 23.Distributor Sample Application Layout <figure_23>`
-
-**Tables**
-
-:ref:`Table 1.Output Traffic Marking <table_1>`
-
-:ref:`Table 2.Entity Types <table_2>`
-
-:ref:`Table 3.Table Types <table_3>`
+ vm_power_management
+ tep_termination
+ ptpclient
+ performance_thread
+ fips_validation
+ ipsec_secgw
+ bbdev_app
+ ntb
git.droids-corp.org / dpdk.git / blobdiff