#include <rte_bus.h>
#include <rte_pci.h>
#include <rte_bus_pci.h>
+#include <rte_lcore.h>
#include <rte_per_lcore.h>
#include <rte_memory.h>
#include <rte_eal.h>
dev->name, sizeof(dev->name));
devargs = pci_devargs_lookup(&dev->addr);
dev->device.devargs = devargs;
- /* In blacklist mode, if the device is not blacklisted, no
- * rte_devargs exists for it.
+
+ /* When using a blocklist, only blocked devices will have
+ * an rte_devargs. Allowed devices won't have one.
*/
if (devargs != NULL)
/* If an rte_devargs exists, the generic rte_device uses the
id_table++) {
/* check if device's identifiers match the driver's ones */
if (id_table->vendor_id != pci_dev->id.vendor_id &&
- id_table->vendor_id != PCI_ANY_ID)
+ id_table->vendor_id != RTE_PCI_ANY_ID)
continue;
if (id_table->device_id != pci_dev->id.device_id &&
- id_table->device_id != PCI_ANY_ID)
+ id_table->device_id != RTE_PCI_ANY_ID)
continue;
if (id_table->subsystem_vendor_id !=
pci_dev->id.subsystem_vendor_id &&
- id_table->subsystem_vendor_id != PCI_ANY_ID)
+ id_table->subsystem_vendor_id != RTE_PCI_ANY_ID)
continue;
if (id_table->subsystem_device_id !=
pci_dev->id.subsystem_device_id &&
- id_table->subsystem_device_id != PCI_ANY_ID)
+ id_table->subsystem_device_id != RTE_PCI_ANY_ID)
continue;
if (id_table->class_id != pci_dev->id.class_id &&
id_table->class_id != RTE_CLASS_ANY_ID)
struct rte_pci_device *dev)
{
int ret;
+ unsigned socket_id;
bool already_probed;
struct rte_pci_addr *loc;
loc = &dev->addr;
- /* The device is not blacklisted; Check if driver supports it */
+ /* The device is not blocked; Check if driver supports it */
if (!rte_pci_match(dr, dev))
/* Match of device and driver failed */
return 1;
loc->domain, loc->bus, loc->devid, loc->function,
dev->device.numa_node);
- /* no initialization when blacklisted, return without error */
+ /* no initialization when marked as blocked, return without error */
if (dev->device.devargs != NULL &&
- dev->device.devargs->policy ==
- RTE_DEV_BLACKLISTED) {
- RTE_LOG(INFO, EAL, " Device is blacklisted, not"
- " initializing\n");
+ dev->device.devargs->policy == RTE_DEV_BLOCKED) {
+ RTE_LOG(INFO, EAL, " Device is blocked, not initializing\n");
return 1;
}
if (dev->device.numa_node < 0) {
- RTE_LOG(WARNING, EAL, " Invalid NUMA socket, default to 0\n");
- dev->device.numa_node = 0;
+ if (rte_socket_count() > 1)
+ RTE_LOG(INFO, EAL, "Device %s is not NUMA-aware, defaulting socket to 0\n",
+ dev->name);
+ socket_id = rte_lcore_to_socket_id(rte_get_next_lcore(-1, 0, 0));
+ dev->device.numa_node = socket_id;
}
already_probed = rte_dev_is_probed(&dev->device);
struct rte_devargs *devargs = pci_devargs_lookup(pci_addr);
switch (rte_pci_bus.bus.conf.scan_mode) {
- case RTE_BUS_SCAN_WHITELIST:
- if (devargs && devargs->policy == RTE_DEV_WHITELISTED)
+ case RTE_BUS_SCAN_ALLOWLIST:
+ if (devargs && devargs->policy == RTE_DEV_ALLOWED)
return false;
break;
case RTE_BUS_SCAN_UNDEFINED:
- case RTE_BUS_SCAN_BLACKLIST:
- if (devargs == NULL ||
- devargs->policy != RTE_DEV_BLACKLISTED)
+ case RTE_BUS_SCAN_BLOCKLIST:
+ if (devargs == NULL || devargs->policy != RTE_DEV_BLOCKED)
return false;
break;
}
return iova_mode;
}
+off_t
+rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap)
+{
+ off_t offset = RTE_PCI_CFG_SPACE_SIZE;
+ uint32_t header;
+ int ttl;
+
+ /* minimum 8 bytes per capability */
+ ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
+
+ if (rte_pci_read_config(dev, &header, 4, offset) < 0) {
+ RTE_LOG(ERR, EAL, "error in reading extended capabilities\n");
+ return -1;
+ }
+
+ /*
+ * If we have no capabilities, this is indicated by cap ID,
+ * cap version and next pointer all being 0.
+ */
+ if (header == 0)
+ return 0;
+
+ while (ttl != 0) {
+ if (RTE_PCI_EXT_CAP_ID(header) == cap)
+ return offset;
+
+ offset = RTE_PCI_EXT_CAP_NEXT(header);
+
+ if (offset < RTE_PCI_CFG_SPACE_SIZE)
+ break;
+
+ if (rte_pci_read_config(dev, &header, 4, offset) < 0) {
+ RTE_LOG(ERR, EAL,
+ "error in reading extended capabilities\n");
+ return -1;
+ }
+
+ ttl--;
+ }
+
+ return 0;
+}
+
+int
+rte_pci_set_bus_master(struct rte_pci_device *dev, bool enable)
+{
+ uint16_t old_cmd, cmd;
+
+ if (rte_pci_read_config(dev, &old_cmd, sizeof(old_cmd),
+ RTE_PCI_COMMAND) < 0) {
+ RTE_LOG(ERR, EAL, "error in reading PCI command register\n");
+ return -1;
+ }
+
+ if (enable)
+ cmd = old_cmd | RTE_PCI_COMMAND_MASTER;
+ else
+ cmd = old_cmd & ~RTE_PCI_COMMAND_MASTER;
+
+ if (cmd == old_cmd)
+ return 0;
+
+ if (rte_pci_write_config(dev, &cmd, sizeof(cmd),
+ RTE_PCI_COMMAND) < 0) {
+ RTE_LOG(ERR, EAL, "error in writing PCI command register\n");
+ return -1;
+ }
+
+ return 0;
+}
+
struct rte_pci_bus rte_pci_bus = {
.bus = {
.scan = rte_pci_scan,
.plug = pci_plug,
.unplug = pci_unplug,
.parse = pci_parse,
+ .devargs_parse = rte_pci_devargs_parse,
.dma_map = pci_dma_map,
.dma_unmap = pci_dma_unmap,
.get_iommu_class = rte_pci_get_iommu_class,
git.droids-corp.org / dpdk.git / blobdiff