common/mlx5: disable relaxed ordering in unsuitable CPUs

[dpdk.git] / drivers / common / mlx5 / mlx5_common.h

diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h
index 961c606..8cd3ea5 100644 (file)
--- a/drivers/common/mlx5/mlx5_common.h
+++ b/drivers/common/mlx5/mlx5_common.h
@@ -8,6 +8,7 @@
 #include <stdio.h>
 
 #include <rte_pci.h>
+#include <rte_debug.h>
 #include <rte_atomic.h>
 #include <rte_log.h>
 #include <rte_kvargs.h>
@@ -16,16 +17,6 @@
 #include "mlx5_prm.h"
 
 
-/*
- * Compilation workaround for PPC64 when AltiVec is fully enabled, e.g. std=c11.
- * Otherwise there would be a type conflict between stdbool and altivec.
- */
-#if defined(__PPC64__) && !defined(__APPLE_ALTIVEC__)
-#undef bool
-/* redefine as in stdbool.h */
-#define bool _Bool
-#endif
-
 /* Bit-field manipulation. */
 #define BITFIELD_DECLARE(bf, type, size) \
        type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \
@@ -205,6 +196,7 @@ check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
        return MLX5_CQE_STATUS_SW_OWN;
 }
 
+__rte_internal
 int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr);
 
 #define MLX5_CLASS_ARG_NAME "class"
@@ -215,8 +207,12 @@ enum mlx5_class {
        MLX5_CLASS_INVALID,
 };
 
+__rte_internal
 enum mlx5_class mlx5_class_get(struct rte_devargs *devargs);
+__rte_internal
 void mlx5_translate_port_name(const char *port_name_in,
                              struct mlx5_switch_info *port_info_out);
 
+extern uint8_t haswell_broadwell_cpu;
+
 #endif /* RTE_PMD_MLX5_COMMON_H_ */