common/mlx5: add functions for single flow dump

[dpdk.git] / drivers / common / mlx5 / mlx5_devx_cmds.h

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index 3e2a0a2..209e7da 100644 (file)
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -31,6 +31,7 @@ struct mlx5_devx_mkey_attr {
        uint32_t pg_access:1;
        uint32_t relaxed_ordering_write:1;
        uint32_t relaxed_ordering_read:1;
+       uint32_t umr_en:1;
        struct mlx5_klm *klm_array;
        int klm_num;
 };
@@ -121,11 +122,18 @@ struct mlx5_hca_attr {
        uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
        uint32_t scatter_fcs_w_decap_disable:1;
        uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */
+       uint32_t roce:1;
+       uint32_t rq_ts_format:2;
+       uint32_t sq_ts_format:2;
+       uint32_t qp_ts_format:2;
        uint32_t regex:1;
        uint32_t reg_c_preserve:1;
        uint32_t regexp_num_of_engines;
        uint32_t log_max_ft_sampler_num:8;
        uint32_t geneve_tlv_opt;
+       uint32_t cqe_compression:1;
+       uint32_t mini_cqe_resp_flow_tag:1;
+       uint32_t mini_cqe_resp_l3_l4_tag:1;
        struct mlx5_hca_qos_attr qos;
        struct mlx5_hca_vdpa_attr vdpa;
        int log_max_qp_sz;
@@ -144,6 +152,8 @@ struct mlx5_hca_attr {
        uint32_t log_max_mmo_dma:5;
        uint32_t log_max_mmo_compress:5;
        uint32_t log_max_mmo_decompress:5;
+       uint32_t umr_modify_entity_size_disabled:1;
+       uint32_t umr_indirect_mkey_disabled:1;
 };
 
 struct mlx5_devx_wq_attr {
@@ -185,6 +195,7 @@ struct mlx5_devx_create_rq_attr {
        uint32_t state:4;
        uint32_t flush_in_error_en:1;
        uint32_t hairpin:1;
+       uint32_t ts_format:2;
        uint32_t user_index:24;
        uint32_t cqn:24;
        uint32_t counter_set_id:8;
@@ -268,6 +279,7 @@ struct mlx5_devx_create_sq_attr {
        uint32_t hairpin:1;
        uint32_t non_wire:1;
        uint32_t static_sq_wq:1;
+       uint32_t ts_format:2;
        uint32_t user_index:24;
        uint32_t cqn:24;
        uint32_t packet_pacing_rate_limit_index:16;
@@ -351,6 +363,7 @@ struct mlx5_devx_qp_attr {
        uint32_t rq_size:17; /* Must be power of 2. */
        uint32_t log_rq_stride:3;
        uint32_t sq_size:17; /* Must be power of 2. */
+       uint32_t ts_format:2;
        uint32_t dbr_umem_valid:1;
        uint32_t dbr_umem_id;
        uint64_t dbr_address;
@@ -464,6 +477,8 @@ __rte_internal
 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
                            FILE *file);
 __rte_internal
+int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file);
+__rte_internal
 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx,
                                              struct mlx5_devx_cq_attr *attr);
 __rte_internal
@@ -536,4 +551,13 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx,
 
 __rte_internal
 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx);
+
+__rte_internal
+int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id);
+
+__rte_internal
+struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx);
+__rte_internal
+int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
+                                     uint32_t *out_of_buffers);
 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */