uint16_t hdr_type_etc;
uint16_t vlan_info;
uint8_t lro_num_seg;
- uint8_t rsvd3[3];
+ union {
+ uint8_t user_index_bytes[3];
+ struct {
+ uint8_t user_index_hi;
+ uint16_t user_index_low;
+ } __rte_packed;
+ };
uint32_t flow_table_metadata;
uint8_t rsvd4[4];
uint32_t byte_cnt;
u8 vxlan_vni[0x18];
u8 reserved_at_b8[0x8];
u8 geneve_vni[0x18];
- u8 reserved_at_e4[0x7];
+ u8 reserved_at_e4[0x6];
+ u8 geneve_tlv_option_0_exist[0x1];
u8 geneve_oam[0x1];
u8 reserved_at_e0[0xc];
u8 outer_ipv6_flow_label[0x14];
u8 tcp_flags[0x9];
u8 tcp_sport[0x10];
u8 tcp_dport[0x10];
- u8 reserved_at_c0[0x18];
+ u8 reserved_at_c0[0x10];
+ u8 ipv4_ihl[0x4];
+ u8 l3_ok[0x1];
+ u8 l4_ok[0x1];
+ u8 ipv4_checksum_ok[0x1];
+ u8 l4_checksum_ok[0x1];
u8 ip_ttl_hoplimit[0x8];
u8 udp_sport[0x10];
u8 udp_dport[0x10];
u8 prog_sample_field_id_2[0x20];
u8 prog_sample_field_value_3[0x20];
u8 prog_sample_field_id_3[0x20];
- u8 reserved_at_100[0x100];
+ u8 prog_sample_field_value_4[0x20];
+ u8 prog_sample_field_id_4[0x20];
+ u8 prog_sample_field_value_5[0x20];
+ u8 prog_sample_field_id_5[0x20];
+ u8 prog_sample_field_value_6[0x20];
+ u8 prog_sample_field_id_6[0x20];
+ u8 prog_sample_field_value_7[0x20];
+ u8 prog_sample_field_id_7[0x20];
+};
+
+struct mlx5_ifc_fte_match_set_misc5_bits {
+ u8 macsec_tag_0[0x20];
+ u8 macsec_tag_1[0x20];
+ u8 macsec_tag_2[0x20];
+ u8 macsec_tag_3[0x20];
+ u8 tunnel_header_0[0x20];
+ u8 tunnel_header_1[0x20];
+ u8 tunnel_header_2[0x20];
+ u8 tunnel_header_3[0x20];
+ u8 reserved[0x100];
};
/* Flow matcher. */
struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
+ struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
/*
* Add reserved bit to match the struct size with the size defined in PRM.
* This extension is not required in Linux.
*/
#ifndef HAVE_INFINIBAND_VERBS_H
- u8 reserved_0[0x400];
+ u8 reserved_0[0x200];
#endif
};
MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,
+ MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT,
};
enum {
MLX5_CMD_OP_DEALLOC_PD = 0x801,
MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
+ MLX5_CMD_OP_QUERY_LAG = 0x842,
MLX5_CMD_OP_CREATE_TIR = 0x900,
MLX5_CMD_OP_MODIFY_TIR = 0x901,
MLX5_CMD_OP_CREATE_SQ = 0X904,
MLX5_CMD_OP_CREATE_RQ = 0x908,
MLX5_CMD_OP_MODIFY_RQ = 0x909,
MLX5_CMD_OP_QUERY_RQ = 0x90b,
+ MLX5_CMD_OP_CREATE_RMP = 0x90c,
+ MLX5_CMD_OP_MODIFY_RMP = 0x90d,
+ MLX5_CMD_OP_DESTROY_RMP = 0x90e,
+ MLX5_CMD_OP_QUERY_RMP = 0x90f,
MLX5_CMD_OP_CREATE_TIS = 0x912,
MLX5_CMD_OP_QUERY_TIS = 0x915,
MLX5_CMD_OP_CREATE_RQT = 0x916,
MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1,
MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
+ MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1,
+ MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1,
};
#define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \
(1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO)
#define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \
(1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT)
+#define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \
+ (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD)
#define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \
(1ULL << MLX5_GENERAL_OBJ_TYPE_DEK)
#define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \
#define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
#define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
+/* The device steering logic format. */
+#define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0
+#define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1
+
struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_0[0x30];
u8 vhca_id[0x10];
u8 wqe_index_ignore_cap[0x1];
u8 dynamic_qp_allocation[0x1];
u8 log_max_qp[0x5];
- u8 regexp[0x1];
- u8 reserved_at_a1[0x3];
+ u8 reserved_at_a0[0x4];
u8 regexp_num_of_engines[0x4];
u8 reserved_at_a8[0x1];
u8 reg_c_preserve[0x1];
u8 reserved_at_aa[0x1];
u8 log_max_srq[0x5];
- u8 reserved_at_b0[0x3];
- u8 regexp_log_crspace_size[0x5];
- u8 reserved_at_b8[0x3];
+ u8 reserved_at_b0[0xb];
u8 scatter_fcs_w_decap_disable[0x1];
u8 reserved_at_bc[0x4];
u8 reserved_at_c0[0x8];
u8 log_max_cq_sz[0x8];
- u8 reserved_at_d0[0xb];
+ u8 reserved_at_d0[0x2];
+ u8 access_register_user[0x1];
+ u8 reserved_at_d3[0x8];
u8 log_max_cq[0x5];
u8 log_max_eq_sz[0x8];
u8 relaxed_ordering_write[0x1];
u8 relaxed_ordering_read[0x1];
- u8 access_register_user[0x1];
- u8 log_max_mkey[0x5];
+ u8 log_max_mkey[0x6];
u8 reserved_at_f0[0x8];
u8 dump_fill_mkey[0x1];
u8 reserved_at_f9[0x3];
u8 rtr2rts_qp_counters_set_id[0x1];
u8 rts2rts_udp_sport[0x1];
u8 rts2rts_lag_tx_port_affinity[0x1];
- u8 dma_mmo[0x1];
+ u8 dma_mmo_sq[0x1];
u8 compress_min_block_size[0x4];
- u8 compress[0x1];
- u8 decompress[0x1];
+ u8 compress_mmo_sq[0x1];
+ u8 decompress_mmo_sq[0x1];
u8 log_max_ra_res_qp[0x6];
u8 end_pad[0x1];
u8 cc_query_allowed[0x1];
u8 uc[0x1];
u8 rc[0x1];
u8 uar_4k[0x1];
- u8 reserved_at_241[0x9];
+ u8 reserved_at_241[0x8];
+ u8 regexp_params[0x1];
u8 uar_sz[0x6];
- u8 reserved_at_250[0x8];
+ u8 port_selection_cap[0x1];
+ u8 reserved_at_251[0x7];
u8 log_pg_sz[0x8];
u8 bf[0x1];
u8 driver_version[0x1];
u8 num_lag_ports[0x4];
u8 reserved_at_280[0x10];
u8 max_wqe_sz_sq[0x10];
- u8 reserved_at_2a0[0x10];
+ u8 reserved_at_2a0[0xc];
+ u8 regexp_mmo_sq[0x1];
+ u8 regexp_version[0x3];
u8 max_wqe_sz_rq[0x10];
u8 max_flow_counter_31_16[0x10];
u8 max_wqe_sz_sq_dc[0x10];
u8 reserved_at_378[0x3];
u8 log_max_tis[0x5];
u8 basic_cyclic_rcv_wqe[0x1];
- u8 reserved_at_381[0x2];
+ u8 reserved_at_381[0x1];
+ u8 mem_rq_rmp[0x1];
u8 log_max_rmp[0x5];
u8 reserved_at_388[0x3];
u8 log_max_rqt[0x5];
u8 general_obj_types[0x40];
u8 sq_ts_format[0x2];
u8 rq_ts_format[0x2];
- u8 reserved_at_444[0x1C];
+ u8 steering_format_version[0x4];
+ u8 reserved_at_448[0x18];
u8 reserved_at_460[0x8];
u8 aes_xts[0x1];
u8 crypto[0x1];
u8 num_vhca_ports[0x8];
u8 reserved_at_618[0x6];
u8 sw_owner_id[0x1];
- u8 reserved_at_61f[0x1e1];
+ u8 reserved_at_61f[0x129];
+ u8 dma_mmo_qp[0x1];
+ u8 regexp_mmo_qp[0x1];
+ u8 compress_mmo_qp[0x1];
+ u8 decompress_mmo_qp[0x1];
+ u8 reserved_at_624[0xd4];
};
struct mlx5_ifc_qos_cap_bits {
u8 reserved_at_1c0[0x620];
};
+/**
+ * PARSE_GRAPH_NODE Capabilities Field Descriptions
+ */
+struct mlx5_ifc_parse_graph_node_cap_bits {
+ u8 node_in[0x20];
+ u8 node_out[0x20];
+ u8 header_length_mode[0x10];
+ u8 sample_offset_mode[0x10];
+ u8 max_num_arc_in[0x08];
+ u8 max_num_arc_out[0x08];
+ u8 max_num_sample[0x08];
+ u8 reserved_at_78[0x07];
+ u8 sample_id_in_out[0x1];
+ u8 max_base_header_length[0x10];
+ u8 reserved_at_90[0x08];
+ u8 max_sample_base_offset[0x08];
+ u8 max_next_header_offset[0x10];
+ u8 reserved_at_b0[0x08];
+ u8 header_length_mask_width[0x08];
+};
+
struct mlx5_ifc_flow_table_prop_layout_bits {
u8 ft_support[0x1];
u8 flow_tag[0x1];
u8 reserved_at_20[0x7e0];
};
+/*
+ * Table 1872 - Flow Table Fields Supported 2 Format
+ */
+struct mlx5_ifc_ft_fields_support_2_bits {
+ u8 reserved_at_0[0xf];
+ u8 tunnel_header_2_3[0x1];
+ u8 tunnel_header_0_1[0x1];
+ u8 macsec_syndrome[0x1];
+ u8 macsec_tag[0x1];
+ u8 outer_lrh_sl[0x1];
+ u8 inner_ipv4_ihl[0x1];
+ u8 outer_ipv4_ihl[0x1];
+ u8 psp_syndrome[0x1];
+ u8 inner_l3_ok[0x1];
+ u8 inner_l4_ok[0x1];
+ u8 outer_l3_ok[0x1];
+ u8 outer_l4_ok[0x1];
+ u8 psp_header[0x1];
+ u8 inner_ipv4_checksum_ok[0x1];
+ u8 inner_l4_checksum_ok[0x1];
+ u8 outer_ipv4_checksum_ok[0x1];
+ u8 outer_l4_checksum_ok[0x1];
+ u8 reserved_at_20[0x60];
+};
+
struct mlx5_ifc_flow_table_nic_cap_bits {
- u8 reserved_at_0[0x200];
- struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties;
+ u8 reserved_at_0[0x200];
+ struct mlx5_ifc_flow_table_prop_layout_bits
+ flow_table_properties_nic_receive;
+ struct mlx5_ifc_flow_table_prop_layout_bits
+ flow_table_properties_nic_receive_rdma;
+ struct mlx5_ifc_flow_table_prop_layout_bits
+ flow_table_properties_nic_receive_sniffer;
+ struct mlx5_ifc_flow_table_prop_layout_bits
+ flow_table_properties_nic_transmit;
+ struct mlx5_ifc_flow_table_prop_layout_bits
+ flow_table_properties_nic_transmit_rdma;
+ struct mlx5_ifc_flow_table_prop_layout_bits
+ flow_table_properties_nic_transmit_sniffer;
+ u8 reserved_at_e00[0x600];
+ struct mlx5_ifc_ft_fields_support_2_bits
+ ft_field_support_2_nic_receive;
+};
+
+/*
+ * HCA Capabilities 2
+ */
+struct mlx5_ifc_cmd_hca_cap_2_bits {
+ u8 reserved_at_0[0x80]; /* End of DW4. */
+ u8 reserved_at_80[0x3];
+ u8 max_num_prog_sample_field[0x5];
+ u8 reserved_at_88[0x3];
+ u8 log_max_num_reserved_qpn[0x5];
+ u8 reserved_at_90[0x3];
+ u8 log_reserved_qpn_granularity[0x5];
+ u8 reserved_at_98[0x3];
+ u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */
+ u8 max_reformat_insert_size[0x8];
+ u8 max_reformat_insert_offset[0x8];
+ u8 max_reformat_remove_size[0x8];
+ u8 max_reformat_remove_offset[0x8]; /* End of DW6. */
+ u8 aso_conntrack_reg_id[0x8];
+ u8 reserved_at_c8[0x3];
+ u8 log_conn_track_granularity[0x5];
+ u8 reserved_at_d0[0x3];
+ u8 log_conn_track_max_alloc[0x5];
+ u8 reserved_at_d8[0x3];
+ u8 log_max_conn_track_offload[0x5];
+ u8 reserved_at_e0[0x20]; /* End of DW7. */
+ u8 reserved_at_100[0x700];
};
union mlx5_ifc_hca_cap_union_bits {
u8 reserved_at_68[0x18];
};
+/*
+ * lag_tx_port_affinity: 0 auto-selection, 1 PF1, 2 PF2 vice versa.
+ * Each TIS binds to one PF by setting lag_tx_port_affinity (>0).
+ * Once LAG enabled, we create multiple TISs and bind each one to
+ * different PFs, then TIS[i] gets affinity i+1 and goes to PF i+1.
+ */
+#define MLX5_IFC_LAG_MAP_TIS_AFFINITY(index, num) ((num) ? \
+ (index) % (num) + 1 : 0)
struct mlx5_ifc_tisc_bits {
u8 strict_lag_tx_port_affinity[0x1];
u8 reserved_at_1[0x3];
u8 reserved_at_60[0x20];
};
+/* port_select_mode definition. */
+enum mlx5_lag_mode_type {
+ MLX5_LAG_MODE_TIS = 0,
+ MLX5_LAG_MODE_HASH = 1,
+};
+
+struct mlx5_ifc_lag_context_bits {
+ u8 fdb_selection_mode[0x1];
+ u8 reserved_at_1[0x14];
+ u8 port_select_mode[0x3];
+ u8 reserved_at_18[0x5];
+ u8 lag_state[0x3];
+ u8 reserved_at_20[0x14];
+ u8 tx_remap_affinity_2[0x4];
+ u8 reserved_at_38[0x4];
+ u8 tx_remap_affinity_1[0x4];
+};
+
+struct mlx5_ifc_query_lag_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_query_lag_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ struct mlx5_ifc_lag_context_bits context;
+};
+
struct mlx5_ifc_alloc_transport_domain_out_bits {
u8 status[0x8];
u8 reserved_at_8[0x18];
u8 reserved_at_60[0x20];
};
+enum {
+ MLX5_RMPC_STATE_RDY = 0x1,
+ MLX5_RMPC_STATE_ERR = 0x3,
+};
+
+struct mlx5_ifc_rmpc_bits {
+ u8 reserved_at_0[0x8];
+ u8 state[0x4];
+ u8 reserved_at_c[0x14];
+ u8 basic_cyclic_rcv_wqe[0x1];
+ u8 reserved_at_21[0x1f];
+ u8 reserved_at_40[0x140];
+ struct mlx5_ifc_wq_bits wq;
+};
+
+struct mlx5_ifc_query_rmp_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0xc0];
+ struct mlx5_ifc_rmpc_bits rmp_context;
+};
+
+struct mlx5_ifc_query_rmp_in_bits {
+ u8 opcode[0x10];
+ u8 reserved_at_10[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x8];
+ u8 rmpn[0x18];
+ u8 reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_modify_rmp_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_rmp_bitmask_bits {
+ u8 reserved_at_0[0x20];
+ u8 reserved_at_20[0x1f];
+ u8 lwm[0x1];
+};
+
+struct mlx5_ifc_modify_rmp_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 rmp_state[0x4];
+ u8 reserved_at_44[0x4];
+ u8 rmpn[0x18];
+ u8 reserved_at_60[0x20];
+ struct mlx5_ifc_rmp_bitmask_bits bitmask;
+ u8 reserved_at_c0[0x40];
+ struct mlx5_ifc_rmpc_bits ctx;
+};
+
+struct mlx5_ifc_create_rmp_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x8];
+ u8 rmpn[0x18];
+ u8 reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_create_rmp_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0xc0];
+ struct mlx5_ifc_rmpc_bits ctx;
+};
+
struct mlx5_ifc_create_tis_out_bits {
u8 status[0x8];
u8 reserved_at_8[0x18];
MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,
MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024,
MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,
+ MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031,
};
struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso;
};
+
+struct mlx5_ifc_tcp_window_params_bits {
+ u8 max_ack[0x20];
+ u8 max_win[0x20];
+ u8 reply_end[0x20];
+ u8 sent_end[0x20];
+};
+
+struct mlx5_ifc_conn_track_aso_bits {
+ struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */
+ struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */
+ u8 last_end[0x20]; /* End of DW8. */
+ u8 last_ack[0x20]; /* End of DW9. */
+ u8 last_seq[0x20]; /* End of DW10. */
+ u8 last_win[0x10];
+ u8 reserved_at_170[0xa];
+ u8 last_dir[0x1];
+ u8 last_index[0x5]; /* End of DW11. */
+ u8 reserved_at_180[0x40]; /* End of DW13. */
+ u8 reply_direction_tcp_scale[0x4];
+ u8 reply_direction_tcp_close_initiated[0x1];
+ u8 reply_direction_tcp_liberal_enabled[0x1];
+ u8 reply_direction_tcp_data_unacked[0x1];
+ u8 reply_direction_tcp_max_ack[0x1];
+ u8 reserved_at_1c8[0x8];
+ u8 original_direction_tcp_scale[0x4];
+ u8 original_direction_tcp_close_initiated[0x1];
+ u8 original_direction_tcp_liberal_enabled[0x1];
+ u8 original_direction_tcp_data_unacked[0x1];
+ u8 original_direction_tcp_max_ack[0x1];
+ u8 reserved_at_1d8[0x8]; /* End of DW14. */
+ u8 valid[0x1];
+ u8 state[0x3];
+ u8 freeze_track[0x1];
+ u8 reserved_at_1e5[0xb];
+ u8 reserved_at_1f0[0x1];
+ u8 connection_assured[0x1];
+ u8 sack_permitted[0x1];
+ u8 challenged_acked[0x1];
+ u8 heartbeat[0x1];
+ u8 max_ack_window[0x3];
+ u8 reserved_at_1f8[0x1];
+ u8 retransmission_counter[0x3];
+ u8 retranmission_limit_exceeded[0x1];
+ u8 retranmission_limit[0x3]; /* End of DW15. */
+};
+
+struct mlx5_ifc_conn_track_offload_bits {
+ u8 modify_field_select[0x40];
+ u8 reserved_at_40[0x40];
+ u8 reserved_at_80[0x8];
+ u8 conn_track_aso_access_pd[0x18];
+ u8 reserved_at_a0[0x160];
+ struct mlx5_ifc_conn_track_aso_bits conn_track_aso;
+};
+
+struct mlx5_ifc_create_conn_track_aso_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_conn_track_offload_bits conn_track_offload;
+};
+
enum mlx5_access_aso_opc_mod {
ASO_OPC_MOD_IPSEC = 0x0,
ASO_OPC_MOD_CONNECTION_TRACKING = 0x1,
#define ASO_DSEG_VALID_OFFSET 31
#define ASO_DSEG_BO_OFFSET 30
#define ASO_DSEG_SC_OFFSET 28
+#define ASO_DSEG_BBOG_OFFSET 27
#define ASO_DSEG_MTR_MODE 24
#define ASO_DSEG_CBS_EXP_OFFSET 24
#define ASO_DSEG_CBS_MAN_OFFSET 16
-#define ASO_DSEG_CIR_EXP_MASK 0x1F
-#define ASO_DSEG_CIR_EXP_OFFSET 8
+#define ASO_DSEG_XIR_EXP_MASK 0x1F
+#define ASO_DSEG_XIR_EXP_OFFSET 8
#define ASO_DSEG_EBS_EXP_OFFSET 24
#define ASO_DSEG_EBS_MAN_OFFSET 16
#define ASO_DSEG_EXP_MASK 0x1F
u8 reserved_at_60[0x20];
};
+struct mlx5_ifc_qpc_extension_bits {
+ u8 reserved_at_0[0x2];
+ u8 mmo[0x1];
+ u8 reserved_at_3[0x5fd];
+};
+
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+struct mlx5_ifc_qpc_pas_list_bits {
+ u8 pas[0][0x40];
+};
+
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+struct mlx5_ifc_qpc_extension_and_pas_list_bits {
+ struct mlx5_ifc_qpc_extension_bits qpc_data_extension;
+ u8 pas[0][0x40];
+};
+
+
#ifdef PEDANTIC
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
u8 uid[0x10];
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
- u8 reserved_at_40[0x40];
+ u8 qpc_ext[0x1];
+ u8 reserved_at_41[0x3f];
u8 opt_param_mask[0x20];
u8 reserved_at_a0[0x20];
struct mlx5_ifc_qpc_bits qpc;
u8 wq_umem_id[0x20];
u8 wq_umem_valid[0x1];
u8 reserved_at_861[0x1f];
- u8 pas[0][0x40];
+ union {
+ struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list;
+ struct mlx5_ifc_qpc_extension_and_pas_list_bits
+ qpc_extension_and_pas_list;
+ };
};
#ifdef PEDANTIC
#pragma GCC diagnostic error "-Wpedantic"
};
struct regexp_params_field_select_bits {
- u8 reserved_at_0[0x1e];
+ u8 reserved_at_0[0x1d];
+ u8 rof_mkey[0x1];
u8 stop_engine[0x1];
- u8 db_umem_id[0x1];
+ u8 reserved_at_1f[0x1];
};
struct mlx5_ifc_regexp_params_bits {
u8 reserved_at_0[0x1f];
u8 stop_engine[0x1];
- u8 db_umem_id[0x20];
- u8 db_umem_offset[0x40];
- u8 reserved_at_80[0x100];
+ u8 reserved_at_20[0x60];
+ u8 rof_mkey[0x20];
+ u8 rof_size[0x20];
+ u8 rof_mkey_va[0x40];
+ u8 reserved_at_100[0x80];
};
struct mlx5_ifc_set_regexp_params_in_bits {
MLX5_FLOW_COLOR_UNDEFINED,
};
-/* Maximum value of srTCM metering parameters. */
-#define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F))
-#define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF)
-#define MLX5_SRTCM_EBS_MAX 0
+/* Maximum value of srTCM & trTCM metering parameters. */
+#define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F))
+#define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF)
/* The bits meter color use. */
#define MLX5_MTR_COLOR_BITS 8
MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2,
};
+enum mlx5_parse_graph_flow_match_sample_tunnel_mode {
+ MLX5_GRAPH_SAMPLE_TUNNEL_OUTER = 0x0,
+ MLX5_GRAPH_SAMPLE_TUNNEL_INNER = 0x1,
+ MLX5_GRAPH_SAMPLE_TUNNEL_FIRST = 0x2
+};
+
/* Node index for an input / output arc of the flex parser graph. */
enum mlx5_parse_graph_arc_node_index {
MLX5_GRAPH_ARC_NODE_NULL = 0x0,
MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8,
MLX5_GRAPH_ARC_NODE_GENEVE = 0x9,
MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa,
+ MLX5_GRAPH_ARC_NODE_IPV4 = 0xb,
+ MLX5_GRAPH_ARC_NODE_IPV6 = 0xc,
MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f,
};
+#define MLX5_PARSE_GRAPH_FLOW_SAMPLE_MAX 8
+#define MLX5_PARSE_GRAPH_IN_ARC_MAX 8
+#define MLX5_PARSE_GRAPH_OUT_ARC_MAX 8
+
/**
* Convert a user mark to flow mark.
*
git.droids-corp.org / dpdk.git / blobdiff