#pragma GCC diagnostic error "-Wpedantic"
#endif
+#include <unistd.h>
+
#include <rte_vect.h>
#include <rte_byteorder.h>
#define MLX5_MAX_LOG_RQ_SEGS 5u
/* The alignment needed for WQ buffer. */
-#define MLX5_WQE_BUF_ALIGNMENT 512
+#define MLX5_WQE_BUF_ALIGNMENT sysconf(_SC_PAGESIZE)
/* Completion mode. */
enum mlx5_completion_mode {
uint8_t op_own;
};
+/* MMO metadata segment */
+
+#define MLX5_OPCODE_MMO 0x2f
+#define MLX5_OPC_MOD_MMO_REGEX 0x4
+
+struct mlx5_wqe_metadata_seg {
+ uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
+ uint32_t lkey;
+ uint64_t addr;
+};
+
+struct mlx5_ifc_regexp_mmo_control_bits {
+ uint8_t reserved_at_31[0x2];
+ uint8_t le[0x1];
+ uint8_t reserved_at_28[0x1];
+ uint8_t subset_id_0[0xc];
+ uint8_t reserved_at_16[0x4];
+ uint8_t subset_id_1[0xc];
+ uint8_t ctrl[0x4];
+ uint8_t subset_id_2[0xc];
+ uint8_t reserved_at_16_1[0x4];
+ uint8_t subset_id_3[0xc];
+};
+
+struct mlx5_ifc_regexp_metadata_bits {
+ uint8_t rof_version[0x10];
+ uint8_t latency_count[0x10];
+ uint8_t instruction_count[0x10];
+ uint8_t primary_thread_count[0x10];
+ uint8_t match_count[0x8];
+ uint8_t detected_match_count[0x8];
+ uint8_t status[0x10];
+ uint8_t job_id[0x20];
+ uint8_t reserved[0x80];
+};
+
/* Adding direct verbs to data-path. */
/* CQ sequence number mask. */
MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
+ MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
+ MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
+ MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
+ MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
};
enum {
#define MLX5_ADAPTER_PAGE_SHIFT 12
#define MLX5_LOG_RQ_STRIDE_SHIFT 4
+/**
+ * The batch counter dcs id starts from 0x800000 and none batch counter
+ * starts from 0. As currently, the counter is changed to be indexed by
+ * pool index and the offset of the counter in the pool counters_raw array.
+ * It means now the counter index is same for batch and none batch counter.
+ * Add the 0x800000 batch counter offset to the batch counter index helps
+ * indicate the counter index is from batch or none batch container pool.
+ */
+#define MLX5_CNT_BATCH_OFFSET 0x800000
/* Flow counters. */
struct mlx5_ifc_alloc_flow_counter_out_bits {
u8 translations_octword_size[0x20];
- u8 reserved_at_1c0[0x1b];
+ u8 reserved_at_1c0[0x19];
+ u8 relaxed_ordering_read[0x1];
+ u8 reserved_at_1da[0x1];
u8 log_page_size[0x5];
u8 reserved_at_1e0[0x20];
enum {
MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q = (1ULL << 0xd),
+ MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS = (1ULL << 0x1c),
};
enum {
u8 log_max_qp_sz[0x8];
u8 reserved_at_90[0xb];
u8 log_max_qp[0x5];
- u8 reserved_at_a0[0xb];
+ u8 regexp[0x1];
+ u8 reserved_at_a1[0x3];
+ u8 regexp_num_of_engines[0x4];
+ u8 reserved_at_a8[0x3];
u8 log_max_srq[0x5];
- u8 reserved_at_b0[0x10];
+ u8 reserved_at_b0[0x3];
+ u8 regexp_log_crspace_size[0x5];
+ u8 reserved_at_b8[0x8];
u8 reserved_at_c0[0x8];
u8 log_max_cq_sz[0x8];
u8 reserved_at_d0[0xb];
u8 log_max_cq[0x5];
u8 log_max_eq_sz[0x8];
- u8 reserved_at_e8[0x2];
+ u8 relaxed_ordering_write[0x1];
+ u8 relaxed_ordering_read[0x1];
u8 log_max_mkey[0x6];
u8 reserved_at_f0[0x8];
u8 dump_fill_mkey[0x1];
enum {
MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
+ MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
};
struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
u8 reserved_at_60[0x20];
};
+struct mlx5_ifc_virtio_q_counters_bits {
+ u8 modify_field_select[0x40];
+ u8 reserved_at_40[0x40];
+ u8 received_desc[0x40];
+ u8 completed_desc[0x40];
+ u8 error_cqes[0x20];
+ u8 bad_desc_errors[0x20];
+ u8 exceed_max_chain[0x20];
+ u8 invalid_buffer[0x20];
+ u8 reserved_at_180[0x50];
+};
+
+struct mlx5_ifc_create_virtio_q_counters_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
+};
+
+struct mlx5_ifc_query_virtio_q_counters_out_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
+};
enum {
MLX5_VIRTQ_STATE_INIT = 0,
MLX5_VIRTQ_STATE_RDY = 1,
u8 umem_3_id[0x20];
u8 umem_3_size[0x20];
u8 umem_3_offset[0x40];
- u8 reserved_at_300[0x100];
+ u8 counter_set_id[0x20];
+ u8 reserved_at_320[0x8];
+ u8 pd[0x18];
+ u8 reserved_at_340[0xc0];
};
struct mlx5_ifc_virtio_net_q_bits {
u8 reserved_at_60[0x20];
};
+struct regexp_params_field_select_bits {
+ u8 reserved_at_0[0x1e];
+ u8 stop_engine[0x1];
+ u8 db_umem_id[0x1];
+};
+
+struct mlx5_ifc_regexp_params_bits {
+ u8 reserved_at_0[0x1f];
+ u8 stop_engine[0x1];
+ u8 db_umem_id[0x20];
+ u8 db_umem_offset[0x40];
+ u8 reserved_at_80[0x100];
+};
+
+struct mlx5_ifc_set_regexp_params_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x18];
+ u8 engine_id[0x8];
+ struct regexp_params_field_select_bits field_select;
+ struct mlx5_ifc_regexp_params_bits regexp_params;
+};
+
+struct mlx5_ifc_set_regexp_params_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_18[0x40];
+};
+
+struct mlx5_ifc_query_regexp_params_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x18];
+ u8 engine_id[0x8];
+ u8 reserved[0x20];
+};
+
+struct mlx5_ifc_query_regexp_params_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved[0x40];
+ struct mlx5_ifc_regexp_params_bits regexp_params;
+};
+
+struct mlx5_ifc_set_regexp_register_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x18];
+ u8 engine_id[0x8];
+ u8 register_address[0x20];
+ u8 register_data[0x20];
+ u8 reserved[0x40];
+};
+
+struct mlx5_ifc_set_regexp_register_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved[0x40];
+};
+
+struct mlx5_ifc_query_regexp_register_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x18];
+ u8 engine_id[0x8];
+ u8 register_address[0x20];
+};
+
+struct mlx5_ifc_query_regexp_register_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved[0x20];
+ u8 register_data[0x20];
+};
+
/* CQE format mask. */
#define MLX5E_CQE_FORMAT_MASK 0xc
git.droids-corp.org / dpdk.git / blobdiff