common/mlx5: fix relaxed ordering count object

[dpdk.git] / drivers / common / mlx5 / mlx5_prm.h

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 15940c4..e4ef2ac 100644 (file)
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -16,6 +16,8 @@
 #pragma GCC diagnostic error "-Wpedantic"
 #endif
 
+#include <unistd.h>
+
 #include <rte_vect.h>
 #include <rte_byteorder.h>
 
@@ -100,7 +102,7 @@
  */
 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
 #define MLX5_MPW_MAX_PACKETS 6
-#define MLX5_MPW_INLINE_MAX_PACKETS 2
+#define MLX5_MPW_INLINE_MAX_PACKETS 6
 
 /*
  * Default packet length threshold to be inlined with
@@ -251,7 +253,7 @@
 #define MLX5_MAX_LOG_RQ_SEGS 5u
 
 /* The alignment needed for WQ buffer. */
-#define MLX5_WQE_BUF_ALIGNMENT 512
+#define MLX5_WQE_BUF_ALIGNMENT sysconf(_SC_PAGESIZE)
 
 /* Completion mode. */
 enum mlx5_completion_mode {
@@ -391,6 +393,10 @@ struct mlx5_cqe {
 /* CQE format value. */
 #define MLX5_COMPRESSED 0x3
 
+/* CQ doorbell cmd types. */
+#define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
+#define MLX5_CQ_DBR_CMD_ALL (0 << 24)
+
 /* Action type of header modification. */
 enum {
        MLX5_MODIFICATION_TYPE_SET = 0x1,
@@ -647,7 +653,8 @@ struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
        u8 tcp_flags[0x9];
        u8 tcp_sport[0x10];
        u8 tcp_dport[0x10];
-       u8 reserved_at_c0[0x20];
+       u8 reserved_at_c0[0x18];
+       u8 ip_ttl_hoplimit[0x8];
        u8 udp_sport[0x10];
        u8 udp_dport[0x10];
        union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
@@ -762,6 +769,15 @@ enum {
 
 #define MLX5_ADAPTER_PAGE_SHIFT 12
 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
+/**
+ * The batch counter dcs id starts from 0x800000 and none batch counter
+ * starts from 0. As currently, the counter is changed to be indexed by
+ * pool index and the offset of the counter in the pool counters_raw array.
+ * It means now the counter index is same for batch and none batch counter.
+ * Add the 0x800000 batch counter offset to the batch counter index helps
+ * indicate the counter index is from batch or none batch container pool.
+ */
+#define MLX5_CNT_BATCH_OFFSET 0x800000
 
 /* Flow counters. */
 struct mlx5_ifc_alloc_flow_counter_out_bits {
@@ -877,7 +893,9 @@ struct mlx5_ifc_mkc_bits {
 
        u8         translations_octword_size[0x20];
 
-       u8         reserved_at_1c0[0x1b];
+       u8         reserved_at_1c0[0x19];
+       u8                 relaxed_ordering_read[0x1];
+       u8                 reserved_at_1da[0x1];
        u8         log_page_size[0x5];
 
        u8         reserved_at_1e0[0x20];
@@ -983,7 +1001,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8 reserved_at_d0[0xb];
        u8 log_max_cq[0x5];
        u8 log_max_eq_sz[0x8];
-       u8 reserved_at_e8[0x2];
+       u8 relaxed_ordering_write[0x1];
+       u8 relaxed_ordering_read[0x1];
        u8 log_max_mkey[0x6];
        u8 reserved_at_f0[0x8];
        u8 dump_fill_mkey[0x1];