cryptodev: rename physical address type to IOVA
[dpdk.git] / drivers / crypto / qat / qat_crypto.h
index d9d8887..c64d775 100644 (file)
        (((num) + (align) - 1) & ~((align) - 1))
 #define QAT_64_BTYE_ALIGN_MASK (~0x3f)
 
+#define QAT_CSR_HEAD_WRITE_THRESH 32U
+/* number of requests to accumulate before writing head CSR */
+#define QAT_CSR_TAIL_WRITE_THRESH 32U
+/* number of requests to accumulate before writing tail CSR */
+#define QAT_CSR_TAIL_FORCE_WRITE_THRESH 256U
+/* number of inflights below which no tail write coalescing should occur */
+
+struct qat_session;
+
+enum qat_device_gen {
+       QAT_GEN1 = 1,
+       QAT_GEN2,
+};
+
 /**
  * Structure associated with each queue.
  */
 struct qat_queue {
        char            memz_name[RTE_MEMZONE_NAMESIZE];
        void            *base_addr;             /* Base address */
-       phys_addr_t     base_phys_addr;         /* Queue physical address */
+       rte_iova_t      base_phys_addr;         /* Queue physical address */
        uint32_t        head;                   /* Shadow copy of the head */
        uint32_t        tail;                   /* Shadow copy of the tail */
        uint32_t        modulo;
@@ -66,17 +80,24 @@ struct qat_queue {
        uint8_t         hw_bundle_number;
        uint8_t         hw_queue_number;
        /* HW queue aka ring offset on bundle */
+       uint32_t        csr_head;               /* last written head value */
+       uint32_t        csr_tail;               /* last written tail value */
+       uint16_t        nb_processed_responses;
+       /* number of responses processed since last CSR head write */
+       uint16_t        nb_pending_requests;
+       /* number of requests pending since last CSR tail write */
 };
 
 struct qat_qp {
        void                    *mmap_bar_addr;
-       rte_atomic16_t          inflights16;
+       uint16_t                inflights16;
        struct  qat_queue       tx_q;
        struct  qat_queue       rx_q;
        struct  rte_cryptodev_stats stats;
        struct rte_mempool *op_cookie_pool;
        void **op_cookies;
        uint32_t nb_descriptors;
+       enum qat_device_gen qat_dev_gen;
 } __rte_cache_aligned;
 
 /** private data structure for each QAT device */
@@ -85,6 +106,8 @@ struct qat_pmd_private {
        /**< Max number of queue pairs supported by device */
        unsigned max_nb_sessions;
        /**< Max number of sessions supported by device */
+       enum qat_device_gen qat_dev_gen;
+       /**< QAT device generation */
        const struct rte_cryptodev_capabilities *qat_dev_capabilities;
 };
 
@@ -103,7 +126,8 @@ void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev);
 
 int qat_crypto_sym_qp_setup(struct rte_cryptodev *dev, uint16_t queue_pair_id,
-       const struct rte_cryptodev_qp_conf *rx_conf, int socket_id);
+       const struct rte_cryptodev_qp_conf *rx_conf, int socket_id,
+       struct rte_mempool *session_pool);
 int qat_crypto_sym_qp_release(struct rte_cryptodev *dev,
        uint16_t queue_pair_id);
 
@@ -125,18 +149,19 @@ int
 qat_crypto_set_session_parameters(struct rte_cryptodev *dev,
                struct rte_crypto_sym_xform *xform, void *session_private);
 
-struct qat_session *
+int
 qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,
-                               struct qat_session *session_private);
+                               struct qat_session *session);
 
-struct qat_session *
+int
 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
                                struct rte_crypto_sym_xform *xform,
-                               struct qat_session *session_private);
+                               struct qat_session *session);
 
-void *
+int
 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
-               struct rte_crypto_sym_xform *xform, void *session_private);
+               struct rte_crypto_sym_xform *xform,
+               struct qat_session *session);
 
 
 extern void