event/octeontx2: support xstats

[dpdk.git] / drivers / event / octeontx2 / otx2_evdev.c

diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c
index 53e6890..51220f4 100644 (file)
--- a/drivers/event/octeontx2/otx2_evdev.c
+++ b/drivers/event/octeontx2/otx2_evdev.c
@@ -12,7 +12,31 @@
 #include <rte_mbuf_pool_ops.h>
 #include <rte_pci.h>
 
+#include "otx2_evdev_stats.h"
 #include "otx2_evdev.h"
+#include "otx2_irq.h"
+
+static inline int
+sso_get_msix_offsets(const struct rte_eventdev *event_dev)
+{
+       struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
+       uint8_t nb_ports = dev->nb_event_ports;
+       struct otx2_mbox *mbox = dev->mbox;
+       struct msix_offset_rsp *msix_rsp;
+       int i, rc;
+
+       /* Get SSO and SSOW MSIX vector offsets */
+       otx2_mbox_alloc_msg_msix_offset(mbox);
+       rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
+
+       for (i = 0; i < nb_ports; i++)
+               dev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];
+
+       for (i = 0; i < dev->nb_event_queues; i++)
+               dev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];
+
+       return rc;
+}
 
 static void
 otx2_sso_info_get(struct rte_eventdev *event_dev,
@@ -491,6 +515,9 @@ otx2_sso_configure(const struct rte_eventdev *event_dev)
                return -EINVAL;
        }
 
+       if (dev->configured)
+               sso_unregister_irqs(event_dev);
+
        if (dev->nb_event_queues) {
                /* Finit any previous queues. */
                sso_lf_teardown(dev, SSO_LF_GGRP);
@@ -527,6 +554,18 @@ otx2_sso_configure(const struct rte_eventdev *event_dev)
                goto teardown_hwggrp;
        }
 
+       rc = sso_get_msix_offsets(event_dev);
+       if (rc < 0) {
+               otx2_err("Failed to get msix offsets %d", rc);
+               goto teardown_hwggrp;
+       }
+
+       rc = sso_register_irqs(event_dev);
+       if (rc < 0) {
+               otx2_err("Failed to register irq %d", rc);
+               goto teardown_hwggrp;
+       }
+
        dev->configured = 1;
        rte_mb();
 
@@ -635,6 +674,82 @@ otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
        return 0;
 }
 
+static int
+otx2_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
+                      uint64_t *tmo_ticks)
+{
+       RTE_SET_USED(event_dev);
+       *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());
+
+       return 0;
+}
+
+static void
+ssogws_dump(struct otx2_ssogws *ws, FILE *f)
+{
+       uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
+
+       fprintf(f, "SSOW_LF_GWS Base addr   0x%" PRIx64 "\n", (uint64_t)base);
+       fprintf(f, "SSOW_LF_GWS_LINKS       0x%" PRIx64 "\n",
+               otx2_read64(base + SSOW_LF_GWS_LINKS));
+       fprintf(f, "SSOW_LF_GWS_PENDWQP     0x%" PRIx64 "\n",
+               otx2_read64(base + SSOW_LF_GWS_PENDWQP));
+       fprintf(f, "SSOW_LF_GWS_PENDSTATE   0x%" PRIx64 "\n",
+               otx2_read64(base + SSOW_LF_GWS_PENDSTATE));
+       fprintf(f, "SSOW_LF_GWS_NW_TIM      0x%" PRIx64 "\n",
+               otx2_read64(base + SSOW_LF_GWS_NW_TIM));
+       fprintf(f, "SSOW_LF_GWS_TAG         0x%" PRIx64 "\n",
+               otx2_read64(base + SSOW_LF_GWS_TAG));
+       fprintf(f, "SSOW_LF_GWS_WQP         0x%" PRIx64 "\n",
+               otx2_read64(base + SSOW_LF_GWS_TAG));
+       fprintf(f, "SSOW_LF_GWS_SWTP        0x%" PRIx64 "\n",
+               otx2_read64(base + SSOW_LF_GWS_SWTP));
+       fprintf(f, "SSOW_LF_GWS_PENDTAG     0x%" PRIx64 "\n",
+               otx2_read64(base + SSOW_LF_GWS_PENDTAG));
+}
+
+static void
+ssoggrp_dump(uintptr_t base, FILE *f)
+{
+       fprintf(f, "SSO_LF_GGRP Base addr   0x%" PRIx64 "\n", (uint64_t)base);
+       fprintf(f, "SSO_LF_GGRP_QCTL        0x%" PRIx64 "\n",
+               otx2_read64(base + SSO_LF_GGRP_QCTL));
+       fprintf(f, "SSO_LF_GGRP_XAQ_CNT     0x%" PRIx64 "\n",
+               otx2_read64(base + SSO_LF_GGRP_XAQ_CNT));
+       fprintf(f, "SSO_LF_GGRP_INT_THR     0x%" PRIx64 "\n",
+               otx2_read64(base + SSO_LF_GGRP_INT_THR));
+       fprintf(f, "SSO_LF_GGRP_INT_CNT     0x%" PRIX64 "\n",
+               otx2_read64(base + SSO_LF_GGRP_INT_CNT));
+       fprintf(f, "SSO_LF_GGRP_AQ_CNT      0x%" PRIX64 "\n",
+               otx2_read64(base + SSO_LF_GGRP_AQ_CNT));
+       fprintf(f, "SSO_LF_GGRP_AQ_THR      0x%" PRIX64 "\n",
+               otx2_read64(base + SSO_LF_GGRP_AQ_THR));
+       fprintf(f, "SSO_LF_GGRP_MISC_CNT    0x%" PRIx64 "\n",
+               otx2_read64(base + SSO_LF_GGRP_MISC_CNT));
+}
+
+static void
+otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)
+{
+       struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
+       uint8_t queue;
+       uint8_t port;
+
+       /* Dump SSOW registers */
+       for (port = 0; port < dev->nb_event_ports; port++) {
+               fprintf(f, "[%s]SSO single workslot[%d] dump\n",
+                       __func__, port);
+               ssogws_dump(event_dev->data->ports[port], f);
+       }
+
+       /* Dump SSO registers */
+       for (queue = 0; queue < dev->nb_event_queues; queue++) {
+               fprintf(f, "[%s]SSO group[%d] dump\n", __func__, queue);
+               struct otx2_ssogws *ws = event_dev->data->ports[0];
+               ssoggrp_dump(ws->grps_base[queue], f);
+       }
+}
+
 /* Initialize and register event driver with DPDK Application */
 static struct rte_eventdev_ops otx2_sso_ops = {
        .dev_infos_get    = otx2_sso_info_get,
@@ -647,6 +762,13 @@ static struct rte_eventdev_ops otx2_sso_ops = {
        .port_release     = otx2_sso_port_release,
        .port_link        = otx2_sso_port_link,
        .port_unlink      = otx2_sso_port_unlink,
+       .timeout_ticks    = otx2_sso_timeout_ticks,
+
+       .xstats_get       = otx2_sso_xstats_get,
+       .xstats_reset     = otx2_sso_xstats_reset,
+       .xstats_get_names = otx2_sso_xstats_get_names,
+
+       .dump             = otx2_sso_dump,
 };
 
 #define OTX2_SSO_XAE_CNT       "xae_cnt"