event/octeontx2: add device configure function

[dpdk.git] / drivers / event / octeontx2 / otx2_evdev.h

diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h
index 1df2332..feb4ed6 100644 (file)
--- a/drivers/event/octeontx2/otx2_evdev.h
+++ b/drivers/event/octeontx2/otx2_evdev.h
@@ -8,6 +8,8 @@
 #include <rte_eventdev.h>
 
 #include "otx2_common.h"
+#include "otx2_dev.h"
+#include "otx2_mempool.h"
 
 #define EVENTDEV_NAME_OCTEONTX2_PMD otx2_eventdev
 
@@ -16,9 +18,37 @@
 #define OTX2_SSO_MAX_VHGRP                  RTE_EVENT_MAX_QUEUES_PER_DEV
 #define OTX2_SSO_MAX_VHWS                   (UINT8_MAX)
 
-struct otx2_sso_evdev {
+#define USEC2NSEC(__us)                 ((__us) * 1E3)
+
+enum otx2_sso_lf_type {
+       SSO_LF_GGRP,
+       SSO_LF_GWS
 };
 
+struct otx2_sso_evdev {
+       OTX2_DEV; /* Base class */
+       uint8_t max_event_queues;
+       uint8_t max_event_ports;
+       uint8_t is_timeout_deq;
+       uint8_t nb_event_queues;
+       uint8_t nb_event_ports;
+       uint8_t configured;
+       uint32_t deq_tmo_ns;
+       uint32_t min_dequeue_timeout_ns;
+       uint32_t max_dequeue_timeout_ns;
+       int32_t max_num_events;
+       /* HW const */
+       uint32_t xae_waes;
+       uint32_t xaq_buf_size;
+       uint32_t iue;
+} __rte_cache_aligned;
+
+static inline struct otx2_sso_evdev *
+sso_pmd_priv(const struct rte_eventdev *event_dev)
+{
+       return event_dev->data->dev_private;
+}
+
 /* Init and Fini API's */
 int otx2_sso_init(struct rte_eventdev *event_dev);
 int otx2_sso_fini(struct rte_eventdev *event_dev);