net/axgbe: support priority flow control

[dpdk.git] / drivers / net / axgbe / axgbe_ethdev.h

diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h
index a1083b1..f10ec4a 100644 (file)
--- a/drivers/net/axgbe/axgbe_ethdev.h
+++ b/drivers/net/axgbe/axgbe_ethdev.h
@@ -16,7 +16,8 @@
 #define AXGBE_TX_MAX_BUF_SIZE          (0x3fff & ~(64 - 1))
 #define AXGBE_RX_MAX_BUF_SIZE          (0x3fff & ~(64 - 1))
 #define AXGBE_RX_MIN_BUF_SIZE          (RTE_ETHER_MAX_LEN + VLAN_HLEN)
-#define AXGBE_MAX_MAC_ADDRS            1
+#define AXGBE_MAX_MAC_ADDRS            32
+#define AXGBE_MAX_HASH_MAC_ADDRS       256
 
 #define AXGBE_RX_BUF_ALIGN             64
 
@@ -83,7 +84,7 @@
        (((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2)
 #define AXGMAC_FLOW_CONTROL_MAX                33280
 
-/* Maximum MAC address hash table size (256 bits = 8 bytes) */
+/* Maximum MAC address hash table size (256 bits = 8 dword) */
 #define AXGBE_MAC_HASH_TABLE_SIZE      8
 
 /* Receive Side Scaling */
@@ -485,6 +486,16 @@ struct axgbe_mmc_stats {
        uint64_t rxwatchdogerror;
 };
 
+/* Flow control parameters */
+struct xgbe_fc_info {
+       uint32_t high_water[AXGBE_PRIORITY_QUEUES];
+       uint32_t low_water[AXGBE_PRIORITY_QUEUES];
+       uint16_t pause_time[AXGBE_PRIORITY_QUEUES];
+       uint16_t send_xon;
+       enum rte_eth_fc_mode mode;
+       uint8_t autoneg;
+};
+
 /*
  * Structure to store private data for each port.
  */
@@ -576,6 +587,7 @@ struct axgbe_port {
        unsigned int rx_rfa[AXGBE_MAX_QUEUES];
        unsigned int rx_rfd[AXGBE_MAX_QUEUES];
        unsigned int fifo;
+       unsigned int pfc_map[AXGBE_MAX_QUEUES];
 
        /* Receive Side Scaling settings */
        u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE];
@@ -625,11 +637,21 @@ struct axgbe_port {
        uint32_t rx_csum_enable;
 
        struct axgbe_mmc_stats mmc_stats;
+       struct xgbe_fc_info fc;
+
+       /* Hash filtering */
+       unsigned int hash_table_shift;
+       unsigned int hash_table_count;
+       unsigned int uc_hash_mac_addr;
+       unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE];
 };
 
 void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if);
 void axgbe_init_function_ptrs_phy(struct axgbe_phy_if *phy_if);
 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if);
 void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if);
+void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr,
+                            uint32_t index);
+void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add);
 
 #endif /* RTE_ETH_AXGBE_H_ */