return rc;
}
-static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
+static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size,
struct bnxt_ctx_mem_buf_info *ctx)
{
if (!ctx)
return -EINVAL;
- ctx->va = rte_zmalloc(type, size, 0);
+ ctx->va = rte_zmalloc_socket(type, size, 0,
+ bp->eth_dev->device->numa_node);
if (ctx->va == NULL)
return -ENOMEM;
rte_mem_lock_page(ctx->va);
sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
/* 4 bytes for each counter-id */
- rc = bnxt_alloc_ctx_mem_buf(type,
+ rc = bnxt_alloc_ctx_mem_buf(bp, type,
max_fc * 4,
&bp->flow_stat->rx_fc_in_tbl);
if (rc)
sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
/* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
- rc = bnxt_alloc_ctx_mem_buf(type,
+ rc = bnxt_alloc_ctx_mem_buf(bp, type,
max_fc * 16,
&bp->flow_stat->rx_fc_out_tbl);
if (rc)
sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
/* 4 bytes for each counter-id */
- rc = bnxt_alloc_ctx_mem_buf(type,
+ rc = bnxt_alloc_ctx_mem_buf(bp, type,
max_fc * 4,
&bp->flow_stat->tx_fc_in_tbl);
if (rc)
sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
/* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
- rc = bnxt_alloc_ctx_mem_buf(type,
+ rc = bnxt_alloc_ctx_mem_buf(bp, type,
max_fc * 16,
&bp->flow_stat->tx_fc_out_tbl);
if (rc)
dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
+ dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
+ RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
dev_info->default_rxconf = (struct rte_eth_rxconf) {
.rx_thresh = {
bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
{
struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
- struct bnxt_tx_ring_info *txr;
- struct bnxt_cp_ring_info *cpr;
- struct rte_mbuf **tx_buf;
- struct tx_pkt_cmpl *txcmp;
- uint32_t cons, cp_cons;
+ struct bnxt_cp_ring_info *cpr = txq->cp_ring;
+ uint32_t ring_mask, raw_cons, nb_tx_pkts = 0;
+ struct bnxt_ring *cp_ring_struct;
+ struct cmpl_base *cp_desc_ring;
int rc;
- if (!txq)
- return -EINVAL;
-
rc = is_bnxt_in_error(txq->bp);
if (rc)
return rc;
- cpr = txq->cp_ring;
- txr = txq->tx_ring;
-
if (offset >= txq->nb_tx_desc)
return -EINVAL;
- cons = RING_CMP(cpr->cp_ring_struct, offset);
- txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
- cp_cons = cpr->cp_raw_cons;
+ /* Return "desc done" if descriptor is available for use. */
+ if (bnxt_tx_bds_in_hw(txq) <= offset)
+ return RTE_ETH_TX_DESC_DONE;
- if (cons > cp_cons) {
- if (CMPL_VALID(txcmp, cpr->valid))
- return RTE_ETH_TX_DESC_UNAVAIL;
- } else {
- if (CMPL_VALID(txcmp, !cpr->valid))
- return RTE_ETH_TX_DESC_UNAVAIL;
+ raw_cons = cpr->cp_raw_cons;
+ cp_desc_ring = cpr->cp_desc_ring;
+ cp_ring_struct = cpr->cp_ring_struct;
+ ring_mask = cpr->cp_ring_struct->ring_mask;
+
+ /* Check to see if hw has posted a completion for the descriptor. */
+ while (1) {
+ struct tx_cmpl *txcmp;
+ uint32_t cons;
+
+ cons = RING_CMPL(ring_mask, raw_cons);
+ txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
+
+ if (!CMP_VALID(txcmp, raw_cons, cp_ring_struct))
+ break;
+
+ if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)
+ nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque);
+
+ if (nb_tx_pkts > offset)
+ return RTE_ETH_TX_DESC_DONE;
+
+ raw_cons = NEXT_RAW_CMP(raw_cons);
}
- tx_buf = &txr->tx_buf_ring[cons];
- if (*tx_buf == NULL)
- return RTE_ETH_TX_DESC_DONE;
+ /* Descriptor is pending transmit, not yet completed by hardware. */
return RTE_ETH_TX_DESC_FULL;
}
if (!mz) {
mz = rte_memzone_reserve_aligned(mz_name,
rmem->nr_pages * 8,
- SOCKET_ID_ANY,
+ bp->eth_dev->device->numa_node,
RTE_MEMZONE_2MB |
RTE_MEMZONE_SIZE_HINT_ONLY |
RTE_MEMZONE_IOVA_CONTIG,
if (!mz) {
mz = rte_memzone_reserve_aligned(mz_name,
mem_size,
- SOCKET_ID_ANY,
+ bp->eth_dev->device->numa_node,
RTE_MEMZONE_1GB |
RTE_MEMZONE_SIZE_HINT_ONLY |
RTE_MEMZONE_IOVA_CONTIG,