/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2018 Broadcom
+ * Copyright(c) 2014-2021 Broadcom
* All rights reserved.
*/
#define HWRM_SPEC_CODE_1_8_3 0x10803
#define HWRM_VERSION_1_9_1 0x10901
#define HWRM_VERSION_1_9_2 0x10903
-
+#define HWRM_VERSION_1_10_2_13 0x10a020d
struct bnxt_plcmodes_cfg {
uint32_t flags;
uint16_t jumbo_thresh;
}
}
+static struct bnxt_cp_ring_info*
+bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
+{
+ struct bnxt_cp_ring_info *cp_ring = NULL;
+ uint16_t i;
+
+ switch (type) {
+ case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
+ case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
+ /* FALLTHROUGH */
+ for (i = 0; i < bp->rx_cp_nr_rings; i++) {
+ struct bnxt_rx_queue *rxq = bp->rx_queues[i];
+
+ if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
+ rte_cpu_to_le_16(rid)) {
+ return rxq->cp_ring;
+ }
+ }
+ break;
+ case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
+ for (i = 0; i < bp->tx_cp_nr_rings; i++) {
+ struct bnxt_tx_queue *txq = bp->tx_queues[i];
+
+ if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
+ rte_cpu_to_le_16(rid)) {
+ return txq->cp_ring;
+ }
+ }
+ break;
+ default:
+ return cp_ring;
+ }
+ return cp_ring;
+}
+
+/* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
+ * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
+ * before timeout, we force the done bit for the cleanup to proceed.
+ * Also if cpr is null, do nothing.. The HWRM command is not for a
+ * Tx/Rx/AGG ring cleanup.
+ */
+static int
+bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
+ bool tx, bool rx, bool timeout)
+{
+ int done = 0;
+
+ if (cpr != NULL) {
+ if (tx)
+ done = bnxt_flush_tx_cmp(cpr);
+
+ if (rx)
+ done = bnxt_flush_rx_cmp(cpr);
+
+ if (done)
+ PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
+ rx ? "Rx" : "Tx");
+
+ /* We are about to timeout and still haven't seen the
+ * HWRM done for the Ring free. Force the cleanup.
+ */
+ if (!done && timeout) {
+ done = 1;
+ PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
+ rx ? "Rx" : "Tx");
+ }
+ } else {
+ /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
+ * Otherwise the cpr would have been valid. So do nothing.
+ */
+ done = 1;
+ }
+
+ return done;
+}
+
/*
* HWRM Functions (sent to HWRM)
* These are named bnxt_hwrm_*() and return 0 on success or -110 if the
GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
uint16_t mb_trigger_offset = use_kong_mb ?
GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
+ struct bnxt_cp_ring_info *cpr = NULL;
+ bool is_rx = false;
+ bool is_tx = false;
uint32_t timeout;
/* Do not send HWRM commands to firmware in error state */
timeout = bp->hwrm_cmd_timeout;
+ /* Update the message length for backing store config for new FW. */
+ if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
+ rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
+ msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
+
if (bp->flags & BNXT_FLAG_SHORT_CMD ||
msg_len > bp->max_req_len) {
void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
*/
rte_io_mb();
+ /* Check ring flush is done.
+ * This is valid only for Tx and Rx rings (including AGG rings).
+ * The Tx and Rx rings should be freed once the HW confirms all
+ * the internal buffers and BDs associated with the rings are
+ * consumed and the corresponding DMA is handled.
+ */
+ if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
+ /* Check if the TxCQ matches. If that fails check if RxCQ
+ * matches. And if neither match, is_rx = false, is_tx = false.
+ */
+ cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
+ HWRM_RING_FREE_INPUT_RING_TYPE_TX);
+ if (cpr == NULL) {
+ /* Not a TxCQ. Check if the RxCQ matches. */
+ cpr =
+ bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
+ HWRM_RING_FREE_INPUT_RING_TYPE_RX);
+ if (cpr != NULL)
+ is_rx = true;
+ } else {
+ is_tx = true;
+ }
+ }
+
/* Poll for the valid bit */
for (i = 0; i < timeout; i++) {
+ int done;
+
+ done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
+ i == timeout - 1);
/* Sanity check on the resp->resp_len */
rte_io_rmb();
if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
/* Last byte of resp contains the valid key */
valid = (uint8_t *)resp + resp->resp_len - 1;
- if (*valid == HWRM_RESP_VALID_KEY)
+ if (*valid == HWRM_RESP_VALID_KEY && done)
break;
}
rte_delay_us(1);
HWRM_CHECK_RESULT();
- if (!BNXT_CHIP_P5(bp) &&
- !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
- return 0;
+ if (BNXT_CHIP_P5(bp)) {
+ if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS))
+ return 0;
+ } else {
+ if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
+ return 0;
+ }
if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
return 0;
}
-void bnxt_hwrm_free_vf_info(struct bnxt *bp)
+void bnxt_free_vf_info(struct bnxt *bp)
{
int i;
+ if (bp->pf == NULL)
+ return;
+
+ if (bp->pf->vf_info == NULL)
+ return;
+
for (i = 0; i < bp->pf->max_vfs; i++) {
rte_free(bp->pf->vf_info[i].vlan_table);
bp->pf->vf_info[i].vlan_table = NULL;
bp->pf->vf_info = NULL;
}
+static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
+{
+ struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
+ int i;
+
+ if (vf_info)
+ bnxt_free_vf_info(bp);
+
+ vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
+ if (vf_info == NULL) {
+ PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
+ return -ENOMEM;
+ }
+
+ bp->pf->max_vfs = max_vfs;
+ for (i = 0; i < max_vfs; i++) {
+ vf_info[i].fid = bp->pf->first_vf_id + i;
+ vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
+ getpagesize(), getpagesize());
+ if (vf_info[i].vlan_table == NULL) {
+ PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
+ goto err;
+ }
+ rte_mem_lock_page(vf_info[i].vlan_table);
+
+ vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
+ getpagesize(), getpagesize());
+ if (vf_info[i].vlan_as_table == NULL) {
+ PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
+ goto err;
+ }
+ rte_mem_lock_page(vf_info[i].vlan_as_table);
+
+ STAILQ_INIT(&vf_info[i].filter);
+ }
+
+ bp->pf->vf_info = vf_info;
+
+ return 0;
+err:
+ bnxt_free_vf_info(bp);
+ return -ENOMEM;
+}
+
static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
{
int rc = 0;
struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
uint16_t new_max_vfs;
uint32_t flags;
- int i;
HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
new_max_vfs = bp->pdev->max_vfs;
if (new_max_vfs != bp->pf->max_vfs) {
- if (bp->pf->vf_info)
- bnxt_hwrm_free_vf_info(bp);
- bp->pf->vf_info = rte_zmalloc("bnxt_vf_info",
- sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
- if (bp->pf->vf_info == NULL) {
- PMD_DRV_LOG(ERR, "Alloc vf info fail\n");
- HWRM_UNLOCK();
- return -ENOMEM;
- }
- bp->pf->max_vfs = new_max_vfs;
- for (i = 0; i < new_max_vfs; i++) {
- bp->pf->vf_info[i].fid =
- bp->pf->first_vf_id + i;
- bp->pf->vf_info[i].vlan_table =
- rte_zmalloc("VF VLAN table",
- getpagesize(),
- getpagesize());
- if (bp->pf->vf_info[i].vlan_table == NULL)
- PMD_DRV_LOG(ERR,
- "Fail to alloc VLAN table for VF %d\n",
- i);
- else
- rte_mem_lock_page(
- bp->pf->vf_info[i].vlan_table);
- bp->pf->vf_info[i].vlan_as_table =
- rte_zmalloc("VF VLAN AS table",
- getpagesize(),
- getpagesize());
- if (bp->pf->vf_info[i].vlan_as_table == NULL)
- PMD_DRV_LOG(ERR,
- "Alloc VLAN AS table for VF %d fail\n",
- i);
- else
- rte_mem_lock_page(
- bp->pf->vf_info[i].vlan_as_table);
- STAILQ_INIT(&bp->pf->vf_info[i].filter);
- }
+ rc = bnxt_alloc_vf_info(bp, new_max_vfs);
+ if (rc)
+ goto unlock;
}
}
if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
+unlock:
HWRM_UNLOCK();
return rc;
int rc;
rc = __bnxt_hwrm_func_qcaps(bp);
+ if (rc == -ENOMEM)
+ return rc;
+
if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
rc = bnxt_alloc_ctx_mem(bp);
if (rc)
req.async_event_fwd[1] |=
rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
+ req.async_event_fwd[2] |=
+ rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST |
+ ASYNC_CMPL_EVENT_ID_ERROR_REPORT);
+
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
HWRM_CHECK_RESULT();
else
HWRM_CHECK_RESULT();
- PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
+ if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
+ rc = -EAGAIN;
+ goto error;
+ }
+
+ PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
- resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
+ resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
+ resp->hwrm_fw_rsvd_8b);
bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
(resp->hwrm_fw_min_8b << 16) |
(resp->hwrm_fw_bld_8b << 8) |
if (bp->max_req_len > resp->max_req_win_len) {
PMD_DRV_LOG(ERR, "Unsupported request length\n");
rc = -EINVAL;
+ goto error;
}
bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
- if (bp->max_resp_len != max_resp_len) {
- sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
- bp->pdev->addr.domain, bp->pdev->addr.bus,
- bp->pdev->addr.devid, bp->pdev->addr.function);
-
- rte_free(bp->hwrm_cmd_resp_addr);
-
- bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
- if (bp->hwrm_cmd_resp_addr == NULL) {
- rc = -ENOMEM;
- goto error;
- }
- bp->hwrm_cmd_resp_dma_addr =
- rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
- if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
- PMD_DRV_LOG(ERR,
- "Unable to map response buffer to physical memory.\n");
- rc = -ENOMEM;
- goto error;
- }
- bp->max_resp_len = max_resp_len;
- }
+ RTE_VERIFY(max_resp_len <= bp->max_resp_len);
+ bp->max_resp_len = max_resp_len;
if ((dev_caps_cfg &
HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
}
+ if (dev_caps_cfg &
+ HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED) {
+ PMD_DRV_LOG(DEBUG, "Host-based truflow feature enabled.\n");
+ bp->fw_cap |= BNXT_FW_CAP_TRUFLOW_EN;
+ }
error:
HWRM_UNLOCK();
HWRM_CHECK_RESULT();
HWRM_UNLOCK();
+ PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
+ bp->eth_dev->data->port_id);
+
return rc;
}
link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
+ link_info->auto_link_speed_mask = rte_le_to_cpu_16(resp->auto_link_speed_mask);
link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
link_info->phy_ver[0] = resp->phy_maj;
rte_le_to_cpu_16(resp->support_pam4_speeds);
link_info->auto_pam4_link_speeds =
rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
+ link_info->module_status = resp->module_status;
HWRM_UNLOCK();
PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
- HWRM_CHECK_RESULT();
+ HWRM_CHECK_RESULT_SILENT();
bp->port_cnt = resp->port_cnt;
if (resp->supported_speeds_auto_mode)
HWRM_UNLOCK();
+ /* Older firmware does not have supported_auto_speeds, so assume
+ * that all supported speeds can be autonegotiated.
+ */
+ if (link_info->auto_link_speed_mask && !link_info->support_auto_speeds)
+ link_info->support_auto_speeds = link_info->support_speeds;
+
return 0;
}
}
int bnxt_hwrm_ring_free(struct bnxt *bp,
- struct bnxt_ring *ring, uint32_t ring_type)
+ struct bnxt_ring *ring, uint32_t ring_type,
+ uint16_t cp_ring_id)
{
int rc;
struct hwrm_ring_free_input req = {.req_type = 0 };
struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
+ if (ring->fw_ring_id == INVALID_HW_RING_ID)
+ return -EINVAL;
+
HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
req.ring_type = ring_type;
req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
+ req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+ ring->fw_ring_id = INVALID_HW_RING_ID;
if (rc || resp->error_code) {
if (rc == 0 && resp->error_code)
struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
- if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
+ if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
return rc;
HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
return rc;
}
-int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
- unsigned int idx __rte_unused)
+int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
{
int rc;
struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
+ if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE)
+ return 0;
+
HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
req.update_period_ms = rte_cpu_to_le_32(0);
return rc;
}
-int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
- unsigned int idx __rte_unused)
+static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
{
int rc;
struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
+ if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
+ return 0;
+
HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
HWRM_CHECK_RESULT();
HWRM_UNLOCK();
+ cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
+
return rc;
}
if (vnic->bd_stall)
req.flags |=
rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
- if (vnic->roce_dual)
- req.flags |= rte_cpu_to_le_32(
- HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
- if (vnic->roce_only)
- req.flags |= rte_cpu_to_le_32(
- HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
if (vnic->rss_dflt_cr)
req.flags |= rte_cpu_to_le_32(
HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
- vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
- HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
- vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
- HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
unsigned int i;
struct bnxt_cp_ring_info *cpr;
- for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
+ for (i = 0; i < bp->rx_cp_nr_rings; i++) {
- if (i >= bp->rx_cp_nr_rings) {
- cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
- } else {
- cpr = bp->rx_queues[i]->cp_ring;
- if (BNXT_HAS_RING_GRPS(bp))
- bp->grp_info[i].fw_stats_ctx = -1;
- }
- if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
- rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
- cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
- if (rc)
- return rc;
- }
+ cpr = bp->rx_queues[i]->cp_ring;
+ if (BNXT_HAS_RING_GRPS(bp))
+ bp->grp_info[i].fw_stats_ctx = -1;
+ rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
+ if (rc)
+ return rc;
}
+
+ for (i = 0; i < bp->tx_cp_nr_rings; i++) {
+ cpr = bp->tx_queues[i]->cp_ring;
+ rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
+ if (rc)
+ return rc;
+ }
+
return 0;
}
int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
{
+ struct bnxt_cp_ring_info *cpr;
unsigned int i;
int rc = 0;
- for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
- struct bnxt_tx_queue *txq;
- struct bnxt_rx_queue *rxq;
- struct bnxt_cp_ring_info *cpr;
+ for (i = 0; i < bp->rx_cp_nr_rings; i++) {
+ struct bnxt_rx_queue *rxq = bp->rx_queues[i];
- if (i >= bp->rx_cp_nr_rings) {
- txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
- cpr = txq->cp_ring;
- } else {
- rxq = bp->rx_queues[i];
- cpr = rxq->cp_ring;
+ cpr = rxq->cp_ring;
+ if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE) {
+ rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
+ if (rc)
+ return rc;
}
+ }
- rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
+ for (i = 0; i < bp->tx_cp_nr_rings; i++) {
+ struct bnxt_tx_queue *txq = bp->tx_queues[i];
- if (rc)
- return rc;
+ cpr = txq->cp_ring;
+ if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE) {
+ rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
+ if (rc)
+ return rc;
+ }
}
+
return rc;
}
struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
bnxt_hwrm_ring_free(bp, cp_ring,
- HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
- cp_ring->fw_ring_id = INVALID_HW_RING_ID;
- memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
- sizeof(*cpr->cp_desc_ring));
+ HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
+ INVALID_HW_RING_ID);
+ memset(cpr->cp_desc_ring, 0,
+ cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
cpr->cp_raw_cons = 0;
- cpr->valid = 0;
}
void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
bnxt_hwrm_ring_free(bp, cp_ring,
- HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
- cp_ring->fw_ring_id = INVALID_HW_RING_ID;
- memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
- sizeof(*cpr->cp_desc_ring));
+ HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
+ INVALID_HW_RING_ID);
+ memset(cpr->cp_desc_ring, 0,
+ cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
cpr->cp_raw_cons = 0;
- cpr->valid = 0;
}
void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
struct bnxt_ring *ring = rxr->rx_ring_struct;
struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
- if (ring->fw_ring_id != INVALID_HW_RING_ID) {
- bnxt_hwrm_ring_free(bp, ring,
- HWRM_RING_FREE_INPUT_RING_TYPE_RX);
- ring->fw_ring_id = INVALID_HW_RING_ID;
- if (BNXT_HAS_RING_GRPS(bp))
- bp->grp_info[queue_index].rx_fw_ring_id =
- INVALID_HW_RING_ID;
- }
+ bnxt_hwrm_ring_free(bp, ring,
+ HWRM_RING_FREE_INPUT_RING_TYPE_RX,
+ cpr->cp_ring_struct->fw_ring_id);
+ if (BNXT_HAS_RING_GRPS(bp))
+ bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
+
ring = rxr->ag_ring_struct;
- if (ring->fw_ring_id != INVALID_HW_RING_ID) {
- bnxt_hwrm_ring_free(bp, ring,
- BNXT_CHIP_P5(bp) ?
- HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
- HWRM_RING_FREE_INPUT_RING_TYPE_RX);
- if (BNXT_HAS_RING_GRPS(bp))
- bp->grp_info[queue_index].ag_fw_ring_id =
- INVALID_HW_RING_ID;
- }
- if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
- bnxt_free_cp_ring(bp, cpr);
+ bnxt_hwrm_ring_free(bp, ring,
+ BNXT_CHIP_P5(bp) ?
+ HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
+ HWRM_RING_FREE_INPUT_RING_TYPE_RX,
+ cpr->cp_ring_struct->fw_ring_id);
+ if (BNXT_HAS_RING_GRPS(bp))
+ bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
+
+ bnxt_hwrm_stat_ctx_free(bp, cpr);
+
+ bnxt_free_cp_ring(bp, cpr);
if (BNXT_HAS_RING_GRPS(bp))
bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
}
+int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int queue_index)
+{
+ int rc;
+ struct hwrm_ring_reset_input req = {.req_type = 0 };
+ struct hwrm_ring_reset_output *resp = bp->hwrm_cmd_resp_addr;
+
+ HWRM_PREP(&req, HWRM_RING_RESET, BNXT_USE_CHIMP_MB);
+
+ req.ring_type = HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP;
+ req.ring_id = rte_cpu_to_le_16(bp->grp_info[queue_index].fw_grp_id);
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+
+ HWRM_CHECK_RESULT();
+
+ HWRM_UNLOCK();
+
+ return rc;
+}
+
static int
bnxt_free_all_hwrm_rings(struct bnxt *bp)
{
unsigned int i;
- for (i = 0; i < bp->tx_cp_nr_rings; i++) {
- struct bnxt_tx_queue *txq = bp->tx_queues[i];
- struct bnxt_tx_ring_info *txr = txq->tx_ring;
- struct bnxt_ring *ring = txr->tx_ring_struct;
- struct bnxt_cp_ring_info *cpr = txq->cp_ring;
-
- if (ring->fw_ring_id != INVALID_HW_RING_ID) {
- bnxt_hwrm_ring_free(bp, ring,
- HWRM_RING_FREE_INPUT_RING_TYPE_TX);
- ring->fw_ring_id = INVALID_HW_RING_ID;
- memset(txr->tx_desc_ring, 0,
- txr->tx_ring_struct->ring_size *
- sizeof(*txr->tx_desc_ring));
- memset(txr->tx_buf_ring, 0,
- txr->tx_ring_struct->ring_size *
- sizeof(*txr->tx_buf_ring));
- txr->tx_raw_prod = 0;
- txr->tx_raw_cons = 0;
- }
- if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
- bnxt_free_cp_ring(bp, cpr);
- cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
- }
- }
+ for (i = 0; i < bp->tx_cp_nr_rings; i++)
+ bnxt_free_hwrm_tx_ring(bp, i);
for (i = 0; i < bp->rx_cp_nr_rings; i++)
bnxt_free_hwrm_rx_ring(bp, i);
sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
- bp->max_resp_len = HWRM_MAX_RESP_LEN;
+ bp->max_resp_len = BNXT_PAGE_SIZE;
bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
if (bp->hwrm_cmd_resp_addr == NULL)
return -ENOMEM;
speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
bp->link_info->link_signal_mode);
link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
- /* Autoneg can be done only when the FW allows.
- * When user configures fixed speed of 40G and later changes to
- * any other speed, auto_link_speed/force_link_speed is still set
- * to 40G until link comes up at new speed.
- */
- if (autoneg == 1 &&
- !(!BNXT_CHIP_P5(bp) &&
- (bp->link_info->auto_link_speed ||
- bp->link_info->force_link_speed))) {
+ /* Autoneg can be done only when the FW allows. */
+ if (autoneg == 1 && bp->link_info->support_auto_speeds) {
link_req.phy_flags |=
HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
link_req.auto_link_speed_mask =
return rc;
}
-/* JIRA 22088 */
int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
{
struct hwrm_func_qcfg_input req = {0};
HWRM_CHECK_RESULT();
- /* Hard Coded.. 0xfff VLAN ID mask */
- bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
+ bp->vlan = rte_le_to_cpu_16(resp->vlan) & ETH_VLAN_ID_MAX;
svif_info = rte_le_to_cpu_16(resp->svif_info);
if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
}
if (mtu)
- *mtu = rte_le_to_cpu_16(resp->mtu);
+ *mtu = rte_le_to_cpu_16(resp->admin_mtu);
switch (resp->port_partition_type) {
case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
- HWRM_CHECK_RESULT();
+ HWRM_CHECK_RESULT_SILENT();
memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
bp->parent->fid = rte_le_to_cpu_16(resp->fid);
bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
- /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
- if (bp->parent->vnic == 0) {
- PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
- /* Use hard-coded values appropriate for current Wh+ fw. */
- if (bp->parent->fid == 2)
- bp->parent->vnic = 0x100;
- else
- bp->parent->vnic = 1;
- }
-
HWRM_UNLOCK();
return 0;
uint32_t enables;
int rc;
- enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
+ enables = HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
+ HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU |
HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
}
req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
- req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
+ req.admin_mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
+ req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
struct hwrm_func_cfg_input *req,
int num_vfs)
{
- req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
+ req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
- req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
- RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
- BNXT_NUM_VLANS);
+ req->admin_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
+ RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
+ BNXT_NUM_VLANS);
req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
(num_vfs + 1));
return rc;
}
-int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
- struct rte_eth_stats *stats, uint8_t rx)
+static void bnxt_update_prev_stat(uint64_t *cntr, uint64_t *prev_cntr)
+{
+ /* One of the HW stat values that make up this counter was zero as
+ * returned by HW in this iteration, so use the previous
+ * iteration's counter value
+ */
+ if (*prev_cntr && *cntr == 0)
+ *cntr = *prev_cntr;
+ else
+ *prev_cntr = *cntr;
+}
+
+int bnxt_hwrm_ring_stats(struct bnxt *bp, uint32_t cid, int idx,
+ struct bnxt_ring_stats *ring_stats, bool rx)
{
int rc = 0;
struct hwrm_stat_ctx_query_input req = {.req_type = 0};
HWRM_CHECK_RESULT();
if (rx) {
- stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
- stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
- stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
- stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
- stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
- stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
- stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_discard_pkts);
- stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_error_pkts);
+ struct bnxt_ring_stats *prev_stats = &bp->prev_rx_ring_stats[idx];
+
+ ring_stats->rx_ucast_pkts = rte_le_to_cpu_64(resp->rx_ucast_pkts);
+ bnxt_update_prev_stat(&ring_stats->rx_ucast_pkts,
+ &prev_stats->rx_ucast_pkts);
+
+ ring_stats->rx_mcast_pkts = rte_le_to_cpu_64(resp->rx_mcast_pkts);
+ bnxt_update_prev_stat(&ring_stats->rx_mcast_pkts,
+ &prev_stats->rx_mcast_pkts);
+
+ ring_stats->rx_bcast_pkts = rte_le_to_cpu_64(resp->rx_bcast_pkts);
+ bnxt_update_prev_stat(&ring_stats->rx_bcast_pkts,
+ &prev_stats->rx_bcast_pkts);
+
+ ring_stats->rx_ucast_bytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
+ bnxt_update_prev_stat(&ring_stats->rx_ucast_bytes,
+ &prev_stats->rx_ucast_bytes);
+
+ ring_stats->rx_mcast_bytes = rte_le_to_cpu_64(resp->rx_mcast_bytes);
+ bnxt_update_prev_stat(&ring_stats->rx_mcast_bytes,
+ &prev_stats->rx_mcast_bytes);
+
+ ring_stats->rx_bcast_bytes = rte_le_to_cpu_64(resp->rx_bcast_bytes);
+ bnxt_update_prev_stat(&ring_stats->rx_bcast_bytes,
+ &prev_stats->rx_bcast_bytes);
+
+ ring_stats->rx_discard_pkts = rte_le_to_cpu_64(resp->rx_discard_pkts);
+ bnxt_update_prev_stat(&ring_stats->rx_discard_pkts,
+ &prev_stats->rx_discard_pkts);
+
+ ring_stats->rx_error_pkts = rte_le_to_cpu_64(resp->rx_error_pkts);
+ bnxt_update_prev_stat(&ring_stats->rx_error_pkts,
+ &prev_stats->rx_error_pkts);
+
+ ring_stats->rx_agg_pkts = rte_le_to_cpu_64(resp->rx_agg_pkts);
+ bnxt_update_prev_stat(&ring_stats->rx_agg_pkts,
+ &prev_stats->rx_agg_pkts);
+
+ ring_stats->rx_agg_bytes = rte_le_to_cpu_64(resp->rx_agg_bytes);
+ bnxt_update_prev_stat(&ring_stats->rx_agg_bytes,
+ &prev_stats->rx_agg_bytes);
+
+ ring_stats->rx_agg_events = rte_le_to_cpu_64(resp->rx_agg_events);
+ bnxt_update_prev_stat(&ring_stats->rx_agg_events,
+ &prev_stats->rx_agg_events);
+
+ ring_stats->rx_agg_aborts = rte_le_to_cpu_64(resp->rx_agg_aborts);
+ bnxt_update_prev_stat(&ring_stats->rx_agg_aborts,
+ &prev_stats->rx_agg_aborts);
} else {
- stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
- stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
- stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
- stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
- stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
- stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
+ struct bnxt_ring_stats *prev_stats = &bp->prev_tx_ring_stats[idx];
+
+ ring_stats->tx_ucast_pkts = rte_le_to_cpu_64(resp->tx_ucast_pkts);
+ bnxt_update_prev_stat(&ring_stats->tx_ucast_pkts,
+ &prev_stats->tx_ucast_pkts);
+
+ ring_stats->tx_mcast_pkts = rte_le_to_cpu_64(resp->tx_mcast_pkts);
+ bnxt_update_prev_stat(&ring_stats->tx_mcast_pkts,
+ &prev_stats->tx_mcast_pkts);
+
+ ring_stats->tx_bcast_pkts = rte_le_to_cpu_64(resp->tx_bcast_pkts);
+ bnxt_update_prev_stat(&ring_stats->tx_bcast_pkts,
+ &prev_stats->tx_bcast_pkts);
+
+ ring_stats->tx_ucast_bytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
+ bnxt_update_prev_stat(&ring_stats->tx_ucast_bytes,
+ &prev_stats->tx_ucast_bytes);
+
+ ring_stats->tx_mcast_bytes = rte_le_to_cpu_64(resp->tx_mcast_bytes);
+ bnxt_update_prev_stat(&ring_stats->tx_mcast_bytes,
+ &prev_stats->tx_mcast_bytes);
+
+ ring_stats->tx_bcast_bytes = rte_le_to_cpu_64(resp->tx_bcast_bytes);
+ bnxt_update_prev_stat(&ring_stats->tx_bcast_bytes,
+ &prev_stats->tx_bcast_bytes);
+
+ ring_stats->tx_discard_pkts = rte_le_to_cpu_64(resp->tx_discard_pkts);
+ bnxt_update_prev_stat(&ring_stats->tx_discard_pkts,
+ &prev_stats->tx_discard_pkts);
}
HWRM_UNLOCK();
req.port_id = bp->pf->port_id;
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
- HWRM_CHECK_RESULT();
+ HWRM_CHECK_RESULT_SILENT();
if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
unsigned int i;
return rc;
}
-
int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
uint16_t dir_ordinal, uint16_t dir_ext,
uint16_t dir_attr, const uint8_t *data,
bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
{
struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
- uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
struct bnxt_rx_queue **rxqs = bp->rx_queues;
uint16_t *ring_tbl = vnic->rss_table;
/* Find next active ring. */
for (cnt = 0; cnt < max_rings; cnt++) {
- if (rx_queue_state[k] !=
- RTE_ETH_QUEUE_STATE_STOPPED)
+ if (rxqs[k]->rx_started)
break;
if (++k == max_rings)
k = 0;
ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
- if (!ctx->tqm_fp_rings_count)
- ctx->tqm_fp_rings_count = bp->max_q;
+ ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
+ RTE_MIN(ctx->tqm_fp_rings_count,
+ BNXT_MAX_TQM_FP_LEGACY_RINGS) :
+ bp->max_q;
+
+ /* Check if the ext ring count needs to be counted.
+ * Ext ring count is available only with new FW so we should not
+ * look at the field on older FW.
+ */
+ if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
+ bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
+ ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
+ ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
+ ctx->tqm_fp_rings_count);
+ }
tqm_rings = ctx->tqm_fp_rings_count + 1;
bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
}
+ if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
+ /* DPDK does not need to configure MRAV and TIM type.
+ * So we are skipping over MRAV and TIM. Skip to configure
+ * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
+ */
+ ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
+ req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
+ bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
+ &req.tqm_ring8_pg_size_tqm_ring_lvl,
+ &req.tqm_ring8_page_dir);
+ }
+
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
HWRM_CHECK_RESULT();
HWRM_UNLOCK();
return rc;
}
+
+int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
+ uint32_t echo_req_data2)
+{
+ struct hwrm_func_echo_response_input req = {0};
+ struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
+ int rc;
+
+ HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
+ req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
+ req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
+
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+
+ HWRM_CHECK_RESULT();
+ HWRM_UNLOCK();
+
+ return rc;
+}
+
+int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
+{
+ struct hwrm_ver_get_input req = {.req_type = 0 };
+ struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
+ int rc = 0;
+
+ bp->max_req_len = HWRM_MAX_REQ_LEN;
+ bp->max_resp_len = BNXT_PAGE_SIZE;
+ bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
+
+ HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
+ req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
+ req.hwrm_intf_min = HWRM_VERSION_MINOR;
+ req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
+
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+
+ HWRM_CHECK_RESULT_SILENT();
+
+ if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
+ rc = -EAGAIN;
+
+ HWRM_UNLOCK();
+
+ return rc;
+}
+
+int bnxt_hwrm_read_sfp_module_eeprom_info(struct bnxt *bp, uint16_t i2c_addr,
+ uint16_t page_number, uint16_t start_addr,
+ uint16_t data_length, uint8_t *buf)
+{
+ struct hwrm_port_phy_i2c_read_output *resp = bp->hwrm_cmd_resp_addr;
+ struct hwrm_port_phy_i2c_read_input req = {0};
+ uint32_t enables = HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET;
+ int rc, byte_offset = 0;
+
+ do {
+ uint16_t xfer_size;
+
+ HWRM_PREP(&req, HWRM_PORT_PHY_I2C_READ, BNXT_USE_CHIMP_MB);
+ req.i2c_slave_addr = i2c_addr;
+ req.page_number = rte_cpu_to_le_16(page_number);
+ req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
+
+ xfer_size = RTE_MIN(data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
+ req.page_offset = rte_cpu_to_le_16(start_addr + byte_offset);
+ req.data_length = xfer_size;
+ req.enables = rte_cpu_to_le_32(start_addr + byte_offset ? enables : 0);
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+ HWRM_CHECK_RESULT();
+
+ memcpy(buf + byte_offset, resp->data, xfer_size);
+
+ data_length -= xfer_size;
+ byte_offset += xfer_size;
+
+ HWRM_UNLOCK();
+ } while (data_length > 0);
+
+ return rc;
+}
+
+void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index)
+{
+ struct bnxt_tx_queue *txq = bp->tx_queues[queue_index];
+ struct bnxt_tx_ring_info *txr = txq->tx_ring;
+ struct bnxt_ring *ring = txr->tx_ring_struct;
+ struct bnxt_cp_ring_info *cpr = txq->cp_ring;
+
+ bnxt_hwrm_ring_free(bp, ring,
+ HWRM_RING_FREE_INPUT_RING_TYPE_TX,
+ cpr->cp_ring_struct->fw_ring_id);
+ txr->tx_raw_prod = 0;
+ txr->tx_raw_cons = 0;
+ memset(txr->tx_desc_ring, 0,
+ txr->tx_ring_struct->ring_size * sizeof(*txr->tx_desc_ring));
+ memset(txr->tx_buf_ring, 0,
+ txr->tx_ring_struct->ring_size * sizeof(*txr->tx_buf_ring));
+
+ bnxt_hwrm_stat_ctx_free(bp, cpr);
+
+ bnxt_free_cp_ring(bp, cpr);
+}
+
+int bnxt_hwrm_config_host_mtu(struct bnxt *bp)
+{
+ struct hwrm_func_cfg_input req = {0};
+ struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
+ int rc;
+
+ if (!BNXT_PF(bp))
+ return 0;
+
+ HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
+
+ req.fid = rte_cpu_to_le_16(0xffff);
+ req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU);
+ req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
+
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+ HWRM_CHECK_RESULT();
+ HWRM_UNLOCK();
+
+ return rc;
+}
git.droids-corp.org / dpdk.git / blobdiff