#define BNXT_ULP_ACT_HID_SHFTR 0
#define BNXT_ULP_ACT_HID_SHFTL 23
#define BNXT_ULP_ACT_HID_MASK 255
+#define BNXT_ULP_DEF_IDENT_INFO_TBL_MAX_SZ 1
enum bnxt_ulp_action_bit {
BNXT_ULP_ACTION_BIT_MARK = 0x0000000000000001,
BNXT_ULP_CHF_IDX_LAST = 14
};
+enum bnxt_ulp_def_regfile_index {
+ BNXT_ULP_DEF_REGFILE_INDEX_DEF_PROF_FUNC_ID = 0,
+ BNXT_ULP_DEF_REGFILE_INDEX_LAST = 1
+};
+
enum bnxt_ulp_device_id {
BNXT_ULP_DEVICE_ID_WH_PLUS = 0,
BNXT_ULP_DEVICE_ID_THOR = 1,
BNXT_ULP_DEVICE_ID_LAST = 4
};
+enum bnxt_ulp_direction {
+ BNXT_ULP_DIRECTION_INGRESS = 0,
+ BNXT_ULP_DIRECTION_EGRESS = 1,
+ BNXT_ULP_DIRECTION_LAST = 2
+};
+
enum bnxt_ulp_hdr_type {
BNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0,
BNXT_ULP_HDR_TYPE_SUPPORTED = 1,
BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,
BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,
BNXT_ULP_MASK_OPC_SET_TO_REGFILE = 2,
- BNXT_ULP_MASK_OPC_ADD_PAD = 3,
- BNXT_ULP_MASK_OPC_LAST = 4
+ BNXT_ULP_MASK_OPC_SET_TO_DEF_REGFILE = 3,
+ BNXT_ULP_MASK_OPC_ADD_PAD = 4,
+ BNXT_ULP_MASK_OPC_LAST = 5
};
enum bnxt_ulp_match_type {
BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1,
BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 2,
BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 3,
- BNXT_ULP_RESULT_OPC_LAST = 4
+ BNXT_ULP_RESULT_OPC_SET_TO_DEF_REGFILE = 4,
+ BNXT_ULP_RESULT_OPC_LAST = 5
};
enum bnxt_ulp_search_before_alloc {
BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT = 0,
BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD = 1,
BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 2,
- BNXT_ULP_SPEC_OPC_ADD_PAD = 3,
- BNXT_ULP_SPEC_OPC_LAST = 4
+ BNXT_ULP_SPEC_OPC_SET_TO_DEF_REGFILE = 3,
+ BNXT_ULP_SPEC_OPC_ADD_PAD = 4,
+ BNXT_ULP_SPEC_OPC_LAST = 5
};
enum bnxt_ulp_encap_vtag_encoding {