net/cxgbe: support flow API for matching IP TOS

[dpdk.git] / drivers / net / cxgbe / base / common.h

diff --git a/drivers/net/cxgbe/base/common.h b/drivers/net/cxgbe/base/common.h
index a276a1e..793cad1 100644 (file)
--- a/drivers/net/cxgbe/base/common.h
+++ b/drivers/net/cxgbe/base/common.h
@@ -6,7 +6,7 @@
 #ifndef __CHELSIO_COMMON_H
 #define __CHELSIO_COMMON_H
 
-#include "cxgbe_compat.h"
+#include "../cxgbe_compat.h"
 #include "t4_hw.h"
 #include "t4vf_hw.h"
 #include "t4_chip_type.h"
@@ -156,6 +156,11 @@ struct tp_params {
        int vnic_shift;
        int port_shift;
        int protocol_shift;
+       int ethertype_shift;
+       int macmatch_shift;
+       int tos_shift;
+
+       u64 hash_filter_mask;
 };
 
 struct vpd_params {
@@ -207,6 +212,14 @@ struct rss_params {
        } u;
 };
 
+/*
+ * Maximum resources provisioned for a PCI PF.
+ */
+struct pf_resources {
+       unsigned int neq;      /* N egress Qs */
+       unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
+};
+
 /*
  * Maximum resources provisioned for a PCI VF.
  */
@@ -230,6 +243,7 @@ struct adapter_params {
        struct pci_params pci;
        struct devlog_params devlog;
        struct rss_params rss;
+       struct pf_resources pfres;
        struct vf_resources vfres;
        enum pcie_memwin drv_memwin;
 
@@ -258,6 +272,8 @@ struct adapter_params {
 
        bool ulptx_memwrite_dsgl;          /* use of T5 DSGL allowed */
        u8 fw_caps_support;               /* 32-bit Port Capabilities */
+       u8 filter2_wr_support;            /* FW support for FILTER2_WR */
+       u32 max_tx_coalesce_num; /* Max # of Tx packets that can be coalesced */
 };
 
 /* Firmware Port Capabilities types.
@@ -376,6 +392,12 @@ int t4_free_vi(struct adapter *adap, unsigned int mbox,
 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
                  int mtu, int promisc, int all_multi, int bcast, int vlanex,
                  bool sleep_ok);
+int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
+                        const u8 *addr, const u8 *mask, unsigned int idx,
+                        u8 lookup_type, u8 port_id, bool sleep_ok);
+int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
+                         const u8 *addr, const u8 *mask, unsigned int idx,
+                         u8 lookup_type, u8 port_id, bool sleep_ok);
 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
                  int idx, const u8 *addr, bool persist, bool add_smt);
 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
@@ -463,6 +485,7 @@ void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
                       unsigned int nregs, unsigned int start_idx);
 
 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
+int t4_get_pfres(struct adapter *adapter);
 int t4_read_flash(struct adapter *adapter, unsigned int addr,
                  unsigned int nwords, u32 *data, int byte_oriented);
 int t4_flash_cfg_addr(struct adapter *adapter);
@@ -501,7 +524,7 @@ void t4_read_rss_key(struct adapter *adap, u32 *key);
 
 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
-                     unsigned int qtype, u64 *pbar2_qoffset,
+                     enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
                      unsigned int *pbar2_qid);
 
 int t4_init_sge_params(struct adapter *adapter);