net/cxgbe: support flow API for source MAC rewrite

[dpdk.git] / drivers / net / cxgbe / base / t4fw_interface.h

diff --git a/drivers/net/cxgbe/base/t4fw_interface.h b/drivers/net/cxgbe/base/t4fw_interface.h
index 2433bf2..51ebe4f 100644 (file)
--- a/drivers/net/cxgbe/base/t4fw_interface.h
+++ b/drivers/net/cxgbe/base/t4fw_interface.h
@@ -55,10 +55,13 @@ enum fw_memtype {
 
 enum fw_wr_opcodes {
        FW_FILTER_WR            = 0x02,
+       FW_ULPTX_WR             = 0x04,
+       FW_TP_WR                = 0x05,
        FW_ETH_TX_PKT_WR        = 0x08,
        FW_ETH_TX_PKTS_WR       = 0x09,
        FW_ETH_TX_PKT_VM_WR     = 0x11,
        FW_ETH_TX_PKTS_VM_WR    = 0x12,
+       FW_FILTER2_WR           = 0x77,
        FW_ETH_TX_PKTS2_WR      = 0x78,
 };
 
@@ -77,6 +80,11 @@ struct fw_wr_hdr {
 #define V_FW_WR_OP(x)          ((x) << S_FW_WR_OP)
 #define G_FW_WR_OP(x)          (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
 
+/* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
+ */
+#define S_FW_WR_ATOMIC         23
+#define V_FW_WR_ATOMIC(x)      ((x) << S_FW_WR_ATOMIC)
+
 /* work request immediate data length (hi)
  */
 #define S_FW_WR_IMMDLEN        0
@@ -93,6 +101,11 @@ struct fw_wr_hdr {
 #define G_FW_WR_EQUEQ(x)       (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
 #define F_FW_WR_EQUEQ          V_FW_WR_EQUEQ(1U)
 
+/* flow context identifier (lo)
+ */
+#define S_FW_WR_FLOWID         8
+#define V_FW_WR_FLOWID(x)      ((x) << S_FW_WR_FLOWID)
+
 /* length in units of 16-bytes (lo)
  */
 #define S_FW_WR_LEN16          0
@@ -153,7 +166,7 @@ enum fw_filter_wr_cookie {
        FW_FILTER_WR_EINVAL,
 };
 
-struct fw_filter_wr {
+struct fw_filter2_wr {
        __be32 op_pkd;
        __be32 len16_pkd;
        __be64 r3;
@@ -183,6 +196,19 @@ struct fw_filter_wr {
        __be16 fpm;
        __be16 r7;
        __u8   sma[6];
+       __be16 r8;
+       __u8   filter_type_swapmac;
+       __u8   natmode_to_ulp_type;
+       __be16 newlport;
+       __be16 newfport;
+       __u8   newlip[16];
+       __u8   newfip[16];
+       __be32 natseqcheck;
+       __be32 r9;
+       __be64 r10;
+       __be64 r11;
+       __be64 r12;
+       __be64 r13;
 };
 
 #define S_FW_FILTER_WR_TID     12
@@ -222,6 +248,9 @@ struct fw_filter_wr {
 #define S_FW_FILTER_WR_DMAC    19
 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
 
+#define S_FW_FILTER_WR_SMAC     18
+#define V_FW_FILTER_WR_SMAC(x)  ((x) << S_FW_FILTER_WR_SMAC)
+
 #define S_FW_FILTER_WR_INSVLAN         17
 #define V_FW_FILTER_WR_INSVLAN(x)      ((x) << S_FW_FILTER_WR_INSVLAN)
 
@@ -288,6 +317,15 @@ struct fw_filter_wr {
 #define S_FW_FILTER_WR_MATCHTYPEM      0
 #define V_FW_FILTER_WR_MATCHTYPEM(x)   ((x) << S_FW_FILTER_WR_MATCHTYPEM)
 
+#define S_FW_FILTER2_WR_SWAPMAC                0
+#define V_FW_FILTER2_WR_SWAPMAC(x)     ((x) << S_FW_FILTER2_WR_SWAPMAC)
+
+#define S_FW_FILTER2_WR_NATMODE                5
+#define V_FW_FILTER2_WR_NATMODE(x)     ((x) << S_FW_FILTER2_WR_NATMODE)
+
+#define S_FW_FILTER2_WR_ULP_TYPE       0
+#define V_FW_FILTER2_WR_ULP_TYPE(x)    ((x) << S_FW_FILTER2_WR_ULP_TYPE)
+
 /******************************************************************************
  *  C O M M A N D s
  *********************/
@@ -643,6 +681,8 @@ enum fw_params_param_dev {
        FW_PARAMS_PARAM_DEV_FWREV       = 0x0B, /* fw version */
        FW_PARAMS_PARAM_DEV_TPREV       = 0x0C, /* tp version */
        FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
+       FW_PARAMS_PARAM_DEV_FILTER2_WR  = 0x1D,
+       FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,
 };
 
 /*
@@ -653,8 +693,13 @@ enum fw_params_param_pfvf {
        FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
        FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
        FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
+       FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
+       FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
        FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
-       FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A
+       FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
+       FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D,
+       FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E,
+       FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F,
 };
 
 /*
@@ -732,6 +777,12 @@ struct fw_pfvf_cmd {
        __be32 r4;
 };
 
+#define S_FW_PFVF_CMD_PFN              8
+#define V_FW_PFVF_CMD_PFN(x)           ((x) << S_FW_PFVF_CMD_PFN)
+
+#define S_FW_PFVF_CMD_VFN              0
+#define V_FW_PFVF_CMD_VFN(x)           ((x) << S_FW_PFVF_CMD_VFN)
+
 #define S_FW_PFVF_CMD_NIQFLINT          20
 #define M_FW_PFVF_CMD_NIQFLINT          0xfff
 #define G_FW_PFVF_CMD_NIQFLINT(x)       \
@@ -791,6 +842,11 @@ enum fw_iq_type {
        FW_IQ_TYPE_FL_INT_CAP,
 };
 
+enum fw_iq_iqtype {
+       FW_IQ_IQTYPE_NIC = 1,
+       FW_IQ_IQTYPE_OFLD,
+};
+
 struct fw_iq_cmd {
        __be32 op_to_vfn;
        __be32 alloc_to_len16;
@@ -924,6 +980,9 @@ struct fw_iq_cmd {
        (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
 #define F_FW_IQ_CMD_IQFLINTCONGEN      V_FW_IQ_CMD_IQFLINTCONGEN(1U)
 
+#define S_FW_IQ_CMD_IQTYPE     24
+#define V_FW_IQ_CMD_IQTYPE(x)  ((x) << S_FW_IQ_CMD_IQTYPE)
+
 #define S_FW_IQ_CMD_FL0CNGCHMAP                20
 #define M_FW_IQ_CMD_FL0CNGCHMAP                0xf
 #define V_FW_IQ_CMD_FL0CNGCHMAP(x)     ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
@@ -1182,6 +1241,18 @@ enum fw_vi_func {
        FW_VI_FUNC_ETH,
 };
 
+/* Macros for VIID parsing:
+ * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
+ */
+
+#define S_FW_VIID_VIVLD         7
+#define M_FW_VIID_VIVLD         0x1
+#define G_FW_VIID_VIVLD(x)      (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD)
+
+#define S_FW_VIID_VIN           0
+#define M_FW_VIID_VIN           0x7F
+#define G_FW_VIID_VIN(x)        (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
+
 struct fw_vi_cmd {
        __be32 op_to_vfn;
        __be32 alloc_to_len16;
@@ -1223,6 +1294,16 @@ struct fw_vi_cmd {
 #define G_FW_VI_CMD_FREE(x)    (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
 #define F_FW_VI_CMD_FREE       V_FW_VI_CMD_FREE(1U)
 
+#define S_FW_VI_CMD_VFVLD       24
+#define M_FW_VI_CMD_VFVLD       0x1
+#define G_FW_VI_CMD_VFVLD(x)    \
+       (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD)
+
+#define S_FW_VI_CMD_VIN         16
+#define M_FW_VI_CMD_VIN         0xff
+#define G_FW_VI_CMD_VIN(x)      \
+       (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN)
+
 #define S_FW_VI_CMD_TYPE       15
 #define M_FW_VI_CMD_TYPE       0x1
 #define V_FW_VI_CMD_TYPE(x)    ((x) << S_FW_VI_CMD_TYPE)
@@ -1254,10 +1335,15 @@ struct fw_vi_cmd {
 /* Special VI_MAC command index ids */
 #define FW_VI_MAC_ADD_MAC              0x3FF
 #define FW_VI_MAC_ADD_PERSIST_MAC      0x3FE
+#define FW_VI_MAC_ID_BASED_FREE         0x3FC
 
 enum fw_vi_mac_smac {
-       FW_VI_MAC_MPS_TCAM_ENTRY,
-       FW_VI_MAC_SMT_AND_MPSTCAM
+       FW_VI_MAC_MPS_TCAM_ENTRY = 0x0,
+       FW_VI_MAC_SMT_AND_MPSTCAM = 0x3
+};
+
+enum fw_vi_mac_entry_types {
+       FW_VI_MAC_TYPE_RAW = 0x2,
 };
 
 struct fw_vi_mac_cmd {
@@ -1271,6 +1357,13 @@ struct fw_vi_mac_cmd {
                struct fw_vi_mac_hash {
                        __be64 hashvec;
                } hash;
+               struct fw_vi_mac_raw {
+                       __be32 raw_idx_pkd;
+                       __be32 data0_pkd;
+                       __be32 data1[2];
+                       __be64 data0m_pkd;
+                       __be32 data1m[2];
+               } raw;
        } u;
 };
 
@@ -1280,6 +1373,12 @@ struct fw_vi_mac_cmd {
 #define G_FW_VI_MAC_CMD_VIID(x)        \
        (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
 
+#define S_FW_VI_MAC_CMD_FREEMACS       31
+#define V_FW_VI_MAC_CMD_FREEMACS(x)    ((x) << S_FW_VI_MAC_CMD_FREEMACS)
+
+#define S_FW_VI_MAC_CMD_ENTRY_TYPE      23
+#define V_FW_VI_MAC_CMD_ENTRY_TYPE(x)   ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
+
 #define S_FW_VI_MAC_CMD_VALID          15
 #define M_FW_VI_MAC_CMD_VALID          0x1
 #define V_FW_VI_MAC_CMD_VALID(x)       ((x) << S_FW_VI_MAC_CMD_VALID)
@@ -1299,6 +1398,12 @@ struct fw_vi_mac_cmd {
 #define G_FW_VI_MAC_CMD_IDX(x) \
        (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
 
+#define S_FW_VI_MAC_CMD_RAW_IDX         16
+#define M_FW_VI_MAC_CMD_RAW_IDX         0xffff
+#define V_FW_VI_MAC_CMD_RAW_IDX(x)      ((x) << S_FW_VI_MAC_CMD_RAW_IDX)
+#define G_FW_VI_MAC_CMD_RAW_IDX(x)      \
+       (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)
+
 struct fw_vi_rxmode_cmd {
        __be32 op_to_viid;
        __be32 retval_len16;