net/cxgbe: support flow API for matching all packets on VF

[dpdk.git] / drivers / net / cxgbe / cxgbe_filter.c

diff --git a/drivers/net/cxgbe/cxgbe_filter.c b/drivers/net/cxgbe/cxgbe_filter.c
index b9d9d5d..9c10520 100644 (file)
--- a/drivers/net/cxgbe/cxgbe_filter.c
+++ b/drivers/net/cxgbe/cxgbe_filter.c
@@ -56,13 +56,15 @@ int cxgbe_init_hash_filter(struct adapter *adap)
 int cxgbe_validate_filter(struct adapter *adapter,
                          struct ch_filter_specification *fs)
 {
-       u32 fconf;
+       u32 fconf, iconf;
 
        /*
         * Check for unconfigured fields being used.
         */
        fconf = adapter->params.tp.vlan_pri_map;
 
+       iconf = adapter->params.tp.ingress_config;
+
 #define S(_field) \
        (fs->val._field || fs->mask._field)
 #define U(_mask, _field) \
@@ -70,7 +72,18 @@ int cxgbe_validate_filter(struct adapter *adapter,
 
        if (U(F_PORT, iport) || U(F_ETHERTYPE, ethtype) ||
            U(F_PROTOCOL, proto) || U(F_MACMATCH, macidx) ||
-           U(F_VLAN, ivlan_vld))
+           U(F_VLAN, ivlan_vld) || U(F_VNIC_ID, ovlan_vld) ||
+           U(F_TOS, tos) || U(F_VNIC_ID, pfvf_vld))
+               return -EOPNOTSUPP;
+
+       /* Either OVLAN or PFVF match is enabled in hardware, but not both */
+       if ((S(pfvf_vld) && !(iconf & F_VNIC)) ||
+           (S(ovlan_vld) && (iconf & F_VNIC)))
+               return -EOPNOTSUPP;
+
+       /* To use OVLAN or PFVF, L4 encapsulation match must not be enabled */
+       if ((S(ovlan_vld) && (iconf & F_USE_ENC_IDX)) ||
+           (S(pfvf_vld) && (iconf & F_USE_ENC_IDX)))
                return -EOPNOTSUPP;
 
 #undef S
@@ -296,6 +309,19 @@ static u64 hash_filter_ntuple(const struct filter_entry *f)
        if (tp->vlan_shift >= 0 && f->fs.mask.ivlan)
                ntuple |= (u64)(F_FT_VLAN_VLD | f->fs.val.ivlan) <<
                          tp->vlan_shift;
+       if (tp->vnic_shift >= 0) {
+               if ((adap->params.tp.ingress_config & F_VNIC) &&
+                   f->fs.mask.pfvf_vld)
+                       ntuple |= (u64)(f->fs.val.pfvf_vld << 16 |
+                                       f->fs.val.pf << 13 | f->fs.val.vf) <<
+                                       tp->vnic_shift;
+               else if (!(adap->params.tp.ingress_config & F_VNIC) &&
+                        f->fs.mask.ovlan_vld)
+                       ntuple |= (u64)(f->fs.val.ovlan_vld << 16 |
+                                       f->fs.val.ovlan) << tp->vnic_shift;
+       }
+       if (tp->tos_shift >= 0 && f->fs.mask.tos)
+               ntuple |= (u64)f->fs.val.tos << tp->tos_shift;
 
        return ntuple;
 }
@@ -775,7 +801,9 @@ static int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
        fwr->ethtypem = cpu_to_be16(f->fs.mask.ethtype);
        fwr->frag_to_ovlan_vldm =
                (V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
-                V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld));
+                V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
+                V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
+                V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
        fwr->smac_sel = 0;
        fwr->rx_chan_rx_rpl_iq =
                cpu_to_be16(V_FW_FILTER_WR_RX_CHAN(0) |
@@ -788,8 +816,12 @@ static int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
                            V_FW_FILTER_WR_PORTM(f->fs.mask.iport));
        fwr->ptcl = f->fs.val.proto;
        fwr->ptclm = f->fs.mask.proto;
+       fwr->ttyp = f->fs.val.tos;
+       fwr->ttypm = f->fs.mask.tos;
        fwr->ivlan = cpu_to_be16(f->fs.val.ivlan);
        fwr->ivlanm = cpu_to_be16(f->fs.mask.ivlan);
+       fwr->ovlan = cpu_to_be16(f->fs.val.ovlan);
+       fwr->ovlanm = cpu_to_be16(f->fs.mask.ovlan);
        rte_memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
        rte_memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
        rte_memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
@@ -940,10 +972,11 @@ int cxgbe_set_filter(struct rte_eth_dev *dev, unsigned int filter_id,
 {
        struct port_info *pi = ethdev2pinfo(dev);
        struct adapter *adapter = pi->adapter;
-       unsigned int fidx, iq;
+       u8 nentries, bitoff[16] = {0};
        struct filter_entry *f;
        unsigned int chip_ver;
-       u8 nentries, bitoff[16] = {0};
+       unsigned int fidx, iq;
+       u32 iconf;
        int ret;
 
        if (is_hashfilter(adapter) && fs->cap)
@@ -1027,6 +1060,20 @@ int cxgbe_set_filter(struct rte_eth_dev *dev, unsigned int filter_id,
        f->fs.iq = iq;
        f->dev = dev;
 
+       iconf = adapter->params.tp.ingress_config;
+
+       /* Either PFVF or OVLAN can be active, but not both
+        * So, if PFVF is enabled, then overwrite the OVLAN
+        * fields with PFVF fields before writing the spec
+        * to hardware.
+        */
+       if (iconf & F_VNIC) {
+               f->fs.val.ovlan = fs->val.pf << 13 | fs->val.vf;
+               f->fs.mask.ovlan = fs->mask.pf << 13 | fs->mask.vf;
+               f->fs.val.ovlan_vld = fs->val.pfvf_vld;
+               f->fs.mask.ovlan_vld = fs->mask.pfvf_vld;
+       }
+
        /*
         * Attempt to set the filter.  If we don't succeed, we clear
         * it and return the failure.