#include "base/t4_regs.h"
#include "base/t4_msg.h"
#include "cxgbe.h"
+#include "cxgbe_pfvf.h"
#include "clip_tbl.h"
#include "l2t.h"
#include "mps_tcam.h"
return ret;
}
-static void cxgbe_get_devargs_int(struct adapter *adap, int *dst,
- const char *key, int default_value)
+static void cxgbe_get_devargs_int(struct adapter *adap, bool *dst,
+ const char *key, bool default_value)
{
struct rte_pci_device *pdev = adap->pdev;
- int ret, devarg_value = default_value;
+ int ret;
+ bool devarg_value = default_value;
*dst = default_value;
if (!pdev)
void cxgbe_process_devargs(struct adapter *adap)
{
cxgbe_get_devargs_int(adap, &adap->devargs.keep_ovlan,
- CXGBE_DEVARG_CMN_KEEP_OVLAN, 0);
+ CXGBE_DEVARG_CMN_KEEP_OVLAN, false);
cxgbe_get_devargs_int(adap, &adap->devargs.tx_mode_latency,
- CXGBE_DEVARG_CMN_TX_MODE_LATENCY, 0);
+ CXGBE_DEVARG_CMN_TX_MODE_LATENCY, false);
cxgbe_get_devargs_int(adap, &adap->devargs.force_link_up,
- CXGBE_DEVARG_VF_FORCE_LINK_UP, 0);
+ CXGBE_DEVARG_VF_FORCE_LINK_UP, false);
}
static void configure_vlan_types(struct adapter *adapter)
V_OVLAN_ETYPE(M_OVLAN_ETYPE),
V_OVLAN_MASK(M_OVLAN_MASK) |
V_OVLAN_ETYPE(0x9100));
- /* OVLAN Type 0x8100 */
- t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN2),
- V_OVLAN_MASK(M_OVLAN_MASK) |
- V_OVLAN_ETYPE(M_OVLAN_ETYPE),
- V_OVLAN_MASK(M_OVLAN_MASK) |
- V_OVLAN_ETYPE(0x8100));
/* IVLAN 0X8100 */
t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
F_OVLAN_EN0 | F_OVLAN_EN1 |
- F_OVLAN_EN2 | F_IVLAN_EN,
+ F_IVLAN_EN,
F_OVLAN_EN0 | F_OVLAN_EN1 |
- F_OVLAN_EN2 | F_IVLAN_EN);
+ F_IVLAN_EN);
}
t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, V_RM_OVLAN(1),
/*
* Grab some of our basic fundamental operating parameters.
*/
-#define FW_PARAM_DEV(param) \
- (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
- V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
-
-#define FW_PARAM_PFVF(param) \
- (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
- V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
- V_FW_PARAMS_PARAM_Y(0) | \
- V_FW_PARAMS_PARAM_Z(0))
-
- params[0] = FW_PARAM_PFVF(L2T_START);
- params[1] = FW_PARAM_PFVF(L2T_END);
- params[2] = FW_PARAM_PFVF(FILTER_START);
- params[3] = FW_PARAM_PFVF(FILTER_END);
+ params[0] = CXGBE_FW_PARAM_PFVF(L2T_START);
+ params[1] = CXGBE_FW_PARAM_PFVF(L2T_END);
+ params[2] = CXGBE_FW_PARAM_PFVF(FILTER_START);
+ params[3] = CXGBE_FW_PARAM_PFVF(FILTER_END);
ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val);
if (ret < 0)
goto bye;
adap->tids.ftid_base = val[2];
adap->tids.nftids = val[3] - val[2] + 1;
- params[0] = FW_PARAM_PFVF(CLIP_START);
- params[1] = FW_PARAM_PFVF(CLIP_END);
+ params[0] = CXGBE_FW_PARAM_PFVF(CLIP_START);
+ params[1] = CXGBE_FW_PARAM_PFVF(CLIP_END);
ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
if (ret < 0)
goto bye;
if (is_t4(adap->params.chip)) {
adap->params.filter2_wr_support = 0;
} else {
- params[0] = FW_PARAM_DEV(FILTER2_WR);
+ params[0] = CXGBE_FW_PARAM_DEV(FILTER2_WR);
ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1, params, val);
adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
}
+ /* Check if FW supports returning vin.
+ * If this is not supported, driver will interpret
+ * these values from viid.
+ */
+ params[0] = CXGBE_FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
+ ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
+ 1, params, val);
+ adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0);
+
/* query tid-related parameters */
- params[0] = FW_PARAM_DEV(NTID);
+ params[0] = CXGBE_FW_PARAM_DEV(NTID);
ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
params, val);
if (ret < 0)
* firmware won't understand this and we'll just get
* unencapsulated messages ...
*/
- params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
+ params[0] = CXGBE_FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
val[0] = 1;
(void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
if (is_t4(adap->params.chip)) {
adap->params.ulptx_memwrite_dsgl = false;
} else {
- params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
+ params[0] = CXGBE_FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1, params, val);
adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
}
+ /* Query for max number of packets that can be coalesced for Tx */
+ params[0] = CXGBE_FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR);
+ ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
+ if (!ret && val[0] > 0)
+ adap->params.max_tx_coalesce_num = val[0];
+ else
+ adap->params.max_tx_coalesce_num = ETH_COALESCE_PKT_NUM;
+
/*
* The MTU/MSS Table is initialized by now, so load their values. If
* we're initializing the adapter, then we'll make any modifications
"filter support disabled. Continuing\n");
}
+ t4_os_lock_init(&adapter->flow_lock);
+
adapter->mpstcam = t4_init_mpstcam(adapter);
if (!adapter->mpstcam)
dev_warn(adapter, "could not allocate mps tcam table."
git.droids-corp.org / dpdk.git / blobdiff