#include <rte_dev.h>
#include <rte_kvargs.h>
-#include "common.h"
-#include "t4_regs.h"
-#include "t4_msg.h"
+#include "base/common.h"
+#include "base/t4_regs.h"
+#include "base/t4_msg.h"
#include "cxgbe.h"
+#include "cxgbe_pfvf.h"
#include "clip_tbl.h"
#include "l2t.h"
#include "mps_tcam.h"
} else if (opcode == CPL_ABORT_RPL_RSS) {
const struct cpl_abort_rpl_rss *p = (const void *)rsp;
- hash_del_filter_rpl(q->adapter, p);
+ cxgbe_hash_del_filter_rpl(q->adapter, p);
} else if (opcode == CPL_SET_TCB_RPL) {
const struct cpl_set_tcb_rpl *p = (const void *)rsp;
- filter_rpl(q->adapter, p);
+ cxgbe_filter_rpl(q->adapter, p);
} else if (opcode == CPL_ACT_OPEN_RPL) {
const struct cpl_act_open_rpl *p = (const void *)rsp;
- hash_filter_rpl(q->adapter, p);
+ cxgbe_hash_filter_rpl(q->adapter, p);
} else if (opcode == CPL_L2T_WRITE_RPL) {
const struct cpl_l2t_write_rpl *p = (const void *)rsp;
- do_l2t_write_rpl(q->adapter, p);
+ cxgbe_do_l2t_write_rpl(q->adapter, p);
} else {
dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
opcode);
/**
* Setup sge control queues to pass control information.
*/
-int setup_sge_ctrl_txq(struct adapter *adapter)
+int cxgbe_setup_sge_ctrl_txq(struct adapter *adapter)
{
struct sge *s = &adapter->sge;
int err = 0, i = 0;
for_each_port(adapter, i) {
+ struct port_info *pi = adap2pinfo(adapter, i);
char name[RTE_ETH_NAME_MAX_LEN];
struct sge_ctrl_txq *q = &s->ctrlq[i];
err);
goto out;
}
- snprintf(name, sizeof(name), "cxgbe_ctrl_pool_%d", i);
+ snprintf(name, sizeof(name), "%s_ctrl_pool_%d",
+ pi->eth_dev->device->driver->name,
+ pi->eth_dev->data->port_id);
q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size,
RTE_CACHE_LINE_SIZE,
RTE_MBUF_PRIV_ALIGN,
RTE_MBUF_DEFAULT_BUF_SIZE,
SOCKET_ID_ANY);
if (!q->mb_pool) {
- dev_err(adapter, "Can't create ctrl pool for port: %d",
- i);
- err = -ENOMEM;
+ err = -rte_errno;
+ dev_err(adapter,
+ "Can't create ctrl pool for port %d. Err: %d\n",
+ pi->eth_dev->data->port_id, err);
goto out;
}
}
/**
* cxgbe_poll_for_completion: Poll rxq for completion
* @q: rxq to poll
- * @us: microseconds to delay
+ * @ms: milliseconds to delay
* @cnt: number of times to poll
* @c: completion to check for 'done' status
*
* Polls the rxq for reples until completion is done or the count
* expires.
*/
-int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int us,
+int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int ms,
unsigned int cnt, struct t4_completion *c)
{
unsigned int i;
- unsigned int work_done, budget = 4;
+ unsigned int work_done, budget = 32;
if (!c)
return -EINVAL;
return 0;
}
t4_os_unlock(&c->lock);
- udelay(us);
+ rte_delay_ms(ms);
}
return -ETIMEDOUT;
}
-int setup_sge_fwevtq(struct adapter *adapter)
+int cxgbe_setup_sge_fwevtq(struct adapter *adapter)
{
struct sge *s = &adapter->sge;
int err = 0;
return -ENOMEM;
t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
- t->ftid_tab = (struct filter_entry *)&t->tid_tab[t->natids];
+ t->ftid_tab = (struct filter_entry *)&t->atid_tab[t->natids];
t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size);
if (!t->ftid_bmap_array) {
tid_free(t);
return high_speeds != 0;
}
-inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
+static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
unsigned int us, unsigned int cnt,
unsigned int size, unsigned int iqe_size)
{
q->size = size;
}
-int cfg_queue_count(struct rte_eth_dev *eth_dev)
+int cxgbe_cfg_queue_count(struct rte_eth_dev *eth_dev)
{
- struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
+ struct port_info *pi = eth_dev->data->dev_private;
struct adapter *adap = pi->adapter;
struct sge *s = &adap->sge;
unsigned int max_queues = s->max_ethqsets / adap->params.nports;
return 0;
}
-void cfg_queues(struct rte_eth_dev *eth_dev)
+void cxgbe_cfg_queues(struct rte_eth_dev *eth_dev)
{
- struct rte_config *config = rte_eal_get_configuration();
- struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
+ struct port_info *pi = eth_dev->data->dev_private;
struct adapter *adap = pi->adapter;
struct sge *s = &adap->sge;
unsigned int i, nb_ports = 0, qidx = 0;
(adap->params.nports - nb_ports)) /
nb_ports;
- if (q_per_port > config->lcore_count)
- q_per_port = config->lcore_count;
+ if (q_per_port > rte_lcore_count())
+ q_per_port = rte_lcore_count();
for_each_port(adap, i) {
struct port_info *pi = adap2pinfo(adap, i);
MEMWIN_NIC));
}
-int init_rss(struct adapter *adap)
+int cxgbe_init_rss(struct adapter *adap)
{
unsigned int i;
/**
* Dump basic information about the adapter.
*/
-void print_adapter_info(struct adapter *adap)
+void cxgbe_print_adapter_info(struct adapter *adap)
{
/**
* Hardware/Firmware/etc. Version/Revision IDs.
t4_dump_version_info(adap);
}
-void print_port_info(struct adapter *adap)
+void cxgbe_print_port_info(struct adapter *adap)
{
int i;
char buf[80];
}
}
-static int
-check_devargs_handler(__rte_unused const char *key, const char *value,
- __rte_unused void *opaque)
+static int check_devargs_handler(const char *key, const char *value, void *p)
{
- if (strcmp(value, "1"))
- return -1;
+ if (!strncmp(key, CXGBE_DEVARG_CMN_KEEP_OVLAN, strlen(key)) ||
+ !strncmp(key, CXGBE_DEVARG_CMN_TX_MODE_LATENCY, strlen(key)) ||
+ !strncmp(key, CXGBE_DEVARG_VF_FORCE_LINK_UP, strlen(key))) {
+ if (!strncmp(value, "1", 1)) {
+ bool *dst_val = (bool *)p;
+
+ *dst_val = true;
+ }
+ }
return 0;
}
-int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key)
+static int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key,
+ void *p)
{
struct rte_kvargs *kvlist;
+ int ret = 0;
if (!devargs)
return 0;
if (!kvlist)
return 0;
- if (!rte_kvargs_count(kvlist, key)) {
- rte_kvargs_free(kvlist);
- return 0;
- }
+ if (!rte_kvargs_count(kvlist, key))
+ goto out;
- if (rte_kvargs_process(kvlist, key,
- check_devargs_handler, NULL) < 0) {
- rte_kvargs_free(kvlist);
- return 0;
- }
+ ret = rte_kvargs_process(kvlist, key, check_devargs_handler, p);
+
+out:
rte_kvargs_free(kvlist);
- return 1;
+ return ret;
+}
+
+static void cxgbe_get_devargs_int(struct adapter *adap, bool *dst,
+ const char *key, bool default_value)
+{
+ struct rte_pci_device *pdev = adap->pdev;
+ int ret;
+ bool devarg_value = default_value;
+
+ *dst = default_value;
+ if (!pdev)
+ return;
+
+ ret = cxgbe_get_devargs(pdev->device.devargs, key, &devarg_value);
+ if (ret)
+ return;
+
+ *dst = devarg_value;
+}
+
+void cxgbe_process_devargs(struct adapter *adap)
+{
+ cxgbe_get_devargs_int(adap, &adap->devargs.keep_ovlan,
+ CXGBE_DEVARG_CMN_KEEP_OVLAN, false);
+ cxgbe_get_devargs_int(adap, &adap->devargs.tx_mode_latency,
+ CXGBE_DEVARG_CMN_TX_MODE_LATENCY, false);
+ cxgbe_get_devargs_int(adap, &adap->devargs.force_link_up,
+ CXGBE_DEVARG_VF_FORCE_LINK_UP, false);
}
static void configure_vlan_types(struct adapter *adapter)
{
- struct rte_pci_device *pdev = adapter->pdev;
int i;
for_each_port(adapter, i) {
V_OVLAN_ETYPE(M_OVLAN_ETYPE),
V_OVLAN_MASK(M_OVLAN_MASK) |
V_OVLAN_ETYPE(0x9100));
- /* OVLAN Type 0x8100 */
- t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN2),
- V_OVLAN_MASK(M_OVLAN_MASK) |
- V_OVLAN_ETYPE(M_OVLAN_ETYPE),
- V_OVLAN_MASK(M_OVLAN_MASK) |
- V_OVLAN_ETYPE(0x8100));
/* IVLAN 0X8100 */
t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
F_OVLAN_EN0 | F_OVLAN_EN1 |
- F_OVLAN_EN2 | F_IVLAN_EN,
+ F_IVLAN_EN,
F_OVLAN_EN0 | F_OVLAN_EN1 |
- F_OVLAN_EN2 | F_IVLAN_EN);
+ F_IVLAN_EN);
}
- if (cxgbe_get_devargs(pdev->device.devargs, CXGBE_DEVARG_KEEP_OVLAN))
- t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
- V_RM_OVLAN(1), V_RM_OVLAN(0));
+ t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, V_RM_OVLAN(1),
+ V_RM_OVLAN(!adapter->devargs.keep_ovlan));
}
static void configure_pcie_ext_tag(struct adapter *adapter)
}
/* Figure out how many Queue Sets we can support */
-void configure_max_ethqsets(struct adapter *adapter)
+void cxgbe_configure_max_ethqsets(struct adapter *adapter)
{
unsigned int ethqsets;
/*
* Grab some of our basic fundamental operating parameters.
*/
-#define FW_PARAM_DEV(param) \
- (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
- V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
-
-#define FW_PARAM_PFVF(param) \
- (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
- V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
- V_FW_PARAMS_PARAM_Y(0) | \
- V_FW_PARAMS_PARAM_Z(0))
-
- params[0] = FW_PARAM_PFVF(L2T_START);
- params[1] = FW_PARAM_PFVF(L2T_END);
- params[2] = FW_PARAM_PFVF(FILTER_START);
- params[3] = FW_PARAM_PFVF(FILTER_END);
+ params[0] = CXGBE_FW_PARAM_PFVF(L2T_START);
+ params[1] = CXGBE_FW_PARAM_PFVF(L2T_END);
+ params[2] = CXGBE_FW_PARAM_PFVF(FILTER_START);
+ params[3] = CXGBE_FW_PARAM_PFVF(FILTER_END);
ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val);
if (ret < 0)
goto bye;
adap->tids.ftid_base = val[2];
adap->tids.nftids = val[3] - val[2] + 1;
- params[0] = FW_PARAM_PFVF(CLIP_START);
- params[1] = FW_PARAM_PFVF(CLIP_END);
+ params[0] = CXGBE_FW_PARAM_PFVF(CLIP_START);
+ params[1] = CXGBE_FW_PARAM_PFVF(CLIP_END);
ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
if (ret < 0)
goto bye;
if ((caps_cmd.niccaps & cpu_to_be16(FW_CAPS_CONFIG_NIC_HASHFILTER)) &&
is_t6(adap->params.chip)) {
- if (init_hash_filter(adap) < 0)
+ if (cxgbe_init_hash_filter(adap) < 0)
goto bye;
}
if (is_t4(adap->params.chip)) {
adap->params.filter2_wr_support = 0;
} else {
- params[0] = FW_PARAM_DEV(FILTER2_WR);
+ params[0] = CXGBE_FW_PARAM_DEV(FILTER2_WR);
ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1, params, val);
adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
}
+ /* Check if FW supports returning vin.
+ * If this is not supported, driver will interpret
+ * these values from viid.
+ */
+ params[0] = CXGBE_FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
+ ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
+ 1, params, val);
+ adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0);
+
/* query tid-related parameters */
- params[0] = FW_PARAM_DEV(NTID);
+ params[0] = CXGBE_FW_PARAM_DEV(NTID);
ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
params, val);
if (ret < 0)
* firmware won't understand this and we'll just get
* unencapsulated messages ...
*/
- params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
+ params[0] = CXGBE_FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
val[0] = 1;
(void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
if (is_t4(adap->params.chip)) {
adap->params.ulptx_memwrite_dsgl = false;
} else {
- params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
+ params[0] = CXGBE_FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1, params, val);
adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
}
+ /* Query for max number of packets that can be coalesced for Tx */
+ params[0] = CXGBE_FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR);
+ ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
+ if (!ret && val[0] > 0)
+ adap->params.max_tx_coalesce_num = val[0];
+ else
+ adap->params.max_tx_coalesce_num = ETH_COALESCE_PKT_NUM;
+
/*
* The MTU/MSS Table is initialized by now, so load their values. If
* we're initializing the adapter, then we'll make any modifications
t4_init_tp_params(adap);
configure_pcie_ext_tag(adap);
configure_vlan_types(adap);
- configure_max_ethqsets(adap);
+ cxgbe_configure_max_ethqsets(adap);
adap->params.drv_memwin = MEMWIN_NIC;
adap->flags |= FW_OK;
pi->port_id, pi->mod_type);
}
-inline bool force_linkup(struct adapter *adap)
+bool cxgbe_force_linkup(struct adapter *adap)
{
- struct rte_pci_device *pdev = adap->pdev;
-
if (is_pf4(adap))
- return false; /* force_linkup not required for pf driver*/
- if (!cxgbe_get_devargs(pdev->device.devargs,
- CXGBE_DEVARG_FORCE_LINK_UP))
- return false;
- return true;
+ return false; /* force_linkup not required for pf driver */
+
+ return adap->devargs.force_link_up;
}
/**
*
* Performs the MAC and PHY actions needed to enable a port.
*/
-int link_start(struct port_info *pi)
+int cxgbe_link_start(struct port_info *pi)
{
struct adapter *adapter = pi->adapter;
u64 conf_offloads;
int ret;
mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
- (ETHER_HDR_LEN + ETHER_CRC_LEN);
+ (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN);
conf_offloads = pi->eth_dev->data->dev_conf.rxmode.offloads;
true, true, false);
}
- if (ret == 0 && force_linkup(adapter))
+ if (ret == 0 && cxgbe_force_linkup(adapter))
pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP;
return ret;
}
* We always configure the RSS mapping for all ports since the mapping
* table has plenty of entries.
*/
-int setup_rss(struct port_info *pi)
+int cxgbe_setup_rss(struct port_info *pi)
{
int j, err;
struct adapter *adapter = pi->adapter;
goto out_free;
allocate_mac:
- pi = (struct port_info *)eth_dev->data->dev_private;
+ pi = eth_dev->data->dev_private;
adapter->port[i] = pi;
pi->eth_dev = eth_dev;
pi->adapter = adapter;
rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
- ETHER_ADDR_LEN, 0);
+ RTE_ETHER_ADDR_LEN, 0);
if (!pi->eth_dev->data->mac_addrs) {
dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
__func__);
}
}
- cfg_queues(adapter->eth_dev);
+ cxgbe_cfg_queues(adapter->eth_dev);
- print_adapter_info(adapter);
- print_port_info(adapter);
+ cxgbe_print_adapter_info(adapter);
+ cxgbe_print_port_info(adapter);
adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
adapter->clipt_end);
"filter support disabled. Continuing\n");
}
+ t4_os_lock_init(&adapter->flow_lock);
+
adapter->mpstcam = t4_init_mpstcam(adapter);
if (!adapter->mpstcam)
dev_warn(adapter, "could not allocate mps tcam table."
"Maskless filter support disabled. Continuing\n");
}
- err = init_rss(adapter);
+ err = cxgbe_init_rss(adapter);
if (err)
goto out_free;
git.droids-corp.org / dpdk.git / blobdiff