#include "dpaa2_ethdev.h"
#include <fsl_qbman_debug.h>
-#define DRIVER_LOOPBACK_MODE "drv_looback"
+#define DRIVER_LOOPBACK_MODE "drv_loopback"
+#define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
/* Supported Rx offloads */
static uint64_t dev_rx_offloads_sup =
- DEV_RX_OFFLOAD_VLAN_STRIP |
- DEV_RX_OFFLOAD_IPV4_CKSUM |
- DEV_RX_OFFLOAD_UDP_CKSUM |
- DEV_RX_OFFLOAD_TCP_CKSUM |
+ DEV_RX_OFFLOAD_CHECKSUM |
+ DEV_RX_OFFLOAD_SCTP_CKSUM |
DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
+ DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
+ DEV_RX_OFFLOAD_VLAN_STRIP |
DEV_RX_OFFLOAD_VLAN_FILTER |
- DEV_RX_OFFLOAD_JUMBO_FRAME;
+ DEV_RX_OFFLOAD_JUMBO_FRAME |
+ DEV_RX_OFFLOAD_TIMESTAMP;
/* Rx offloads which cannot be disabled */
static uint64_t dev_rx_offloads_nodis =
DEV_TX_OFFLOAD_UDP_CKSUM |
DEV_TX_OFFLOAD_TCP_CKSUM |
DEV_TX_OFFLOAD_SCTP_CKSUM |
- DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
+ DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
+ DEV_TX_OFFLOAD_MT_LOCKFREE |
+ DEV_TX_OFFLOAD_MBUF_FAST_FREE;
/* Tx offloads which cannot be disabled */
static uint64_t dev_tx_offloads_nodis =
- DEV_TX_OFFLOAD_MULTI_SEGS |
- DEV_TX_OFFLOAD_MT_LOCKFREE |
- DEV_TX_OFFLOAD_MBUF_FAST_FREE;
+ DEV_TX_OFFLOAD_MULTI_SEGS;
/* enable timestamp in mbuf */
enum pmd_dpaa2_ts dpaa2_enable_ts;
{"ingress_nobuffer_discards", 2, 2},
{"egress_discarded_frames", 2, 3},
{"egress_confirmed_frames", 2, 4},
+ {"cgr_reject_frames", 4, 0},
+ {"cgr_reject_bytes", 4, 1},
};
static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
int dpaa2_logtype_pmd;
-__rte_experimental void
+void
rte_pmd_dpaa2_set_timestamp(enum pmd_dpaa2_ts enable)
{
dpaa2_enable_ts = enable;
return 0;
}
-static void
+static int
dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
{
struct dpaa2_dev_priv *priv = dev->data->dev_private;
dev_info->max_vfs = 0;
dev_info->max_vmdq_pools = ETH_16_POOLS;
dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
+
+ return 0;
}
static int
PMD_INIT_FUNC_TRACE();
num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
- tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
+ if (priv->tx_conf_en)
+ tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
+ else
+ tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
RTE_CACHE_LINE_SIZE);
if (!mc_q) {
goto fail_tx;
}
+ if (priv->tx_conf_en) {
+ /*Setup tx confirmation queues*/
+ for (i = 0; i < priv->nb_tx_queues; i++) {
+ mc_q->eth_data = dev->data;
+ mc_q->tc_index = i;
+ mc_q->flow_id = 0;
+ priv->tx_conf_vq[i] = mc_q++;
+ dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
+ dpaa2_q->q_storage =
+ rte_malloc("dq_storage",
+ sizeof(struct queue_storage_info_t),
+ RTE_CACHE_LINE_SIZE);
+ if (!dpaa2_q->q_storage)
+ goto fail_tx_conf;
+
+ memset(dpaa2_q->q_storage, 0,
+ sizeof(struct queue_storage_info_t));
+ if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
+ goto fail_tx_conf;
+ }
+ }
+
vq_id = 0;
for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
}
return 0;
+fail_tx_conf:
+ i -= 1;
+ while (i >= 0) {
+ dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
+ rte_free(dpaa2_q->q_storage);
+ priv->tx_conf_vq[i--] = NULL;
+ }
+ i = priv->nb_tx_queues;
fail_tx:
i -= 1;
while (i >= 0) {
dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
rte_free(dpaa2_q->cscn);
}
+ if (priv->tx_conf_en) {
+ /* cleanup tx conf queue storage */
+ for (i = 0; i < priv->nb_tx_queues; i++) {
+ dpaa2_q = (struct dpaa2_queue *)
+ priv->tx_conf_vq[i];
+ rte_free(dpaa2_q->q_storage);
+ }
+ }
/*free memory for all queues (RX+TX) */
rte_free(priv->rx_vq[0]);
priv->rx_vq[0] = NULL;
PMD_INIT_FUNC_TRACE();
- /* Rx offloads validation */
+ /* Rx offloads which are enabled by default */
if (dev_rx_offloads_nodis & ~rx_offloads) {
- DPAA2_PMD_WARN(
- "Rx offloads non configurable - requested 0x%" PRIx64
- " ignored 0x%" PRIx64,
- rx_offloads, dev_rx_offloads_nodis);
+ DPAA2_PMD_INFO(
+ "Some of rx offloads enabled by default - requested 0x%" PRIx64
+ " fixed are 0x%" PRIx64,
+ rx_offloads, dev_rx_offloads_nodis);
}
- /* Tx offloads validation */
+ /* Tx offloads which are enabled by default */
if (dev_tx_offloads_nodis & ~tx_offloads) {
- DPAA2_PMD_WARN(
- "Tx offloads non configurable - requested 0x%" PRIx64
- " ignored 0x%" PRIx64,
- tx_offloads, dev_tx_offloads_nodis);
+ DPAA2_PMD_INFO(
+ "Some of tx offloads enabled by default - requested 0x%" PRIx64
+ " fixed are 0x%" PRIx64,
+ tx_offloads, dev_tx_offloads_nodis);
}
if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
- priv->token, eth_conf->rxmode.max_rx_pkt_len);
+ priv->token, eth_conf->rxmode.max_rx_pkt_len
+ - RTE_ETHER_CRC_LEN);
if (ret) {
DPAA2_PMD_ERR(
"Unable to set mtu. check config");
return ret;
}
+ dev->data->mtu =
+ dev->data->dev_conf.rxmode.max_rx_pkt_len -
+ RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
+ VLAN_TAG_SIZE;
} else {
return -1;
}
rx_l3_csum_offload = true;
if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
- (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM))
+ (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
+ (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
rx_l4_csum_offload = true;
ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
return ret;
}
+ if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
+ dpaa2_enable_ts = true;
+
if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
tx_l3_csum_offload = true;
static int
dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
uint16_t rx_queue_id,
- uint16_t nb_rx_desc __rte_unused,
+ uint16_t nb_rx_desc,
unsigned int socket_id __rte_unused,
const struct rte_eth_rxconf *rx_conf __rte_unused,
struct rte_mempool *mb_pool)
uint8_t options = 0;
uint8_t flow_id;
uint32_t bpid;
- int ret;
+ int i, ret;
PMD_INIT_FUNC_TRACE();
dpaa2_q->bp_array = rte_dpaa2_bpid_info;
/*Get the flow id from given VQ id*/
- flow_id = rx_queue_id % priv->nb_rx_queues;
+ flow_id = dpaa2_q->flow_id;
memset(&cfg, 0, sizeof(struct dpni_queue));
options = options | DPNI_QUEUE_OPT_USER_CTX;
cfg.user_context = (size_t)(dpaa2_q);
+ /* check if a private cgr available. */
+ for (i = 0; i < priv->max_cgs; i++) {
+ if (!priv->cgid_in_use[i]) {
+ priv->cgid_in_use[i] = 1;
+ break;
+ }
+ }
+
+ if (i < priv->max_cgs) {
+ options |= DPNI_QUEUE_OPT_SET_CGID;
+ cfg.cgid = i;
+ dpaa2_q->cgid = cfg.cgid;
+ } else {
+ dpaa2_q->cgid = 0xff;
+ }
+
/*if ls2088 or rev2 device, enable the stashing */
if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
struct dpni_taildrop taildrop;
taildrop.enable = 1;
- /*enabling per rx queue congestion control */
- taildrop.threshold = CONG_THRESHOLD_RX_Q;
- taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
- taildrop.oal = CONG_RX_OAL;
- DPAA2_PMD_DEBUG("Enabling Early Drop on queue = %d",
- rx_queue_id);
- ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
+
+ /* Private CGR will use tail drop length as nb_rx_desc.
+ * for rest cases we can use standard byte based tail drop.
+ * There is no HW restriction, but number of CGRs are limited,
+ * hence this restriction is placed.
+ */
+ if (dpaa2_q->cgid != 0xff) {
+ /*enabling per rx queue congestion control */
+ taildrop.threshold = nb_rx_desc;
+ taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
+ taildrop.oal = 0;
+ DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
+ rx_queue_id);
+ ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_CP_CONGESTION_GROUP,
+ DPNI_QUEUE_RX,
+ dpaa2_q->tc_index,
+ flow_id, &taildrop);
+ } else {
+ /*enabling per rx queue congestion control */
+ taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
+ taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
+ taildrop.oal = CONG_RX_OAL;
+ DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
+ rx_queue_id);
+ ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_CP_QUEUE, DPNI_QUEUE_RX,
+ dpaa2_q->tc_index, flow_id,
+ &taildrop);
+ }
+ if (ret) {
+ DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
+ ret);
+ return -1;
+ }
+ } else { /* Disable tail Drop */
+ struct dpni_taildrop taildrop = {0};
+ DPAA2_PMD_INFO("Tail drop is disabled on queue");
+
+ taildrop.enable = 0;
+ if (dpaa2_q->cgid != 0xff) {
+ ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
+ dpaa2_q->tc_index,
+ flow_id, &taildrop);
+ } else {
+ ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
DPNI_CP_QUEUE, DPNI_QUEUE_RX,
dpaa2_q->tc_index, flow_id, &taildrop);
+ }
if (ret) {
DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
ret);
struct dpaa2_dev_priv *priv = dev->data->dev_private;
struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
priv->tx_vq[tx_queue_id];
+ struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
+ priv->tx_conf_vq[tx_queue_id];
struct fsl_mc_io *dpni = priv->hw;
struct dpni_queue tx_conf_cfg;
struct dpni_queue tx_flow_cfg;
uint8_t options = 0, flow_id;
+ struct dpni_queue_id qid;
uint32_t tc_id;
int ret;
if (tx_queue_id == 0) {
/*Set tx-conf and error configuration*/
- ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
- priv->token,
- DPNI_CONF_DISABLE);
+ if (priv->tx_conf_en)
+ ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
+ priv->token,
+ DPNI_CONF_AFFINE);
+ else
+ ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
+ priv->token,
+ DPNI_CONF_DISABLE);
if (ret) {
DPAA2_PMD_ERR("Error in set tx conf mode settings: "
"err=%d", ret);
}
dpaa2_q->tc_index = tc_id;
+ ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_QUEUE_TX, dpaa2_q->tc_index,
+ dpaa2_q->flow_id, &tx_flow_cfg, &qid);
+ if (ret) {
+ DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
+ return -1;
+ }
+ dpaa2_q->fqid = qid.fqid;
+
if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
- struct dpni_congestion_notification_cfg cong_notif_cfg;
+ struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
cong_notif_cfg.threshold_entry = CONG_ENTER_TX_THRESHOLD;
}
dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
dev->data->tx_queues[tx_queue_id] = dpaa2_q;
+
+ if (priv->tx_conf_en) {
+ dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
+ options = options | DPNI_QUEUE_OPT_USER_CTX;
+ tx_conf_cfg.user_context = (size_t)(dpaa2_q);
+ ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
+ dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
+ if (ret) {
+ DPAA2_PMD_ERR("Error in setting the tx conf flow: "
+ "tc_index=%d, flow=%d err=%d",
+ dpaa2_tx_conf_q->tc_index,
+ dpaa2_tx_conf_q->flow_id, ret);
+ return -1;
+ }
+
+ ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
+ dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
+ if (ret) {
+ DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
+ return -1;
+ }
+ dpaa2_tx_conf_q->fqid = qid.fqid;
+ }
return 0;
}
static void
dpaa2_dev_rx_queue_release(void *q __rte_unused)
{
+ struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
+ struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
+ uint8_t options = 0;
+ int ret;
+ struct dpni_queue cfg;
+
+ memset(&cfg, 0, sizeof(struct dpni_queue));
PMD_INIT_FUNC_TRACE();
+ if (dpaa2_q->cgid != 0xff) {
+ options = DPNI_QUEUE_OPT_CLEAR_CGID;
+ cfg.cgid = dpaa2_q->cgid;
+
+ ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_QUEUE_RX,
+ dpaa2_q->tc_index, dpaa2_q->flow_id,
+ options, &cfg);
+ if (ret)
+ DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
+ dpaa2_q->fqid, ret);
+ priv->cgid_in_use[dpaa2_q->cgid] = 0;
+ dpaa2_q->cgid = 0xff;
+ }
}
static void
};
if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
+ dev->rx_pkt_burst == dpaa2_dev_rx ||
dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
return ptypes;
return NULL;
rte_eth_linkstatus_set(dev, &link);
}
-static void
+static int
dpaa2_dev_promiscuous_enable(
struct rte_eth_dev *dev)
{
if (dpni == NULL) {
DPAA2_PMD_ERR("dpni is NULL");
- return;
+ return -ENODEV;
}
ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
if (ret < 0)
DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
+
+ return ret;
}
-static void
+static int
dpaa2_dev_promiscuous_disable(
struct rte_eth_dev *dev)
{
if (dpni == NULL) {
DPAA2_PMD_ERR("dpni is NULL");
- return;
+ return -ENODEV;
}
ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
ret);
}
+
+ return ret;
}
-static void
+static int
dpaa2_dev_allmulticast_enable(
struct rte_eth_dev *dev)
{
if (dpni == NULL) {
DPAA2_PMD_ERR("dpni is NULL");
- return;
+ return -ENODEV;
}
ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
if (ret < 0)
DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
+
+ return ret;
}
-static void
+static int
dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
{
int ret;
if (dpni == NULL) {
DPAA2_PMD_ERR("dpni is NULL");
- return;
+ return -ENODEV;
}
/* must remain on for all promiscuous */
if (dev->data->promiscuous == 1)
- return;
+ return 0;
ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
if (ret < 0)
DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
+
+ return ret;
}
static int
int ret;
struct dpaa2_dev_priv *priv = dev->data->dev_private;
struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
- uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN
+ uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
+ VLAN_TAG_SIZE;
PMD_INIT_FUNC_TRACE();
}
/* check that mtu is within the allowed range */
- if ((mtu < ETHER_MIN_MTU) || (frame_size > DPAA2_MAX_RX_PKT_LEN))
+ if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
return -EINVAL;
- if (frame_size > ETHER_MAX_LEN)
+ if (frame_size > RTE_ETHER_MAX_LEN)
dev->data->dev_conf.rxmode.offloads &=
DEV_RX_OFFLOAD_JUMBO_FRAME;
else
* Maximum Ethernet header length
*/
ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
- frame_size);
+ frame_size - RTE_ETHER_CRC_LEN);
if (ret) {
DPAA2_PMD_ERR("Setting the max frame length failed");
return -1;
static int
dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
- struct ether_addr *addr,
+ struct rte_ether_addr *addr,
__rte_unused uint32_t index,
__rte_unused uint32_t pool)
{
struct dpaa2_dev_priv *priv = dev->data->dev_private;
struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
struct rte_eth_dev_data *data = dev->data;
- struct ether_addr *macaddr;
+ struct rte_ether_addr *macaddr;
PMD_INIT_FUNC_TRACE();
static int
dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
- struct ether_addr *addr)
+ struct rte_ether_addr *addr)
{
int ret;
struct dpaa2_dev_priv *priv = dev->data->dev_private;
struct dpaa2_dev_priv *priv = dev->data->dev_private;
struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
int32_t retcode;
- union dpni_statistics value[3] = {};
+ union dpni_statistics value[5] = {};
unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
if (n < num)
if (retcode)
goto err;
+ for (i = 0; i < priv->max_cgs; i++) {
+ if (!priv->cgid_in_use[i]) {
+ /* Get Counters from page_4*/
+ retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
+ priv->token,
+ 4, 0, &value[4]);
+ if (retcode)
+ goto err;
+ break;
+ }
+ }
+
for (i = 0; i < num; i++) {
xstats[i].id = i;
xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
struct dpaa2_dev_priv *priv = dev->data->dev_private;
struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
int32_t retcode;
- union dpni_statistics value[3] = {};
+ union dpni_statistics value[5] = {};
if (n < stat_cnt)
return stat_cnt;
if (retcode)
return 0;
+ /* Get Counters from page_4*/
+ retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
+ 4, 0, &value[4]);
+ if (retcode)
+ return 0;
+
for (i = 0; i < stat_cnt; i++) {
values[i] = value[dpaa2_xstats_strings[i].page_id].
raw.counter[dpaa2_xstats_strings[i].stats_id];
return limit;
}
-static void
+static int
dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
{
struct dpaa2_dev_priv *priv = dev->data->dev_private;
struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
- int32_t retcode;
+ int retcode;
int i;
struct dpaa2_queue *dpaa2_q;
if (dpni == NULL) {
DPAA2_PMD_ERR("dpni is NULL");
- return;
+ return -EINVAL;
}
retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
dpaa2_q->tx_pkts = 0;
}
- return;
+ return 0;
error:
DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
- return;
+ return retcode;
};
/* return 0 means link status changed, -1 means not changed */
*/
static int
populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
- struct ether_addr *mac_entry)
+ struct rte_ether_addr *mac_entry)
{
int ret;
- struct ether_addr phy_mac, prime_mac;
+ struct rte_ether_addr phy_mac, prime_mac;
- memset(&phy_mac, 0, sizeof(struct ether_addr));
- memset(&prime_mac, 0, sizeof(struct ether_addr));
+ memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
+ memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
/* Get the physical device MAC address */
ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
* If empty_mac(phy), return prime.
* if both are empty, create random MAC, set as prime and return
*/
- if (!is_zero_ether_addr(&phy_mac)) {
+ if (!rte_is_zero_ether_addr(&phy_mac)) {
/* If the addresses are not same, overwrite prime */
- if (!is_same_ether_addr(&phy_mac, &prime_mac)) {
+ if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
priv->token,
phy_mac.addr_bytes);
ret);
goto cleanup;
}
- memcpy(&prime_mac, &phy_mac, sizeof(struct ether_addr));
+ memcpy(&prime_mac, &phy_mac,
+ sizeof(struct rte_ether_addr));
}
- } else if (is_zero_ether_addr(&prime_mac)) {
+ } else if (rte_is_zero_ether_addr(&prime_mac)) {
/* In case phys and prime, both are zero, create random MAC */
- eth_random_addr(prime_mac.addr_bytes);
+ rte_eth_random_addr(prime_mac.addr_bytes);
ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
priv->token,
prime_mac.addr_bytes);
}
/* prime_mac the final MAC address */
- memcpy(mac_entry, &prime_mac, sizeof(struct ether_addr));
+ memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
return 0;
cleanup:
eth_dev->dev_ops = &dpaa2_ethdev_ops;
if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
+ else if (dpaa2_get_devargs(dev->devargs,
+ DRIVER_NO_PREFETCH_MODE))
+ eth_dev->rx_pkt_burst = dpaa2_dev_rx;
else
eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
eth_dev->tx_pkt_burst = dpaa2_dev_tx;
}
priv->num_rx_tc = attr.num_rx_tcs;
+ /* only if the custom CG is enabled */
+ if (attr.options & DPNI_OPT_CUSTOM_CG)
+ priv->max_cgs = attr.num_cgs;
+ else
+ priv->max_cgs = 0;
+
+ for (i = 0; i < priv->max_cgs; i++)
+ priv->cgid_in_use[i] = 0;
for (i = 0; i < attr.num_rx_tcs; i++)
priv->nb_rx_queues += attr.num_queues;
/* Using number of TX queues as number of TX TCs */
priv->nb_tx_queues = attr.num_tx_tcs;
- DPAA2_PMD_DEBUG("RX-TC= %d, nb_rx_queues= %d, nb_tx_queues=%d",
+ DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
priv->num_rx_tc, priv->nb_rx_queues,
- priv->nb_tx_queues);
+ priv->nb_tx_queues, priv->max_cgs);
priv->hw = dpni_dev;
priv->hw_id = hw_id;
priv->max_mac_filters = attr.mac_filter_entries;
priv->max_vlan_filters = attr.vlan_filter_entries;
priv->flags = 0;
+#if defined(RTE_LIBRTE_IEEE1588)
+ priv->tx_conf_en = 1;
+#else
+ priv->tx_conf_en = 0;
+#endif
/* Allocate memory for hardware structure for queues */
ret = dpaa2_alloc_rx_tx_queues(eth_dev);
* can add MAC entries when rte_eth_dev_mac_addr_add is called.
*/
eth_dev->data->mac_addrs = rte_zmalloc("dpni",
- ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
+ RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
if (eth_dev->data->mac_addrs == NULL) {
DPAA2_PMD_ERR(
"Failed to allocate %d bytes needed to store MAC addresses",
- ETHER_ADDR_LEN * attr.mac_filter_entries);
+ RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
ret = -ENOMEM;
goto init_err;
}
/* ... tx buffer layout ... */
memset(&layout, 0, sizeof(struct dpni_buffer_layout));
- layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
+ if (priv->tx_conf_en) {
+ layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
+ DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
+ layout.pass_timestamp = true;
+ } else {
+ layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
+ }
layout.pass_frame_status = 1;
ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
DPNI_QUEUE_TX, &layout);
/* ... tx-conf and error buffer layout ... */
memset(&layout, 0, sizeof(struct dpni_buffer_layout));
- layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
+ if (priv->tx_conf_en) {
+ layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
+ DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
+ layout.pass_timestamp = true;
+ } else {
+ layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
+ }
layout.pass_frame_status = 1;
ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
DPNI_QUEUE_TX_CONFIRM, &layout);
if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
DPAA2_PMD_INFO("Loopback mode");
+ } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
+ eth_dev->rx_pkt_burst = dpaa2_dev_rx;
+ DPAA2_PMD_INFO("No Prefetch mode");
} else {
eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
}
}
}
+ ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
+ RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
+ + VLAN_TAG_SIZE);
+ if (ret) {
+ DPAA2_PMD_ERR("Unable to set mtu. check config");
+ goto init_err;
+ }
+
RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
return 0;
init_err:
struct rte_dpaa2_device *dpaa2_dev)
{
struct rte_eth_dev *eth_dev;
+ struct dpaa2_dev_priv *priv;
int diag;
+ if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
+ RTE_PKTMBUF_HEADROOM) {
+ DPAA2_PMD_ERR(
+ "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
+ RTE_PKTMBUF_HEADROOM,
+ DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
+
+ return -1;
+ }
+
if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
if (!eth_dev)
return 0;
}
+ priv = eth_dev->data->dev_private;
+ priv->tx_conf_en = 0;
+
rte_eth_dev_release_port(eth_dev);
return diag;
}
RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
- DRIVER_LOOPBACK_MODE "=<int>");
+ DRIVER_LOOPBACK_MODE "=<int> "
+ DRIVER_NO_PREFETCH_MODE "=<int>");
RTE_INIT(dpaa2_pmd_init_log)
{
dpaa2_logtype_pmd = rte_log_register("pmd.net.dpaa2");
git.droids-corp.org / dpdk.git / blobdiff