net/hns3: support RAS process in Kunpeng 930

[dpdk.git] / drivers / net / hns3 / hns3_cmd.h

diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h
index 5d1fb67..bf1772d 100644 (file)
--- a/drivers/net/hns3/hns3_cmd.h
+++ b/drivers/net/hns3/hns3_cmd.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2018-2019 Hisilicon Limited.
+ * Copyright(c) 2018-2021 HiSilicon Limited.
  */
 
 #ifndef _HNS3_CMD_H_
@@ -56,13 +56,6 @@ enum hns3_cmd_return_status {
        HNS3_CMD_ROH_CHECK_FAIL = 12
 };
 
-enum hns3_cmd_status {
-       HNS3_STATUS_SUCCESS     = 0,
-       HNS3_ERR_CSQ_FULL       = -1,
-       HNS3_ERR_CSQ_TIMEOUT    = -2,
-       HNS3_ERR_CSQ_ERROR      = -3,
-};
-
 struct hns3_misc_vector {
        uint8_t *addr;
        int vector_irq;
@@ -72,7 +65,7 @@ struct hns3_cmq {
        struct hns3_cmq_ring csq;
        struct hns3_cmq_ring crq;
        uint16_t tx_timeout;
-       enum hns3_cmd_status last_status;
+       enum hns3_cmd_return_status last_status;
 };
 
 enum hns3_opcode_type {
@@ -115,6 +108,7 @@ enum hns3_opcode_type {
 
        /* MAC command */
        HNS3_OPC_CONFIG_MAC_MODE        = 0x0301,
+       HNS3_OPC_CONFIG_AN_MODE         = 0x0304,
        HNS3_OPC_QUERY_LINK_STATUS      = 0x0307,
        HNS3_OPC_CONFIG_MAX_FRM_SIZE    = 0x0308,
        HNS3_OPC_CONFIG_SPEED_DUP       = 0x0309,
@@ -237,7 +231,7 @@ enum hns3_opcode_type {
        /* SFP command */
        HNS3_OPC_GET_SFP_EEPROM         = 0x7100,
        HNS3_OPC_GET_SFP_EXIST          = 0x7101,
-       HNS3_OPC_SFP_GET_SPEED          = 0x7104,
+       HNS3_OPC_GET_SFP_INFO           = 0x7104,
 
        /* Interrupts commands */
        HNS3_OPC_ADD_RING_TO_VECTOR     = 0x1503,
@@ -258,6 +252,8 @@ enum hns3_opcode_type {
        HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM      = 0x1513,
        HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT   = 0x1514,
        HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT    = 0x1515,
+       HNS3_OPC_QUERY_ALL_ERR_BD_NUM           = 0x1516,
+       HNS3_OPC_QUERY_ALL_ERR_INFO             = 0x1517,
        HNS3_OPC_IGU_EGU_TNL_INT_EN             = 0x1803,
        HNS3_OPC_IGU_COMMON_INT_EN              = 0x1806,
        HNS3_OPC_TM_QCN_MEM_INT_CFG             = 0x1A14,
@@ -686,6 +682,7 @@ struct hns3_firmware_compat_cmd {
 #define HNS3_PHY_LINK_SPEED_10M_BIT            BIT(1)
 #define HNS3_PHY_LINK_SPEED_100M_HD_BIT                BIT(2)
 #define HNS3_PHY_LINK_SPEED_100M_BIT           BIT(3)
+#define HNS3_PHY_LINK_SPEED_1000M_BIT          BIT(5)
 #define HNS3_PHY_LINK_MODE_AUTONEG_BIT         BIT(6)
 #define HNS3_PHY_LINK_MODE_PAUSE_BIT           BIT(13)
 #define HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT      BIT(14)
@@ -773,13 +770,6 @@ struct hns3_config_auto_neg_cmd {
        uint8_t   rsv[20];
 };
 
-#define HNS3_MAC_CFG_FEC_AUTO_EN_B     0
-#define HNS3_MAC_CFG_FEC_MODE_S                1
-#define HNS3_MAC_CFG_FEC_MODE_M        GENMASK(3, 1)
-#define HNS3_MAC_FEC_OFF               0
-#define HNS3_MAC_FEC_BASER             1
-#define HNS3_MAC_FEC_RS                        2
-
 #define HNS3_SFP_INFO_BD0_LEN  20UL
 #define HNS3_SFP_INFO_BDX_LEN  24UL
 
@@ -794,14 +784,36 @@ struct hns3_sfp_type {
        uint8_t ext_type;
 };
 
-struct hns3_sfp_speed_cmd {
-       uint32_t  sfp_speed;
-       uint8_t   query_type; /* 0: sfp speed, 1: active fec */
-       uint8_t   active_fec; /* current FEC mode */
-       uint16_t  rsv1;
-       uint32_t  rsv2[4];
+/* Bitmap flags in supported_speed */
+#define HNS3_FIBER_LINK_SPEED_1G_BIT           BIT(0)
+#define HNS3_FIBER_LINK_SPEED_10G_BIT          BIT(1)
+#define HNS3_FIBER_LINK_SPEED_25G_BIT          BIT(2)
+#define HNS3_FIBER_LINK_SPEED_50G_BIT          BIT(3)
+#define HNS3_FIBER_LINK_SPEED_100G_BIT         BIT(4)
+#define HNS3_FIBER_LINK_SPEED_40G_BIT          BIT(5)
+#define HNS3_FIBER_LINK_SPEED_100M_BIT         BIT(6)
+#define HNS3_FIBER_LINK_SPEED_10M_BIT          BIT(7)
+#define HNS3_FIBER_LINK_SPEED_200G_BIT         BIT(8)
+
+struct hns3_sfp_info_cmd {
+       uint32_t sfp_speed;
+       uint8_t query_type; /* 0: sfp speed, 1: active */
+       uint8_t active_fec; /* current FEC mode */
+       uint8_t autoneg; /* current autoneg state */
+       /* 0: not support autoneg, 1: support autoneg */
+       uint8_t autoneg_ability;
+       uint32_t supported_speed; /* speed supported by current media */
+       uint32_t module_type;
+       uint8_t rsv1[8];
 };
 
+#define HNS3_MAC_CFG_FEC_AUTO_EN_B     0
+#define HNS3_MAC_CFG_FEC_MODE_S                1
+#define HNS3_MAC_CFG_FEC_MODE_M        GENMASK(3, 1)
+#define HNS3_MAC_FEC_OFF               0
+#define HNS3_MAC_FEC_BASER             1
+#define HNS3_MAC_FEC_RS                        2
+
 /* Configure FEC mode, opcode:0x031A */
 struct hns3_config_fec_cmd {
        uint8_t fec_mode;