* Copyright(c) 2018-2019 Hisilicon Limited.
*/
-#include <errno.h>
-#include <inttypes.h>
-#include <stdbool.h>
-#include <string.h>
-#include <unistd.h>
#include <rte_io.h>
-#include <rte_common.h>
#include <rte_ethdev.h>
#include "hns3_logs.h"
-#include "hns3_regs.h"
#include "hns3_ethdev.h"
#include "hns3_dcb.h"
/* Calc tick */
if (shaper_level >= HNS3_SHAPER_LVL_CNT) {
hns3_err(hw,
- "shaper_level(%d) is greater than HNS3_SHAPER_LVL_CNT(%d)",
+ "shaper_level(%u) is greater than HNS3_SHAPER_LVL_CNT(%d)",
shaper_level, HNS3_SHAPER_LVL_CNT);
return -EINVAL;
}
if (ir > hw->max_tm_rate) {
- hns3_err(hw, "rate(%d) exceeds the max rate(%d) driver "
+ hns3_err(hw, "rate(%u) exceeds the max rate(%u) driver "
"supported.", ir, hw->max_tm_rate);
return -EINVAL;
}
shaper_para->ir_b = SHAPER_DEFAULT_IR_B;
} else if (ir_calc > ir) {
/* Increasing the denominator to select ir_s value */
- do {
+ while (ir_calc >= ir && ir) {
ir_s_calc++;
ir_calc = DIVISOR_IR_B_126 / (tick * (1 << ir_s_calc));
- } while (ir_calc > ir);
+ }
- if (ir_calc == ir)
- shaper_para->ir_b = SHAPER_DEFAULT_IR_B;
- else
- shaper_para->ir_b = (ir * tick * (1 << ir_s_calc) +
- (DIVISOR_CLK >> 1)) / DIVISOR_CLK;
+ shaper_para->ir_b = (ir * tick * (1 << ir_s_calc) +
+ (DIVISOR_CLK >> 1)) / DIVISOR_CLK;
} else {
/*
* Increasing the numerator to select ir_u value. ir_u_calc will
{
uint32_t shapping_para = 0;
+ /* If ir_b is zero it means IR is 0Mbps, return zero of shapping_para */
+ if (ir_b == 0)
+ return shapping_para;
+
hns3_dcb_set_field(shapping_para, IR_B, ir_b);
hns3_dcb_set_field(shapping_para, IR_U, ir_u);
hns3_dcb_set_field(shapping_para, IR_S, ir_s);
return shapping_para;
}
-static int
+int
hns3_dcb_port_shaper_cfg(struct hns3_hw *hw)
{
struct hns3_port_shapping_cmd *shap_cfg_cmd;
return hns3_cmd_send(hw, &desc, 1);
}
-static int
-hns3_dcb_pg_shaper_cfg(struct hns3_hw *hw)
+int
+hns3_pg_shaper_rate_cfg(struct hns3_hw *hw, uint8_t pg_id, uint32_t rate)
{
- struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
struct hns3_shaper_parameter shaper_parameter;
- struct hns3_pf *pf = &hns->pf;
uint32_t ir_u, ir_b, ir_s;
uint32_t shaper_para;
+ int ret;
+
+ /* Calc shaper para */
+ ret = hns3_shaper_para_calc(hw, rate, HNS3_SHAPER_LVL_PG,
+ &shaper_parameter);
+ if (ret) {
+ hns3_err(hw, "calculate shaper parameter fail, ret = %d.",
+ ret);
+ return ret;
+ }
+
+ shaper_para = hns3_dcb_get_shapping_para(0, 0, 0,
+ HNS3_SHAPER_BS_U_DEF,
+ HNS3_SHAPER_BS_S_DEF);
+
+ ret = hns3_dcb_pg_shapping_cfg(hw, HNS3_DCB_SHAP_C_BUCKET, pg_id,
+ shaper_para, rate);
+ if (ret) {
+ hns3_err(hw, "config PG CIR shaper parameter fail, ret = %d.",
+ ret);
+ return ret;
+ }
+
+ ir_b = shaper_parameter.ir_b;
+ ir_u = shaper_parameter.ir_u;
+ ir_s = shaper_parameter.ir_s;
+ shaper_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
+ HNS3_SHAPER_BS_U_DEF,
+ HNS3_SHAPER_BS_S_DEF);
+
+ ret = hns3_dcb_pg_shapping_cfg(hw, HNS3_DCB_SHAP_P_BUCKET, pg_id,
+ shaper_para, rate);
+ if (ret) {
+ hns3_err(hw, "config PG PIR shaper parameter fail, ret = %d.",
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int
+hns3_dcb_pg_shaper_cfg(struct hns3_hw *hw)
+{
+ struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
uint32_t rate;
uint8_t i;
int ret;
/* Pg to pri */
for (i = 0; i < hw->dcb_info.num_pg; i++) {
rate = hw->dcb_info.pg_info[i].bw_limit;
-
- /* Calc shaper para */
- ret = hns3_shaper_para_calc(hw, rate, HNS3_SHAPER_LVL_PG,
- &shaper_parameter);
- if (ret) {
- hns3_err(hw, "calculate shaper parameter failed: %d",
- ret);
- return ret;
- }
-
- shaper_para = hns3_dcb_get_shapping_para(0, 0, 0,
- HNS3_SHAPER_BS_U_DEF,
- HNS3_SHAPER_BS_S_DEF);
-
- ret = hns3_dcb_pg_shapping_cfg(hw, HNS3_DCB_SHAP_C_BUCKET, i,
- shaper_para, rate);
- if (ret) {
- hns3_err(hw,
- "config PG CIR shaper parameter failed: %d",
- ret);
- return ret;
- }
-
- ir_b = shaper_parameter.ir_b;
- ir_u = shaper_parameter.ir_u;
- ir_s = shaper_parameter.ir_s;
- shaper_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
- HNS3_SHAPER_BS_U_DEF,
- HNS3_SHAPER_BS_S_DEF);
-
- ret = hns3_dcb_pg_shapping_cfg(hw, HNS3_DCB_SHAP_P_BUCKET, i,
- shaper_para, rate);
- if (ret) {
- hns3_err(hw,
- "config PG PIR shaper parameter failed: %d",
- ret);
+ ret = hns3_pg_shaper_rate_cfg(hw, i, rate);
+ if (ret)
return ret;
- }
}
return 0;
return hns3_cmd_send(hw, &desc, 1);
}
-static int
-hns3_dcb_pri_tc_base_shaper_cfg(struct hns3_hw *hw)
+int
+hns3_pri_shaper_rate_cfg(struct hns3_hw *hw, uint8_t tc_no, uint32_t rate)
{
struct hns3_shaper_parameter shaper_parameter;
uint32_t ir_u, ir_b, ir_s;
uint32_t shaper_para;
- uint32_t rate;
- int ret, i;
+ int ret;
- for (i = 0; i < hw->dcb_info.num_tc; i++) {
- rate = hw->dcb_info.tc_info[i].bw_limit;
- ret = hns3_shaper_para_calc(hw, rate, HNS3_SHAPER_LVL_PRI,
- &shaper_parameter);
- if (ret) {
- hns3_err(hw, "calculate shaper parameter failed: %d",
- ret);
- return ret;
- }
+ ret = hns3_shaper_para_calc(hw, rate, HNS3_SHAPER_LVL_PRI,
+ &shaper_parameter);
+ if (ret) {
+ hns3_err(hw, "calculate shaper parameter failed: %d.",
+ ret);
+ return ret;
+ }
- shaper_para = hns3_dcb_get_shapping_para(0, 0, 0,
- HNS3_SHAPER_BS_U_DEF,
- HNS3_SHAPER_BS_S_DEF);
+ shaper_para = hns3_dcb_get_shapping_para(0, 0, 0,
+ HNS3_SHAPER_BS_U_DEF,
+ HNS3_SHAPER_BS_S_DEF);
- ret = hns3_dcb_pri_shapping_cfg(hw, HNS3_DCB_SHAP_C_BUCKET, i,
- shaper_para, rate);
- if (ret) {
- hns3_err(hw,
- "config priority CIR shaper parameter failed: %d",
- ret);
- return ret;
- }
+ ret = hns3_dcb_pri_shapping_cfg(hw, HNS3_DCB_SHAP_C_BUCKET, tc_no,
+ shaper_para, rate);
+ if (ret) {
+ hns3_err(hw,
+ "config priority CIR shaper parameter failed: %d.",
+ ret);
+ return ret;
+ }
- ir_b = shaper_parameter.ir_b;
- ir_u = shaper_parameter.ir_u;
- ir_s = shaper_parameter.ir_s;
- shaper_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
- HNS3_SHAPER_BS_U_DEF,
- HNS3_SHAPER_BS_S_DEF);
+ ir_b = shaper_parameter.ir_b;
+ ir_u = shaper_parameter.ir_u;
+ ir_s = shaper_parameter.ir_s;
+ shaper_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
+ HNS3_SHAPER_BS_U_DEF,
+ HNS3_SHAPER_BS_S_DEF);
- ret = hns3_dcb_pri_shapping_cfg(hw, HNS3_DCB_SHAP_P_BUCKET, i,
- shaper_para, rate);
- if (ret) {
- hns3_err(hw,
- "config priority PIR shaper parameter failed: %d",
- ret);
- return ret;
- }
+ ret = hns3_dcb_pri_shapping_cfg(hw, HNS3_DCB_SHAP_P_BUCKET, tc_no,
+ shaper_para, rate);
+ if (ret) {
+ hns3_err(hw,
+ "config priority PIR shaper parameter failed: %d.",
+ ret);
+ return ret;
}
return 0;
}
-
static int
hns3_dcb_pri_shaper_cfg(struct hns3_hw *hw)
{
- struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
- struct hns3_pf *pf = &hns->pf;
+ struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
+ uint32_t rate;
+ uint8_t i;
int ret;
if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
return -EINVAL;
- ret = hns3_dcb_pri_tc_base_shaper_cfg(hw);
- if (ret)
- hns3_err(hw, "config port shaper failed: %d", ret);
+ for (i = 0; i < hw->dcb_info.num_tc; i++) {
+ rate = hw->dcb_info.tc_info[i].bw_limit;
+ ret = hns3_pri_shaper_rate_cfg(hw, i, rate);
+ if (ret) {
+ hns3_err(hw, "config pri shaper failed: %d.", ret);
+ return ret;
+ }
+ }
- return ret;
+ return 0;
}
static int
* and configured directly to the hardware in the RESET_STAGE_RESTORE
* stage of the reset process.
*/
- if (rte_atomic16_read(&hw->reset.resetting) == 0) {
+ if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
for (i = 0; i < HNS3_RSS_IND_TBL_SIZE; i++)
rss_cfg->rss_indirection_tbl[i] =
i % hw->alloc_rss_size;
return 0;
}
+uint8_t
+hns3_txq_mapped_tc_get(struct hns3_hw *hw, uint16_t txq_no)
+{
+ struct hns3_tc_queue_info *tc_queue;
+ uint8_t i;
+
+ for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
+ tc_queue = &hw->tc_queue[i];
+ if (!tc_queue->enable)
+ continue;
+
+ if (txq_no >= tc_queue->tqp_offset &&
+ txq_no < tc_queue->tqp_offset + tc_queue->tqp_count)
+ return i;
+ }
+
+ /* return TC0 in default case */
+ return 0;
+}
+
int
hns3_queue_to_tc_mapping(struct hns3_hw *hw, uint16_t nb_rx_q, uint16_t nb_tx_q)
{
pause_time <= PAUSE_TIME_DIV_BY * HNS3_DEFAULT_PAUSE_TRANS_GAP)
pause_trans_gap = pause_time / PAUSE_TIME_DIV_BY - 1;
else {
- hns3_warn(hw, "pause_time(%d) is adjusted to 4", pause_time);
+ hns3_warn(hw, "pause_time(%u) is adjusted to 4", pause_time);
pause_time = PAUSE_TIME_MIN_VALUE;
pause_trans_gap = pause_time / PAUSE_TIME_DIV_BY - 1;
}
{
struct rte_eth_dcb_rx_conf *dcb_rx_conf;
struct hns3_hw *hw = &hns->hw;
+ uint16_t nb_rx_q = hw->data->nb_rx_queues;
+ uint16_t nb_tx_q = hw->data->nb_tx_queues;
uint8_t max_tc = 0;
uint8_t pfc_en;
int i;
pfc_en = RTE_LEN2MASK((uint8_t)dcb_rx_conf->nb_tcs, uint8_t);
if (hw->dcb_info.pfc_en != pfc_en)
*changed = true;
+
+ /* tx/rx queue number is reconfigured. */
+ if (nb_rx_q != hw->used_rx_queues || nb_tx_q != hw->used_tx_queues)
+ *changed = true;
}
static int
return -EINVAL;
if (nb_rx_q < num_tc) {
- hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
+ hns3_err(hw, "number of Rx queues(%u) is less than tcs(%u).",
nb_rx_q, num_tc);
return -EINVAL;
}
if (nb_tx_q < num_tc) {
- hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
+ hns3_err(hw, "number of Tx queues(%u) is less than tcs(%u).",
nb_tx_q, num_tc);
return -EINVAL;
}
int ret;
hns3_dcb_cfg_validate(hns, &num_tc, &map_changed);
- if (map_changed || rte_atomic16_read(&hw->reset.resetting)) {
+ if (map_changed ||
+ __atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
ret = hns3_dcb_info_update(hns, num_tc);
if (ret) {
hns3_err(hw, "dcb info update failed: %d", ret);
git.droids-corp.org / dpdk.git / blobdiff