* Copyright(c) 2018-2019 Hisilicon Limited.
*/
-#include <errno.h>
-#include <stdarg.h>
-#include <stdbool.h>
-#include <stdio.h>
-#include <stdint.h>
-#include <inttypes.h>
-#include <unistd.h>
-#include <rte_atomic.h>
+#include <rte_alarm.h>
#include <rte_bus_pci.h>
-#include <rte_common.h>
-#include <rte_cycles.h>
-#include <rte_dev.h>
-#include <rte_eal.h>
-#include <rte_ether.h>
-#include <rte_ethdev_driver.h>
#include <rte_ethdev_pci.h>
-#include <rte_interrupts.h>
-#include <rte_io.h>
-#include <rte_log.h>
#include <rte_pci.h>
#include "hns3_ethdev.h"
#define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
#define HNS3_SERVICE_INTERVAL 1000000 /* us */
-#define HNS3_PORT_BASE_VLAN_DISABLE 0
-#define HNS3_PORT_BASE_VLAN_ENABLE 1
-#define HNS3_INVLID_PVID 0xFFFF
+#define HNS3_INVALID_PVID 0xFFFF
#define HNS3_FILTER_TYPE_VF 0
#define HNS3_FILTER_TYPE_PORT 1
#define HNS3_FUN_RST_ING_B 0
#define HNS3_VECTOR0_IMP_RESET_INT_B 1
+#define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
+#define HNS3_VECTOR0_IMP_RD_POISON_B 5U
+#define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
#define HNS3_RESET_WAIT_MS 100
#define HNS3_RESET_WAIT_CNT 200
-int hns3_logtype_init;
-int hns3_logtype_driver;
+/* FEC mode order defined in HNS3 hardware */
+#define HNS3_HW_FEC_MODE_NOFEC 0
+#define HNS3_HW_FEC_MODE_BASER 1
+#define HNS3_HW_FEC_MODE_RS 2
enum hns3_evt_cause {
HNS3_VECTOR0_EVENT_RST,
HNS3_VECTOR0_EVENT_OTHER,
};
+static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
+ { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
+ RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
+ RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
+
+ { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
+ RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
+ RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
+ RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
+
+ { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
+ RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
+ RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
+
+ { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
+ RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
+ RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
+ RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
+
+ { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
+ RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
+ RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
+
+ { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
+ RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
+ RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
+};
+
static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
uint64_t *levels);
static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
int on);
static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
+static int hns3_add_mc_addr(struct hns3_hw *hw,
+ struct rte_ether_addr *mac_addr);
+static int hns3_remove_mc_addr(struct hns3_hw *hw,
+ struct rte_ether_addr *mac_addr);
+static int hns3_restore_fec(struct hns3_hw *hw);
+static int hns3_query_dev_fec_info(struct hns3_hw *hw);
+
+void hns3_ether_format_addr(char *buf, uint16_t size,
+ const struct rte_ether_addr *ether_addr)
+{
+ snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
+ ether_addr->addr_bytes[0],
+ ether_addr->addr_bytes[4],
+ ether_addr->addr_bytes[5]);
+}
+
static void
hns3_pf_disable_irq0(struct hns3_hw *hw)
{
struct hns3_hw *hw = &hns->hw;
uint32_t vector0_int_stats;
uint32_t cmdq_src_val;
+ uint32_t hw_err_src_reg;
uint32_t val;
enum hns3_evt_cause ret;
/* fetch the events from their corresponding regs */
vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
+ hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
/*
* Assumption: If by any chance reset and mailbox events are reported
}
/* check for vector0 msix event source */
- if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
- val = vector0_int_stats;
+ if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
+ hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
+ val = vector0_int_stats | hw_err_src_reg;
ret = HNS3_VECTOR0_EVENT_ERR;
goto out;
}
goto out;
}
- if (clearval && (vector0_int_stats || cmdq_src_val))
- hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
- vector0_int_stats, cmdq_src_val);
+ if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
+ hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
+ vector0_int_stats, cmdq_src_val, hw_err_src_reg);
val = vector0_int_stats;
ret = HNS3_VECTOR0_EVENT_OTHER;
out:
hns3_pf_disable_irq0(hw);
event_cause = hns3_check_event_cause(hns, &clearval);
-
/* vector 0 interrupt is shared with reset and mailbox source events. */
if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
+ hns3_warn(hw, "Received err interrupt");
hns3_handle_msix_error(hns, &hw->reset.request);
+ hns3_handle_ras_error(hns, &hw->reset.request);
hns3_schedule_reset(hns);
- } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
+ } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
+ hns3_warn(hw, "Received reset interrupt");
hns3_schedule_reset(hns);
- else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
+ } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
hns3_dev_handle_mbx_msg(hw);
else
hns3_err(hw, "Received unknown event");
static int
hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
{
-#define HNS3_VLAN_OFFSET_160 160
+#define HNS3_VLAN_ID_OFFSET_STEP 160
+#define HNS3_VLAN_BYTE_SIZE 8
struct hns3_vlan_filter_pf_cfg_cmd *req;
struct hns3_hw *hw = &hns->hw;
uint8_t vlan_offset_byte_val;
struct hns3_cmd_desc desc;
uint8_t vlan_offset_byte;
- uint8_t vlan_offset_160;
+ uint8_t vlan_offset_base;
int ret;
hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
- vlan_offset_160 = vlan_id / HNS3_VLAN_OFFSET_160;
- vlan_offset_byte = (vlan_id % HNS3_VLAN_OFFSET_160) / 8;
- vlan_offset_byte_val = 1 << (vlan_id % 8);
+ vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
+ vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
+ HNS3_VLAN_BYTE_SIZE;
+ vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
- req->vlan_offset = vlan_offset_160;
+ req->vlan_offset = vlan_offset_base;
req->vlan_cfg = on ? 0 : 1;
req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
hns3_restore_vlan_table(struct hns3_adapter *hns)
{
struct hns3_user_vlan_table *vlan_entry;
+ struct hns3_hw *hw = &hns->hw;
struct hns3_pf *pf = &hns->pf;
uint16_t vlan_id;
int ret = 0;
- if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) {
- ret = hns3_vlan_pvid_configure(hns, pf->port_base_vlan_cfg.pvid,
- 1);
- return ret;
- }
+ if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
+ return hns3_vlan_pvid_configure(hns,
+ hw->port_base_vlan_cfg.pvid, 1);
LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
if (vlan_entry->hd_tbl_status) {
static int
hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
{
- struct hns3_pf *pf = &hns->pf;
+ struct hns3_hw *hw = &hns->hw;
bool writen_to_tbl = false;
int ret = 0;
/*
- * When vlan filter is enabled, hardware regards vlan id 0 as the entry
- * for normal packet, deleting vlan id 0 is not allowed.
+ * When vlan filter is enabled, hardware regards packets without vlan
+ * as packets with vlan 0. So, to receive packets without vlan, vlan id
+ * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
*/
if (on == 0 && vlan_id == 0)
return 0;
* vlan list. The vlan id in vlan list will be writen in vlan filter
* table until port base vlan disabled
*/
- if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
+ if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
writen_to_tbl = true;
}
- if (ret == 0 && vlan_id) {
+ if (ret == 0) {
if (on)
hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
else
hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
vcfg->vlan2_vlan_prionly ? 1 : 0);
+ /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
+ hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
+ vcfg->strip_tag1_discard_en ? 1 : 0);
+ hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
+ vcfg->strip_tag2_discard_en ? 1 : 0);
/*
* In current version VF is not supported when PF is driven by DPDK
- * driver, the PF-related vf_id is 0, just need to configure parameters
- * for vport_id 0.
+ * driver, just need to configure parameters for PF vport.
*/
- vport_id = 0;
+ vport_id = HNS3_PF_FUNC_ID;
req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
req->vf_bitmap[req->vf_offset] = bitmap;
hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
{
struct hns3_rx_vtag_cfg rxvlan_cfg;
- struct hns3_pf *pf = &hns->pf;
struct hns3_hw *hw = &hns->hw;
int ret;
- if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
+ if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
rxvlan_cfg.strip_tag1_en = false;
rxvlan_cfg.strip_tag2_en = enable;
+ rxvlan_cfg.strip_tag2_discard_en = false;
} else {
rxvlan_cfg.strip_tag1_en = enable;
rxvlan_cfg.strip_tag2_en = true;
+ rxvlan_cfg.strip_tag2_discard_en = true;
}
+ rxvlan_cfg.strip_tag1_discard_en = false;
rxvlan_cfg.vlan1_vlan_prionly = false;
rxvlan_cfg.vlan2_vlan_prionly = false;
rxvlan_cfg.rx_vlan_offload_en = enable;
}
static int
-hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
+hns3_vlan_filter_init(struct hns3_adapter *hns)
{
struct hns3_hw *hw = &hns->hw;
int ret;
ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
- HNS3_FILTER_FE_EGRESS, false, 0);
+ HNS3_FILTER_FE_EGRESS, false,
+ HNS3_PF_FUNC_ID);
if (ret) {
- hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
+ hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
return ret;
}
ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
- HNS3_FILTER_FE_INGRESS, enable, 0);
+ HNS3_FILTER_FE_INGRESS, false,
+ HNS3_PF_FUNC_ID);
+ if (ret)
+ hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
+
+ return ret;
+}
+
+static int
+hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
+{
+ struct hns3_hw *hw = &hns->hw;
+ int ret;
+
+ ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
+ HNS3_FILTER_FE_INGRESS, enable,
+ HNS3_PF_FUNC_ID);
if (ret)
- hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
+ hns3_err(hw, "failed to %s port vlan filter, ret = %d",
+ enable ? "enable" : "disable", ret);
return ret;
}
rte_spinlock_lock(&hw->lock);
rxmode = &dev->data->dev_conf.rxmode;
tmp_mask = (unsigned int)mask;
+ if (tmp_mask & ETH_VLAN_FILTER_MASK) {
+ /* ignore vlan filter configuration during promiscuous mode */
+ if (!dev->data->promiscuous) {
+ /* Enable or disable VLAN filter */
+ enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
+ true : false;
+
+ ret = hns3_enable_vlan_filter(hns, enable);
+ if (ret) {
+ rte_spinlock_unlock(&hw->lock);
+ hns3_err(hw, "failed to %s rx filter, ret = %d",
+ enable ? "enable" : "disable", ret);
+ return ret;
+ }
+ }
+ }
+
if (tmp_mask & ETH_VLAN_STRIP_MASK) {
/* Enable or disable VLAN stripping */
enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
ret = hns3_en_hw_strip_rxvtag(hns, enable);
if (ret) {
rte_spinlock_unlock(&hw->lock);
- hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
+ hns3_err(hw, "failed to %s rx strip, ret = %d",
+ enable ? "enable" : "disable", ret);
return ret;
}
}
vcfg->insert_tag2_en ? 1 : 0);
hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
+ /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
+ hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
+ vcfg->tag_shift_mode_en ? 1 : 0);
+
/*
* In current version VF is not supported when PF is driven by DPDK
- * driver, the PF-related vf_id is 0, just need to configure parameters
- * for vport_id 0.
+ * driver, just need to configure parameters for PF vport.
*/
- vport_id = 0;
+ vport_id = HNS3_PF_FUNC_ID;
req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
req->vf_bitmap[req->vf_offset] = bitmap;
txvlan_cfg.insert_tag1_en = false;
txvlan_cfg.default_tag1 = 0;
} else {
- txvlan_cfg.accept_tag1 = false;
+ txvlan_cfg.accept_tag1 =
+ hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
txvlan_cfg.insert_tag1_en = true;
txvlan_cfg.default_tag1 = pvid;
}
txvlan_cfg.accept_untag2 = true;
txvlan_cfg.insert_tag2_en = false;
txvlan_cfg.default_tag2 = 0;
+ txvlan_cfg.tag_shift_mode_en = true;
ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
if (ret) {
return ret;
}
-static void
-hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
-{
- struct hns3_pf *pf = &hns->pf;
-
- pf->port_base_vlan_cfg.state = on ?
- HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
-
- pf->port_base_vlan_cfg.pvid = pvid;
-}
static void
hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
struct hns3_pf *pf = &hns->pf;
LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
- if (vlan_entry->hd_tbl_status)
+ if (vlan_entry->hd_tbl_status) {
hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
-
- vlan_entry->hd_tbl_status = false;
+ vlan_entry->hd_tbl_status = false;
+ }
}
if (is_del_list) {
struct hns3_pf *pf = &hns->pf;
LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
- if (!vlan_entry->hd_tbl_status)
+ if (!vlan_entry->hd_tbl_status) {
hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
-
- vlan_entry->hd_tbl_status = true;
+ vlan_entry->hd_tbl_status = true;
+ }
}
}
hns3_remove_all_vlan_table(struct hns3_adapter *hns)
{
struct hns3_hw *hw = &hns->hw;
- struct hns3_pf *pf = &hns->pf;
int ret;
hns3_rm_all_vlan_table(hns, true);
- if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
+ if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
ret = hns3_set_port_vlan_filter(hns,
- pf->port_base_vlan_cfg.pvid, 0);
+ hw->port_base_vlan_cfg.pvid, 0);
if (ret) {
hns3_err(hw, "Failed to remove all vlan table, ret =%d",
ret);
static int
hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
- uint16_t port_base_vlan_state,
- uint16_t new_pvid, uint16_t old_pvid)
+ uint16_t port_base_vlan_state, uint16_t new_pvid)
{
- struct hns3_pf *pf = &hns->pf;
struct hns3_hw *hw = &hns->hw;
- int ret = 0;
+ uint16_t old_pvid;
+ int ret;
if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
- if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
+ old_pvid = hw->port_base_vlan_cfg.pvid;
+ if (old_pvid != HNS3_INVALID_PVID) {
ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
if (ret) {
- hns3_err(hw,
- "Failed to clear clear old pvid filter, ret =%d",
- ret);
+ hns3_err(hw, "failed to remove old pvid %u, "
+ "ret = %d", old_pvid, ret);
return ret;
}
}
hns3_rm_all_vlan_table(hns, false);
- return hns3_set_port_vlan_filter(hns, new_pvid, 1);
- }
-
- if (new_pvid != 0) {
+ ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
+ if (ret) {
+ hns3_err(hw, "failed to add new pvid %u, ret = %d",
+ new_pvid, ret);
+ return ret;
+ }
+ } else {
ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
if (ret) {
- hns3_err(hw, "Failed to set port vlan filter, ret =%d",
- ret);
+ hns3_err(hw, "failed to remove pvid %u, ret = %d",
+ new_pvid, ret);
return ret;
}
- }
- if (new_pvid == pf->port_base_vlan_cfg.pvid)
hns3_add_all_vlan_table(hns);
-
- return ret;
+ }
+ return 0;
}
static int
-hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
+hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
{
+ struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
struct hns3_rx_vtag_cfg rx_vlan_cfg;
- struct hns3_hw *hw = &hns->hw;
bool rx_strip_en;
int ret;
- rx_strip_en = on ? true : false;
- rx_vlan_cfg.strip_tag1_en = rx_strip_en;
- rx_vlan_cfg.strip_tag2_en = rx_strip_en;
+ rx_strip_en = old_cfg->rx_vlan_offload_en;
+ if (on) {
+ rx_vlan_cfg.strip_tag1_en = rx_strip_en;
+ rx_vlan_cfg.strip_tag2_en = true;
+ rx_vlan_cfg.strip_tag2_discard_en = true;
+ } else {
+ rx_vlan_cfg.strip_tag1_en = false;
+ rx_vlan_cfg.strip_tag2_en = rx_strip_en;
+ rx_vlan_cfg.strip_tag2_discard_en = false;
+ }
+ rx_vlan_cfg.strip_tag1_discard_en = false;
rx_vlan_cfg.vlan1_vlan_prionly = false;
rx_vlan_cfg.vlan2_vlan_prionly = false;
- rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
+ rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
- if (ret) {
- hns3_err(hw, "enable strip rx failed, ret =%d", ret);
+ if (ret)
return ret;
- }
hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
return ret;
static int
hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
{
- struct hns3_pf *pf = &hns->pf;
struct hns3_hw *hw = &hns->hw;
uint16_t port_base_vlan_state;
- uint16_t old_pvid;
int ret;
- if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
- if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
+ if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
+ if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
hns3_warn(hw, "Invalid operation! As current pvid set "
"is %u, disable pvid %u is invalid",
- pf->port_base_vlan_cfg.pvid, pvid);
+ hw->port_base_vlan_cfg.pvid, pvid);
return 0;
}
HNS3_PORT_BASE_VLAN_DISABLE;
ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
if (ret) {
- hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
+ hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
+ ret);
return ret;
}
- ret = hns3_en_rx_strip_all(hns, on);
+ ret = hns3_en_pvid_strip(hns, on);
if (ret) {
- hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
+ hns3_err(hw, "failed to config rx vlan strip for pvid, "
+ "ret = %d", ret);
return ret;
}
- if (pvid == HNS3_INVLID_PVID)
+ if (pvid == HNS3_INVALID_PVID)
goto out;
- old_pvid = pf->port_base_vlan_cfg.pvid;
- ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
- old_pvid);
+ ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
if (ret) {
- hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
+ hns3_err(hw, "failed to update vlan filter entries, ret = %d",
ret);
return ret;
}
out:
- hns3_store_port_base_vlan_info(hns, pvid, on);
+ hw->port_base_vlan_cfg.state = port_base_vlan_state;
+ hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
return ret;
}
{
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
+ bool pvid_en_state_change;
+ uint16_t pvid_state;
int ret;
+ if (pvid > RTE_ETHER_MAX_VLAN_ID) {
+ hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
+ RTE_ETHER_MAX_VLAN_ID);
+ return -EINVAL;
+ }
+
+ /*
+ * If PVID configuration state change, should refresh the PVID
+ * configuration state in struct hns3_tx_queue/hns3_rx_queue.
+ */
+ pvid_state = hw->port_base_vlan_cfg.state;
+ if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
+ (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
+ pvid_en_state_change = false;
+ else
+ pvid_en_state_change = true;
+
rte_spinlock_lock(&hw->lock);
ret = hns3_vlan_pvid_configure(hns, pvid, on);
rte_spinlock_unlock(&hw->lock);
- return ret;
-}
-
-static void
-init_port_base_vlan_info(struct hns3_hw *hw)
-{
- struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
- struct hns3_pf *pf = &hns->pf;
+ if (ret)
+ return ret;
+ /*
+ * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
+ * need be processed by PMD driver.
+ */
+ if (pvid_en_state_change &&
+ hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
+ hns3_update_all_queues_pvid_proc_en(hw);
- pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
- pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
+ return 0;
}
static int
struct hns3_hw *hw = &hns->hw;
int ret;
- ret = hns3_set_port_vlan_filter(hns, 0, 1);
+ /*
+ * When vlan filter is enabled, hardware regards packets without vlan
+ * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
+ * table, packets without vlan won't be received. So, add vlan 0 as
+ * the default vlan.
+ */
+ ret = hns3_vlan_filter_configure(hns, 0, 1);
if (ret)
hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
return ret;
* ensure that the hardware configuration remains unchanged before and
* after reset.
*/
- if (rte_atomic16_read(&hw->reset.resetting) == 0)
- init_port_base_vlan_info(hw);
+ if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
+ hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
+ hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
+ }
- ret = hns3_enable_vlan_filter(hns, true);
+ ret = hns3_vlan_filter_init(hns);
if (ret) {
hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
return ret;
* we will restore configurations to hardware in hns3_restore_vlan_table
* and hns3_restore_vlan_conf later.
*/
- if (rte_atomic16_read(&hw->reset.resetting) == 0) {
- ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
+ if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
+ ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
if (ret) {
hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
return ret;
{
struct hns3_pf *pf = &hns->pf;
struct hns3_hw *hw = &hns->hw;
+ uint64_t offloads;
+ bool enable;
int ret;
+ if (!hw->data->promiscuous) {
+ /* restore vlan filter states */
+ offloads = hw->data->dev_conf.rxmode.offloads;
+ enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
+ ret = hns3_enable_vlan_filter(hns, enable);
+ if (ret) {
+ hns3_err(hw, "failed to restore vlan rx filter conf, "
+ "ret = %d", ret);
+ return ret;
+ }
+ }
+
ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
if (ret) {
- hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
+ hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
return ret;
}
ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
if (ret)
- hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
+ hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
return ret;
}
struct rte_eth_dev_data *data = dev->data;
struct rte_eth_txmode *txmode;
struct hns3_hw *hw = &hns->hw;
+ int mask;
int ret;
txmode = &data->dev_conf.txmode;
hns3_warn(hw,
"hw_vlan_reject_tagged or hw_vlan_reject_untagged "
"configuration is not supported! Ignore these two "
- "parameters: hw_vlan_reject_tagged(%d), "
- "hw_vlan_reject_untagged(%d)",
+ "parameters: hw_vlan_reject_tagged(%u), "
+ "hw_vlan_reject_untagged(%u)",
txmode->hw_vlan_reject_tagged,
txmode->hw_vlan_reject_untagged);
/* Apply vlan offload setting */
- ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
+ mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
+ ret = hns3_vlan_offload_set(dev, mask);
if (ret) {
- hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
+ hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
+ ret);
return ret;
}
+ /*
+ * If pvid config is not set in rte_eth_conf, driver needn't to set
+ * VLAN pvid related configuration to hardware.
+ */
+ if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
+ return 0;
+
/* Apply pvid setting */
ret = hns3_vlan_pvid_set(dev, txmode->pvid,
txmode->hw_vlan_insert_pvid);
if (ret)
- hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
+ hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
txmode->pvid, ret);
return ret;
return hns3_cmd_send(hw, &desc, 1);
}
-int
-hns3_config_gro(struct hns3_hw *hw, bool en)
-{
- struct hns3_cfg_gro_status_cmd *req;
- struct hns3_cmd_desc desc;
- int ret;
-
- hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
- req = (struct hns3_cfg_gro_status_cmd *)desc.data;
-
- req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
-
- ret = hns3_cmd_send(hw, &desc, 1);
- if (ret)
- hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
-
- return ret;
-}
-
static int
hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
uint16_t *allocated_size, bool is_alloc)
struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
struct hns3_mac_vlan_tbl_entry_cmd req;
struct hns3_pf *pf = &hns->pf;
- struct hns3_cmd_desc desc;
+ struct hns3_cmd_desc desc[3];
char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
uint16_t egress_port = 0;
uint8_t vf_id;
/* check if mac addr is valid */
if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
- rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
mac_addr);
hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
mac_str);
/*
* In current version VF is not supported when PF is driven by DPDK
- * driver, the PF-related vf_id is 0, just need to configure parameters
- * for vf_id 0.
+ * driver, just need to configure parameters for PF vport.
*/
- vf_id = 0;
+ vf_id = HNS3_PF_FUNC_ID;
hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
HNS3_MAC_EPORT_VFID_S, vf_id);
* it if the entry is inexistent. Repeated unicast entry
* is not allowed in the mac vlan table.
*/
- ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
+ ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
if (ret == -ENOENT) {
if (!hns3_is_umv_space_full(hw)) {
ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
return -ENOSPC;
}
- rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
/* check if we just hit the duplicate */
if (ret == 0) {
return ret;
}
+static int
+hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
+{
+ char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
+ struct rte_ether_addr *addr;
+ int ret;
+ int i;
+
+ for (i = 0; i < hw->mc_addrs_num; i++) {
+ addr = &hw->mc_addrs[i];
+ /* Check if there are duplicate addresses */
+ if (rte_is_same_ether_addr(addr, mac_addr)) {
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ addr);
+ hns3_err(hw, "failed to add mc mac addr, same addrs"
+ "(%s) is added by the set_mc_mac_addr_list "
+ "API", mac_str);
+ return -EINVAL;
+ }
+ }
+
+ ret = hns3_add_mc_addr(hw, mac_addr);
+ if (ret) {
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ mac_addr);
+ hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
+ mac_str, ret);
+ }
+ return ret;
+}
+
+static int
+hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
+{
+ char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
+ int ret;
+
+ ret = hns3_remove_mc_addr(hw, mac_addr);
+ if (ret) {
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ mac_addr);
+ hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
+ mac_str, ret);
+ }
+ return ret;
+}
+
static int
hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
- uint32_t idx, __attribute__ ((unused)) uint32_t pool)
+ uint32_t idx, __rte_unused uint32_t pool)
{
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
int ret;
rte_spinlock_lock(&hw->lock);
- ret = hns3_add_uc_addr_common(hw, mac_addr);
+
+ /*
+ * In hns3 network engine adding UC and MC mac address with different
+ * commands with firmware. We need to determine whether the input
+ * address is a UC or a MC address to call different commands.
+ * By the way, it is recommended calling the API function named
+ * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
+ * using the rte_eth_dev_mac_addr_add API function to set MC mac address
+ * may affect the specifications of UC mac addresses.
+ */
+ if (rte_is_multicast_ether_addr(mac_addr))
+ ret = hns3_add_mc_addr_common(hw, mac_addr);
+ else
+ ret = hns3_add_uc_addr_common(hw, mac_addr);
+
if (ret) {
rte_spinlock_unlock(&hw->lock);
- rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
mac_addr);
- hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
+ hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
+ ret);
return ret;
}
/* check if mac addr is valid */
if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
- rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
mac_addr);
- hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
+ hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
mac_str);
return -EINVAL;
}
int ret;
rte_spinlock_lock(&hw->lock);
- ret = hns3_remove_uc_addr_common(hw, mac_addr);
+
+ if (rte_is_multicast_ether_addr(mac_addr))
+ ret = hns3_remove_mc_addr_common(hw, mac_addr);
+ else
+ ret = hns3_remove_uc_addr_common(hw, mac_addr);
+ rte_spinlock_unlock(&hw->lock);
if (ret) {
- rte_spinlock_unlock(&hw->lock);
- rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
mac_addr);
- hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
- return;
+ hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
+ ret);
}
-
- if (idx == 0)
- hw->mac.default_addr_setted = false;
- rte_spinlock_unlock(&hw->lock);
}
static int
bool rm_succes = false;
int ret, ret_val;
- /* check if mac addr is valid */
- if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
- rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
- mac_addr);
- hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
- mac_str);
- return -EINVAL;
- }
-
+ /*
+ * It has been guaranteed that input parameter named mac_addr is valid
+ * address in the rte layer of DPDK framework.
+ */
oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
default_addr_setted = hw->mac.default_addr_setted;
if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
if (default_addr_setted) {
ret = hns3_remove_uc_addr_common(hw, oaddr);
if (ret) {
- rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
oaddr);
hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
mac_str, ret);
ret = hns3_add_uc_addr_common(hw, mac_addr);
if (ret) {
- rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
mac_addr);
hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
goto err_add_uc_addr;
err_pause_addr_cfg:
ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
if (ret_val) {
- rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
mac_addr);
hns3_warn(hw,
"Failed to roll back to del setted mac addr(%s): %d",
if (rm_succes) {
ret_val = hns3_add_uc_addr_common(hw, oaddr);
if (ret_val) {
- rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
oaddr);
hns3_warn(hw,
"Failed to restore old uc mac addr(%s): %d",
for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
addr = &hw->data->mac_addrs[i];
- if (!rte_is_valid_assigned_ether_addr(addr))
+ if (rte_is_zero_ether_addr(addr))
continue;
- if (del)
- ret = hns3_remove_uc_addr_common(hw, addr);
+ if (rte_is_multicast_ether_addr(addr))
+ ret = del ? hns3_remove_mc_addr(hw, addr) :
+ hns3_add_mc_addr(hw, addr);
else
- ret = hns3_add_uc_addr_common(hw, addr);
+ ret = del ? hns3_remove_uc_addr_common(hw, addr) :
+ hns3_add_uc_addr_common(hw, addr);
+
if (ret) {
err = ret;
- rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
addr);
- hns3_dbg(hw,
- "Failed to %s mac addr(%s). ret:%d i:%d",
- del ? "remove" : "restore", mac_str, ret, i);
+ hns3_err(hw, "failed to %s mac addr(%s) index:%d "
+ "ret = %d.", del ? "remove" : "restore",
+ mac_str, i, ret);
}
}
return err;
/* Check if mac addr is valid */
if (!rte_is_multicast_ether_addr(mac_addr)) {
- rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
mac_addr);
- hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
+ hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
mac_str);
return -EINVAL;
}
/*
* In current version VF is not supported when PF is driven by DPDK
- * driver, the PF-related vf_id is 0, just need to configure parameters
- * for vf_id 0.
+ * driver, just need to configure parameters for PF vport.
*/
- vf_id = 0;
+ vf_id = HNS3_PF_FUNC_ID;
hns3_update_desc_vfid(desc, vf_id, false);
ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
if (ret) {
if (ret == -ENOSPC)
hns3_err(hw, "mc mac vlan table is full");
- rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
mac_addr);
- hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
+ hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
}
return ret;
/* Check if mac addr is valid */
if (!rte_is_multicast_ether_addr(mac_addr)) {
- rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
mac_addr);
hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
mac_str);
/*
* This mac addr exist, remove this handle's VFID for it.
* In current version VF is not supported when PF is driven by
- * DPDK driver, the PF-related vf_id is 0, just need to
- * configure parameters for vf_id 0.
+ * DPDK driver, just need to configure parameters for PF vport.
*/
- vf_id = 0;
+ vf_id = HNS3_PF_FUNC_ID;
hns3_update_desc_vfid(desc, vf_id, true);
/* All the vfid is zero, so need to delete this entry */
}
if (ret) {
- rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
mac_addr);
hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
}
uint32_t j;
if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
- hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
+ hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
"invalid. valid range: 0~%d",
nb_mc_addr, HNS3_MC_MACADDR_NUM);
return -EINVAL;
for (i = 0; i < nb_mc_addr; i++) {
addr = &mc_addr_set[i];
if (!rte_is_multicast_ether_addr(addr)) {
- rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
addr);
hns3_err(hw,
- "Failed to set mc mac addr, addr(%s) invalid.",
+ "failed to set mc mac addr, addr(%s) invalid.",
mac_str);
return -EINVAL;
}
/* Check if there are duplicate addresses */
for (j = i + 1; j < nb_mc_addr; j++) {
if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
- rte_ether_format_addr(mac_str,
+ hns3_ether_format_addr(mac_str,
RTE_ETHER_ADDR_FMT_SIZE,
addr);
- hns3_err(hw, "Failed to set mc mac addr, "
+ hns3_err(hw, "failed to set mc mac addr, "
"addrs invalid. two same addrs(%s).",
mac_str);
return -EINVAL;
}
}
+
+ /*
+ * Check if there are duplicate addresses between mac_addrs
+ * and mc_addr_set
+ */
+ for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
+ if (rte_is_same_ether_addr(addr,
+ &hw->data->mac_addrs[j])) {
+ hns3_ether_format_addr(mac_str,
+ RTE_ETHER_ADDR_FMT_SIZE,
+ addr);
+ hns3_err(hw, "failed to set mc mac addr, "
+ "addrs invalid. addrs(%s) has already "
+ "configured in mac_addr add API",
+ mac_str);
+ return -EINVAL;
+ }
+ }
}
return 0;
ret = hns3_add_mc_addr(hw, addr);
if (ret) {
err = ret;
- rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
addr);
- hns3_dbg(hw, "%s mc mac addr: %s failed",
- del ? "Remove" : "Restore", mac_str);
+ hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
+ del ? "Remove" : "Restore", mac_str, ret);
}
}
return err;
for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
- hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
+ hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
"is not equal to one in tx direction.",
i, dcb_rx_conf->dcb_tc[i]);
return -EINVAL;
}
static int
-hns3_bind_ring_with_vector(struct rte_eth_dev *dev, uint8_t vector_id,
- bool mmap, uint16_t queue_id)
+hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
+ enum hns3_ring_type queue_type, uint16_t queue_id)
{
- struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct hns3_cmd_desc desc;
struct hns3_ctrl_vector_chain_cmd *req =
(struct hns3_ctrl_vector_chain_cmd *)desc.data;
enum hns3_cmd_status status;
enum hns3_opcode_type op;
uint16_t tqp_type_and_id = 0;
+ const char *op_str;
+ uint16_t type;
+ uint16_t gl;
op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
hns3_cmd_setup_basic_desc(&desc, op, false);
req->int_vector_id = vector_id;
+ if (queue_type == HNS3_RING_TYPE_RX)
+ gl = HNS3_RING_GL_RX;
+ else
+ gl = HNS3_RING_GL_TX;
+
+ type = queue_type;
+
hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
- HNS3_RING_TYPE_RX);
+ type);
hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
- HNS3_RING_GL_RX);
+ gl);
req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
-
req->int_cause_num = 1;
+ op_str = mmap ? "Map" : "Unmap";
status = hns3_cmd_send(hw, &desc, 1);
if (status) {
- hns3_err(hw, "Map TQP %d fail, vector_id is %d, status is %d.",
- queue_id, vector_id, status);
- return -EIO;
+ hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
+ op_str, queue_id, req->int_vector_id, status);
+ return status;
+ }
+
+ return 0;
+}
+
+static int
+hns3_init_ring_with_vector(struct hns3_hw *hw)
+{
+ uint16_t vec;
+ int ret;
+ int i;
+
+ /*
+ * In hns3 network engine, vector 0 is always the misc interrupt of this
+ * function, vector 1~N can be used respectively for the queues of the
+ * function. Tx and Rx queues with the same number share the interrupt
+ * vector. In the initialization clearing the all hardware mapping
+ * relationship configurations between queues and interrupt vectors is
+ * needed, so some error caused by the residual configurations, such as
+ * the unexpected Tx interrupt, can be avoid.
+ */
+ vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
+ if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
+ vec = vec - 1; /* the last interrupt is reserved */
+ hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
+ for (i = 0; i < hw->intr_tqps_num; i++) {
+ /*
+ * Set gap limiter/rate limiter/quanity limiter algorithm
+ * configuration for interrupt coalesce of queue's interrupt.
+ */
+ hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
+ HNS3_TQP_INTR_GL_DEFAULT);
+ hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
+ HNS3_TQP_INTR_GL_DEFAULT);
+ hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
+ /*
+ * QL(quantity limiter) is not used currently, just set 0 to
+ * close it.
+ */
+ hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
+
+ ret = hns3_bind_ring_with_vector(hw, vec, false,
+ HNS3_RING_TYPE_TX, i);
+ if (ret) {
+ PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
+ "vector: %u, ret=%d", i, vec, ret);
+ return ret;
+ }
+
+ ret = hns3_bind_ring_with_vector(hw, vec, false,
+ HNS3_RING_TYPE_RX, i);
+ if (ret) {
+ PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
+ "vector: %u, ret=%d", i, vec, ret);
+ return ret;
+ }
}
return 0;
uint16_t nb_tx_q = dev->data->nb_tx_queues;
struct rte_eth_rss_conf rss_conf;
uint16_t mtu;
+ bool gro_en;
int ret;
+ hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
+
/*
- * Hardware does not support individually enable/disable/reset the Tx or
- * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
- * and Rx queues at the same time. When the numbers of Tx queues
- * allocated by upper applications are not equal to the numbers of Rx
- * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
- * of Tx/Rx queues. otherwise, network engine can not work as usual. But
- * these fake queues are imperceptible, and can not be used by upper
- * applications.
+ * Some versions of hardware network engine does not support
+ * individually enable/disable/reset the Tx or Rx queue. These devices
+ * must enable/disable/reset Tx and Rx queues at the same time. When the
+ * numbers of Tx queues allocated by upper applications are not equal to
+ * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
+ * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
+ * work as usual. But these fake queues are imperceptible, and can not
+ * be used by upper applications.
*/
- ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
- if (ret) {
- hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
- return ret;
+ if (!hns3_dev_indep_txrx_supported(hw)) {
+ ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
+ if (ret) {
+ hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
+ ret);
+ return ret;
+ }
}
hw->adapter_state = HNS3_NIC_CONFIGURING;
/* When RSS is not configured, redirect the packet queue 0 */
if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
+ conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
rss_conf = conf->rx_adv_conf.rss_conf;
+ hw->rss_dis_flag = false;
if (rss_conf.rss_key == NULL) {
rss_conf.rss_key = rss_cfg->key;
rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
if (ret)
goto cfg_err;
+ /* config hardware GRO */
+ gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
+ ret = hns3_config_gro(hw, gro_en);
+ if (ret)
+ goto cfg_err;
+
+ hns->rx_simple_allowed = true;
+ hns->rx_vec_allowed = true;
+ hns->tx_simple_allowed = true;
+ hns->tx_vec_allowed = true;
+
+ hns3_init_rx_ptype_tble(dev);
hw->adapter_state = HNS3_NIC_CONFIGURED;
return 0;
}
ret = hns3_buffer_alloc(hw);
- if (ret) {
+ if (ret)
hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
- return ret;
- }
- return 0;
+ return ret;
}
static int
}
rte_spinlock_lock(&hw->lock);
- is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
+ is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
/*
return 0;
}
-static int
+int
hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
{
struct hns3_adapter *hns = eth_dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
+ uint16_t queue_num = hw->tqps_num;
+
+ /*
+ * In interrupt mode, 'max_rx_queues' is set based on the number of
+ * MSI-X interrupt resources of the hardware.
+ */
+ if (hw->data->dev_conf.intr_conf.rxq == 1)
+ queue_num = hw->intr_tqps_num;
- info->max_rx_queues = hw->tqps_num;
+ info->max_rx_queues = queue_num;
info->max_tx_queues = hw->tqps_num;
info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
- info->min_rx_bufsize = hw->rx_buf_len;
+ info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
+ info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
DEV_RX_OFFLOAD_TCP_CKSUM |
DEV_RX_OFFLOAD_UDP_CKSUM |
DEV_RX_OFFLOAD_KEEP_CRC |
DEV_RX_OFFLOAD_SCATTER |
DEV_RX_OFFLOAD_VLAN_STRIP |
- DEV_RX_OFFLOAD_QINQ_STRIP |
DEV_RX_OFFLOAD_VLAN_FILTER |
- DEV_RX_OFFLOAD_VLAN_EXTEND |
- DEV_RX_OFFLOAD_JUMBO_FRAME);
- info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
+ DEV_RX_OFFLOAD_JUMBO_FRAME |
+ DEV_RX_OFFLOAD_RSS_HASH |
+ DEV_RX_OFFLOAD_TCP_LRO);
info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
DEV_TX_OFFLOAD_IPV4_CKSUM |
DEV_TX_OFFLOAD_TCP_CKSUM |
DEV_TX_OFFLOAD_UDP_CKSUM |
DEV_TX_OFFLOAD_SCTP_CKSUM |
- DEV_TX_OFFLOAD_VLAN_INSERT |
- DEV_TX_OFFLOAD_QINQ_INSERT |
DEV_TX_OFFLOAD_MULTI_SEGS |
- info->tx_queue_offload_capa);
+ DEV_TX_OFFLOAD_TCP_TSO |
+ DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
+ DEV_TX_OFFLOAD_GRE_TNL_TSO |
+ DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
+ DEV_TX_OFFLOAD_MBUF_FAST_FREE |
+ hns3_txvlan_cap_get(hw));
+
+ if (hns3_dev_indep_txrx_supported(hw))
+ info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
+ RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
info->rx_desc_lim = (struct rte_eth_desc_lim) {
.nb_max = HNS3_MAX_RING_DESC,
.nb_max = HNS3_MAX_RING_DESC,
.nb_min = HNS3_MIN_RING_DESC,
.nb_align = HNS3_ALIGN_RING_DESC,
+ .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
+ .nb_mtu_seg_max = hw->max_non_tso_bd_num,
+ };
+
+ info->default_rxconf = (struct rte_eth_rxconf) {
+ .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
+ /*
+ * If there are no available Rx buffer descriptors, incoming
+ * packets are always dropped by hardware based on hns3 network
+ * engine.
+ */
+ .rx_drop_en = 1,
+ .offloads = 0,
+ };
+ info->default_txconf = (struct rte_eth_txconf) {
+ .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
+ .offloads = 0,
};
info->vmdq_queue_num = 0;
{
struct hns3_adapter *hns = eth_dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
+ uint32_t version = hw->fw_version;
int ret;
- ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
+ ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
+ hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
+ HNS3_FW_VERSION_BYTE3_S),
+ hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
+ HNS3_FW_VERSION_BYTE2_S),
+ hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
+ HNS3_FW_VERSION_BYTE1_S),
+ hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
+ HNS3_FW_VERSION_BYTE0_S));
ret += 1; /* add the size of '\0' */
if (fw_size < (uint32_t)ret)
return ret;
case ETH_SPEED_NUM_40G:
case ETH_SPEED_NUM_50G:
case ETH_SPEED_NUM_100G:
+ case ETH_SPEED_NUM_200G:
new_link.link_speed = mac->link_speed;
break;
default:
}
static int
-hns3_query_pf_resource(struct hns3_hw *hw)
+hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
{
struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
struct hns3_pf *pf = &hns->pf;
- struct hns3_pf_res_cmd *req;
- struct hns3_cmd_desc desc;
- int ret;
- hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
- ret = hns3_cmd_send(hw, &desc, 1);
+ if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
+ /*
+ * The total_tqps_num obtained from firmware is maximum tqp
+ * numbers of this port, which should be used for PF and VFs.
+ * There is no need for pf to have so many tqp numbers in
+ * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
+ * coming from config file, is assigned to maximum queue number
+ * for the PF of this port by user. So users can modify the
+ * maximum queue number of PF according to their own application
+ * scenarios, which is more flexible to use. In addition, many
+ * memories can be saved due to allocating queue statistics
+ * room according to the actual number of queues required. The
+ * maximum queue number of PF for network engine with
+ * revision_id greater than 0x30 is assigned by config file.
+ */
+ if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
+ hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
+ "must be greater than 0.",
+ RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
+ return -EINVAL;
+ }
+
+ hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
+ hw->total_tqps_num);
+ } else {
+ /*
+ * Due to the limitation on the number of PF interrupts
+ * available, the maximum queue number assigned to PF on
+ * the network engine with revision_id 0x21 is 64.
+ */
+ hw->tqps_num = RTE_MIN(hw->total_tqps_num,
+ HNS3_MAX_TQP_NUM_HIP08_PF);
+ }
+
+ return 0;
+}
+
+static int
+hns3_query_pf_resource(struct hns3_hw *hw)
+{
+ struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
+ struct hns3_pf *pf = &hns->pf;
+ struct hns3_pf_res_cmd *req;
+ struct hns3_cmd_desc desc;
+ int ret;
+
+ hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
+ ret = hns3_cmd_send(hw, &desc, 1);
if (ret) {
PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
return ret;
}
req = (struct hns3_pf_res_cmd *)desc.data;
- hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
+ hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
+ rte_le_to_cpu_16(req->ext_tqp_num);
+ ret = hns3_get_pf_max_tqp_num(hw);
+ if (ret)
+ return ret;
+
pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
- hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
if (req->tx_buf_size)
pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
hw->num_msi =
- hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
- HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
+ hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
+ HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
return 0;
}
{
struct hns3_cfg_param_cmd *req;
uint64_t mac_addr_tmp_high;
+ uint8_t ext_rss_size_max;
uint64_t mac_addr_tmp;
uint32_t i;
HNS3_CFG_UMV_TBL_SPACE_S);
if (!cfg->umv_space)
cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
+
+ ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
+ HNS3_CFG_EXT_RSS_SIZE_M,
+ HNS3_CFG_EXT_RSS_SIZE_S);
+
+ /*
+ * Field ext_rss_size_max obtained from firmware will be more flexible
+ * for future changes and expansions, which is an exponent of 2, instead
+ * of reading out directly. If this field is not zero, hns3 PF PMD
+ * driver uses it as rss_size_max under one TC. Device, whose revision
+ * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
+ * maximum number of queues supported under a TC through this field.
+ */
+ if (ext_rss_size_max)
+ cfg->rss_size_max = 1U << ext_rss_size_max;
}
/* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
case HNS3_CFG_SPEED_100G:
*speed = ETH_SPEED_NUM_100G;
break;
+ case HNS3_CFG_SPEED_200G:
+ *speed = ETH_SPEED_NUM_200G;
+ break;
default:
return -EINVAL;
}
return 0;
}
+static void
+hns3_set_default_dev_specifications(struct hns3_hw *hw)
+{
+ hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
+ hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
+ hw->rss_key_size = HNS3_RSS_KEY_SIZE;
+ hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
+ hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
+}
+
+static void
+hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
+{
+ struct hns3_dev_specs_0_cmd *req0;
+
+ req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
+
+ hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
+ hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
+ hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
+ hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
+ hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
+}
+
+static int
+hns3_query_dev_specifications(struct hns3_hw *hw)
+{
+ struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
+ int ret;
+ int i;
+
+ for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
+ hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
+ true);
+ desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
+ }
+ hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
+
+ ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
+ if (ret)
+ return ret;
+
+ hns3_parse_dev_specifications(hw, desc);
+
+ return 0;
+}
+
+static int
+hns3_get_capability(struct hns3_hw *hw)
+{
+ struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
+ struct rte_pci_device *pci_dev;
+ struct hns3_pf *pf = &hns->pf;
+ struct rte_eth_dev *eth_dev;
+ uint16_t device_id;
+ uint8_t revision;
+ int ret;
+
+ eth_dev = &rte_eth_devices[hw->data->port_id];
+ pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
+ device_id = pci_dev->id.device_id;
+
+ if (device_id == HNS3_DEV_ID_25GE_RDMA ||
+ device_id == HNS3_DEV_ID_50GE_RDMA ||
+ device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
+ device_id == HNS3_DEV_ID_200G_RDMA)
+ hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
+
+ /* Get PCI revision id */
+ ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
+ HNS3_PCI_REVISION_ID);
+ if (ret != HNS3_PCI_REVISION_ID_LEN) {
+ PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
+ ret);
+ return -EIO;
+ }
+ hw->revision = revision;
+
+ if (revision < PCI_REVISION_ID_HIP09_A) {
+ hns3_set_default_dev_specifications(hw);
+ hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
+ hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
+ hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
+ hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
+ hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
+ pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
+ hw->rss_info.ipv6_sctp_offload_supported = false;
+ return 0;
+ }
+
+ ret = hns3_query_dev_specifications(hw);
+ if (ret) {
+ PMD_INIT_LOG(ERR,
+ "failed to query dev specifications, ret = %d",
+ ret);
+ return ret;
+ }
+
+ hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
+ hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
+ hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
+ hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
+ hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
+ pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
+ hw->rss_info.ipv6_sctp_offload_supported = true;
+
+ return 0;
+}
+
static int
hns3_get_board_configuration(struct hns3_hw *hw)
{
return ret;
}
- if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
+ if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
+ !hns3_dev_copper_supported(hw)) {
PMD_INIT_LOG(ERR, "media type is copper, not supported.");
return -EOPNOTSUPP;
}
hw->mac.media_type = cfg.media_type;
hw->rss_size_max = cfg.rss_size_max;
- hw->rx_buf_len = cfg.rx_buf_len;
+ hw->rss_dis_flag = false;
memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
hw->mac.phy_addr = cfg.phy_addr;
hw->mac.default_addr_setted = false;
ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
if (ret) {
- PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
+ PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
cfg.default_speed, ret);
return ret;
}
return ret;
}
+ /* Get device capability */
+ ret = hns3_get_capability(hw);
+ if (ret) {
+ PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
+ return ret;
+ }
+
/* Get pf resource */
ret = hns3_query_pf_resource(hw);
if (ret) {
ret = hns3_get_board_configuration(hw);
if (ret) {
- PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
+ PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
return ret;
}
- return 0;
+ ret = hns3_query_dev_fec_info(hw);
+ if (ret)
+ PMD_INIT_LOG(ERR,
+ "failed to query FEC information, ret = %d", ret);
+
+ return ret;
}
static int
static int
hns3_map_tqp(struct hns3_hw *hw)
{
- uint16_t tqps_num = hw->total_tqps_num;
- uint16_t func_id;
- uint16_t tqp_id;
- bool is_pf;
- int num;
int ret;
int i;
/*
- * In current version VF is not supported when PF is driven by DPDK
- * driver, so we allocate tqps to PF as much as possible.
+ * In current version, VF is not supported when PF is driven by DPDK
+ * driver, so we assign total tqps_num tqps allocated to this port
+ * to PF.
*/
- tqp_id = 0;
- num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
- for (func_id = 0; func_id < num; func_id++) {
- is_pf = func_id == 0 ? true : false;
- for (i = 0;
- i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
- ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
- is_pf);
- if (ret)
- return ret;
- }
+ for (i = 0; i < hw->total_tqps_num; i++) {
+ ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
+ if (ret)
+ return ret;
}
return 0;
hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
break;
+ case ETH_SPEED_NUM_200G:
+ hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
+ HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
+ break;
default:
PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
return -EINVAL;
+ pf->dv_buf_size;
shared_buf_tc = tc_num * aligned_mps + aligned_mps;
- shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
+ shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
HNS3_BUF_SIZE_UNIT);
rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
hi_thrd = shared_buf - pf->dv_buf_size;
if (tc_num <= NEED_RESERVE_TC_NUM)
- hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
- / BUF_MAX_PERCENT;
+ hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
+ BUF_MAX_PERCENT;
if (tc_num)
hi_thrd = hi_thrd / tc_num;
- hi_thrd = max_t(uint32_t, hi_thrd,
- HNS3_BUF_MUL_BY * aligned_mps);
+ hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
} else {
for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
priv = &buf_alloc->priv_buf[i];
mask = BIT((uint8_t)i);
-
- if (hw->hw_tc_map & mask &&
- hw->dcb_info.hw_pfc_map & mask) {
+ if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
/* Reduce the number of pfc TC with private buffer */
priv->wl.low = 0;
priv->enable = 0;
for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
priv = &buf_alloc->priv_buf[i];
-
priv->enable = 0;
priv->wl.low = 0;
priv->wl.high = 0;
if (cmdq_resp) {
PMD_INIT_LOG(ERR,
- "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
+ "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
cmdq_resp);
return -EIO;
}
break;
default:
PMD_INIT_LOG(ERR,
- "add mac ethertype failed for undefined, code=%d.",
+ "add mac ethertype failed for undefined, code=%u.",
resp_code);
return_status = -EIO;
+ break;
}
return return_status;
ret = hns3_cmd_send(hw, &desc, 1);
if (ret)
- PMD_INIT_LOG(ERR, "Set promisc mode fail, status is %d", ret);
+ PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
return ret;
}
struct hns3_promisc_param param;
bool en_bc_pmc = true;
uint8_t vf_id;
- int ret;
/*
* In current version VF is not supported when PF is driven by DPDK
- * driver, the PF-related vf_id is 0, just need to configure parameters
- * for vf_id 0.
+ * driver, just need to configure parameters for PF vport.
*/
- vf_id = 0;
+ vf_id = HNS3_PF_FUNC_ID;
hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
- ret = hns3_cmd_set_promisc_mode(hw, ¶m);
- if (ret)
- return ret;
-
- return 0;
+ return hns3_cmd_set_promisc_mode(hw, ¶m);
}
static int
-hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
+hns3_promisc_init(struct hns3_hw *hw)
{
struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
struct hns3_pf *pf = &hns->pf;
uint16_t func_id;
int ret;
- /* func_id 0 is denoted PF, the VFs start from 1 */
- for (func_id = 1; func_id < pf->func_num; func_id++) {
+ ret = hns3_set_promisc_mode(hw, false, false);
+ if (ret) {
+ PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
+ return ret;
+ }
+
+ /*
+ * In current version VFs are not supported when PF is driven by DPDK
+ * driver. After PF has been taken over by DPDK, the original VF will
+ * be invalid. So, there is a possibility of entry residues. It should
+ * clear VFs's promisc mode to avoid unnecessary bandwidth usage
+ * during init.
+ */
+ for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
hns3_promisc_param_init(¶m, false, false, false, func_id);
ret = hns3_cmd_set_promisc_mode(hw, ¶m);
- if (ret)
+ if (ret) {
+ PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
+ " ret = %d", func_id, ret);
return ret;
+ }
}
return 0;
}
+static void
+hns3_promisc_uninit(struct hns3_hw *hw)
+{
+ struct hns3_promisc_param param;
+ uint16_t func_id;
+ int ret;
+
+ func_id = HNS3_PF_FUNC_ID;
+
+ /*
+ * In current version VFs are not supported when PF is driven by
+ * DPDK driver, and VFs' promisc mode status has been cleared during
+ * init and their status will not change. So just clear PF's promisc
+ * mode status during uninit.
+ */
+ hns3_promisc_param_init(¶m, false, false, false, func_id);
+ ret = hns3_cmd_set_promisc_mode(hw, ¶m);
+ if (ret)
+ PMD_INIT_LOG(ERR, "failed to clear promisc status during"
+ " uninit, ret = %d", ret);
+}
+
static int
hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
{
+ bool allmulti = dev->data->all_multicast ? true : false;
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
- bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false;
+ uint64_t offloads;
+ int err;
int ret;
rte_spinlock_lock(&hw->lock);
- ret = hns3_set_promisc_mode(hw, true, en_mc_pmc);
+ ret = hns3_set_promisc_mode(hw, true, true);
+ if (ret) {
+ rte_spinlock_unlock(&hw->lock);
+ hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
+ ret);
+ return ret;
+ }
+
+ /*
+ * When promiscuous mode was enabled, disable the vlan filter to let
+ * all packets coming in in the receiving direction.
+ */
+ offloads = dev->data->dev_conf.rxmode.offloads;
+ if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
+ ret = hns3_enable_vlan_filter(hns, false);
+ if (ret) {
+ hns3_err(hw, "failed to enable promiscuous mode due to "
+ "failure to disable vlan filter, ret = %d",
+ ret);
+ err = hns3_set_promisc_mode(hw, false, allmulti);
+ if (err)
+ hns3_err(hw, "failed to restore promiscuous "
+ "status after disable vlan filter "
+ "failed during enabling promiscuous "
+ "mode, ret = %d", ret);
+ }
+ }
+
rte_spinlock_unlock(&hw->lock);
- if (ret)
- hns3_err(hw, "Failed to enable promiscuous mode: %d", ret);
return ret;
}
static int
hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
{
+ bool allmulti = dev->data->all_multicast ? true : false;
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
- bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false;
+ uint64_t offloads;
+ int err;
int ret;
/* If now in all_multicast mode, must remain in all_multicast mode. */
rte_spinlock_lock(&hw->lock);
- ret = hns3_set_promisc_mode(hw, false, en_mc_pmc);
+ ret = hns3_set_promisc_mode(hw, false, allmulti);
+ if (ret) {
+ rte_spinlock_unlock(&hw->lock);
+ hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
+ ret);
+ return ret;
+ }
+ /* when promiscuous mode was disabled, restore the vlan filter status */
+ offloads = dev->data->dev_conf.rxmode.offloads;
+ if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
+ ret = hns3_enable_vlan_filter(hns, true);
+ if (ret) {
+ hns3_err(hw, "failed to disable promiscuous mode due to"
+ " failure to restore vlan filter, ret = %d",
+ ret);
+ err = hns3_set_promisc_mode(hw, true, true);
+ if (err)
+ hns3_err(hw, "failed to restore promiscuous "
+ "status after enabling vlan filter "
+ "failed during disabling promiscuous "
+ "mode, ret = %d", ret);
+ }
+ }
rte_spinlock_unlock(&hw->lock);
- if (ret)
- hns3_err(hw, "Failed to disable promiscuous mode: %d", ret);
return ret;
}
{
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
- bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false;
int ret;
+ if (dev->data->promiscuous)
+ return 0;
+
rte_spinlock_lock(&hw->lock);
- ret = hns3_set_promisc_mode(hw, en_uc_pmc, true);
+ ret = hns3_set_promisc_mode(hw, false, true);
rte_spinlock_unlock(&hw->lock);
if (ret)
- hns3_err(hw, "Failed to enable allmulticast mode: %d", ret);
+ hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
+ ret);
return ret;
}
{
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
- bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false;
int ret;
/* If now in promiscuous mode, must remain in all_multicast mode. */
- if (dev->data->promiscuous == 1)
+ if (dev->data->promiscuous)
return 0;
rte_spinlock_lock(&hw->lock);
- ret = hns3_set_promisc_mode(hw, en_uc_pmc, false);
+ ret = hns3_set_promisc_mode(hw, false, false);
rte_spinlock_unlock(&hw->lock);
if (ret)
- hns3_err(hw, "Failed to disable allmulticast mode: %d", ret);
+ hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
+ ret);
return ret;
}
hns3_dev_promisc_restore(struct hns3_adapter *hns)
{
struct hns3_hw *hw = &hns->hw;
- bool en_mc_pmc;
- bool en_uc_pmc;
+ bool allmulti = hw->data->all_multicast ? true : false;
+ int ret;
- en_uc_pmc = (hw->data->promiscuous == 1) ? true : false;
- en_mc_pmc = (hw->data->all_multicast == 1) ? true : false;
+ if (hw->data->promiscuous) {
+ ret = hns3_set_promisc_mode(hw, true, true);
+ if (ret)
+ hns3_err(hw, "failed to restore promiscuous mode, "
+ "ret = %d", ret);
+ return ret;
+ }
- return hns3_set_promisc_mode(hw, en_uc_pmc, en_mc_pmc);
+ ret = hns3_set_promisc_mode(hw, false, allmulti);
+ if (ret)
+ hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
+ ret);
+ return ret;
}
static int
hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
{
struct hns3_mac *mac = &hw->mac;
+ uint32_t cur_speed = mac->link_speed;
int ret;
duplex = hns3_check_speed_dup(duplex, speed);
return ret;
mac->link_speed = speed;
+ ret = hns3_dcb_port_shaper_cfg(hw);
+ if (ret) {
+ hns3_err(hw, "failed to configure port shaper, ret = %d.", ret);
+ mac->link_speed = cur_speed;
+ return ret;
+ }
+
mac->link_duplex = duplex;
return 0;
hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
- hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
+
+ /*
+ * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
+ * when receiving frames. Otherwise, CRC will be stripped.
+ */
+ if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
+ hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
+ else
+ hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
goto err_mac_init;
}
- ret = hns3_set_promisc_mode(hw, false, false);
- if (ret) {
- PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
- goto err_mac_init;
- }
-
- ret = hns3_clear_all_vfs_promisc_mode(hw);
+ ret = hns3_promisc_init(hw);
if (ret) {
- PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
+ PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
ret);
goto err_mac_init;
}
PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
goto err_mac_init;
}
+
+ /*
+ * In the initialization clearing the all hardware mapping relationship
+ * configurations between queues and interrupt vectors is needed, so
+ * some error caused by the residual configurations, such as the
+ * unexpected interrupt, can be avoid.
+ */
+ ret = hns3_init_ring_with_vector(hw);
+ if (ret) {
+ PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
+ goto err_mac_init;
+ }
+
return 0;
err_mac_init:
return ret;
}
+static int
+hns3_clear_hw(struct hns3_hw *hw)
+{
+ struct hns3_cmd_desc desc;
+ int ret;
+
+ hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
+
+ ret = hns3_cmd_send(hw, &desc, 1);
+ if (ret && ret != -EOPNOTSUPP)
+ return ret;
+
+ return 0;
+}
+
+static void
+hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
+{
+ uint32_t val;
+
+ /*
+ * The new firmware support report more hardware error types by
+ * msix mode. These errors are defined as RAS errors in hardware
+ * and belong to a different type from the MSI-x errors processed
+ * by the network driver.
+ *
+ * Network driver should open the new error report on initialition
+ */
+ val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
+ hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
+ hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
+}
+
static int
hns3_init_pf(struct rte_eth_dev *eth_dev)
{
goto err_cmd_init;
}
+ /*
+ * To ensure that the hardware environment is clean during
+ * initialization, the driver actively clear the hardware environment
+ * during initialization, including PF and corresponding VFs' vlan, mac,
+ * flow table configurations, etc.
+ */
+ ret = hns3_clear_hw(hw);
+ if (ret) {
+ PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
+ goto err_cmd_init;
+ }
+
+ hns3_config_all_msix_error(hw, true);
+
ret = rte_intr_callback_register(&pci_dev->intr_handle,
hns3_interrupt_handler,
eth_dev);
goto err_get_config;
}
+ ret = hns3_tqp_stats_init(hw);
+ if (ret)
+ goto err_get_config;
+
ret = hns3_init_hardware(hns);
if (ret) {
PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
- goto err_get_config;
+ goto err_init_hw;
}
/* Initialize flow director filter list & hash */
ret = hns3_fdir_filter_init(hns);
if (ret) {
PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
- goto err_hw_init;
+ goto err_fdir;
}
hns3_set_default_rss_args(hw);
if (ret) {
PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
ret);
- goto err_fdir;
+ goto err_enable_intr;
}
+ hns3_tm_conf_init(eth_dev);
+
return 0;
-err_fdir:
+err_enable_intr:
hns3_fdir_filter_uninit(hns);
-err_hw_init:
+err_fdir:
hns3_uninit_umv_space(hw);
-
+err_init_hw:
+ hns3_tqp_stats_uninit(hw);
err_get_config:
hns3_pf_disable_irq0(hw);
rte_intr_disable(&pci_dev->intr_handle);
hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
eth_dev);
-
err_intr_callback_register:
- hns3_cmd_uninit(hw);
-
err_cmd_init:
+ hns3_cmd_uninit(hw);
hns3_cmd_destroy_queue(hw);
-
err_cmd_init_queue:
hw->io_base = NULL;
PMD_INIT_FUNC_TRACE();
+ hns3_tm_conf_uninit(eth_dev);
hns3_enable_hw_error_intr(hns, false);
hns3_rss_uninit(hns);
+ (void)hns3_config_gro(hw, false);
+ hns3_promisc_uninit(hw);
hns3_fdir_filter_uninit(hns);
hns3_uninit_umv_space(hw);
+ hns3_tqp_stats_uninit(hw);
hns3_pf_disable_irq0(hw);
rte_intr_disable(&pci_dev->intr_handle);
hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
eth_dev);
+ hns3_config_all_msix_error(hw, false);
hns3_cmd_uninit(hw);
hns3_cmd_destroy_queue(hw);
hw->io_base = NULL;
if (ret)
return ret;
- /* Enable queues */
- ret = hns3_start_queues(hns, reset_queue);
+ /*
+ * The hns3_dcb_cfg_update may configure TM module, so
+ * hns3_tm_conf_update must called later.
+ */
+ ret = hns3_tm_conf_update(hw);
+ if (ret) {
+ PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
+ return ret;
+ }
+
+ ret = hns3_init_queues(hns, reset_queue);
if (ret) {
- PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
+ PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
return ret;
}
- /* Enable MAC */
ret = hns3_cfg_mac_mode(hw, true);
if (ret) {
- PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
+ PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
goto err_config_mac_mode;
}
return 0;
err_config_mac_mode:
- hns3_stop_queues(hns, true);
+ hns3_dev_release_mbufs(hns);
+ /*
+ * Here is exception handling, hns3_reset_all_tqps will have the
+ * corresponding error message if it is handled incorrectly, so it is
+ * not necessary to check hns3_reset_all_tqps return value, here keep
+ * ret as the error code causing the exception.
+ */
+ (void)hns3_reset_all_tqps(hns);
return ret;
}
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
+ uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
uint32_t intr_vector;
- uint8_t base = 0;
- uint8_t vec = 0;
uint16_t q_id;
int ret;
rte_zmalloc("intr_vec",
hw->used_rx_queues * sizeof(int), 0);
if (intr_handle->intr_vec == NULL) {
- hns3_err(hw, "Failed to allocate %d rx_queues"
+ hns3_err(hw, "Failed to allocate %u rx_queues"
" intr_vec", hw->used_rx_queues);
ret = -ENOMEM;
goto alloc_intr_vec_error;
}
if (rte_intr_dp_is_en(intr_handle)) {
for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
- ret = hns3_bind_ring_with_vector(dev, vec, true, q_id);
+ ret = hns3_bind_ring_with_vector(hw, vec, true,
+ HNS3_RING_TYPE_RX,
+ q_id);
if (ret)
goto bind_vector_error;
intr_handle->intr_vec[q_id] = vec;
}
static int
-hns3_dev_start(struct rte_eth_dev *dev)
+hns3_restore_rx_interrupt(struct hns3_hw *hw)
{
- struct hns3_adapter *hns = dev->data->dev_private;
- struct hns3_hw *hw = &hns->hw;
+ struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
+ struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
+ struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ uint16_t q_id;
int ret;
- PMD_INIT_FUNC_TRACE();
- if (rte_atomic16_read(&hw->reset.resetting))
- return -EBUSY;
-
- rte_spinlock_lock(&hw->lock);
- hw->adapter_state = HNS3_NIC_STARTING;
+ if (dev->data->dev_conf.intr_conf.rxq == 0)
+ return 0;
- ret = hns3_do_start(hns, true);
+ if (rte_intr_dp_is_en(intr_handle)) {
+ for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
+ ret = hns3_bind_ring_with_vector(hw,
+ intr_handle->intr_vec[q_id], true,
+ HNS3_RING_TYPE_RX, q_id);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static void
+hns3_restore_filter(struct rte_eth_dev *dev)
+{
+ hns3_restore_rss_filter(dev);
+}
+
+static int
+hns3_dev_start(struct rte_eth_dev *dev)
+{
+ struct hns3_adapter *hns = dev->data->dev_private;
+ struct hns3_hw *hw = &hns->hw;
+ int ret;
+
+ PMD_INIT_FUNC_TRACE();
+ if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
+ return -EBUSY;
+
+ rte_spinlock_lock(&hw->lock);
+ hw->adapter_state = HNS3_NIC_STARTING;
+
+ ret = hns3_do_start(hns, true);
+ if (ret) {
+ hw->adapter_state = HNS3_NIC_CONFIGURED;
+ rte_spinlock_unlock(&hw->lock);
+ return ret;
+ }
+ ret = hns3_map_rx_interrupt(dev);
if (ret) {
hw->adapter_state = HNS3_NIC_CONFIGURED;
rte_spinlock_unlock(&hw->lock);
return ret;
}
+ /*
+ * There are three register used to control the status of a TQP
+ * (contains a pair of Tx queue and Rx queue) in the new version network
+ * engine. One is used to control the enabling of Tx queue, the other is
+ * used to control the enabling of Rx queue, and the last is the master
+ * switch used to control the enabling of the tqp. The Tx register and
+ * TQP register must be enabled at the same time to enable a Tx queue.
+ * The same applies to the Rx queue. For the older network engine, this
+ * function only refresh the enabled flag, and it is used to update the
+ * status of queue in the dpdk framework.
+ */
+ ret = hns3_start_all_txqs(dev);
+ if (ret) {
+ hw->adapter_state = HNS3_NIC_CONFIGURED;
+ rte_spinlock_unlock(&hw->lock);
+ return ret;
+ }
+
+ ret = hns3_start_all_rxqs(dev);
+ if (ret) {
+ hns3_stop_all_txqs(dev);
+ hw->adapter_state = HNS3_NIC_CONFIGURED;
+ rte_spinlock_unlock(&hw->lock);
+ return ret;
+ }
+
hw->adapter_state = HNS3_NIC_STARTED;
rte_spinlock_unlock(&hw->lock);
- ret = hns3_map_rx_interrupt(dev);
- if (ret)
- return ret;
+ hns3_rx_scattered_calc(dev);
hns3_set_rxtx_function(dev);
hns3_mp_req_start_rxtx(dev);
rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
+ hns3_restore_filter(dev);
+
+ /* Enable interrupt of all rx queues before enabling queues */
+ hns3_dev_all_rx_queue_intr_enable(hw, true);
+
+ /*
+ * After finished the initialization, enable tqps to receive/transmit
+ * packets and refresh all queue status.
+ */
+ hns3_start_tqps(hw);
+
+ hns3_tm_dev_start_proc(hw);
+
hns3_info(hw, "hns3 dev start successful!");
return 0;
}
hns3_do_stop(struct hns3_adapter *hns)
{
struct hns3_hw *hw = &hns->hw;
- bool reset_queue;
int ret;
ret = hns3_cfg_mac_mode(hw, false);
if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
hns3_configure_all_mac_addr(hns, true);
- reset_queue = true;
- } else
- reset_queue = false;
+ ret = hns3_reset_all_tqps(hns);
+ if (ret) {
+ hns3_err(hw, "failed to reset all queues ret = %d.",
+ ret);
+ return ret;
+ }
+ }
hw->mac.default_addr_setted = false;
- return hns3_stop_queues(hns, reset_queue);
+ return 0;
}
static void
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
- uint8_t base = 0;
- uint8_t vec = 0;
+ uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
+ uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
uint16_t q_id;
if (dev->data->dev_conf.intr_conf.rxq == 0)
}
if (rte_intr_dp_is_en(intr_handle)) {
for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
- (void)hns3_bind_ring_with_vector(dev, vec, false, q_id);
+ (void)hns3_bind_ring_with_vector(hw, vec, false,
+ HNS3_RING_TYPE_RX,
+ q_id);
if (vec < base + intr_handle->nb_efd - 1)
vec++;
}
}
}
-static void
+static int
hns3_dev_stop(struct rte_eth_dev *dev)
{
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
PMD_INIT_FUNC_TRACE();
+ dev->data->dev_started = 0;
hw->adapter_state = HNS3_NIC_STOPPING;
hns3_set_rxtx_function(dev);
rte_delay_ms(hw->tqps_num);
rte_spinlock_lock(&hw->lock);
- if (rte_atomic16_read(&hw->reset.resetting) == 0) {
+ if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
+ hns3_tm_dev_stop_proc(hw);
+ hns3_stop_tqps(hw);
hns3_do_stop(hns);
+ hns3_unmap_rx_interrupt(dev);
hns3_dev_release_mbufs(hns);
hw->adapter_state = HNS3_NIC_CONFIGURED;
}
+ hns3_rx_scattered_reset(dev);
rte_eal_alarm_cancel(hns3_service_handler, dev);
rte_spinlock_unlock(&hw->lock);
- hns3_unmap_rx_interrupt(dev);
+
+ return 0;
}
-static void
+static int
hns3_dev_close(struct rte_eth_dev *eth_dev)
{
struct hns3_adapter *hns = eth_dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
+ int ret = 0;
if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
rte_free(eth_dev->process_private);
eth_dev->process_private = NULL;
- return;
+ return 0;
}
if (hw->adapter_state == HNS3_NIC_STARTED)
- hns3_dev_stop(eth_dev);
+ ret = hns3_dev_stop(eth_dev);
hw->adapter_state = HNS3_NIC_CLOSING;
hns3_reset_abort(hns);
rte_free(eth_dev->process_private);
eth_dev->process_private = NULL;
hns3_mp_uninit_primary();
- hns3_warn(hw, "Close port %d finished", hw->data->port_id);
+ hns3_warn(hw, "Close port %u finished", hw->data->port_id);
+
+ return ret;
}
static int
return -EINVAL;
}
if (!fc_conf->pause_time) {
- hns3_err(hw, "Invalid pause time %d setting.",
+ hns3_err(hw, "Invalid pause time %u setting.",
fc_conf->pause_time);
return -EINVAL;
}
return -EINVAL;
}
if (pfc_conf->fc.pause_time == 0) {
- hns3_err(hw, "Invalid pause time %d setting.",
+ hns3_err(hw, "Invalid pause time %u setting.",
pfc_conf->fc.pause_time);
return -EINVAL;
}
return ret;
}
- ret = hns3_reset_all_queues(hns);
+ ret = hns3_reset_all_tqps(hns);
if (ret) {
hns3_err(hw, "Failed to reset all queues: %d", ret);
- goto err_init;
+ return ret;
}
ret = hns3_init_hardware(hns);
if (ret) {
hns3_err(hw, "Failed to init hardware: %d", ret);
- goto err_init;
+ return ret;
}
ret = hns3_enable_hw_error_intr(hns, true);
if (ret) {
hns3_err(hw, "fail to enable hw error interrupts: %d",
ret);
- goto err_mac_init;
+ return ret;
}
hns3_info(hw, "Reset done, driver initialization finished.");
return 0;
-
-err_mac_init:
- hns3_uninit_umv_space(hw);
-err_init:
- hns3_cmd_uninit(hw);
-
- return ret;
}
static bool
return reset_level;
}
+static void
+hns3_record_imp_error(struct hns3_adapter *hns)
+{
+ struct hns3_hw *hw = &hns->hw;
+ uint32_t reg_val;
+
+ reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
+ if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
+ hns3_warn(hw, "Detected IMP RD poison!");
+ hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
+ hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
+ hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
+ }
+
+ if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
+ hns3_warn(hw, "Detected IMP CMDQ error!");
+ hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
+ hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
+ hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
+ }
+}
+
static int
hns3_prepare_reset(struct hns3_adapter *hns)
{
switch (hw->reset.level) {
case HNS3_FUNC_RESET:
- ret = hns3_func_reset_cmd(hw, 0);
+ ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
if (ret)
return ret;
hw->reset.stats.request_cnt++;
break;
case HNS3_IMP_RESET:
+ hns3_record_imp_error(hns);
reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
rte_spinlock_lock(&hw->lock);
if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
hw->adapter_state == HNS3_NIC_STOPPING) {
+ hns3_enable_all_queues(hw, false);
hns3_do_stop(hns);
hw->reset.mbuf_deferred_free = true;
} else
eth_dev = &rte_eth_devices[hw->data->port_id];
hns3_set_rxtx_function(eth_dev);
hns3_mp_req_start_rxtx(eth_dev);
- if (hw->adapter_state == HNS3_NIC_STARTED)
+ if (hw->adapter_state == HNS3_NIC_STARTED) {
hns3_service_handler(eth_dev);
+ /* Enable interrupt of all rx queues before enabling queues */
+ hns3_dev_all_rx_queue_intr_enable(hw, true);
+ /*
+ * Enable state of each rxq and txq will be recovered after
+ * reset, so we need to restore them before enable all tqps;
+ */
+ hns3_restore_tqp_enable_state(hw);
+ /*
+ * When finished the initialization, enable queues to receive
+ * and transmit packets.
+ */
+ hns3_enable_all_queues(hw, true);
+ }
+
return 0;
}
if (ret)
goto err_promisc;
+ ret = hns3_restore_rx_interrupt(hw);
+ if (ret)
+ goto err_promisc;
+
+ ret = hns3_restore_gro_conf(hw);
+ if (ret)
+ goto err_promisc;
+
+ ret = hns3_restore_fec(hw);
+ if (ret)
+ goto err_promisc;
+
if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
ret = hns3_do_start(hns, false);
if (ret)
hns3_msix_process(hns, reset_level);
}
+static unsigned int
+hns3_get_speed_capa_num(uint16_t device_id)
+{
+ unsigned int num;
+
+ switch (device_id) {
+ case HNS3_DEV_ID_25GE:
+ case HNS3_DEV_ID_25GE_RDMA:
+ num = 2;
+ break;
+ case HNS3_DEV_ID_100G_RDMA_MACSEC:
+ case HNS3_DEV_ID_200G_RDMA:
+ num = 1;
+ break;
+ default:
+ num = 0;
+ break;
+ }
+
+ return num;
+}
+
+static int
+hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
+ uint16_t device_id)
+{
+ switch (device_id) {
+ case HNS3_DEV_ID_25GE:
+ /* fallthrough */
+ case HNS3_DEV_ID_25GE_RDMA:
+ speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
+ speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
+
+ /* In HNS3 device, the 25G NIC is compatible with 10G rate */
+ speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
+ speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
+ break;
+ case HNS3_DEV_ID_100G_RDMA_MACSEC:
+ speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
+ speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
+ break;
+ case HNS3_DEV_ID_200G_RDMA:
+ speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
+ speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
+ break;
+ default:
+ return -ENOTSUP;
+ }
+
+ return 0;
+}
+
+static int
+hns3_fec_get_capability(struct rte_eth_dev *dev,
+ struct rte_eth_fec_capa *speed_fec_capa,
+ unsigned int num)
+{
+ struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
+ uint16_t device_id = pci_dev->id.device_id;
+ unsigned int capa_num;
+ int ret;
+
+ capa_num = hns3_get_speed_capa_num(device_id);
+ if (capa_num == 0) {
+ hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
+ device_id);
+ return -ENOTSUP;
+ }
+
+ if (speed_fec_capa == NULL || num < capa_num)
+ return capa_num;
+
+ ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
+ if (ret)
+ return -ENOTSUP;
+
+ return capa_num;
+}
+
+static int
+get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
+{
+ struct hns3_config_fec_cmd *req;
+ struct hns3_cmd_desc desc;
+ int ret;
+
+ /*
+ * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
+ * in device of link speed
+ * below 10 Gbps.
+ */
+ if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
+ *state = 0;
+ return 0;
+ }
+
+ hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
+ req = (struct hns3_config_fec_cmd *)desc.data;
+ ret = hns3_cmd_send(hw, &desc, 1);
+ if (ret) {
+ hns3_err(hw, "get current fec auto state failed, ret = %d",
+ ret);
+ return ret;
+ }
+
+ *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
+ return 0;
+}
+
+static int
+hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
+{
+#define QUERY_ACTIVE_SPEED 1
+ struct hns3_sfp_speed_cmd *resp;
+ uint32_t tmp_fec_capa;
+ uint8_t auto_state;
+ struct hns3_cmd_desc desc;
+ int ret;
+
+ /*
+ * If link is down and AUTO is enabled, AUTO is returned, otherwise,
+ * configured FEC mode is returned.
+ * If link is up, current FEC mode is returned.
+ */
+ if (hw->mac.link_status == ETH_LINK_DOWN) {
+ ret = get_current_fec_auto_state(hw, &auto_state);
+ if (ret)
+ return ret;
+
+ if (auto_state == 0x1) {
+ *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
+ return 0;
+ }
+ }
+
+ hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
+ resp = (struct hns3_sfp_speed_cmd *)desc.data;
+ resp->query_type = QUERY_ACTIVE_SPEED;
+
+ ret = hns3_cmd_send(hw, &desc, 1);
+ if (ret == -EOPNOTSUPP) {
+ hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
+ return ret;
+ } else if (ret) {
+ hns3_err(hw, "get FEC failed, ret = %d", ret);
+ return ret;
+ }
+
+ /*
+ * FEC mode order defined in hns3 hardware is inconsistend with
+ * that defined in the ethdev library. So the sequence needs
+ * to be converted.
+ */
+ switch (resp->active_fec) {
+ case HNS3_HW_FEC_MODE_NOFEC:
+ tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
+ break;
+ case HNS3_HW_FEC_MODE_BASER:
+ tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
+ break;
+ case HNS3_HW_FEC_MODE_RS:
+ tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
+ break;
+ default:
+ tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
+ break;
+ }
+
+ *fec_capa = tmp_fec_capa;
+ return 0;
+}
+
+static int
+hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
+{
+ struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+
+ return hns3_fec_get_internal(hw, fec_capa);
+}
+
+static int
+hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
+{
+ struct hns3_config_fec_cmd *req;
+ struct hns3_cmd_desc desc;
+ int ret;
+
+ hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
+
+ req = (struct hns3_config_fec_cmd *)desc.data;
+ switch (mode) {
+ case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
+ hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
+ HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
+ break;
+ case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
+ hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
+ HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
+ break;
+ case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
+ hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
+ HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
+ break;
+ case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
+ hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
+ break;
+ default:
+ return 0;
+ }
+ ret = hns3_cmd_send(hw, &desc, 1);
+ if (ret)
+ hns3_err(hw, "set fec mode failed, ret = %d", ret);
+
+ return ret;
+}
+
+static uint32_t
+get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
+{
+ struct hns3_mac *mac = &hw->mac;
+ uint32_t cur_capa;
+
+ switch (mac->link_speed) {
+ case ETH_SPEED_NUM_10G:
+ cur_capa = fec_capa[1].capa;
+ break;
+ case ETH_SPEED_NUM_25G:
+ case ETH_SPEED_NUM_100G:
+ case ETH_SPEED_NUM_200G:
+ cur_capa = fec_capa[0].capa;
+ break;
+ default:
+ cur_capa = 0;
+ break;
+ }
+
+ return cur_capa;
+}
+
+static bool
+is_fec_mode_one_bit_set(uint32_t mode)
+{
+ int cnt = 0;
+ uint8_t i;
+
+ for (i = 0; i < sizeof(mode); i++)
+ if (mode >> i & 0x1)
+ cnt++;
+
+ return cnt == 1 ? true : false;
+}
+
+static int
+hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
+{
+#define FEC_CAPA_NUM 2
+ struct hns3_adapter *hns = dev->data->dev_private;
+ struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
+ struct hns3_pf *pf = &hns->pf;
+
+ struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
+ uint32_t cur_capa;
+ uint32_t num = FEC_CAPA_NUM;
+ int ret;
+
+ ret = hns3_fec_get_capability(dev, fec_capa, num);
+ if (ret < 0)
+ return ret;
+
+ /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
+ if (!is_fec_mode_one_bit_set(mode))
+ hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
+ "FEC mode should be only one bit set", mode);
+
+ /*
+ * Check whether the configured mode is within the FEC capability.
+ * If not, the configured mode will not be supported.
+ */
+ cur_capa = get_current_speed_fec_cap(hw, fec_capa);
+ if (!(cur_capa & mode)) {
+ hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
+ return -EINVAL;
+ }
+
+ ret = hns3_set_fec_hw(hw, mode);
+ if (ret)
+ return ret;
+
+ pf->fec_mode = mode;
+ return 0;
+}
+
+static int
+hns3_restore_fec(struct hns3_hw *hw)
+{
+ struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
+ struct hns3_pf *pf = &hns->pf;
+ uint32_t mode = pf->fec_mode;
+ int ret;
+
+ ret = hns3_set_fec_hw(hw, mode);
+ if (ret)
+ hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
+ mode, ret);
+
+ return ret;
+}
+
+static int
+hns3_query_dev_fec_info(struct hns3_hw *hw)
+{
+ struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
+ struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
+ int ret;
+
+ ret = hns3_fec_get_internal(hw, &pf->fec_mode);
+ if (ret)
+ hns3_err(hw, "query device FEC info failed, ret = %d", ret);
+
+ return ret;
+}
+
static const struct eth_dev_ops hns3_eth_dev_ops = {
+ .dev_configure = hns3_dev_configure,
.dev_start = hns3_dev_start,
.dev_stop = hns3_dev_stop,
.dev_close = hns3_dev_close,
.tx_queue_setup = hns3_tx_queue_setup,
.rx_queue_release = hns3_dev_rx_queue_release,
.tx_queue_release = hns3_dev_tx_queue_release,
+ .rx_queue_start = hns3_dev_rx_queue_start,
+ .rx_queue_stop = hns3_dev_rx_queue_stop,
+ .tx_queue_start = hns3_dev_tx_queue_start,
+ .tx_queue_stop = hns3_dev_tx_queue_stop,
.rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
.rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
- .dev_configure = hns3_dev_configure,
+ .rxq_info_get = hns3_rxq_info_get,
+ .txq_info_get = hns3_txq_info_get,
+ .rx_burst_mode_get = hns3_rx_burst_mode_get,
+ .tx_burst_mode_get = hns3_tx_burst_mode_get,
.flow_ctrl_get = hns3_flow_ctrl_get,
.flow_ctrl_set = hns3_flow_ctrl_set,
.priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
.get_reg = hns3_get_regs,
.get_dcb_info = hns3_get_dcb_info,
.dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
+ .fec_get_capability = hns3_fec_get_capability,
+ .fec_get = hns3_fec_get,
+ .fec_set = hns3_fec_set,
+ .tm_ops_get = hns3_tm_ops_get,
};
static const struct hns3_reset_ops hns3_reset_ops = {
static int
hns3_dev_init(struct rte_eth_dev *eth_dev)
{
- struct rte_device *dev = eth_dev->device;
- struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
struct hns3_adapter *hns = eth_dev->data->dev_private;
+ char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
+ struct rte_ether_addr *eth_addr;
struct hns3_hw *hw = &hns->hw;
- uint16_t device_id = pci_dev->id.device_id;
int ret;
PMD_INIT_FUNC_TRACE();
+
eth_dev->process_private = (struct hns3_process_private *)
rte_zmalloc_socket("hns3_filter_list",
sizeof(struct hns3_process_private),
hns3_set_rxtx_function(eth_dev);
eth_dev->dev_ops = &hns3_eth_dev_ops;
+ eth_dev->rx_queue_count = hns3_rx_queue_count;
if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
- hns3_mp_init_secondary();
+ ret = hns3_mp_init_secondary();
+ if (ret) {
+ PMD_INIT_LOG(ERR, "Failed to init for secondary "
+ "process, ret = %d", ret);
+ goto err_mp_init_secondary;
+ }
+
hw->secondary_cnt++;
return 0;
}
- hns3_mp_init_primary();
- hw->adapter_state = HNS3_NIC_UNINITIALIZED;
+ eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
- if (device_id == HNS3_DEV_ID_25GE_RDMA ||
- device_id == HNS3_DEV_ID_50GE_RDMA ||
- device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
- hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
+ ret = hns3_mp_init_primary();
+ if (ret) {
+ PMD_INIT_LOG(ERR,
+ "Failed to init for primary process, ret = %d",
+ ret);
+ goto err_mp_init_primary;
+ }
+ hw->adapter_state = HNS3_NIC_UNINITIALIZED;
hns->is_vf = false;
hw->data = eth_dev->data;
goto err_rte_zmalloc;
}
+ eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
+ if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
+ rte_eth_random_addr(hw->mac.mac_addr);
+ hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
+ (struct rte_ether_addr *)hw->mac.mac_addr);
+ hns3_warn(hw, "default mac_addr from firmware is an invalid "
+ "unicast address, using random MAC address %s",
+ mac_str);
+ }
rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
ð_dev->data->mac_addrs[0]);
hw->adapter_state = HNS3_NIC_INITIALIZED;
- /*
- * Pass the information to the rte_eth_dev_close() that it should also
- * release the private port resources.
- */
- eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
hns3_err(hw, "Reschedule reset service after dev_init");
err_init_pf:
rte_free(hw->reset.wait_data);
+
err_init_reset:
+ hns3_mp_uninit_primary();
+
+err_mp_init_primary:
+err_mp_init_secondary:
eth_dev->dev_ops = NULL;
eth_dev->rx_pkt_burst = NULL;
eth_dev->tx_pkt_burst = NULL;
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return -EPERM;
- eth_dev->dev_ops = NULL;
- eth_dev->rx_pkt_burst = NULL;
- eth_dev->tx_pkt_burst = NULL;
- eth_dev->tx_pkt_prepare = NULL;
if (hw->adapter_state < HNS3_NIC_CLOSING)
hns3_dev_close(eth_dev);
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
- { .vendor_id = 0, /* sentinel */ },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
+ { .vendor_id = 0, }, /* sentinel */
};
static struct rte_pci_driver rte_hns3_pmd = {
RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
-
-RTE_INIT(hns3_init_log)
-{
- hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
- if (hns3_logtype_init >= 0)
- rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
- hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
- if (hns3_logtype_driver >= 0)
- rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
-}
+RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
+RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);
git.droids-corp.org / dpdk.git / blobdiff