#include "hns3_dcb.h"
#include "hns3_mp.h"
-#define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
-#define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
-
#define HNS3_SERVICE_INTERVAL 1000000 /* us */
#define HNS3_SERVICE_QUICK_INTERVAL 10
#define HNS3_INVALID_PVID 0xFFFF
static int hns3_restore_fec(struct hns3_hw *hw);
static int hns3_query_dev_fec_info(struct hns3_hw *hw);
static int hns3_do_stop(struct hns3_adapter *hns);
+static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
void hns3_ether_format_addr(char *buf, uint16_t size,
const struct rte_ether_addr *ether_addr)
hns3_clear_all_event_cause(struct hns3_hw *hw)
{
uint32_t vector0_int_stats;
- vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
+ vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
hns3_warn(hw, "Probe during IMP reset interrupt");
uint32_t status;
int ret;
- /* query and clear mac tnl interruptions */
+ /* query and clear mac tnl interrupt */
hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
ret = hns3_cmd_send(hw, &desc, 1);
if (ret) {
hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
"ras_int_stat:0x%x cmdq_int_stat:0x%x",
vector0_int, ras_int, cmdq_int);
- hns3_handle_msix_error(hns, &hw->reset.request);
- hns3_handle_ras_error(hns, &hw->reset.request);
hns3_handle_mac_tnl(hw);
- hns3_schedule_reset(hns);
+ hns3_handle_error(hns);
} else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
hns3_warn(hw, "received reset interrupt");
hns3_schedule_reset(hns);
* When port base vlan enabled, we use port base vlan as the vlan
* filter condition. In this case, we don't update vlan filter table
* when user add new vlan or remove exist vlan, just update the
- * vlan list. The vlan id in vlan list will be writen in vlan filter
+ * vlan list. The vlan id in vlan list will be written in vlan filter
* table until port base vlan disabled
*/
if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
if (ret) {
- hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
+ hns3_err(hw, "%s strip rx vtag failed, ret = %d.",
+ enable ? "enable" : "disable", ret);
return ret;
}
int max_tc = 0;
int i;
- dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
- dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
-
- if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
- hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
- "rx_mq_mode = %d", rx_mq_mode);
- return -EINVAL;
- }
-
- if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
- tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
- hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
- "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
+ if ((rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG) ||
+ (tx_mq_mode == ETH_MQ_TX_VMDQ_DCB ||
+ tx_mq_mode == ETH_MQ_TX_VMDQ_ONLY)) {
+ hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
rx_mq_mode, tx_mq_mode);
- return -EINVAL;
+ return -EOPNOTSUPP;
}
- if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
+ dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
+ dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
+ if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
if (dcb_rx_conf->nb_tcs > pf->tc_max) {
hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
dcb_rx_conf->nb_tcs, pf->tc_max);
return 0;
}
-static int
-hns3_check_dcb_cfg(struct rte_eth_dev *dev)
-{
- struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
-
- if (!hns3_dev_dcb_supported(hw)) {
- hns3_err(hw, "this port does not support dcb configurations.");
- return -EOPNOTSUPP;
- }
-
- if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
- hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
- return -EOPNOTSUPP;
- }
-
- /* Check multiple queue mode */
- return hns3_check_mq_mode(dev);
-}
-
static int
hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
enum hns3_ring_type queue_type, uint16_t queue_id)
return 0;
}
+static int
+hns3_setup_dcb(struct rte_eth_dev *dev)
+{
+ struct hns3_adapter *hns = dev->data->dev_private;
+ struct hns3_hw *hw = &hns->hw;
+ int ret;
+
+ if (!hns3_dev_dcb_supported(hw)) {
+ hns3_err(hw, "this port does not support dcb configurations.");
+ return -EOPNOTSUPP;
+ }
+
+ if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
+ hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
+ return -EOPNOTSUPP;
+ }
+
+ ret = hns3_dcb_configure(hns);
+ if (ret)
+ hns3_err(hw, "failed to config dcb: %d", ret);
+
+ return ret;
+}
+
+static int
+hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
+{
+ int ret;
+
+ /*
+ * Some hardware doesn't support auto-negotiation, but users may not
+ * configure link_speeds (default 0), which means auto-negotiation.
+ * In this case, a warning message need to be printed, instead of
+ * an error.
+ */
+ if (link_speeds == ETH_LINK_SPEED_AUTONEG &&
+ hw->mac.support_autoneg == 0) {
+ hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
+ return 0;
+ }
+
+ if (link_speeds != ETH_LINK_SPEED_AUTONEG) {
+ ret = hns3_check_port_speed(hw, link_speeds);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int
+hns3_check_dev_conf(struct rte_eth_dev *dev)
+{
+ struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct rte_eth_conf *conf = &dev->data->dev_conf;
+ int ret;
+
+ ret = hns3_check_mq_mode(dev);
+ if (ret)
+ return ret;
+
+ return hns3_check_link_speed(hw, conf->link_speeds);
+}
+
static int
hns3_dev_configure(struct rte_eth_dev *dev)
{
* work as usual. But these fake queues are imperceptible, and can not
* be used by upper applications.
*/
- if (!hns3_dev_indep_txrx_supported(hw)) {
- ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
- if (ret) {
- hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
- ret);
- return ret;
- }
+ ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
+ if (ret) {
+ hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
+ hw->cfg_max_queues = 0;
+ return ret;
}
hw->adapter_state = HNS3_NIC_CONFIGURING;
- if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
- hns3_err(hw, "setting link speed/duplex not supported");
- ret = -EINVAL;
+ ret = hns3_check_dev_conf(dev);
+ if (ret)
goto cfg_err;
- }
if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
- ret = hns3_check_dcb_cfg(dev);
+ ret = hns3_setup_dcb(dev);
if (ret)
goto cfg_err;
}
return 0;
cfg_err:
+ hw->cfg_max_queues = 0;
(void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
hw->adapter_state = HNS3_NIC_INITIALIZED;
.offloads = 0,
};
- info->vmdq_queue_num = 0;
-
info->reta_size = hw->rss_ind_tbl_size;
info->hash_key_size = HNS3_RSS_KEY_SIZE;
info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
HNS3_FW_VERSION_BYTE1_S),
hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
HNS3_FW_VERSION_BYTE0_S));
+ if (ret < 0)
+ return -EINVAL;
+
ret += 1; /* add the size of '\0' */
- if (fw_size < (uint32_t)ret)
+ if (fw_size < (size_t)ret)
return ret;
else
return 0;
case ETH_SPEED_NUM_50G:
case ETH_SPEED_NUM_100G:
case ETH_SPEED_NUM_200G:
- new_link->link_speed = mac->link_speed;
+ if (mac->link_status)
+ new_link->link_speed = mac->link_speed;
break;
default:
if (mac->link_status)
new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
- else
- new_link->link_speed = ETH_SPEED_NUM_NONE;
break;
}
+ if (!mac->link_status)
+ new_link->link_speed = ETH_SPEED_NUM_NONE;
+
new_link->link_duplex = mac->link_duplex;
new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
new_link->link_autoneg = mac->link_autoneg;
struct rte_eth_link new_link;
int ret;
+ /* When port is stopped, report link down. */
+ if (eth_dev->data->dev_started == 0) {
+ new_link.link_autoneg = mac->link_autoneg;
+ new_link.link_duplex = mac->link_duplex;
+ new_link.link_speed = ETH_SPEED_NUM_NONE;
+ new_link.link_status = ETH_LINK_DOWN;
+ goto out;
+ }
+
do {
ret = hns3_update_port_link_info(eth_dev);
if (ret) {
memset(&new_link, 0, sizeof(new_link));
hns3_setup_linkstatus(eth_dev, &new_link);
+out:
return rte_eth_linkstatus_set(eth_dev, &new_link);
}
req = (struct hns3_cfg_param_cmd *)desc[0].data;
/* get the configuration */
- cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
- HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
HNS3_CFG_EXT_RSS_SIZE_M,
HNS3_CFG_EXT_RSS_SIZE_S);
-
/*
* Field ext_rss_size_max obtained from firmware will be more flexible
* for future changes and expansions, which is an exponent of 2, instead
for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
priv = &buf_alloc->priv_buf[i];
mask = BIT((uint8_t)i);
-
if (hw->hw_tc_map & mask &&
!(hw->dcb_info.hw_pfc_map & mask)) {
/* Clear the no pfc TC private buffer */
COMPENSATE_HALF_MPS_NUM * half_mps;
min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
-
if (rx_priv < min_rx_priv)
return false;
* For different application scenes, the enabled port number, TC number
* and no_drop TC number are different. In order to obtain the better
* performance, software could allocate the buffer size and configure
- * the waterline by tring to decrease the private buffer size according
- * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
+ * the waterline by trying to decrease the private buffer size according
+ * to the order, namely, waterline of valid tc, pfc disabled tc, pfc
* enabled tc.
*/
if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
if (state != hw->mac.link_status) {
hw->mac.link_status = state;
hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
- hns3_config_mac_tnl_int(hw,
- state == ETH_LINK_UP ? true : false);
return true;
}
* and belong to a different type from the MSI-x errors processed
* by the network driver.
*
- * Network driver should open the new error report on initialition
+ * Network driver should open the new error report on initialization.
*/
val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
goto err_cmd_init;
}
+ hns3_tx_push_init(eth_dev);
+
/*
* To ensure that the hardware environment is clean during
* initialization, the driver actively clear the hardware environment
hw->io_base = NULL;
}
+static uint32_t
+hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
+{
+ uint32_t speed_bit;
+
+ switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
+ case ETH_LINK_SPEED_10M:
+ speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
+ break;
+ case ETH_LINK_SPEED_10M_HD:
+ speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
+ break;
+ case ETH_LINK_SPEED_100M:
+ speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
+ break;
+ case ETH_LINK_SPEED_100M_HD:
+ speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
+ break;
+ case ETH_LINK_SPEED_1G:
+ speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
+ break;
+ default:
+ speed_bit = 0;
+ break;
+ }
+
+ return speed_bit;
+}
+
+static uint32_t
+hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
+{
+ uint32_t speed_bit;
+
+ switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
+ case ETH_LINK_SPEED_1G:
+ speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
+ break;
+ case ETH_LINK_SPEED_10G:
+ speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
+ break;
+ case ETH_LINK_SPEED_25G:
+ speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
+ break;
+ case ETH_LINK_SPEED_40G:
+ speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
+ break;
+ case ETH_LINK_SPEED_50G:
+ speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
+ break;
+ case ETH_LINK_SPEED_100G:
+ speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
+ break;
+ case ETH_LINK_SPEED_200G:
+ speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
+ break;
+ default:
+ speed_bit = 0;
+ break;
+ }
+
+ return speed_bit;
+}
+
+static int
+hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
+{
+ struct hns3_mac *mac = &hw->mac;
+ uint32_t supported_speed = mac->supported_speed;
+ uint32_t speed_bit = 0;
+
+ if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
+ speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
+ else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
+ speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
+
+ if (!(speed_bit & supported_speed)) {
+ hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
+ link_speeds);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static inline uint32_t
+hns3_get_link_speed(uint32_t link_speeds)
+{
+ uint32_t speed = ETH_SPEED_NUM_NONE;
+
+ if (link_speeds & ETH_LINK_SPEED_10M ||
+ link_speeds & ETH_LINK_SPEED_10M_HD)
+ speed = ETH_SPEED_NUM_10M;
+ if (link_speeds & ETH_LINK_SPEED_100M ||
+ link_speeds & ETH_LINK_SPEED_100M_HD)
+ speed = ETH_SPEED_NUM_100M;
+ if (link_speeds & ETH_LINK_SPEED_1G)
+ speed = ETH_SPEED_NUM_1G;
+ if (link_speeds & ETH_LINK_SPEED_10G)
+ speed = ETH_SPEED_NUM_10G;
+ if (link_speeds & ETH_LINK_SPEED_25G)
+ speed = ETH_SPEED_NUM_25G;
+ if (link_speeds & ETH_LINK_SPEED_40G)
+ speed = ETH_SPEED_NUM_40G;
+ if (link_speeds & ETH_LINK_SPEED_50G)
+ speed = ETH_SPEED_NUM_50G;
+ if (link_speeds & ETH_LINK_SPEED_100G)
+ speed = ETH_SPEED_NUM_100G;
+ if (link_speeds & ETH_LINK_SPEED_200G)
+ speed = ETH_SPEED_NUM_200G;
+
+ return speed;
+}
+
+static uint8_t
+hns3_get_link_duplex(uint32_t link_speeds)
+{
+ if ((link_speeds & ETH_LINK_SPEED_10M_HD) ||
+ (link_speeds & ETH_LINK_SPEED_100M_HD))
+ return ETH_LINK_HALF_DUPLEX;
+ else
+ return ETH_LINK_FULL_DUPLEX;
+}
+
static int
hns3_set_copper_port_link_speed(struct hns3_hw *hw,
struct hns3_set_link_speed_cfg *cfg)
HNS3_PHY_LINK_SPEED_100M_BIT |
HNS3_PHY_LINK_SPEED_100M_HD_BIT |
HNS3_PHY_LINK_SPEED_1000M_BIT;
+ } else {
+ req->speed = cfg->speed;
+ req->duplex = cfg->duplex;
}
return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
/*
* Some hardware doesn't support auto-negotiation, but users may not
- * configure link_speeds (default 0), which means auto-negotiation
- * In this case, a warning message need to be printed, instead of
- * an error.
+ * configure link_speeds (default 0), which means auto-negotiation.
+ * In this case, it should return success.
*/
- if (cfg->autoneg) {
- hns3_warn(hw, "auto-negotiation is not supported.");
+ if (cfg->autoneg)
return 0;
- }
- return 0;
+ return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
}
static int
cfg.autoneg = (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) ?
ETH_LINK_AUTONEG : ETH_LINK_FIXED;
if (cfg.autoneg != ETH_LINK_AUTONEG) {
- hns3_err(hw, "device doesn't support to force link speed.");
- return -EOPNOTSUPP;
+ cfg.speed = hns3_get_link_speed(conf->link_speeds);
+ cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
}
return hns3_set_port_link_speed(hw, &cfg);
struct hns3_hw *hw = &hns->hw;
int ret;
- ret = hns3_dcb_cfg_update(hns);
- if (ret)
+ ret = hns3_update_queue_map_configure(hns);
+ if (ret) {
+ hns3_err(hw, "failed to update queue mapping configuration, ret = %d",
+ ret);
return ret;
+ }
- /*
- * The hns3_dcb_cfg_update may configure TM module, so
- * hns3_tm_conf_update must called later.
- */
+ /* Note: hns3_tm_conf_update must be called after configuring DCB. */
ret = hns3_tm_conf_update(hw);
if (ret) {
PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
ret = hns3_apply_link_speed(hw);
if (ret)
- goto err_config_mac_mode;
+ goto err_set_link_speed;
return 0;
-err_config_mac_mode:
+err_set_link_speed:
(void)hns3_cfg_mac_mode(hw, false);
+
+err_config_mac_mode:
hns3_dev_release_mbufs(hns);
/*
* Here is exception handling, hns3_reset_all_tqps will have the
/* Disable datapath on secondary process. */
hns3_mp_req_stop_rxtx(dev);
/* Prevent crashes when queues are still in use. */
- rte_delay_ms(hw->tqps_num);
+ rte_delay_ms(hw->cfg_max_queues);
rte_spinlock_lock(&hw->lock);
if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
return 0;
}
-static void
-hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
-{
- switch (mode) {
- case RTE_FC_NONE:
- hw->requested_fc_mode = HNS3_FC_NONE;
- break;
- case RTE_FC_RX_PAUSE:
- hw->requested_fc_mode = HNS3_FC_RX_PAUSE;
- break;
- case RTE_FC_TX_PAUSE:
- hw->requested_fc_mode = HNS3_FC_TX_PAUSE;
- break;
- case RTE_FC_FULL:
- hw->requested_fc_mode = HNS3_FC_FULL;
- break;
- default:
- hw->requested_fc_mode = HNS3_FC_NONE;
- hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
- "configured to RTE_FC_NONE", mode);
- break;
- }
-}
-
static int
hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
{
return -EOPNOTSUPP;
}
- hns3_get_fc_mode(hw, fc_conf->mode);
-
rte_spinlock_lock(&hw->lock);
ret = hns3_fc_enable(dev, fc_conf);
rte_spinlock_unlock(&hw->lock);
return -EOPNOTSUPP;
}
- hns3_get_fc_mode(hw, pfc_conf->fc.mode);
-
rte_spinlock_lock(&hw->lock);
ret = hns3_dcb_pfc_enable(dev, pfc_conf);
rte_spinlock_unlock(&hw->lock);
hns3_check_event_cause(hns, NULL);
reset = hns3_get_reset_level(hns, &hw->reset.pending);
- if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
+ if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
+ hw->reset.level < reset) {
hns3_warn(hw, "High level reset %d is pending", reset);
return true;
}
reset = hns3_get_reset_level(hns, &hw->reset.request);
- if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
+ if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
+ hw->reset.level < reset) {
hns3_warn(hw, "High level reset %d is request", reset);
return true;
}
if (wait_data->result == HNS3_WAIT_SUCCESS)
return 0;
else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
- gettimeofday(&tv, NULL);
+ hns3_clock_gettime(&tv);
hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
tv.tv_sec, tv.tv_usec);
return -ETIME;
wait_data->hns = hns;
wait_data->check_completion = is_pf_reset_done;
wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
- HNS3_RESET_WAIT_MS + get_timeofday_ms();
+ HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms();
wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
wait_data->count = HNS3_RESET_WAIT_CNT;
wait_data->result = HNS3_WAIT_REQUEST;
struct timeval tv;
uint32_t val;
- gettimeofday(&tv, NULL);
+ hns3_clock_gettime(&tv);
if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
rte_wmb();
/* Disable datapath on secondary process. */
hns3_mp_req_stop_rxtx(eth_dev);
- rte_delay_ms(hw->tqps_num);
+ rte_delay_ms(hw->cfg_max_queues);
rte_spinlock_lock(&hw->lock);
if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
*/
reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
if (reset_level != HNS3_NONE_RESET) {
- gettimeofday(&tv_start, NULL);
+ hns3_clock_gettime(&tv_start);
ret = hns3_reset_process(hns, reset_level);
- gettimeofday(&tv, NULL);
+ hns3_clock_gettime(&tv);
timersub(&tv, &tv_start, &tv_delta);
- msec = tv_delta.tv_sec * MSEC_PER_SEC +
- tv_delta.tv_usec / USEC_PER_MSEC;
+ msec = hns3_clock_calctime_ms(&tv_delta);
if (msec > HNS3_RESET_PROCESS_MS)
- hns3_err(hw, "%d handle long time delta %" PRIx64
+ hns3_err(hw, "%d handle long time delta %" PRIu64
" ms time=%ld.%.6ld",
hw->reset.level, msec,
tv.tv_sec, tv.tv_usec);
return ret;
/* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
- if (!is_fec_mode_one_bit_set(mode))
- hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
+ if (!is_fec_mode_one_bit_set(mode)) {
+ hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, "
"FEC mode should be only one bit set", mode);
+ return -EINVAL;
+ }
/*
* Check whether the configured mode is within the FEC capability.
return 0;
}
+void
+hns3_clock_gettime(struct timeval *tv)
+{
+#ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */
+#define CLOCK_TYPE CLOCK_MONOTONIC_RAW
+#else
+#define CLOCK_TYPE CLOCK_MONOTONIC
+#endif
+#define NSEC_TO_USEC_DIV 1000
+
+ struct timespec spec;
+ (void)clock_gettime(CLOCK_TYPE, &spec);
+
+ tv->tv_sec = spec.tv_sec;
+ tv->tv_usec = spec.tv_nsec / NSEC_TO_USEC_DIV;
+}
+
+uint64_t
+hns3_clock_calctime_ms(struct timeval *tv)
+{
+ return (uint64_t)tv->tv_sec * MSEC_PER_SEC +
+ tv->tv_usec / USEC_PER_MSEC;
+}
+
+uint64_t
+hns3_clock_gettime_ms(void)
+{
+ struct timeval tv;
+
+ hns3_clock_gettime(&tv);
+ return hns3_clock_calctime_ms(&tv);
+}
+
static int
hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
{
}
}
+static int
+hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args)
+{
+ uint64_t val;
+
+ RTE_SET_USED(key);
+
+ val = strtoull(value, NULL, 16);
+ *(uint64_t *)extra_args = val;
+
+ return 0;
+}
+
void
hns3_parse_devargs(struct rte_eth_dev *dev)
{
uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
struct hns3_hw *hw = &hns->hw;
+ uint64_t dev_caps_mask = 0;
struct rte_kvargs *kvlist;
if (dev->device->devargs == NULL)
if (!kvlist)
return;
- rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
+ (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
&hns3_parse_io_hint_func, &rx_func_hint);
- rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
+ (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
&hns3_parse_io_hint_func, &tx_func_hint);
+ (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK,
+ &hns3_parse_dev_caps_mask, &dev_caps_mask);
rte_kvargs_free(kvlist);
if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
hns3_get_io_hint_func_name(tx_func_hint));
hns->tx_func_hint = tx_func_hint;
+
+ if (dev_caps_mask != 0)
+ hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".",
+ HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask);
+ hns->dev_caps_mask = dev_caps_mask;
}
static const struct eth_dev_ops hns3_eth_dev_ops = {
PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
return -ENOMEM;
}
- /* initialize flow filter lists */
- hns3_filterlist_init(eth_dev);
+
+ hns3_flow_init(eth_dev);
hns3_set_rxtx_function(eth_dev);
eth_dev->dev_ops = &hns3_eth_dev_ops;
"process, ret = %d", ret);
goto err_mp_init_secondary;
}
-
hw->secondary_cnt++;
+ hns3_tx_push_init(eth_dev);
return 0;
}
RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
- HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common ");
-RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
-RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);
+ HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
+ HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");
+RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE);
+RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE);
git.droids-corp.org / dpdk.git / blobdiff