#define HNS3_MC_MACADDR_NUM 128
#define HNS3_MAX_BD_SIZE 65535
-#define HNS3_MAX_TX_BD_PER_PKT 8
+#define HNS3_MAX_NON_TSO_BD_PER_PKT 8
+#define HNS3_MAX_TSO_BD_PER_PKT 63
#define HNS3_MAX_FRAME_LEN 9728
-#define HNS3_MIN_FRAME_LEN 64
#define HNS3_VLAN_TAG_SIZE 4
#define HNS3_DEFAULT_RX_BUF_LEN 2048
+#define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1)
+#define HNS3_MAX_TSO_HDR_SIZE 512
+#define HNS3_MAX_TSO_HDR_BD_NUM 3
#define HNS3_ETH_OVERHEAD \
(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
uint32_t link_speed; /* ETH_SPEED_NUM_ */
};
+struct hns3_fake_queue_data {
+ void **rx_queues; /* Array of pointers to fake RX queues. */
+ void **tx_queues; /* Array of pointers to fake TX queues. */
+ uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */
+ uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */
+};
/* Primary process maintains driver state in main thread.
*
struct hns3_dcb_info dcb_info;
enum hns3_fc_status current_fc_status; /* current flow control status */
struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
- uint16_t alloc_tqps;
- uint16_t alloc_rss_size; /* Queue number per TC */
+ uint16_t used_rx_queues;
+ uint16_t used_tx_queues;
+
+ /* Config max queue numbers between rx and tx queues from user */
+ uint16_t cfg_max_queues;
+ struct hns3_fake_queue_data fkq_data; /* fake queue data */
+ uint16_t alloc_rss_size; /* RX queue number per TC */
+ uint16_t tx_qnum_per_tc; /* TX queue number per TC */
uint32_t flag;
/*
struct hns3_pf {
struct hns3_adapter *adapter;
bool is_main_pf;
+ uint16_t func_num; /* num functions of this pf, include pf and vfs */
uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
uint32_t tx_buf_size; /* Tx buffer size for each TC */