#define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
#define I40E_CLEAR_PXE_WAIT_MS 200
+#define I40E_VSI_TSR_QINQ_STRIP 0x4010
+#define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
/* Maximun number of capability elements */
#define I40E_MAX_CAP_ELE_NUM 128
static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
static int i40e_dev_configure(struct rte_eth_dev *dev);
static int i40e_dev_start(struct rte_eth_dev *dev);
-static void i40e_dev_stop(struct rte_eth_dev *dev);
-static void i40e_dev_close(struct rte_eth_dev *dev);
+static int i40e_dev_stop(struct rte_eth_dev *dev);
+static int i40e_dev_close(struct rte_eth_dev *dev);
static int i40e_dev_reset(struct rte_eth_dev *dev);
static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
static int i40e_veb_release(struct i40e_veb *veb);
static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
struct i40e_vsi *vsi);
-static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
struct i40e_macvlan_filter *mv_f,
static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
struct rte_eth_udp_tunnel *udp_tunnel);
static void i40e_filter_input_set_init(struct i40e_pf *pf);
-static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
- enum rte_filter_op filter_op,
- void *arg);
static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
enum rte_filter_type filter_type,
enum rte_filter_op filter_op,
static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
static void i40e_filter_restore(struct i40e_pf *pf);
static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
+static int i40e_pf_config_rss(struct i40e_pf *pf);
static const char *const valid_keys[] = {
ETH_I40E_FLOATING_VEB_ARG,
.rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
.rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
.rx_queue_release = i40e_dev_rx_queue_release,
- .rx_queue_count = i40e_dev_rx_queue_count,
- .rx_descriptor_done = i40e_dev_rx_descriptor_done,
- .rx_descriptor_status = i40e_dev_rx_descriptor_status,
- .tx_descriptor_status = i40e_dev_tx_descriptor_status,
.tx_queue_setup = i40e_dev_tx_queue_setup,
.tx_queue_release = i40e_dev_tx_queue_release,
.dev_led_on = i40e_dev_led_on,
PMD_INIT_FUNC_TRACE();
dev->dev_ops = &i40e_eth_dev_ops;
+ dev->rx_queue_count = i40e_dev_rx_queue_count;
+ dev->rx_descriptor_done = i40e_dev_rx_descriptor_done;
+ dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
+ dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
dev->rx_pkt_burst = i40e_recv_pkts;
dev->tx_pkt_burst = i40e_xmit_pkts;
dev->tx_pkt_prepare = i40e_prep_pkts;
intr_handle = &pci_dev->intr_handle;
rte_eth_copy_pci_info(dev, pci_dev);
+ dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
pf->adapter->eth_dev = dev;
rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
&dev->data->mac_addrs[0]);
- /* Pass the information to the rte_eth_dev_close() that it should also
- * release the private port resources.
- */
- dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
-
/* Init dcb to sw mode by default */
ret = i40e_dcb_init_configure(dev, TRUE);
if (ret != I40E_SUCCESS) {
if (fdir_info->hash_table)
rte_hash_free(fdir_info->hash_table);
if (fdir_info->fdir_flow_pool.bitmap)
- rte_bitmap_free(fdir_info->fdir_flow_pool.bitmap);
+ rte_free(fdir_info->fdir_flow_pool.bitmap);
if (fdir_info->fdir_flow_pool.pool)
rte_free(fdir_info->fdir_flow_pool.pool);
if (fdir_info->fdir_filter_array)
goto err;
/* VMDQ setup.
- * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
- * RSS setting have different requirements.
* General PMD driver call sequence are NIC init, configure,
* rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
* will try to lookup the VSI that specific queue belongs to if VMDQ
I40E_WRITE_FLUSH(hw);
}
-void
+int
i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
{
struct rte_eth_dev *dev = vsi->adapter->eth_dev;
/* VF bind interrupt */
if (vsi->type == I40E_VSI_SRIOV) {
+ if (vsi->nb_msix == 0) {
+ PMD_DRV_LOG(ERR, "No msix resource");
+ return -EINVAL;
+ }
__vsi_queues_bind_intr(vsi, msix_vect,
vsi->base_queue, vsi->nb_qps,
itr_idx);
- return;
+ return 0;
}
/* PF & VMDq bind interrupt */
}
for (i = 0; i < vsi->nb_used_qps; i++) {
- if (nb_msix <= 1) {
+ if (vsi->nb_msix == 0) {
+ PMD_DRV_LOG(ERR, "No msix resource");
+ return -EINVAL;
+ } else if (nb_msix <= 1) {
if (!rte_intr_allow_others(intr_handle))
/* allow to share MISC_VEC_ID */
msix_vect = I40E_MISC_VEC_ID;
msix_vect++;
nb_msix--;
}
+
+ return 0;
}
-static void
+void
i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
{
struct rte_eth_dev *dev = vsi->adapter->eth_dev;
I40E_WRITE_FLUSH(hw);
}
-static void
+void
i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
{
struct rte_eth_dev *dev = vsi->adapter->eth_dev;
/* Map queues with MSIX interrupt */
main_vsi->nb_used_qps = dev->data->nb_rx_queues -
pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
- i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
+ ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
+ if (ret < 0)
+ return ret;
i40e_vsi_enable_queues_intr(main_vsi);
/* Map VMDQ VSI queues with MSIX interrupt */
for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
- i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
- I40E_ITR_INDEX_DEFAULT);
+ ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
+ I40E_ITR_INDEX_DEFAULT);
+ if (ret < 0)
+ return ret;
i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
}
- /* enable FDIR MSIX interrupt */
- if (pf->fdir.fdir_vsi) {
- i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
- I40E_ITR_INDEX_NONE);
- i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
- }
-
/* Enable all queues which have been configured */
for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
ret = i40e_dev_rx_queue_start(dev, nb_rxq);
return ret;
}
-static void
+static int
i40e_dev_stop(struct rte_eth_dev *dev)
{
struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
int i;
if (hw->adapter_stopped == 1)
- return;
+ return 0;
if (dev->data->dev_conf.intr_conf.rxq == 0) {
rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
}
- if (pf->fdir.fdir_vsi) {
- i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
- i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
- }
/* Clear all queues and release memory */
i40e_dev_clear_queues(dev);
pf->tm_conf.committed = false;
hw->adapter_stopped = 1;
+ dev->data->dev_started = 0;
pf->adapter->rss_reta_updated = 0;
+
+ return 0;
}
-static void
+static int
i40e_dev_close(struct rte_eth_dev *dev)
{
struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
int retries = 0;
PMD_INIT_FUNC_TRACE();
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+ return 0;
ret = rte_eth_switch_domain_free(pf->switch_domain_id);
if (ret)
PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
- i40e_dev_stop(dev);
+ ret = i40e_dev_stop(dev);
/* Remove all mirror rules */
while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
(reg | I40E_PFGEN_CTRL_PFSWR_MASK));
I40E_WRITE_FLUSH(hw);
- dev->dev_ops = NULL;
- dev->rx_pkt_burst = NULL;
- dev->tx_pkt_burst = NULL;
-
/* Clear PXE mode */
i40e_clear_pxe_mode(hw);
i40e_tm_conf_uninit(dev);
hw->adapter_closed = 1;
+ return ret;
}
/*
link->link_speed = ETH_SPEED_NUM_40G;
break;
default:
- link->link_speed = ETH_SPEED_NUM_NONE;
+ if (link->link_status)
+ link->link_speed = ETH_SPEED_NUM_UNKNOWN;
+ else
+ link->link_speed = ETH_SPEED_NUM_NONE;
break;
}
}
return ret;
}
+static void
+i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg,
+ uint32_t loreg, bool offset_loaded, uint64_t *offset,
+ uint64_t *stat, uint64_t *prev_stat)
+{
+ i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat);
+ /* enlarge the limitation when statistics counters overflowed */
+ if (offset_loaded) {
+ if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat)
+ *stat += (uint64_t)1 << I40E_48_BIT_WIDTH;
+ *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat);
+ }
+ *prev_stat = *stat;
+}
+
/* Get all the statistics of a VSI */
void
i40e_update_vsi_stats(struct i40e_vsi *vsi)
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
- i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
- vsi->offset_loaded, &oes->rx_bytes,
- &nes->rx_bytes);
+ i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
+ vsi->offset_loaded, &oes->rx_bytes,
+ &nes->rx_bytes, &vsi->prev_rx_bytes);
i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
vsi->offset_loaded, &oes->rx_unicast,
&nes->rx_unicast);
i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
&oes->rx_unknown_protocol,
&nes->rx_unknown_protocol);
- i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
- vsi->offset_loaded, &oes->tx_bytes,
- &nes->tx_bytes);
+ i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
+ vsi->offset_loaded, &oes->tx_bytes,
+ &nes->tx_bytes, &vsi->prev_tx_bytes);
i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
vsi->offset_loaded, &oes->tx_unicast,
&nes->tx_unicast);
struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
/* Get rx/tx bytes of internal transfer packets */
- i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
- I40E_GLV_GORCL(hw->port),
- pf->offset_loaded,
- &pf->internal_stats_offset.rx_bytes,
- &pf->internal_stats.rx_bytes);
-
- i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
- I40E_GLV_GOTCL(hw->port),
- pf->offset_loaded,
- &pf->internal_stats_offset.tx_bytes,
- &pf->internal_stats.tx_bytes);
+ i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port),
+ I40E_GLV_GORCL(hw->port),
+ pf->offset_loaded,
+ &pf->internal_stats_offset.rx_bytes,
+ &pf->internal_stats.rx_bytes,
+ &pf->internal_prev_rx_bytes);
+ i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port),
+ I40E_GLV_GOTCL(hw->port),
+ pf->offset_loaded,
+ &pf->internal_stats_offset.tx_bytes,
+ &pf->internal_stats.tx_bytes,
+ &pf->internal_prev_tx_bytes);
/* Get total internal rx packet count */
i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
I40E_GLV_UPRCL(hw->port),
pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
/* Get statistics of struct i40e_eth_stats */
- i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
- I40E_GLPRT_GORCL(hw->port),
- pf->offset_loaded, &os->eth.rx_bytes,
- &ns->eth.rx_bytes);
+ i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port),
+ I40E_GLPRT_GORCL(hw->port),
+ pf->offset_loaded, &os->eth.rx_bytes,
+ &ns->eth.rx_bytes, &pf->prev_rx_bytes);
i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
I40E_GLPRT_UPRCL(hw->port),
pf->offset_loaded, &os->eth.rx_unicast,
pf->offset_loaded,
&os->eth.rx_unknown_protocol,
&ns->eth.rx_unknown_protocol);
- i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
- I40E_GLPRT_GOTCL(hw->port),
- pf->offset_loaded, &os->eth.tx_bytes,
- &ns->eth.tx_bytes);
+ i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port),
+ I40E_GLPRT_GOTCL(hw->port),
+ pf->offset_loaded, &os->eth.tx_bytes,
+ &ns->eth.tx_bytes, &pf->prev_tx_bytes);
i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
I40E_GLPRT_UPTCL(hw->port),
pf->offset_loaded, &os->eth.tx_unicast,
return ret;
}
+/* Configure outer vlan stripping on or off in QinQ mode */
+static int
+i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
+{
+ struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
+ int ret = I40E_SUCCESS;
+ uint32_t reg;
+
+ if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
+ PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
+ return -EINVAL;
+ }
+
+ /* Configure for outer VLAN RX stripping */
+ reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
+
+ if (on)
+ reg |= I40E_VSI_TSR_QINQ_STRIP;
+ else
+ reg &= ~I40E_VSI_TSR_QINQ_STRIP;
+
+ ret = i40e_aq_debug_write_register(hw,
+ I40E_VSI_TSR(vsi->vsi_id),
+ reg, NULL);
+ if (ret < 0) {
+ PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
+ vsi->vsi_id);
+ return I40E_ERR_CONFIG;
+ }
+
+ return ret;
+}
+
static int
i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
{
i40e_vsi_config_double_vlan(vsi, FALSE);
}
+ if (mask & ETH_QINQ_STRIP_MASK) {
+ /* Enable or disable outer VLAN stripping */
+ if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
+ i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
+ else
+ i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
+ }
+
return 0;
}
rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
- mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
+ mac_filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
else
- mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
+ mac_filter.filter_type = I40E_MAC_PERFECT_MATCH;
if (pool == 0)
vsi = pf->main_vsi;
}
}
-/* Set perfect match or hash match of MAC and VLAN for a VF */
-static int
-i40e_vf_mac_filter_set(struct i40e_pf *pf,
- struct rte_eth_mac_filter *filter,
- bool add)
-{
- struct i40e_hw *hw;
- struct i40e_mac_filter_info mac_filter;
- struct rte_ether_addr old_mac;
- struct rte_ether_addr *new_mac;
- struct i40e_pf_vf *vf = NULL;
- uint16_t vf_id;
- int ret;
-
- if (pf == NULL) {
- PMD_DRV_LOG(ERR, "Invalid PF argument.");
- return -EINVAL;
- }
- hw = I40E_PF_TO_HW(pf);
-
- if (filter == NULL) {
- PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
- return -EINVAL;
- }
-
- new_mac = &filter->mac_addr;
-
- if (rte_is_zero_ether_addr(new_mac)) {
- PMD_DRV_LOG(ERR, "Invalid ethernet address.");
- return -EINVAL;
- }
-
- vf_id = filter->dst_id;
-
- if (vf_id > pf->vf_num - 1 || !pf->vfs) {
- PMD_DRV_LOG(ERR, "Invalid argument.");
- return -EINVAL;
- }
- vf = &pf->vfs[vf_id];
-
- if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
- PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
- return -EINVAL;
- }
-
- if (add) {
- rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
- rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
- RTE_ETHER_ADDR_LEN);
- rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
- RTE_ETHER_ADDR_LEN);
-
- mac_filter.filter_type = filter->filter_type;
- ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
- if (ret != I40E_SUCCESS) {
- PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
- return -1;
- }
- rte_ether_addr_copy(new_mac, &pf->dev_addr);
- } else {
- rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
- RTE_ETHER_ADDR_LEN);
- ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
- if (ret != I40E_SUCCESS) {
- PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
- return -1;
- }
-
- /* Clear device address as it has been removed */
- if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
- memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
- }
-
- return 0;
-}
-
-/* MAC filter handle */
-static int
-i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
- void *arg)
-{
- struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
- struct rte_eth_mac_filter *filter;
- struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- int ret = I40E_NOT_SUPPORTED;
-
- filter = (struct rte_eth_mac_filter *)(arg);
-
- switch (filter_op) {
- case RTE_ETH_FILTER_NOP:
- ret = I40E_SUCCESS;
- break;
- case RTE_ETH_FILTER_ADD:
- i40e_pf_disable_irq0(hw);
- if (filter->is_vf)
- ret = i40e_vf_mac_filter_set(pf, filter, 1);
- i40e_pf_enable_irq0(hw);
- break;
- case RTE_ETH_FILTER_DELETE:
- i40e_pf_disable_irq0(hw);
- if (filter->is_vf)
- ret = i40e_vf_mac_filter_set(pf, filter, 0);
- i40e_pf_enable_irq0(hw);
- break;
- default:
- PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
- ret = I40E_ERR_PARAM;
- break;
- }
-
- return ret;
-}
-
static int
i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
{
mac = &f->mac_info.mac_addr;
rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
ETH_ADDR_LEN);
- f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
+ f->mac_info.filter_type = I40E_MACVLAN_PERFECT_MATCH;
TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
vsi->mac_num++;
}
rte_memcpy(&filter.mac_addr,
(struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
- filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
+ filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
return i40e_vsi_add_mac(vsi, &filter);
}
ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
if (ret < 0) {
PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
- goto fail_queue_alloc;
+ if (type != I40E_VSI_FDIR)
+ goto fail_queue_alloc;
+ vsi->msix_intr = 0;
+ vsi->nb_msix = 0;
+ } else {
+ vsi->msix_intr = ret;
+ vsi->nb_msix = 1;
}
- vsi->msix_intr = ret;
- vsi->nb_msix = 1;
} else {
vsi->msix_intr = 0;
vsi->nb_msix = 0;
/* MAC/VLAN configuration */
rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
- filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
+ filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
ret = i40e_vsi_add_mac(vsi, &filter);
if (ret != I40E_SUCCESS) {
struct i40e_mac_filter *f;
void *temp;
struct i40e_mac_filter_info *mac_filter;
- enum rte_mac_filter_type desired_filter;
+ enum i40e_mac_filter_type desired_filter;
int ret = I40E_SUCCESS;
if (on) {
/* Filter to match MAC and VLAN */
- desired_filter = RTE_MACVLAN_PERFECT_MATCH;
+ desired_filter = I40E_MACVLAN_PERFECT_MATCH;
} else {
/* Filter to match only MAC */
- desired_filter = RTE_MAC_PERFECT_MATCH;
+ desired_filter = I40E_MAC_PERFECT_MATCH;
}
num = vsi->mac_num;
/* Apply vlan offload setting */
mask = ETH_VLAN_STRIP_MASK |
+ ETH_QINQ_STRIP_MASK |
ETH_VLAN_FILTER_MASK |
ETH_VLAN_EXTEND_MASK;
ret = i40e_vlan_offload_set(dev, mask);
uint16_t i;
struct i40e_rx_queue *rxq;
- i40e_pf_config_mq_rx(pf);
+ i40e_pf_config_rss(pf);
for (i = 0; i < data->nb_rx_queues; i++) {
rxq = data->rx_queues[i];
if (!rxq || !rxq->q_set)
case i40e_aqc_opc_get_link_status:
ret = i40e_dev_link_update(dev, 0);
if (!ret)
- _rte_eth_dev_callback_process(dev,
+ rte_eth_dev_callback_process(dev,
RTE_ETH_EVENT_INTR_LSC, NULL);
break;
default:
rte_cpu_to_le_16(filter[num + i].vlan_id);
switch (filter[num + i].filter_type) {
- case RTE_MAC_PERFECT_MATCH:
+ case I40E_MAC_PERFECT_MATCH:
flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
break;
- case RTE_MACVLAN_PERFECT_MATCH:
+ case I40E_MACVLAN_PERFECT_MATCH:
flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
break;
- case RTE_MAC_HASH_MATCH:
+ case I40E_MAC_HASH_MATCH:
flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
break;
- case RTE_MACVLAN_HASH_MATCH:
+ case I40E_MACVLAN_HASH_MATCH:
flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
break;
default:
rte_cpu_to_le_16(filter[num + i].vlan_id);
switch (filter[num + i].filter_type) {
- case RTE_MAC_PERFECT_MATCH:
+ case I40E_MAC_PERFECT_MATCH:
flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
break;
- case RTE_MACVLAN_PERFECT_MATCH:
+ case I40E_MACVLAN_PERFECT_MATCH:
flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
break;
- case RTE_MAC_HASH_MATCH:
+ case I40E_MAC_HASH_MATCH:
flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
break;
- case RTE_MACVLAN_HASH_MATCH:
+ case I40E_MACVLAN_HASH_MATCH:
flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
break;
default:
f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
if (f != NULL)
return I40E_SUCCESS;
- if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
- (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
+ if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
+ mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
/**
* If vlan_num is 0, that's the first time to add mac,
vsi->vlan_num = 1;
}
vlan_num = vsi->vlan_num;
- } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
- (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
+ } else if (mac_filter->filter_type == I40E_MAC_PERFECT_MATCH ||
+ mac_filter->filter_type == I40E_MAC_HASH_MATCH)
vlan_num = 1;
mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
ETH_ADDR_LEN);
}
- if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
- mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
+ if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
+ mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
&mac_filter->mac_addr);
if (ret != I40E_SUCCESS)
struct i40e_mac_filter *f;
struct i40e_macvlan_filter *mv_f;
int i, vlan_num;
- enum rte_mac_filter_type filter_type;
+ enum i40e_mac_filter_type filter_type;
int ret = I40E_SUCCESS;
/* Can't find it, return an error */
vlan_num = vsi->vlan_num;
filter_type = f->mac_info.filter_type;
- if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
- filter_type == RTE_MACVLAN_HASH_MATCH) {
+ if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
+ filter_type == I40E_MACVLAN_HASH_MATCH) {
if (vlan_num == 0) {
PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
return I40E_ERR_PARAM;
}
- } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
- filter_type == RTE_MAC_HASH_MATCH)
+ } else if (filter_type == I40E_MAC_PERFECT_MATCH ||
+ filter_type == I40E_MAC_HASH_MATCH)
vlan_num = 1;
mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
ETH_ADDR_LEN);
}
- if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
- filter_type == RTE_MACVLAN_HASH_MATCH) {
+ if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
+ filter_type == I40E_MACVLAN_HASH_MATCH) {
ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
if (ret != I40E_SUCCESS)
goto DONE;
return 0;
}
-int
-i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
- struct rte_eth_tunnel_filter_conf *tunnel_filter,
- uint8_t add)
+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
+#define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
+#define I40E_TR_GENEVE_KEY_MASK 0x8
+#define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
+#define I40E_TR_GRE_KEY_MASK 0x400
+#define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
+#define I40E_TR_GRE_NO_KEY_MASK 0x8000
+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
+#define I40E_DIRECTION_INGRESS_KEY 0x8000
+#define I40E_TR_L4_TYPE_TCP 0x2
+#define I40E_TR_L4_TYPE_UDP 0x4
+#define I40E_TR_L4_TYPE_SCTP 0x8
+
+static enum
+i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
{
- uint16_t ip_type;
- uint32_t ipv4_addr, ipv4_addr_le;
- uint8_t i, tun_type = 0;
- /* internal varialbe to convert ipv6 byte order */
- uint32_t convert_ipv6[4];
- int val, ret = 0;
+ struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
+ struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- struct i40e_vsi *vsi = pf->main_vsi;
- struct i40e_aqc_cloud_filters_element_bb *cld_filter;
- struct i40e_aqc_cloud_filters_element_bb *pfilter;
- struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
- struct i40e_tunnel_filter *tunnel, *node;
- struct i40e_tunnel_filter check_filter; /* Check if filter exists */
-
- cld_filter = rte_zmalloc("tunnel_filter",
- sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
- 0);
+ struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
+ enum i40e_status_code status = I40E_SUCCESS;
- if (NULL == cld_filter) {
- PMD_DRV_LOG(ERR, "Failed to alloc memory.");
- return -ENOMEM;
+ if (pf->support_multi_driver) {
+ PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
+ return I40E_NOT_SUPPORTED;
}
- pfilter = cld_filter;
-
- rte_ether_addr_copy(&tunnel_filter->outer_mac,
- (struct rte_ether_addr *)&pfilter->element.outer_mac);
- rte_ether_addr_copy(&tunnel_filter->inner_mac,
- (struct rte_ether_addr *)&pfilter->element.inner_mac);
- pfilter->element.inner_vlan =
- rte_cpu_to_le_16(tunnel_filter->inner_vlan);
- if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
- ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
- ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
- ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
- rte_memcpy(&pfilter->element.ipaddr.v4.data,
- &ipv4_addr_le,
- sizeof(pfilter->element.ipaddr.v4.data));
- } else {
- ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
- for (i = 0; i < 4; i++) {
- convert_ipv6[i] =
- rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
- }
- rte_memcpy(&pfilter->element.ipaddr.v6.data,
- &convert_ipv6,
- sizeof(pfilter->element.ipaddr.v6.data));
- }
+ memset(&filter_replace, 0,
+ sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
+ memset(&filter_replace_buf, 0,
+ sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
- /* check tunneled type */
- switch (tunnel_filter->tunnel_type) {
- case RTE_TUNNEL_TYPE_VXLAN:
- tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
- break;
- case RTE_TUNNEL_TYPE_NVGRE:
- tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
- break;
- case RTE_TUNNEL_TYPE_IP_IN_GRE:
- tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
- break;
- case RTE_TUNNEL_TYPE_VXLAN_GPE:
- tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
- break;
- default:
- /* Other tunnel types is not supported. */
- PMD_DRV_LOG(ERR, "tunnel type is not supported.");
- rte_free(cld_filter);
- return -EINVAL;
- }
+ /* create L1 filter */
+ filter_replace.old_filter_type =
+ I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
+ filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
+ filter_replace.tr_bit = 0;
- val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
- &pfilter->element.flags);
- if (val < 0) {
- rte_free(cld_filter);
- return -EINVAL;
- }
-
- pfilter->element.flags |= rte_cpu_to_le_16(
- I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
- ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
- pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
- pfilter->element.queue_number =
- rte_cpu_to_le_16(tunnel_filter->queue_id);
-
- /* Check if there is the filter in SW list */
- memset(&check_filter, 0, sizeof(check_filter));
- i40e_tunnel_filter_convert(cld_filter, &check_filter);
- node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
- if (add && node) {
- PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
- rte_free(cld_filter);
- return -EINVAL;
- }
-
- if (!add && !node) {
- PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
- rte_free(cld_filter);
- return -EINVAL;
- }
-
- if (add) {
- ret = i40e_aq_add_cloud_filters(hw,
- vsi->seid, &cld_filter->element, 1);
- if (ret < 0) {
- PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
- rte_free(cld_filter);
- return -ENOTSUP;
- }
- tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
- if (tunnel == NULL) {
- PMD_DRV_LOG(ERR, "Failed to alloc memory.");
- rte_free(cld_filter);
- return -ENOMEM;
- }
-
- rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
- ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
- if (ret < 0)
- rte_free(tunnel);
- } else {
- ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
- &cld_filter->element, 1);
- if (ret < 0) {
- PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
- rte_free(cld_filter);
- return -ENOTSUP;
- }
- ret = i40e_sw_tunnel_filter_del(pf, &node->input);
- }
-
- rte_free(cld_filter);
- return ret;
-}
-
-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
-#define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
-#define I40E_TR_GENEVE_KEY_MASK 0x8
-#define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
-#define I40E_TR_GRE_KEY_MASK 0x400
-#define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
-#define I40E_TR_GRE_NO_KEY_MASK 0x8000
-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
-#define I40E_DIRECTION_INGRESS_KEY 0x8000
-#define I40E_TR_L4_TYPE_TCP 0x2
-#define I40E_TR_L4_TYPE_UDP 0x4
-#define I40E_TR_L4_TYPE_SCTP 0x8
-
-static enum
-i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
-{
- struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
- struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
- struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
- enum i40e_status_code status = I40E_SUCCESS;
-
- if (pf->support_multi_driver) {
- PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
- return I40E_NOT_SUPPORTED;
- }
-
- memset(&filter_replace, 0,
- sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
- memset(&filter_replace_buf, 0,
- sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
-
- /* create L1 filter */
- filter_replace.old_filter_type =
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
- filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
- filter_replace.tr_bit = 0;
-
- /* Prepare the buffer, 3 entries */
- filter_replace_buf.data[0] =
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
- filter_replace_buf.data[0] |=
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
- filter_replace_buf.data[2] = 0xFF;
- filter_replace_buf.data[3] = 0xFF;
- filter_replace_buf.data[4] =
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
- filter_replace_buf.data[4] |=
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
- filter_replace_buf.data[7] = 0xF0;
- filter_replace_buf.data[8]
- = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
- filter_replace_buf.data[8] |=
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
- filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
- I40E_TR_GENEVE_KEY_MASK |
- I40E_TR_GENERIC_UDP_TUNNEL_MASK;
- filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
- I40E_TR_GRE_KEY_WITH_XSUM_MASK |
- I40E_TR_GRE_NO_KEY_MASK) >> 8;
+ /* Prepare the buffer, 3 entries */
+ filter_replace_buf.data[0] =
+ I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
+ filter_replace_buf.data[0] |=
+ I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
+ filter_replace_buf.data[2] = 0xFF;
+ filter_replace_buf.data[3] = 0xFF;
+ filter_replace_buf.data[4] =
+ I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
+ filter_replace_buf.data[4] |=
+ I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
+ filter_replace_buf.data[7] = 0xF0;
+ filter_replace_buf.data[8]
+ = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
+ filter_replace_buf.data[8] |=
+ I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
+ filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
+ I40E_TR_GENEVE_KEY_MASK |
+ I40E_TR_GENERIC_UDP_TUNNEL_MASK;
+ filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
+ I40E_TR_GRE_KEY_WITH_XSUM_MASK |
+ I40E_TR_GRE_NO_KEY_MASK) >> 8;
status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
&filter_replace_buf);
static int
i40e_pf_config_rss(struct i40e_pf *pf)
{
+ enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
struct rte_eth_rss_conf rss_conf;
uint32_t i, lut = 0;
}
rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
- if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
+ if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0 ||
+ !(mq_mode & ETH_MQ_RX_RSS_FLAG)) {
i40e_pf_disable_rss(pf);
return 0;
}
return i40e_hw_rss_hash_set(pf, &rss_conf);
}
-static int
-i40e_tunnel_filter_param_check(struct i40e_pf *pf,
- struct rte_eth_tunnel_filter_conf *filter)
-{
- if (pf == NULL || filter == NULL) {
- PMD_DRV_LOG(ERR, "Invalid parameter");
- return -EINVAL;
- }
-
- if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
- PMD_DRV_LOG(ERR, "Invalid queue ID");
- return -EINVAL;
- }
-
- if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
- PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
- return -EINVAL;
- }
-
- if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
- (rte_is_zero_ether_addr(&filter->outer_mac))) {
- PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
- return -EINVAL;
- }
-
- if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
- (rte_is_zero_ether_addr(&filter->inner_mac))) {
- PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
- return -EINVAL;
- }
-
- return 0;
-}
-
#define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
#define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
int
return ret;
}
-static int
-i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
-{
- int ret = -EINVAL;
-
- if (!hw || !cfg)
- return -EINVAL;
-
- switch (cfg->cfg_type) {
- case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
- ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
- break;
- default:
- PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
- break;
- }
-
- return ret;
-}
-
-static int
-i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
- enum rte_filter_op filter_op,
- void *arg)
-{
- struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- int ret = I40E_ERR_PARAM;
-
- switch (filter_op) {
- case RTE_ETH_FILTER_SET:
- ret = i40e_dev_global_config_set(hw,
- (struct rte_eth_global_cfg *)arg);
- break;
- default:
- PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
- break;
- }
-
- return ret;
-}
-
-static int
-i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
- enum rte_filter_op filter_op,
- void *arg)
-{
- struct rte_eth_tunnel_filter_conf *filter;
- struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
- int ret = I40E_SUCCESS;
-
- filter = (struct rte_eth_tunnel_filter_conf *)(arg);
-
- if (i40e_tunnel_filter_param_check(pf, filter) < 0)
- return I40E_ERR_PARAM;
-
- switch (filter_op) {
- case RTE_ETH_FILTER_NOP:
- if (!(pf->flags & I40E_FLAG_VXLAN))
- ret = I40E_NOT_SUPPORTED;
- break;
- case RTE_ETH_FILTER_ADD:
- ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
- break;
- case RTE_ETH_FILTER_DELETE:
- ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
- break;
- default:
- PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
- ret = I40E_ERR_PARAM;
- break;
- }
-
- return ret;
-}
-
-static int
-i40e_pf_config_mq_rx(struct i40e_pf *pf)
-{
- int ret = 0;
- enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
-
- /* RSS setup */
- if (mq_mode & ETH_MQ_RX_RSS_FLAG)
- ret = i40e_pf_config_rss(pf);
- else
- i40e_pf_disable_rss(pf);
-
- return ret;
-}
-
-/* Get the symmetric hash enable configurations per port */
-static void
-i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
-{
- uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
-
- *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
-}
-
/* Set the symmetric hash enable configurations per port */
static void
i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
I40E_WRITE_FLUSH(hw);
}
-/*
- * Get global configurations of hash function type and symmetric hash enable
- * per flow type (pctype). Note that global configuration means it affects all
- * the ports on the same NIC.
- */
-static int
-i40e_get_hash_filter_global_config(struct i40e_hw *hw,
- struct rte_eth_hash_global_conf *g_cfg)
-{
- struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
- uint32_t reg;
- uint16_t i, j;
-
- memset(g_cfg, 0, sizeof(*g_cfg));
- reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
- if (reg & I40E_GLQF_CTL_HTOEP_MASK)
- g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
- else
- g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
- PMD_DRV_LOG(DEBUG, "Hash function is %s",
- (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
-
- /*
- * As i40e supports less than 64 flow types, only first 64 bits need to
- * be checked.
- */
- for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
- g_cfg->valid_bit_mask[i] = 0ULL;
- g_cfg->sym_hash_enable_mask[i] = 0ULL;
- }
-
- g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
-
- for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
- if (!adapter->pctypes_tbl[i])
- continue;
- for (j = I40E_FILTER_PCTYPE_INVALID + 1;
- j < I40E_FILTER_PCTYPE_MAX; j++) {
- if (adapter->pctypes_tbl[i] & (1ULL << j)) {
- reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
- if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
- g_cfg->sym_hash_enable_mask[0] |=
- (1ULL << i);
- }
- }
- }
- }
-
- return 0;
-}
-
-static int
-i40e_hash_global_config_check(const struct i40e_adapter *adapter,
- const struct rte_eth_hash_global_conf *g_cfg)
-{
- uint32_t i;
- uint64_t mask0, i40e_mask = adapter->flow_types_mask;
-
- if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
- g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
- g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
- PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
- g_cfg->hash_func);
- return -EINVAL;
- }
-
- /*
- * As i40e supports less than 64 flow types, only first 64 bits need to
- * be checked.
- */
- mask0 = g_cfg->valid_bit_mask[0];
- for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
- if (i == 0) {
- /* Check if any unsupported flow type configured */
- if ((mask0 | i40e_mask) ^ i40e_mask)
- goto mask_err;
- } else {
- if (g_cfg->valid_bit_mask[i])
- goto mask_err;
- }
- }
-
- return 0;
-
-mask_err:
- PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
-
- return -EINVAL;
-}
-
-/*
- * Set global configurations of hash function type and symmetric hash enable
- * per flow type (pctype). Note any modifying global configuration will affect
- * all the ports on the same NIC.
- */
-static int
-i40e_set_hash_filter_global_config(struct i40e_hw *hw,
- struct rte_eth_hash_global_conf *g_cfg)
-{
- struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
- struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
- int ret;
- uint16_t i, j;
- uint32_t reg;
- uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
-
- if (pf->support_multi_driver) {
- PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
- return -ENOTSUP;
- }
-
- /* Check the input parameters */
- ret = i40e_hash_global_config_check(adapter, g_cfg);
- if (ret < 0)
- return ret;
-
- /*
- * As i40e supports less than 64 flow types, only first 64 bits need to
- * be configured.
- */
- for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
- if (mask0 & (1UL << i)) {
- reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
- I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
-
- for (j = I40E_FILTER_PCTYPE_INVALID + 1;
- j < I40E_FILTER_PCTYPE_MAX; j++) {
- if (adapter->pctypes_tbl[i] & (1ULL << j))
- i40e_write_global_rx_ctl(hw,
- I40E_GLQF_HSYM(j),
- reg);
- }
- }
- }
-
- reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
- if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
- /* Toeplitz */
- if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
- PMD_DRV_LOG(DEBUG,
- "Hash function already set to Toeplitz");
- goto out;
- }
- reg |= I40E_GLQF_CTL_HTOEP_MASK;
- } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
- /* Simple XOR */
- if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
- PMD_DRV_LOG(DEBUG,
- "Hash function already set to Simple XOR");
- goto out;
- }
- reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
- } else
- /* Use the default, and keep it as it is */
- goto out;
-
- i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
-
-out:
- I40E_WRITE_FLUSH(hw);
-
- return 0;
-}
-
/**
* Valid input sets for hash and flow director filters per PCTYPE
*/
return 0;
}
-int
-i40e_fdir_filter_inset_select(struct i40e_pf *pf,
- struct rte_eth_input_set_conf *conf)
-{
- struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- enum i40e_filter_pctype pctype;
- uint64_t input_set, inset_reg = 0;
- uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
- int ret, i, num;
-
- if (!hw || !conf) {
- PMD_DRV_LOG(ERR, "Invalid pointer");
- return -EFAULT;
- }
- if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
- conf->op != RTE_ETH_INPUT_SET_ADD) {
- PMD_DRV_LOG(ERR, "Unsupported input set operation");
- return -EINVAL;
- }
-
- pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
-
- if (pctype == I40E_FILTER_PCTYPE_INVALID) {
- PMD_DRV_LOG(ERR, "invalid flow_type input.");
- return -EINVAL;
- }
-
- ret = i40e_parse_input_set(&input_set, pctype, conf->field,
- conf->inset_size);
- if (ret) {
- PMD_DRV_LOG(ERR, "Failed to parse input set");
- return -EINVAL;
- }
-
- /* get inset value in register */
- inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
- inset_reg <<= I40E_32_BIT_WIDTH;
- inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
-
- /* Can not change the inset reg for flex payload for fdir,
- * it is done by writing I40E_PRTQF_FD_FLXINSET
- * in i40e_set_flex_mask_on_pctype.
- */
- if (conf->op == RTE_ETH_INPUT_SET_SELECT)
- inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
- else
- input_set |= pf->fdir.input_set[pctype];
- num = i40e_generate_inset_mask_reg(input_set, mask_reg,
- I40E_INSET_MASK_NUM_REG);
- if (num < 0)
- return -EINVAL;
- if (pf->support_multi_driver && num > 0) {
- PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
- return -ENOTSUP;
- }
-
- inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
-
- i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
- (uint32_t)(inset_reg & UINT32_MAX));
- i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
- (uint32_t)((inset_reg >>
- I40E_32_BIT_WIDTH) & UINT32_MAX));
-
- if (!pf->support_multi_driver) {
- for (i = 0; i < num; i++)
- i40e_check_write_global_reg(hw,
- I40E_GLQF_FD_MSK(i, pctype),
- mask_reg[i]);
- /*clear unused mask registers of the pctype */
- for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
- i40e_check_write_global_reg(hw,
- I40E_GLQF_FD_MSK(i, pctype),
- 0);
- } else {
- PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
- }
- I40E_WRITE_FLUSH(hw);
-
- pf->fdir.input_set[pctype] = input_set;
- return 0;
-}
-
-static int
-i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
-{
- int ret = 0;
-
- if (!hw || !info) {
- PMD_DRV_LOG(ERR, "Invalid pointer");
- return -EFAULT;
- }
-
- switch (info->info_type) {
- case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
- i40e_get_symmetric_hash_enable_per_port(hw,
- &(info->info.enable));
- break;
- case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
- ret = i40e_get_hash_filter_global_config(hw,
- &(info->info.global_conf));
- break;
- default:
- PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
- info->info_type);
- ret = -EINVAL;
- break;
- }
-
- return ret;
-}
-
-static int
-i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
-{
- int ret = 0;
-
- if (!hw || !info) {
- PMD_DRV_LOG(ERR, "Invalid pointer");
- return -EFAULT;
- }
-
- switch (info->info_type) {
- case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
- i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
- break;
- case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
- ret = i40e_set_hash_filter_global_config(hw,
- &(info->info.global_conf));
- break;
- case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
- ret = i40e_hash_filter_inset_select(hw,
- &(info->info.input_set_conf));
- break;
-
- default:
- PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
- info->info_type);
- ret = -EINVAL;
- break;
- }
-
- return ret;
-}
-
-/* Operations for hash function */
-static int
-i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
- enum rte_filter_op filter_op,
- void *arg)
-{
- struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- int ret = 0;
-
- switch (filter_op) {
- case RTE_ETH_FILTER_NOP:
- break;
- case RTE_ETH_FILTER_GET:
- ret = i40e_hash_filter_get(hw,
- (struct rte_eth_hash_filter_info *)arg);
- break;
- case RTE_ETH_FILTER_SET:
- ret = i40e_hash_filter_set(hw,
- (struct rte_eth_hash_filter_info *)arg);
- break;
- default:
- PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
- filter_op);
- ret = -ENOTSUP;
- break;
- }
-
- return ret;
-}
-
/* Convert ethertype filter structure */
static int
i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
return ret;
}
-/*
- * Handle operations for ethertype filter.
- */
-static int
-i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
- enum rte_filter_op filter_op,
- void *arg)
-{
- struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
- int ret = 0;
-
- if (filter_op == RTE_ETH_FILTER_NOP)
- return ret;
-
- if (arg == NULL) {
- PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
- filter_op);
- return -EINVAL;
- }
-
- switch (filter_op) {
- case RTE_ETH_FILTER_ADD:
- ret = i40e_ethertype_filter_set(pf,
- (struct rte_eth_ethertype_filter *)arg,
- TRUE);
- break;
- case RTE_ETH_FILTER_DELETE:
- ret = i40e_ethertype_filter_set(pf,
- (struct rte_eth_ethertype_filter *)arg,
- FALSE);
- break;
- default:
- PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
- ret = -ENOSYS;
- break;
- }
- return ret;
-}
-
static int
i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
enum rte_filter_type filter_type,
return -EINVAL;
switch (filter_type) {
- case RTE_ETH_FILTER_NONE:
- /* For global configuration */
- ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
- break;
- case RTE_ETH_FILTER_HASH:
- ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
- break;
- case RTE_ETH_FILTER_MACVLAN:
- ret = i40e_mac_filter_handle(dev, filter_op, arg);
- break;
- case RTE_ETH_FILTER_ETHERTYPE:
- ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
- break;
- case RTE_ETH_FILTER_TUNNEL:
- ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
- break;
- case RTE_ETH_FILTER_FDIR:
- ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
- break;
case RTE_ETH_FILTER_GENERIC:
if (filter_op != RTE_ETH_FILTER_GET)
return -EINVAL;
}
}
-#define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
#define I40E_VSI_TSR_QINQ_CONFIG 0xc030
#define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
#define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
git.droids-corp.org / dpdk.git / blobdiff